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emx: Remove dependency on opt_rss.h; RSS is always enabled
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
5330213c
SZ		 1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
e6cde6e6 68#include "opt_emx.h"
5330213c
SZ		 69
70#include <sys/param.h>
71#include <sys/bus.h>
72#include <sys/endian.h>
73#include <sys/interrupt.h>
74#include <sys/kernel.h>
75#include <sys/ktr.h>
76#include <sys/malloc.h>
77#include <sys/mbuf.h>
78#include <sys/proc.h>
79#include <sys/rman.h>
80#include <sys/serialize.h>
bc197380 81#include <sys/serialize2.h>
5330213c
SZ		 82#include <sys/socket.h>
83#include <sys/sockio.h>
84#include <sys/sysctl.h>
85#include <sys/systm.h>
86
87#include <net/bpf.h>
88#include <net/ethernet.h>
89#include <net/if.h>
90#include <net/if_arp.h>
91#include <net/if_dl.h>
92#include <net/if_media.h>
93#include <net/ifq_var.h>
89d8e73d 94#include <net/toeplitz.h>
9cc86e17 95#include <net/toeplitz2.h>
5330213c
SZ		 96#include <net/vlan/if_vlan_var.h>
97#include <net/vlan/if_vlan_ether.h>
b3a7093f 98#include <net/if_poll.h>
5330213c
SZ		 99
100#include <netinet/in_systm.h>
101#include <netinet/in.h>
102#include <netinet/ip.h>
103#include <netinet/tcp.h>
104#include <netinet/udp.h>
105
106#include <bus/pci/pcivar.h>
107#include <bus/pci/pcireg.h>
108
109#include <dev/netif/ig_hal/e1000_api.h>
110#include <dev/netif/ig_hal/e1000_82571.h>
111#include <dev/netif/emx/if_emx.h>
112
3f939c23
SZ		 113#ifdef EMX_RSS_DEBUG
114#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
115do { \
89d8e73d 116 if (sc->rss_debug >= lvl) \
3f939c23
SZ		 117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
118} while (0)
119#else /* !EMX_RSS_DEBUG */
120#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121#endif /* EMX_RSS_DEBUG */
122
8f594b38
SZ		 123#define EMX_TX_SERIALIZE 1
124#define EMX_RX_SERIALIZE 2
125
5330213c
SZ		 126#define EMX_NAME "Intel(R) PRO/1000 "
127
128#define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130#define EMX_DEVICE_NULL { 0, 0, NULL }
131
132static const struct emx_device {
133 uint16_t vid;
134 uint16_t did;
135 const char *desc;
136} emx_devices[] = {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
5330213c
SZ		 144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
147
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
151 EMX_DEVICE(82572EI),
152
153 EMX_DEVICE(82573E),
154 EMX_DEVICE(82573E_IAMT),
155 EMX_DEVICE(82573L),
156
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
161
162 EMX_DEVICE(82574L),
2d0e5700 163 EMX_DEVICE(82574LA),
5330213c
SZ		 164
165 /* required last entry */
166 EMX_DEVICE_NULL
167};
168
169static int emx_probe(device_t);
170static int emx_attach(device_t);
171static int emx_detach(device_t);
172static int emx_shutdown(device_t);
173static int emx_suspend(device_t);
174static int emx_resume(device_t);
175
176static void emx_init(void *);
177static void emx_stop(struct emx_softc *);
178static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179static void emx_start(struct ifnet *);
b3a7093f
SZ		 180#ifdef IFPOLL_ENABLE
181static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
5330213c
SZ		 182#endif
183static void emx_watchdog(struct ifnet *);
184static void emx_media_status(struct ifnet *, struct ifmediareq *);
185static int emx_media_change(struct ifnet *);
186static void emx_timer(void *);
6d435846
SZ		 187static void emx_serialize(struct ifnet *, enum ifnet_serialize);
188static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
189static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
2c9effcf
SZ		 190#ifdef INVARIANTS
191static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
192 boolean_t);
193#endif
5330213c
SZ		 194
195static void emx_intr(void *);
4cb541ae
SZ		 196static void emx_intr_mask(void *);
197static void emx_intr_body(struct emx_softc *, boolean_t);
c39e3a1f 198static void emx_rxeof(struct emx_softc *, int, int);
5330213c
SZ		 199static void emx_txeof(struct emx_softc *);
200static void emx_tx_collect(struct emx_softc *);
201static void emx_tx_purge(struct emx_softc *);
202static void emx_enable_intr(struct emx_softc *);
203static void emx_disable_intr(struct emx_softc *);
204
071699f8
SZ		 205static int emx_dma_alloc(struct emx_softc *);
206static void emx_dma_free(struct emx_softc *);
5330213c 207static void emx_init_tx_ring(struct emx_softc *);
c39e3a1f
SZ		 208static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
209static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 210static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 211static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 212static void emx_destroy_tx_ring(struct emx_softc *, int);
c39e3a1f
SZ		 213static void emx_destroy_rx_ring(struct emx_softc *,
214 struct emx_rxdata *, int);
215static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 216static int emx_encap(struct emx_softc *, struct mbuf **);
5330213c
SZ		 217static int emx_txcsum(struct emx_softc *, struct mbuf *,
218 uint32_t *, uint32_t *);
3eb0ea09
SZ		 219static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
220static int emx_tso_setup(struct emx_softc *, struct mbuf *,
221 uint32_t *, uint32_t *);
5330213c
SZ		 222
223static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 224static int emx_reset(struct emx_softc *);
5330213c
SZ		 225static void emx_setup_ifp(struct emx_softc *);
226static void emx_init_tx_unit(struct emx_softc *);
227static void emx_init_rx_unit(struct emx_softc *);
228static void emx_update_stats(struct emx_softc *);
229static void emx_set_promisc(struct emx_softc *);
230static void emx_disable_promisc(struct emx_softc *);
231static void emx_set_multi(struct emx_softc *);
232static void emx_update_link_status(struct emx_softc *);
233static void emx_smartspeed(struct emx_softc *);
2d0e5700 234static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 235static void emx_disable_aspm(struct emx_softc *);
5330213c
SZ		 236
237static void emx_print_debug_info(struct emx_softc *);
238static void emx_print_nvm_info(struct emx_softc *);
239static void emx_print_hw_stats(struct emx_softc *);
240
241static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
242static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
243static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
244static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
245static void emx_add_sysctl(struct emx_softc *);
246
bca7c435
SZ		 247static void emx_serialize_skipmain(struct emx_softc *);
248static void emx_deserialize_skipmain(struct emx_softc *);
249
5330213c
SZ		 250/* Management and WOL Support */
251static void emx_get_mgmt(struct emx_softc *);
252static void emx_rel_mgmt(struct emx_softc *);
253static void emx_get_hw_control(struct emx_softc *);
254static void emx_rel_hw_control(struct emx_softc *);
255static void emx_enable_wol(device_t);
256
257static device_method_t emx_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, emx_probe),
260 DEVMETHOD(device_attach, emx_attach),
261 DEVMETHOD(device_detach, emx_detach),
262 DEVMETHOD(device_shutdown, emx_shutdown),
263 DEVMETHOD(device_suspend, emx_suspend),
264 DEVMETHOD(device_resume, emx_resume),
265 { 0, 0 }
266};
267
268static driver_t emx_driver = {
269 "emx",
270 emx_methods,
271 sizeof(struct emx_softc),
272};
273
274static devclass_t emx_devclass;
275
276DECLARE_DUMMY_MODULE(if_emx);
277MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 278DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
5330213c
SZ		 279
280/*
281 * Tunables
282 */
283static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
284static int emx_rxd = EMX_DEFAULT_RXD;
285static int emx_txd = EMX_DEFAULT_TXD;
704b6287 286static int emx_smart_pwr_down = 0;
724cbff8 287static int emx_rxr = 0;
5330213c
SZ		 288
289/* Controls whether promiscuous also shows bad packets */
b4d8c36b 290static int emx_debug_sbp = 0;
5330213c 291
704b6287
SZ		 292static int emx_82573_workaround = 1;
293static int emx_msi_enable = 1;
5330213c
SZ		 294
295TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
296TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 297TUNABLE_INT("hw.emx.rxr", &emx_rxr);
5330213c
SZ		 298TUNABLE_INT("hw.emx.txd", &emx_txd);
299TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
300TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
301TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 302TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
5330213c
SZ		 303
304/* Global used in WOL setup with multiport cards */
305static int emx_global_quad_port_a = 0;
306
307/* Set this to one to display debug statistics */
308static int emx_display_debug_stats = 0;
309
310#if !defined(KTR_IF_EMX)
311#define KTR_IF_EMX KTR_ALL
312#endif
313KTR_INFO_MASTER(if_emx);
5bf48697
AE		 314KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
315KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
316KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
317KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
318KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
5330213c
SZ		 319#define logif(name) KTR_LOG(if_emx_ ## name)
320
235b9d30
SZ		 321static __inline void
322emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
323{
324 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 325 /* DD bit must be cleared */
235b9d30
SZ		 326 rxd->rxd_staterr = 0;
327}
328
329static __inline void
330emx_rxcsum(uint32_t staterr, struct mbuf *mp)
331{
332 /* Ignore Checksum bit is set */
333 if (staterr & E1000_RXD_STAT_IXSM)
334 return;
335
336 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
337 E1000_RXD_STAT_IPCS)
338 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
339
340 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
341 E1000_RXD_STAT_TCPCS) {
342 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
343 CSUM_PSEUDO_HDR |
344 CSUM_FRAG_NOT_CHECKED;
345 mp->m_pkthdr.csum_data = htons(0xffff);
346 }
347}
348
9cc86e17
SZ		 349static __inline struct pktinfo *
350emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
351 uint32_t mrq, uint32_t hash, uint32_t staterr)
352{
353 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
354 case EMX_RXDMRQ_IPV4_TCP:
355 pi->pi_netisr = NETISR_IP;
356 pi->pi_flags = 0;
357 pi->pi_l3proto = IPPROTO_TCP;
358 break;
359
360 case EMX_RXDMRQ_IPV6_TCP:
361 pi->pi_netisr = NETISR_IPV6;
362 pi->pi_flags = 0;
363 pi->pi_l3proto = IPPROTO_TCP;
364 break;
365
366 case EMX_RXDMRQ_IPV4:
367 if (staterr & E1000_RXD_STAT_IXSM)
368 return NULL;
369
370 if ((staterr &
371 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
372 E1000_RXD_STAT_TCPCS) {
373 pi->pi_netisr = NETISR_IP;
374 pi->pi_flags = 0;
375 pi->pi_l3proto = IPPROTO_UDP;
376 break;
377 }
378 /* FALL THROUGH */
379 default:
380 return NULL;
381 }
382
383 m->m_flags |= M_HASH;
384 m->m_pkthdr.hash = toeplitz_hash(hash);
385 return pi;
386}
387
5330213c
SZ		 388static int
389emx_probe(device_t dev)
390{
391 const struct emx_device *d;
392 uint16_t vid, did;
393
394 vid = pci_get_vendor(dev);
395 did = pci_get_device(dev);
396
397 for (d = emx_devices; d->desc != NULL; ++d) {
398 if (vid == d->vid && did == d->did) {
399 device_set_desc(dev, d->desc);
400 device_set_async_attach(dev, TRUE);
401 return 0;
402 }
403 }
404 return ENXIO;
405}
406
407static int
408emx_attach(device_t dev)
409{
410 struct emx_softc *sc = device_get_softc(dev);
411 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 412 int error = 0, i, throttle, msi_enable;
704b6287 413 u_int intr_flags;
2d0e5700 414 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 415 driver_intr_t *intr_func;
5330213c 416
6d435846
SZ		 417 lwkt_serialize_init(&sc->main_serialize);
418 lwkt_serialize_init(&sc->tx_serialize);
419 for (i = 0; i < EMX_NRX_RING; ++i)
420 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
421
6d435846
SZ		 422 i = 0;
423 sc->serializes[i++] = &sc->main_serialize;
424 sc->serializes[i++] = &sc->tx_serialize;
425 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
426 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
427 KKASSERT(i == EMX_NSERIALIZE);
428
c2022416 429 callout_init_mp(&sc->timer);
5330213c
SZ		 430
431 sc->dev = sc->osdep.dev = dev;
432
433 /*
434 * Determine hardware and mac type
435 */
436 sc->hw.vendor_id = pci_get_vendor(dev);
437 sc->hw.device_id = pci_get_device(dev);
438 sc->hw.revision_id = pci_get_revid(dev);
439 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
440 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
441
442 if (e1000_set_mac_type(&sc->hw))
443 return ENXIO;
444
3eb0ea09
SZ		 445 /*
446 * Pullup extra 4bytes into the first data segment, see:
447 * 82571/82572 specification update errata #7
448 *
449 * NOTE:
450 * 4bytes instead of 2bytes, which are mentioned in the errata,
451 * are pulled; mainly to keep rest of the data properly aligned.
452 */
453 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
454 sc->flags |= EMX_FLAG_TSO_PULLEX;
455
5330213c
SZ		 456 /* Enable bus mastering */
457 pci_enable_busmaster(dev);
458
459 /*
460 * Allocate IO memory
461 */
462 sc->memory_rid = EMX_BAR_MEM;
463 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
464 &sc->memory_rid, RF_ACTIVE);
465 if (sc->memory == NULL) {
466 device_printf(dev, "Unable to allocate bus resource: memory\n");
467 error = ENXIO;
468 goto fail;
469 }
470 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
471 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
472
473 /* XXX This is quite goofy, it is not actually used */
474 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
475
476 /*
a835687d
SZ		 477 * Don't enable MSI-X on 82574, see:
478 * 82574 specification update errata #15
479 *
d01335e8 480 * Don't enable MSI on 82571/82572, see:
a835687d 481 * 82571/82572 specification update errata #63
d01335e8
SZ		 482 */
483 msi_enable = emx_msi_enable;
484 if (msi_enable &&
485 (sc->hw.mac.type == e1000_82571 ||
486 sc->hw.mac.type == e1000_82572))
487 msi_enable = 0;
488
489 /*
5330213c
SZ		 490 * Allocate interrupt
491 */
d01335e8 492 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 493 &sc->intr_rid, &intr_flags);
704b6287 494
4cb541ae
SZ		 495 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
496 int unshared;
497
498 unshared = device_getenv_int(dev, "irq.unshared", 0);
499 if (!unshared) {
500 sc->flags |= EMX_FLAG_SHARED_INTR;
501 if (bootverbose)
502 device_printf(dev, "IRQ shared\n");
503 } else {
504 intr_flags &= ~RF_SHAREABLE;
505 if (bootverbose)
506 device_printf(dev, "IRQ unshared\n");
507 }
508 }
509
5330213c 510 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 511 intr_flags);
5330213c
SZ		 512 if (sc->intr_res == NULL) {
513 device_printf(dev, "Unable to allocate bus resource: "
514 "interrupt\n");
515 error = ENXIO;
516 goto fail;
517 }
518
519 /* Save PCI command register for Shared Code */
520 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
521 sc->hw.back = &sc->osdep;
522
523 /* Do Shared Code initialization */
524 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
525 device_printf(dev, "Setup of Shared code failed\n");
526 error = ENXIO;
527 goto fail;
528 }
529 e1000_get_bus_info(&sc->hw);
530
5330213c
SZ		 531 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
532 sc->hw.phy.autoneg_wait_to_complete = FALSE;
533 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
5330213c
SZ		 534
535 /*
536 * Interrupt throttle rate
537 */
b4d8c36b
SZ		 538 throttle = device_getenv_int(dev, "int_throttle_ceil",
539 emx_int_throttle_ceil);
540 if (throttle == 0) {
5330213c
SZ		 541 sc->int_throttle_ceil = 0;
542 } else {
5330213c
SZ		 543 if (throttle < 0)
544 throttle = EMX_DEFAULT_ITR;
545
546 /* Recalculate the tunable value to get the exact frequency. */
547 throttle = 1000000000 / 256 / throttle;
548
549 /* Upper 16bits of ITR is reserved and should be zero */
550 if (throttle & 0xffff0000)
551 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
552
553 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
554 }
555
556 e1000_init_script_state_82541(&sc->hw, TRUE);
557 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
558
559 /* Copper options */
560 if (sc->hw.phy.media_type == e1000_media_type_copper) {
561 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
562 sc->hw.phy.disable_polarity_correction = FALSE;
563 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
564 }
565
566 /* Set the frame limits assuming standard ethernet sized frames. */
567 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
568 sc->min_frame_size = ETHER_MIN_LEN;
569
570 /* This controls when hardware reports transmit completion status. */
571 sc->hw.mac.report_tx_early = 1;
572
65c7a6af 573 /* Calculate # of RX rings */
724cbff8 574 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 575 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 576
071699f8
SZ		 577 /* Allocate RX/TX rings' busdma(9) stuffs */
578 error = emx_dma_alloc(sc);
579 if (error)
e5b3bcc4 580 goto fail;
e5b3bcc4 581
2d0e5700
SZ		 582 /* Allocate multicast array memory. */
583 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
584 M_DEVBUF, M_WAITOK);
585
586 /* Indicate SOL/IDER usage */
587 if (e1000_check_reset_block(&sc->hw)) {
588 device_printf(dev,
589 "PHY reset is blocked due to SOL/IDER session.\n");
590 }
591
592 /*
593 * Start from a known state, this is important in reading the
594 * nvm and mac from that.
595 */
596 e1000_reset_hw(&sc->hw);
597
5330213c
SZ		 598 /* Make sure we have a good EEPROM before we read from it */
599 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
600 /*
601 * Some PCI-E parts fail the first check due to
602 * the link being in sleep state, call it again,
603 * if it fails a second time its a real issue.
604 */
605 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
606 device_printf(dev,
607 "The EEPROM Checksum Is Not Valid\n");
608 error = EIO;
609 goto fail;
610 }
611 }
612
5330213c
SZ		 613 /* Copy the permanent MAC address out of the EEPROM */
614 if (e1000_read_mac_addr(&sc->hw) < 0) {
615 device_printf(dev, "EEPROM read error while reading MAC"
616 " address\n");
617 error = EIO;
618 goto fail;
619 }
620 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
621 device_printf(dev, "Invalid MAC address\n");
622 error = EIO;
623 goto fail;
624 }
625
5330213c
SZ		 626 /* Determine if we have to control management hardware */
627 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
628
629 /*
630 * Setup Wake-on-Lan
631 */
2d0e5700
SZ		 632 apme_mask = EMX_EEPROM_APME;
633 eeprom_data = 0;
5330213c 634 switch (sc->hw.mac.type) {
2d0e5700
SZ		 635 case e1000_82573:
636 sc->has_amt = 1;
637 /* FALL THROUGH */
638
5330213c 639 case e1000_82571:
2d0e5700 640 case e1000_82572:
5330213c
SZ		 641 case e1000_80003es2lan:
642 if (sc->hw.bus.func == 1) {
643 e1000_read_nvm(&sc->hw,
644 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
645 } else {
646 e1000_read_nvm(&sc->hw,
647 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
648 }
5330213c
SZ		 649 break;
650
651 default:
2d0e5700
SZ		 652 e1000_read_nvm(&sc->hw,
653 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ		 654 break;
655 }
2d0e5700
SZ		 656 if (eeprom_data & apme_mask)
657 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
658
5330213c
SZ		 659 /*
660 * We have the eeprom settings, now apply the special cases
661 * where the eeprom may be wrong or the board won't support
662 * wake on lan on a particular port
663 */
664 device_id = pci_get_device(dev);
665 switch (device_id) {
666 case E1000_DEV_ID_82571EB_FIBER:
667 /*
668 * Wake events only supported on port A for dual fiber
669 * regardless of eeprom setting
670 */
671 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
672 E1000_STATUS_FUNC_1)
673 sc->wol = 0;
674 break;
675
676 case E1000_DEV_ID_82571EB_QUAD_COPPER:
677 case E1000_DEV_ID_82571EB_QUAD_FIBER:
678 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
679 /* if quad port sc, disable WoL on all but port A */
680 if (emx_global_quad_port_a != 0)
681 sc->wol = 0;
682 /* Reset for multiple quad port adapters */
683 if (++emx_global_quad_port_a == 4)
684 emx_global_quad_port_a = 0;
685 break;
686 }
687
688 /* XXX disable wol */
689 sc->wol = 0;
690
2d0e5700
SZ		 691 /* Setup OS specific network interface */
692 emx_setup_ifp(sc);
693
694 /* Add sysctl tree, must after em_setup_ifp() */
695 emx_add_sysctl(sc);
696
697 /* Reset the hardware */
698 error = emx_reset(sc);
699 if (error) {
700 device_printf(dev, "Unable to reset the hardware\n");
701 goto fail;
702 }
703
704 /* Initialize statistics */
705 emx_update_stats(sc);
706
707 sc->hw.mac.get_link_status = 1;
708 emx_update_link_status(sc);
709
5330213c
SZ		 710 sc->spare_tx_desc = EMX_TX_SPARE;
711
712 /*
713 * Keep following relationship between spare_tx_desc, oact_tx_desc
714 * and tx_int_nsegs:
715 * (spare_tx_desc + EMX_TX_RESERVED) <=
716 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
717 */
718 sc->oact_tx_desc = sc->num_tx_desc / 8;
719 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
720 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
721 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
722 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
723
724 sc->tx_int_nsegs = sc->num_tx_desc / 16;
725 if (sc->tx_int_nsegs < sc->oact_tx_desc)
726 sc->tx_int_nsegs = sc->oact_tx_desc;
727
2d0e5700
SZ		 728 /* Non-AMT based hardware can now take control from firmware */
729 if (sc->has_manage && !sc->has_amt)
730 emx_get_hw_control(sc);
731
4cb541ae
SZ		 732 /*
733 * Missing Interrupt Following ICR read:
734 *
a835687d
SZ		 735 * 82571/82572 specification update errata #76
736 * 82573 specification update errata #31
737 * 82574 specification update errata #12
4cb541ae
SZ		 738 */
739 intr_func = emx_intr;
740 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
741 (sc->hw.mac.type == e1000_82571 ||
742 sc->hw.mac.type == e1000_82572 ||
743 sc->hw.mac.type == e1000_82573 ||
744 sc->hw.mac.type == e1000_82574))
745 intr_func = emx_intr_mask;
746
747 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 748 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ		 749 if (error) {
750 device_printf(dev, "Failed to register interrupt handler");
751 ether_ifdetach(&sc->arpcom.ac_if);
752 goto fail;
753 }
754
704b6287 755 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ		 756 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
757 return (0);
758fail:
759 emx_detach(dev);
760 return (error);
761}
762
763static int
764emx_detach(device_t dev)
765{
766 struct emx_softc *sc = device_get_softc(dev);
767
768 if (device_is_attached(dev)) {
769 struct ifnet *ifp = &sc->arpcom.ac_if;
770
6d435846 771 ifnet_serialize_all(ifp);
5330213c
SZ		 772
773 emx_stop(sc);
774
775 e1000_phy_hw_reset(&sc->hw);
776
777 emx_rel_mgmt(sc);
2d0e5700 778 emx_rel_hw_control(sc);
5330213c
SZ		 779
780 if (sc->wol) {
781 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
782 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
783 emx_enable_wol(dev);
784 }
785
786 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
787
6d435846 788 ifnet_deserialize_all(ifp);
5330213c
SZ		 789
790 ether_ifdetach(ifp);
2d0e5700
SZ		 791 } else {
792 emx_rel_hw_control(sc);
5330213c
SZ		 793 }
794 bus_generic_detach(dev);
795
796 if (sc->intr_res != NULL) {
797 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
798 sc->intr_res);
799 }
800
7fb43956 801 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ		 802 pci_release_msi(dev);
803
5330213c
SZ		 804 if (sc->memory != NULL) {
805 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
806 sc->memory);
807 }
808
071699f8 809 emx_dma_free(sc);
5330213c
SZ		 810
811 /* Free sysctl tree */
812 if (sc->sysctl_tree != NULL)
813 sysctl_ctx_free(&sc->sysctl_ctx);
814
815 return (0);
816}
817
818static int
819emx_shutdown(device_t dev)
820{
821 return emx_suspend(dev);
822}
823
824static int
825emx_suspend(device_t dev)
826{
827 struct emx_softc *sc = device_get_softc(dev);
828 struct ifnet *ifp = &sc->arpcom.ac_if;
829
6d435846 830 ifnet_serialize_all(ifp);
5330213c
SZ		 831
832 emx_stop(sc);
833
834 emx_rel_mgmt(sc);
2d0e5700 835 emx_rel_hw_control(sc);
5330213c 836
2d0e5700 837 if (sc->wol) {
5330213c
SZ		 838 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
839 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
840 emx_enable_wol(dev);
2d0e5700 841 }
5330213c 842
6d435846 843 ifnet_deserialize_all(ifp);
5330213c
SZ		 844
845 return bus_generic_suspend(dev);
846}
847
848static int
849emx_resume(device_t dev)
850{
851 struct emx_softc *sc = device_get_softc(dev);
852 struct ifnet *ifp = &sc->arpcom.ac_if;
853
6d435846 854 ifnet_serialize_all(ifp);
5330213c
SZ		 855
856 emx_init(sc);
857 emx_get_mgmt(sc);
858 if_devstart(ifp);
859
6d435846 860 ifnet_deserialize_all(ifp);
5330213c
SZ		 861
862 return bus_generic_resume(dev);
863}
864
865static void
866emx_start(struct ifnet *ifp)
867{
868 struct emx_softc *sc = ifp->if_softc;
869 struct mbuf *m_head;
870
6d435846 871 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ		 872
873 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
874 return;
875
876 if (!sc->link_active) {
877 ifq_purge(&ifp->if_snd);
878 return;
879 }
880
881 while (!ifq_is_empty(&ifp->if_snd)) {
882 /* Now do we at least have a minimal? */
883 if (EMX_IS_OACTIVE(sc)) {
884 emx_tx_collect(sc);
885 if (EMX_IS_OACTIVE(sc)) {
886 ifp->if_flags |= IFF_OACTIVE;
887 sc->no_tx_desc_avail1++;
888 break;
889 }
890 }
891
892 logif(pkt_txqueue);
893 m_head = ifq_dequeue(&ifp->if_snd, NULL);
894 if (m_head == NULL)
895 break;
896
897 if (emx_encap(sc, &m_head)) {
898 ifp->if_oerrors++;
899 emx_tx_collect(sc);
900 continue;
901 }
902
903 /* Send a copy of the frame to the BPF listener */
904 ETHER_BPF_MTAP(ifp, m_head);
905
906 /* Set timeout in case hardware has problems transmitting. */
907 ifp->if_timer = EMX_TX_TIMEOUT;
908 }
909}
910
911static int
912emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
913{
914 struct emx_softc *sc = ifp->if_softc;
915 struct ifreq *ifr = (struct ifreq *)data;
916 uint16_t eeprom_data = 0;
917 int max_frame_size, mask, reinit;
918 int error = 0;
919
2c9effcf 920 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 921
922 switch (command) {
923 case SIOCSIFMTU:
924 switch (sc->hw.mac.type) {
925 case e1000_82573:
926 /*
927 * 82573 only supports jumbo frames
928 * if ASPM is disabled.
929 */
930 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
931 &eeprom_data);
932 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
933 max_frame_size = ETHER_MAX_LEN;
934 break;
935 }
936 /* FALL THROUGH */
937
938 /* Limit Jumbo Frame size */
939 case e1000_82571:
940 case e1000_82572:
941 case e1000_82574:
942 case e1000_80003es2lan:
943 max_frame_size = 9234;
944 break;
945
946 default:
947 max_frame_size = MAX_JUMBO_FRAME_SIZE;
948 break;
949 }
950 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
951 ETHER_CRC_LEN) {
952 error = EINVAL;
953 break;
954 }
955
956 ifp->if_mtu = ifr->ifr_mtu;
957 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
958 ETHER_CRC_LEN;
959
960 if (ifp->if_flags & IFF_RUNNING)
961 emx_init(sc);
962 break;
963
964 case SIOCSIFFLAGS:
965 if (ifp->if_flags & IFF_UP) {
966 if ((ifp->if_flags & IFF_RUNNING)) {
967 if ((ifp->if_flags ^ sc->if_flags) &
968 (IFF_PROMISC | IFF_ALLMULTI)) {
969 emx_disable_promisc(sc);
970 emx_set_promisc(sc);
971 }
972 } else {
973 emx_init(sc);
974 }
975 } else if (ifp->if_flags & IFF_RUNNING) {
976 emx_stop(sc);
977 }
978 sc->if_flags = ifp->if_flags;
979 break;
980
981 case SIOCADDMULTI:
982 case SIOCDELMULTI:
983 if (ifp->if_flags & IFF_RUNNING) {
984 emx_disable_intr(sc);
985 emx_set_multi(sc);
b3a7093f
SZ		 986#ifdef IFPOLL_ENABLE
987 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ		 988#endif
989 emx_enable_intr(sc);
990 }
991 break;
992
993 case SIOCSIFMEDIA:
994 /* Check SOL/IDER usage */
995 if (e1000_check_reset_block(&sc->hw)) {
996 device_printf(sc->dev, "Media change is"
997 " blocked due to SOL/IDER session.\n");
998 break;
999 }
1000 /* FALL THROUGH */
1001
1002 case SIOCGIFMEDIA:
1003 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1004 break;
1005
1006 case SIOCSIFCAP:
1007 reinit = 0;
1008 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3eb0ea09
SZ		 1009 if (mask & IFCAP_RXCSUM) {
1010 ifp->if_capenable ^= IFCAP_RXCSUM;
5330213c
SZ		 1011 reinit = 1;
1012 }
1013 if (mask & IFCAP_VLAN_HWTAGGING) {
1014 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1015 reinit = 1;
1016 }
3eb0ea09
SZ		 1017 if (mask & IFCAP_TXCSUM) {
1018 ifp->if_capenable ^= IFCAP_TXCSUM;
1019 if (ifp->if_capenable & IFCAP_TXCSUM)
1020 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1021 else
1022 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1023 }
1024 if (mask & IFCAP_TSO) {
1025 ifp->if_capenable ^= IFCAP_TSO;
1026 if (ifp->if_capenable & IFCAP_TSO)
1027 ifp->if_hwassist |= CSUM_TSO;
1028 else
1029 ifp->if_hwassist &= ~CSUM_TSO;
1030 }
13890b61 1031 if (mask & IFCAP_RSS)
8434a83b 1032 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ		 1033 if (reinit && (ifp->if_flags & IFF_RUNNING))
1034 emx_init(sc);
1035 break;
1036
1037 default:
1038 error = ether_ioctl(ifp, command, data);
1039 break;
1040 }
1041 return (error);
1042}
1043
1044static void
1045emx_watchdog(struct ifnet *ifp)
1046{
1047 struct emx_softc *sc = ifp->if_softc;
1048
2c9effcf 1049 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1050
1051 /*
1052 * The timer is set to 5 every time start queues a packet.
1053 * Then txeof keeps resetting it as long as it cleans at
1054 * least one descriptor.
1055 * Finally, anytime all descriptors are clean the timer is
1056 * set to 0.
1057 */
1058
1059 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1060 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1061 /*
1062 * If we reach here, all TX jobs are completed and
1063 * the TX engine should have been idled for some time.
1064 * We don't need to call if_devstart() here.
1065 */
1066 ifp->if_flags &= ~IFF_OACTIVE;
1067 ifp->if_timer = 0;
1068 return;
1069 }
1070
1071 /*
1072 * If we are in this routine because of pause frames, then
1073 * don't reset the hardware.
1074 */
1075 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1076 ifp->if_timer = EMX_TX_TIMEOUT;
1077 return;
1078 }
1079
1080 if (e1000_check_for_link(&sc->hw) == 0)
1081 if_printf(ifp, "watchdog timeout -- resetting\n");
1082
1083 ifp->if_oerrors++;
1084 sc->watchdog_events++;
1085
1086 emx_init(sc);
1087
1088 if (!ifq_is_empty(&ifp->if_snd))
1089 if_devstart(ifp);
1090}
1091
1092static void
1093emx_init(void *xsc)
1094{
1095 struct emx_softc *sc = xsc;
1096 struct ifnet *ifp = &sc->arpcom.ac_if;
1097 device_t dev = sc->dev;
1098 uint32_t pba;
3f939c23 1099 int i;
5330213c 1100
2c9effcf 1101 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1102
1103 emx_stop(sc);
1104
1105 /*
1106 * Packet Buffer Allocation (PBA)
1107 * Writing PBA sets the receive portion of the buffer
1108 * the remainder is used for the transmit buffer.
1109 */
1110 switch (sc->hw.mac.type) {
1111 /* Total Packet Buffer on these is 48K */
1112 case e1000_82571:
1113 case e1000_82572:
1114 case e1000_80003es2lan:
1115 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1116 break;
1117
1118 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1119 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1120 break;
1121
1122 case e1000_82574:
1123 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1124 break;
1125
1126 default:
1127 /* Devices before 82547 had a Packet Buffer of 64K. */
1128 if (sc->max_frame_size > 8192)
1129 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1130 else
1131 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1132 }
1133 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1134
1135 /* Get the latest mac address, User can use a LAA */
1136 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1137
1138 /* Put the address into the Receive Address Array */
1139 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1140
1141 /*
1142 * With the 82571 sc, RAR[0] may be overwritten
1143 * when the other port is reset, we make a duplicate
1144 * in RAR[14] for that eventuality, this assures
1145 * the interface continues to function.
1146 */
1147 if (sc->hw.mac.type == e1000_82571) {
1148 e1000_set_laa_state_82571(&sc->hw, TRUE);
1149 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1150 E1000_RAR_ENTRIES - 1);
1151 }
1152
1153 /* Initialize the hardware */
2d0e5700
SZ		 1154 if (emx_reset(sc)) {
1155 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ		 1156 /* XXX emx_stop()? */
1157 return;
1158 }
1159 emx_update_link_status(sc);
1160
1161 /* Setup VLAN support, basic and offload if available */
1162 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1163
1164 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1165 uint32_t ctrl;
1166
1167 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1168 ctrl |= E1000_CTRL_VME;
1169 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1170 }
1171
5330213c
SZ		 1172 /* Configure for OS presence */
1173 emx_get_mgmt(sc);
1174
1175 /* Prepare transmit descriptors and buffers */
1176 emx_init_tx_ring(sc);
1177 emx_init_tx_unit(sc);
1178
1179 /* Setup Multicast table */
1180 emx_set_multi(sc);
1181
1182 /* Prepare receive descriptors and buffers */
13890b61 1183 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 1184 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1185 device_printf(dev,
1186 "Could not setup receive structures\n");
1187 emx_stop(sc);
1188 return;
1189 }
5330213c
SZ		 1190 }
1191 emx_init_rx_unit(sc);
1192
1193 /* Don't lose promiscuous settings */
1194 emx_set_promisc(sc);
1195
1196 ifp->if_flags |= IFF_RUNNING;
1197 ifp->if_flags &= ~IFF_OACTIVE;
1198
1199 callout_reset(&sc->timer, hz, emx_timer, sc);
1200 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1201
1202 /* MSI/X configuration for 82574 */
1203 if (sc->hw.mac.type == e1000_82574) {
1204 int tmp;
1205
1206 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1207 tmp |= E1000_CTRL_EXT_PBA_CLR;
1208 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1209 /*
2d0e5700 1210 * XXX MSIX
5330213c
SZ		 1211 * Set the IVAR - interrupt vector routing.
1212 * Each nibble represents a vector, high bit
1213 * is enable, other 3 bits are the MSIX table
1214 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1215 * Link (other) to 2, hence the magic number.
1216 */
1217 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1218 }
1219
b3a7093f 1220#ifdef IFPOLL_ENABLE
5330213c
SZ		 1221 /*
1222 * Only enable interrupts if we are not polling, make sure
1223 * they are off otherwise.
1224 */
b3a7093f 1225 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ		 1226 emx_disable_intr(sc);
1227 else
b3a7093f 1228#endif /* IFPOLL_ENABLE */
5330213c
SZ		 1229 emx_enable_intr(sc);
1230
2d0e5700
SZ		 1231 /* AMT based hardware can now take control from firmware */
1232 if (sc->has_manage && sc->has_amt)
1233 emx_get_hw_control(sc);
1234
5330213c
SZ		 1235 /* Don't reset the phy next time init gets called */
1236 sc->hw.phy.reset_disable = TRUE;
1237}
1238
5330213c
SZ		 1239static void
1240emx_intr(void *xsc)
1241{
4cb541ae
SZ		 1242 emx_intr_body(xsc, TRUE);
1243}
1244
1245static void
1246emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1247{
5330213c
SZ		 1248 struct ifnet *ifp = &sc->arpcom.ac_if;
1249 uint32_t reg_icr;
1250
1251 logif(intr_beg);
6d435846 1252 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ		 1253
1254 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1255
4cb541ae 1256 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ		 1257 logif(intr_end);
1258 return;
1259 }
1260
1261 /*
1262 * XXX: some laptops trigger several spurious interrupts
df50f778 1263 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ		 1264 * reports all-ones value in this case. Processing such
1265 * interrupts would lead to a freeze. I don't know why.
1266 */
1267 if (reg_icr == 0xffffffff) {
1268 logif(intr_end);
1269 return;
1270 }
1271
1272 if (ifp->if_flags & IFF_RUNNING) {
1273 if (reg_icr &
3f939c23
SZ		 1274 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1275 int i;
1276
13890b61 1277 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ		 1278 lwkt_serialize_enter(
1279 &sc->rx_data[i].rx_serialize);
3f939c23 1280 emx_rxeof(sc, i, -1);
6d435846
SZ		 1281 lwkt_serialize_exit(
1282 &sc->rx_data[i].rx_serialize);
1283 }
3f939c23 1284 }
6446af7b 1285 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1286 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ		 1287 emx_txeof(sc);
1288 if (!ifq_is_empty(&ifp->if_snd))
1289 if_devstart(ifp);
6d435846 1290 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ		 1291 }
1292 }
1293
1294 /* Link status change */
1295 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1296 emx_serialize_skipmain(sc);
6d435846 1297
5330213c
SZ		 1298 callout_stop(&sc->timer);
1299 sc->hw.mac.get_link_status = 1;
1300 emx_update_link_status(sc);
1301
1302 /* Deal with TX cruft when link lost */
1303 emx_tx_purge(sc);
1304
1305 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1306
bca7c435 1307 emx_deserialize_skipmain(sc);
5330213c
SZ		 1308 }
1309
1310 if (reg_icr & E1000_ICR_RXO)
1311 sc->rx_overruns++;
1312
1313 logif(intr_end);
1314}
1315
1316static void
4cb541ae
SZ		 1317emx_intr_mask(void *xsc)
1318{
1319 struct emx_softc *sc = xsc;
1320
1321 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1322 /*
1323 * NOTE:
1324 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1325 * so don't check it.
1326 */
1327 emx_intr_body(sc, FALSE);
1328 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1329}
1330
1331static void
5330213c
SZ		 1332emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1333{
1334 struct emx_softc *sc = ifp->if_softc;
1335
2c9effcf 1336 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1337
1338 emx_update_link_status(sc);
1339
1340 ifmr->ifm_status = IFM_AVALID;
1341 ifmr->ifm_active = IFM_ETHER;
1342
1343 if (!sc->link_active)
1344 return;
1345
1346 ifmr->ifm_status |= IFM_ACTIVE;
1347
1348 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1349 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1350 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1351 } else {
1352 switch (sc->link_speed) {
1353 case 10:
1354 ifmr->ifm_active |= IFM_10_T;
1355 break;
1356 case 100:
1357 ifmr->ifm_active |= IFM_100_TX;
1358 break;
1359
1360 case 1000:
1361 ifmr->ifm_active |= IFM_1000_T;
1362 break;
1363 }
1364 if (sc->link_duplex == FULL_DUPLEX)
1365 ifmr->ifm_active |= IFM_FDX;
1366 else
1367 ifmr->ifm_active |= IFM_HDX;
1368 }
1369}
1370
1371static int
1372emx_media_change(struct ifnet *ifp)
1373{
1374 struct emx_softc *sc = ifp->if_softc;
1375 struct ifmedia *ifm = &sc->media;
1376
2c9effcf 1377 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1378
1379 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1380 return (EINVAL);
1381
1382 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1383 case IFM_AUTO:
1384 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1385 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1386 break;
1387
1388 case IFM_1000_LX:
1389 case IFM_1000_SX:
1390 case IFM_1000_T:
1391 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1392 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1393 break;
1394
1395 case IFM_100_TX:
1396 sc->hw.mac.autoneg = FALSE;
1397 sc->hw.phy.autoneg_advertised = 0;
1398 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1399 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1400 else
1401 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1402 break;
1403
1404 case IFM_10_T:
1405 sc->hw.mac.autoneg = FALSE;
1406 sc->hw.phy.autoneg_advertised = 0;
1407 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1408 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1409 else
1410 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1411 break;
1412
1413 default:
1414 if_printf(ifp, "Unsupported media type\n");
1415 break;
1416 }
1417
1418 /*
1419 * As the speed/duplex settings my have changed we need to
1420 * reset the PHY.
1421 */
1422 sc->hw.phy.reset_disable = FALSE;
1423
1424 emx_init(sc);
1425
1426 return (0);
1427}
1428
1429static int
1430emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1431{
1432 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1433 bus_dmamap_t map;
323e5ecd 1434 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ		 1435 struct e1000_tx_desc *ctxd = NULL;
1436 struct mbuf *m_head = *m_headp;
1437 uint32_t txd_upper, txd_lower, cmd = 0;
1438 int maxsegs, nsegs, i, j, first, last = 0, error;
1439
3eb0ea09
SZ		 1440 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1441 error = emx_tso_pullup(sc, m_headp);
1442 if (error)
1443 return error;
1444 m_head = *m_headp;
1445 }
1446
5330213c
SZ		 1447 txd_upper = txd_lower = 0;
1448
1449 /*
1450 * Capture the first descriptor index, this descriptor
1451 * will have the index of the EOP which is the only one
1452 * that now gets a DONE bit writeback.
1453 */
1454 first = sc->next_avail_tx_desc;
323e5ecd 1455 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 1456 tx_buffer_mapped = tx_buffer;
1457 map = tx_buffer->map;
1458
1459 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1460 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ		 1461 if (maxsegs > EMX_MAX_SCATTER)
1462 maxsegs = EMX_MAX_SCATTER;
1463
1464 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1465 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1466 if (error) {
1467 if (error == ENOBUFS)
1468 sc->mbuf_alloc_failed++;
1469 else
1470 sc->no_tx_dma_setup++;
1471
1472 m_freem(*m_headp);
1473 *m_headp = NULL;
1474 return error;
1475 }
1476 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1477
1478 m_head = *m_headp;
1479 sc->tx_nsegs += nsegs;
1480
3eb0ea09
SZ		 1481 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1482 /* TSO will consume one TX desc */
1483 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1484 &txd_upper, &txd_lower);
1485 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
5330213c
SZ		 1486 /* TX csum offloading will consume one TX desc */
1487 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1488 }
1489 i = sc->next_avail_tx_desc;
1490
1491 /* Set up our transmit descriptors */
1492 for (j = 0; j < nsegs; j++) {
323e5ecd 1493 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 1494 ctxd = &sc->tx_desc_base[i];
1495
1496 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1497 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1498 txd_lower | segs[j].ds_len);
1499 ctxd->upper.data = htole32(txd_upper);
1500
1501 last = i;
1502 if (++i == sc->num_tx_desc)
1503 i = 0;
5330213c
SZ		 1504 }
1505
1506 sc->next_avail_tx_desc = i;
1507
1508 KKASSERT(sc->num_tx_desc_avail > nsegs);
1509 sc->num_tx_desc_avail -= nsegs;
1510
1511 /* Handle VLAN tag */
1512 if (m_head->m_flags & M_VLANTAG) {
1513 /* Set the vlan id. */
1514 ctxd->upper.fields.special =
1515 htole16(m_head->m_pkthdr.ether_vlantag);
1516
1517 /* Tell hardware to add tag */
1518 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1519 }
1520
1521 tx_buffer->m_head = m_head;
1522 tx_buffer_mapped->map = tx_buffer->map;
1523 tx_buffer->map = map;
1524
1525 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1526 sc->tx_nsegs = 0;
4e4e8481
SZ		 1527
1528 /*
1529 * Report Status (RS) is turned on
1530 * every tx_int_nsegs descriptors.
1531 */
5330213c
SZ		 1532 cmd = E1000_TXD_CMD_RS;
1533
b4b0a2b4
SZ		 1534 /*
1535 * Keep track of the descriptor, which will
1536 * be written back by hardware.
1537 */
5330213c
SZ		 1538 sc->tx_dd[sc->tx_dd_tail] = last;
1539 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1540 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1541 }
1542
1543 /*
1544 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ		 1545 */
1546 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1547
1548 /*
5330213c
SZ		 1549 * Advance the Transmit Descriptor Tail (TDT), this tells
1550 * the E1000 that this frame is available to transmit.
1551 */
1552 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1553
1554 return (0);
1555}
1556
1557static void
1558emx_set_promisc(struct emx_softc *sc)
1559{
1560 struct ifnet *ifp = &sc->arpcom.ac_if;
1561 uint32_t reg_rctl;
1562
1563 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1564
1565 if (ifp->if_flags & IFF_PROMISC) {
1566 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1567 /* Turn this on if you want to see bad packets */
1568 if (emx_debug_sbp)
1569 reg_rctl |= E1000_RCTL_SBP;
1570 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1571 } else if (ifp->if_flags & IFF_ALLMULTI) {
1572 reg_rctl |= E1000_RCTL_MPE;
1573 reg_rctl &= ~E1000_RCTL_UPE;
1574 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1575 }
1576}
1577
1578static void
1579emx_disable_promisc(struct emx_softc *sc)
1580{
1581 uint32_t reg_rctl;
1582
1583 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1584
1585 reg_rctl &= ~E1000_RCTL_UPE;
1586 reg_rctl &= ~E1000_RCTL_MPE;
1587 reg_rctl &= ~E1000_RCTL_SBP;
1588 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1589}
1590
1591static void
1592emx_set_multi(struct emx_softc *sc)
1593{
1594 struct ifnet *ifp = &sc->arpcom.ac_if;
1595 struct ifmultiaddr *ifma;
1596 uint32_t reg_rctl = 0;
2d0e5700 1597 uint8_t *mta;
5330213c
SZ		 1598 int mcnt = 0;
1599
2d0e5700
SZ		 1600 mta = sc->mta;
1601 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1602
441d34b2 1603 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ		 1604 if (ifma->ifma_addr->sa_family != AF_LINK)
1605 continue;
1606
1607 if (mcnt == EMX_MCAST_ADDR_MAX)
1608 break;
1609
1610 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1611 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1612 mcnt++;
1613 }
1614
1615 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1616 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1617 reg_rctl |= E1000_RCTL_MPE;
1618 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1619 } else {
6a5a645e 1620 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ		 1621 }
1622}
1623
1624/*
1625 * This routine checks for link status and updates statistics.
1626 */
1627static void
1628emx_timer(void *xsc)
1629{
1630 struct emx_softc *sc = xsc;
1631 struct ifnet *ifp = &sc->arpcom.ac_if;
1632
6d435846 1633 ifnet_serialize_all(ifp);
5330213c
SZ		 1634
1635 emx_update_link_status(sc);
1636 emx_update_stats(sc);
1637
1638 /* Reset LAA into RAR[0] on 82571 */
1639 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1640 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1641
1642 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1643 emx_print_hw_stats(sc);
1644
1645 emx_smartspeed(sc);
1646
1647 callout_reset(&sc->timer, hz, emx_timer, sc);
1648
6d435846 1649 ifnet_deserialize_all(ifp);
5330213c
SZ		 1650}
1651
1652static void
1653emx_update_link_status(struct emx_softc *sc)
1654{
1655 struct e1000_hw *hw = &sc->hw;
1656 struct ifnet *ifp = &sc->arpcom.ac_if;
1657 device_t dev = sc->dev;
1658 uint32_t link_check = 0;
1659
1660 /* Get the cached link value or read phy for real */
1661 switch (hw->phy.media_type) {
1662 case e1000_media_type_copper:
1663 if (hw->mac.get_link_status) {
1664 /* Do the work to read phy */
1665 e1000_check_for_link(hw);
1666 link_check = !hw->mac.get_link_status;
1667 if (link_check) /* ESB2 fix */
1668 e1000_cfg_on_link_up(hw);
1669 } else {
1670 link_check = TRUE;
1671 }
1672 break;
1673
1674 case e1000_media_type_fiber:
1675 e1000_check_for_link(hw);
1676 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1677 break;
1678
1679 case e1000_media_type_internal_serdes:
1680 e1000_check_for_link(hw);
1681 link_check = sc->hw.mac.serdes_has_link;
1682 break;
1683
1684 case e1000_media_type_unknown:
1685 default:
1686 break;
1687 }
1688
1689 /* Now check for a transition */
1690 if (link_check && sc->link_active == 0) {
1691 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1692 &sc->link_duplex);
1693
1694 /*
1695 * Check if we should enable/disable SPEED_MODE bit on
1696 * 82571EB/82572EI
1697 */
2d0e5700
SZ		 1698 if (sc->link_speed != SPEED_1000 &&
1699 (hw->mac.type == e1000_82571 ||
1700 hw->mac.type == e1000_82572)) {
5330213c
SZ		 1701 int tarc0;
1702
1703 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1704 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ		 1705 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1706 }
1707 if (bootverbose) {
1708 device_printf(dev, "Link is up %d Mbps %s\n",
1709 sc->link_speed,
1710 ((sc->link_duplex == FULL_DUPLEX) ?
1711 "Full Duplex" : "Half Duplex"));
1712 }
1713 sc->link_active = 1;
1714 sc->smartspeed = 0;
1715 ifp->if_baudrate = sc->link_speed * 1000000;
1716 ifp->if_link_state = LINK_STATE_UP;
1717 if_link_state_change(ifp);
1718 } else if (!link_check && sc->link_active == 1) {
1719 ifp->if_baudrate = sc->link_speed = 0;
1720 sc->link_duplex = 0;
1721 if (bootverbose)
1722 device_printf(dev, "Link is Down\n");
1723 sc->link_active = 0;
1724#if 0
1725 /* Link down, disable watchdog */
1726 if->if_timer = 0;
1727#endif
1728 ifp->if_link_state = LINK_STATE_DOWN;
1729 if_link_state_change(ifp);
1730 }
1731}
1732
1733static void
1734emx_stop(struct emx_softc *sc)
1735{
1736 struct ifnet *ifp = &sc->arpcom.ac_if;
1737 int i;
1738
2c9effcf 1739 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1740
1741 emx_disable_intr(sc);
1742
1743 callout_stop(&sc->timer);
1744
1745 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1746 ifp->if_timer = 0;
1747
3f939c23
SZ		 1748 /*
1749 * Disable multiple receive queues.
1750 *
1751 * NOTE:
1752 * We should disable multiple receive queues before
1753 * resetting the hardware.
1754 */
1755 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1756
5330213c
SZ		 1757 e1000_reset_hw(&sc->hw);
1758 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1759
1760 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1761 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 1762
1763 if (tx_buffer->m_head != NULL) {
1764 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1765 m_freem(tx_buffer->m_head);
1766 tx_buffer->m_head = NULL;
1767 }
1768 }
1769
13890b61 1770 for (i = 0; i < sc->rx_ring_cnt; ++i)
3f939c23 1771 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ		 1772
1773 sc->csum_flags = 0;
3eb0ea09 1774 sc->csum_lhlen = 0;
5330213c 1775 sc->csum_iphlen = 0;
3eb0ea09
SZ		 1776 sc->csum_thlen = 0;
1777 sc->csum_mss = 0;
1778 sc->csum_pktlen = 0;
5330213c
SZ		 1779
1780 sc->tx_dd_head = 0;
1781 sc->tx_dd_tail = 0;
1782 sc->tx_nsegs = 0;
1783}
1784
1785static int
2d0e5700 1786emx_reset(struct emx_softc *sc)
5330213c
SZ		 1787{
1788 device_t dev = sc->dev;
1789 uint16_t rx_buffer_size;
1790
5330213c
SZ		 1791 /* Set up smart power down as default off on newer adapters. */
1792 if (!emx_smart_pwr_down &&
1793 (sc->hw.mac.type == e1000_82571 ||
1794 sc->hw.mac.type == e1000_82572)) {
1795 uint16_t phy_tmp = 0;
1796
1797 /* Speed up time to link by disabling smart power down. */
1798 e1000_read_phy_reg(&sc->hw,
1799 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1800 phy_tmp &= ~IGP02E1000_PM_SPD;
1801 e1000_write_phy_reg(&sc->hw,
1802 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1803 }
1804
1805 /*
1806 * These parameters control the automatic generation (Tx) and
1807 * response (Rx) to Ethernet PAUSE frames.
1808 * - High water mark should allow for at least two frames to be
1809 * received after sending an XOFF.
1810 * - Low water mark works best when it is very near the high water mark.
1811 * This allows the receiver to restart by sending XON when it has
1812 * drained a bit. Here we use an arbitary value of 1500 which will
1813 * restart after one full frame is pulled from the buffer. There
1814 * could be several smaller frames in the buffer and if so they will
1815 * not trigger the XON until their total number reduces the buffer
1816 * by 1500.
1817 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1818 */
1819 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1820
1821 sc->hw.fc.high_water = rx_buffer_size -
1822 roundup2(sc->max_frame_size, 1024);
1823 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1824
1825 if (sc->hw.mac.type == e1000_80003es2lan)
1826 sc->hw.fc.pause_time = 0xFFFF;
1827 else
1828 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1829 sc->hw.fc.send_xon = TRUE;
1830 sc->hw.fc.requested_mode = e1000_fc_full;
1831
2d0e5700
SZ		 1832 /* Issue a global reset */
1833 e1000_reset_hw(&sc->hw);
1834 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1835 emx_disable_aspm(sc);
2d0e5700 1836
5330213c
SZ		 1837 if (e1000_init_hw(&sc->hw) < 0) {
1838 device_printf(dev, "Hardware Initialization Failed\n");
1839 return (EIO);
1840 }
1841
2d0e5700
SZ		 1842 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1843 e1000_get_phy_info(&sc->hw);
5330213c
SZ		 1844 e1000_check_for_link(&sc->hw);
1845
1846 return (0);
1847}
1848
1849static void
1850emx_setup_ifp(struct emx_softc *sc)
1851{
1852 struct ifnet *ifp = &sc->arpcom.ac_if;
1853
1854 if_initname(ifp, device_get_name(sc->dev),
1855 device_get_unit(sc->dev));
1856 ifp->if_softc = sc;
1857 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1858 ifp->if_init = emx_init;
1859 ifp->if_ioctl = emx_ioctl;
1860 ifp->if_start = emx_start;
b3a7093f
SZ		 1861#ifdef IFPOLL_ENABLE
1862 ifp->if_qpoll = emx_qpoll;
5330213c
SZ		 1863#endif
1864 ifp->if_watchdog = emx_watchdog;
6d435846
SZ		 1865 ifp->if_serialize = emx_serialize;
1866 ifp->if_deserialize = emx_deserialize;
1867 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ		 1868#ifdef INVARIANTS
1869 ifp->if_serialize_assert = emx_serialize_assert;
1870#endif
5330213c
SZ		 1871 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1872 ifq_set_ready(&ifp->if_snd);
1873
ae474cfa 1874 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ		 1875
1876 ifp->if_capabilities = IFCAP_HWCSUM |
1877 IFCAP_VLAN_HWTAGGING |
3eb0ea09
SZ		 1878 IFCAP_VLAN_MTU |
1879 IFCAP_TSO;
8434a83b
SZ		 1880 if (sc->rx_ring_cnt > 1)
1881 ifp->if_capabilities |= IFCAP_RSS;
5330213c 1882 ifp->if_capenable = ifp->if_capabilities;
3eb0ea09 1883 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
5330213c
SZ		 1884
1885 /*
1886 * Tell the upper layer(s) we support long frames.
1887 */
1888 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1889
1890 /*
1891 * Specify the media types supported by this sc and register
1892 * callbacks to update media and link information
1893 */
1894 ifmedia_init(&sc->media, IFM_IMASK,
1895 emx_media_change, emx_media_status);
1896 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1897 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1898 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1899 0, NULL);
1900 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1901 } else {
1902 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1903 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1904 0, NULL);
1905 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1906 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1907 0, NULL);
1908 if (sc->hw.phy.type != e1000_phy_ife) {
1909 ifmedia_add(&sc->media,
1910 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1911 ifmedia_add(&sc->media,
1912 IFM_ETHER | IFM_1000_T, 0, NULL);
1913 }
1914 }
1915 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1916 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1917}
1918
1919/*
1920 * Workaround for SmartSpeed on 82541 and 82547 controllers
1921 */
1922static void
1923emx_smartspeed(struct emx_softc *sc)
1924{
1925 uint16_t phy_tmp;
1926
1927 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1928 sc->hw.mac.autoneg == 0 ||
1929 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1930 return;
1931
1932 if (sc->smartspeed == 0) {
1933 /*
1934 * If Master/Slave config fault is asserted twice,
1935 * we assume back-to-back
1936 */
1937 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1938 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1939 return;
1940 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1941 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1942 e1000_read_phy_reg(&sc->hw,
1943 PHY_1000T_CTRL, &phy_tmp);
1944 if (phy_tmp & CR_1000T_MS_ENABLE) {
1945 phy_tmp &= ~CR_1000T_MS_ENABLE;
1946 e1000_write_phy_reg(&sc->hw,
1947 PHY_1000T_CTRL, phy_tmp);
1948 sc->smartspeed++;
1949 if (sc->hw.mac.autoneg &&
1950 !e1000_phy_setup_autoneg(&sc->hw) &&
1951 !e1000_read_phy_reg(&sc->hw,
1952 PHY_CONTROL, &phy_tmp)) {
1953 phy_tmp |= MII_CR_AUTO_NEG_EN |
1954 MII_CR_RESTART_AUTO_NEG;
1955 e1000_write_phy_reg(&sc->hw,
1956 PHY_CONTROL, phy_tmp);
1957 }
1958 }
1959 }
1960 return;
1961 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1962 /* If still no link, perhaps using 2/3 pair cable */
1963 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1964 phy_tmp |= CR_1000T_MS_ENABLE;
1965 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1966 if (sc->hw.mac.autoneg &&
1967 !e1000_phy_setup_autoneg(&sc->hw) &&
1968 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1969 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1970 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1971 }
1972 }
1973
1974 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1975 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1976 sc->smartspeed = 0;
1977}
1978
1979static int
5330213c
SZ		 1980emx_create_tx_ring(struct emx_softc *sc)
1981{
1982 device_t dev = sc->dev;
323e5ecd 1983 struct emx_txbuf *tx_buffer;
b4d8c36b 1984 int error, i, tsize, ntxd;
bdca134f
SZ		 1985
1986 /*
1987 * Validate number of transmit descriptors. It must not exceed
1988 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1989 */
b4d8c36b
SZ		 1990 ntxd = device_getenv_int(dev, "txd", emx_txd);
1991 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1992 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 1993 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 1994 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ		 1995 sc->num_tx_desc = EMX_DEFAULT_TXD;
1996 } else {
b4d8c36b 1997 sc->num_tx_desc = ntxd;
bdca134f
SZ		 1998 }
1999
2000 /*
2001 * Allocate Transmit Descriptor ring
2002 */
2003 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2004 EMX_DBA_ALIGN);
a596084c
SZ		 2005 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2006 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2007 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2008 &sc->tx_desc_paddr);
2009 if (sc->tx_desc_base == NULL) {
bdca134f 2010 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 2011 return ENOMEM;
bdca134f 2012 }
5330213c 2013
323e5ecd
SZ		 2014 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2015 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ		 2016
2017 /*
2018 * Create DMA tags for tx buffers
2019 */
2020 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2021 1, 0, /* alignment, bounds */
2022 BUS_SPACE_MAXADDR, /* lowaddr */
2023 BUS_SPACE_MAXADDR, /* highaddr */
2024 NULL, NULL, /* filter, filterarg */
2025 EMX_TSO_SIZE, /* maxsize */
2026 EMX_MAX_SCATTER, /* nsegments */
2027 EMX_MAX_SEGSIZE, /* maxsegsize */
2028 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2029 BUS_DMA_ONEBPAGE, /* flags */
2030 &sc->txtag);
2031 if (error) {
2032 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ		 2033 kfree(sc->tx_buf, M_DEVBUF);
2034 sc->tx_buf = NULL;
5330213c
SZ		 2035 return error;
2036 }
2037
2038 /*
2039 * Create DMA maps for tx buffers
2040 */
2041 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2042 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 2043
2044 error = bus_dmamap_create(sc->txtag,
2045 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2046 &tx_buffer->map);
2047 if (error) {
2048 device_printf(dev, "Unable to create TX DMA map\n");
2049 emx_destroy_tx_ring(sc, i);
2050 return error;
2051 }
2052 }
2053 return (0);
2054}
2055
2056static void
2057emx_init_tx_ring(struct emx_softc *sc)
2058{
2059 /* Clear the old ring contents */
2060 bzero(sc->tx_desc_base,
2061 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2062
2063 /* Reset state */
2064 sc->next_avail_tx_desc = 0;
2065 sc->next_tx_to_clean = 0;
2066 sc->num_tx_desc_avail = sc->num_tx_desc;
2067}
2068
2069static void
2070emx_init_tx_unit(struct emx_softc *sc)
2071{
2072 uint32_t tctl, tarc, tipg = 0;
2073 uint64_t bus_addr;
2074
2075 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2076 bus_addr = sc->tx_desc_paddr;
5330213c
SZ		 2077 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2078 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2079 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2080 (uint32_t)(bus_addr >> 32));
2081 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2082 (uint32_t)bus_addr);
2083 /* Setup the HW Tx Head and Tail descriptor pointers */
2084 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2085 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2086
2087 /* Set the default values for the Tx Inter Packet Gap timer */
2088 switch (sc->hw.mac.type) {
2089 case e1000_80003es2lan:
2090 tipg = DEFAULT_82543_TIPG_IPGR1;
2091 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2092 E1000_TIPG_IPGR2_SHIFT;
2093 break;
2094
2095 default:
2096 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2097 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2098 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2099 else
2100 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2101 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2102 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2103 break;
2104 }
2105
2106 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2107
2108 /* NOTE: 0 is not allowed for TIDV */
2109 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2110 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2111
2112 if (sc->hw.mac.type == e1000_82571 ||
2113 sc->hw.mac.type == e1000_82572) {
2114 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2115 tarc |= EMX_TARC_SPEED_MODE;
2116 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2117 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2118 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2119 tarc |= 1;
2120 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2121 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2122 tarc |= 1;
2123 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2124 }
2125
2126 /* Program the Transmit Control Register */
2127 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2128 tctl &= ~E1000_TCTL_CT;
2129 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2130 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2131 tctl |= E1000_TCTL_MULR;
2132
2133 /* This write will effectively turn on the transmit unit. */
2134 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2135}
2136
2137static void
2138emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2139{
323e5ecd 2140 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2141 int i;
2142
bdca134f 2143 /* Free Transmit Descriptor ring */
a596084c
SZ		 2144 if (sc->tx_desc_base) {
2145 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2146 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2147 sc->tx_desc_dmap);
2148 bus_dma_tag_destroy(sc->tx_desc_dtag);
2149
2150 sc->tx_desc_base = NULL;
2151 }
bdca134f 2152
323e5ecd 2153 if (sc->tx_buf == NULL)
5330213c
SZ		 2154 return;
2155
2156 for (i = 0; i < ndesc; i++) {
323e5ecd 2157 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 2158
2159 KKASSERT(tx_buffer->m_head == NULL);
2160 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2161 }
2162 bus_dma_tag_destroy(sc->txtag);
2163
323e5ecd
SZ		 2164 kfree(sc->tx_buf, M_DEVBUF);
2165 sc->tx_buf = NULL;
5330213c
SZ		 2166}
2167
2168/*
2169 * The offload context needs to be set when we transfer the first
2170 * packet of a particular protocol (TCP/UDP). This routine has been
2171 * enhanced to deal with inserted VLAN headers.
2172 *
2173 * If the new packet's ether header length, ip header length and
2174 * csum offloading type are same as the previous packet, we should
2175 * avoid allocating a new csum context descriptor; mainly to take
2176 * advantage of the pipeline effect of the TX data read request.
2177 *
2178 * This function returns number of TX descrptors allocated for
2179 * csum context.
2180 */
2181static int
2182emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2183 uint32_t *txd_upper, uint32_t *txd_lower)
2184{
2185 struct e1000_context_desc *TXD;
5330213c
SZ		 2186 int curr_txd, ehdrlen, csum_flags;
2187 uint32_t cmd, hdr_len, ip_hlen;
5330213c
SZ		 2188
2189 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
68447568
SZ		 2190 ip_hlen = mp->m_pkthdr.csum_iphlen;
2191 ehdrlen = mp->m_pkthdr.csum_lhlen;
5330213c 2192
3eb0ea09 2193 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
5330213c
SZ		 2194 sc->csum_flags == csum_flags) {
2195 /*
2196 * Same csum offload context as the previous packets;
2197 * just return.
2198 */
2199 *txd_upper = sc->csum_txd_upper;
2200 *txd_lower = sc->csum_txd_lower;
2201 return 0;
2202 }
2203
2204 /*
2205 * Setup a new csum offload context.
2206 */
2207
2208 curr_txd = sc->next_avail_tx_desc;
5330213c
SZ		 2209 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2210
2211 cmd = 0;
2212
2213 /* Setup of IP header checksum. */
2214 if (csum_flags & CSUM_IP) {
2215 /*
2216 * Start offset for header checksum calculation.
2217 * End offset for header checksum calculation.
2218 * Offset of place to put the checksum.
2219 */
2220 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2221 TXD->lower_setup.ip_fields.ipcse =
2222 htole16(ehdrlen + ip_hlen - 1);
2223 TXD->lower_setup.ip_fields.ipcso =
2224 ehdrlen + offsetof(struct ip, ip_sum);
2225 cmd |= E1000_TXD_CMD_IP;
2226 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2227 }
2228 hdr_len = ehdrlen + ip_hlen;
2229
2230 if (csum_flags & CSUM_TCP) {
2231 /*
2232 * Start offset for payload checksum calculation.
2233 * End offset for payload checksum calculation.
2234 * Offset of place to put the checksum.
2235 */
2236 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2237 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2238 TXD->upper_setup.tcp_fields.tucso =
2239 hdr_len + offsetof(struct tcphdr, th_sum);
2240 cmd |= E1000_TXD_CMD_TCP;
2241 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2242 } else if (csum_flags & CSUM_UDP) {
2243 /*
2244 * Start offset for header checksum calculation.
2245 * End offset for header checksum calculation.
2246 * Offset of place to put the checksum.
2247 */
2248 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2249 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2250 TXD->upper_setup.tcp_fields.tucso =
2251 hdr_len + offsetof(struct udphdr, uh_sum);
2252 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2253 }
2254
2255 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2256 E1000_TXD_DTYP_D; /* Data descr */
2257
2258 /* Save the information for this csum offloading context */
3eb0ea09 2259 sc->csum_lhlen = ehdrlen;
5330213c
SZ		 2260 sc->csum_iphlen = ip_hlen;
2261 sc->csum_flags = csum_flags;
2262 sc->csum_txd_upper = *txd_upper;
2263 sc->csum_txd_lower = *txd_lower;
2264
2265 TXD->tcp_seg_setup.data = htole32(0);
2266 TXD->cmd_and_length =
2267 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ		 2268
2269 if (++curr_txd == sc->num_tx_desc)
2270 curr_txd = 0;
2271
2272 KKASSERT(sc->num_tx_desc_avail > 0);
2273 sc->num_tx_desc_avail--;
2274
2275 sc->next_avail_tx_desc = curr_txd;
2276 return 1;
2277}
2278
5330213c
SZ		 2279static void
2280emx_txeof(struct emx_softc *sc)
2281{
2282 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2283 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2284 int first, num_avail;
2285
2286 if (sc->tx_dd_head == sc->tx_dd_tail)
2287 return;
2288
2289 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2290 return;
2291
2292 num_avail = sc->num_tx_desc_avail;
2293 first = sc->next_tx_to_clean;
2294
2295 while (sc->tx_dd_head != sc->tx_dd_tail) {
2296 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2297 struct e1000_tx_desc *tx_desc;
5330213c
SZ		 2298
2299 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ		 2300 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2301 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2302
2303 if (++dd_idx == sc->num_tx_desc)
2304 dd_idx = 0;
2305
2306 while (first != dd_idx) {
2307 logif(pkt_txclean);
2308
5330213c
SZ		 2309 num_avail++;
2310
323e5ecd 2311 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 2312 if (tx_buffer->m_head) {
2313 ifp->if_opackets++;
2314 bus_dmamap_unload(sc->txtag,
2315 tx_buffer->map);
2316 m_freem(tx_buffer->m_head);
2317 tx_buffer->m_head = NULL;
2318 }
2319
2320 if (++first == sc->num_tx_desc)
2321 first = 0;
2322 }
2323 } else {
2324 break;
2325 }
2326 }
2327 sc->next_tx_to_clean = first;
2328 sc->num_tx_desc_avail = num_avail;
2329
2330 if (sc->tx_dd_head == sc->tx_dd_tail) {
2331 sc->tx_dd_head = 0;
2332 sc->tx_dd_tail = 0;
2333 }
2334
2335 if (!EMX_IS_OACTIVE(sc)) {
2336 ifp->if_flags &= ~IFF_OACTIVE;
2337
2338 /* All clean, turn off the timer */
2339 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2340 ifp->if_timer = 0;
2341 }
2342}
2343
2344static void
2345emx_tx_collect(struct emx_softc *sc)
2346{
2347 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2348 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2349 int tdh, first, num_avail, dd_idx = -1;
2350
2351 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2352 return;
2353
2354 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2355 if (tdh == sc->next_tx_to_clean)
2356 return;
2357
2358 if (sc->tx_dd_head != sc->tx_dd_tail)
2359 dd_idx = sc->tx_dd[sc->tx_dd_head];
2360
2361 num_avail = sc->num_tx_desc_avail;
2362 first = sc->next_tx_to_clean;
2363
2364 while (first != tdh) {
2365 logif(pkt_txclean);
2366
5330213c
SZ		 2367 num_avail++;
2368
323e5ecd 2369 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 2370 if (tx_buffer->m_head) {
2371 ifp->if_opackets++;
2372 bus_dmamap_unload(sc->txtag,
2373 tx_buffer->map);
2374 m_freem(tx_buffer->m_head);
2375 tx_buffer->m_head = NULL;
2376 }
2377
2378 if (first == dd_idx) {
2379 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2380 if (sc->tx_dd_head == sc->tx_dd_tail) {
2381 sc->tx_dd_head = 0;
2382 sc->tx_dd_tail = 0;
2383 dd_idx = -1;
2384 } else {
2385 dd_idx = sc->tx_dd[sc->tx_dd_head];
2386 }
2387 }
2388
2389 if (++first == sc->num_tx_desc)
2390 first = 0;
2391 }
2392 sc->next_tx_to_clean = first;
2393 sc->num_tx_desc_avail = num_avail;
2394
2395 if (!EMX_IS_OACTIVE(sc)) {
2396 ifp->if_flags &= ~IFF_OACTIVE;
2397
2398 /* All clean, turn off the timer */
2399 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2400 ifp->if_timer = 0;
2401 }
2402}
2403
2404/*
2405 * When Link is lost sometimes there is work still in the TX ring
2406 * which will result in a watchdog, rather than allow that do an
2407 * attempted cleanup and then reinit here. Note that this has been
2408 * seens mostly with fiber adapters.
2409 */
2410static void
2411emx_tx_purge(struct emx_softc *sc)
2412{
2413 struct ifnet *ifp = &sc->arpcom.ac_if;
2414
2415 if (!sc->link_active && ifp->if_timer) {
2416 emx_tx_collect(sc);
2417 if (ifp->if_timer) {
2418 if_printf(ifp, "Link lost, TX pending, reinit\n");
2419 ifp->if_timer = 0;
2420 emx_init(sc);
2421 }
2422 }
2423}
2424
2425static int
c39e3a1f 2426emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ		 2427{
2428 struct mbuf *m;
2429 bus_dma_segment_t seg;
2430 bus_dmamap_t map;
323e5ecd 2431 struct emx_rxbuf *rx_buffer;
5330213c
SZ		 2432 int error, nseg;
2433
2434 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2435 if (m == NULL) {
c39e3a1f 2436 rdata->mbuf_cluster_failed++;
5330213c
SZ		 2437 if (init) {
2438 if_printf(&sc->arpcom.ac_if,
2439 "Unable to allocate RX mbuf\n");
2440 }
2441 return (ENOBUFS);
2442 }
2443 m->m_len = m->m_pkthdr.len = MCLBYTES;
2444
2445 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2446 m_adj(m, ETHER_ALIGN);
2447
c39e3a1f
SZ		 2448 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2449 rdata->rx_sparemap, m,
5330213c
SZ		 2450 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2451 if (error) {
2452 m_freem(m);
2453 if (init) {
2454 if_printf(&sc->arpcom.ac_if,
2455 "Unable to load RX mbuf\n");
2456 }
2457 return (error);
2458 }
2459
323e5ecd 2460 rx_buffer = &rdata->rx_buf[i];
5330213c 2461 if (rx_buffer->m_head != NULL)
c39e3a1f 2462 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ		 2463
2464 map = rx_buffer->map;
c39e3a1f
SZ		 2465 rx_buffer->map = rdata->rx_sparemap;
2466 rdata->rx_sparemap = map;
5330213c
SZ		 2467
2468 rx_buffer->m_head = m;
235b9d30 2469 rx_buffer->paddr = seg.ds_addr;
5330213c 2470
235b9d30 2471 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ		 2472 return (0);
2473}
2474
2475static int
c39e3a1f 2476emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ		 2477{
2478 device_t dev = sc->dev;
323e5ecd 2479 struct emx_rxbuf *rx_buffer;
b4d8c36b 2480 int i, error, rsize, nrxd;
bdca134f
SZ		 2481
2482 /*
2483 * Validate number of receive descriptors. It must not exceed
2484 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2485 */
b4d8c36b
SZ		 2486 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2487 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2488 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2489 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2490 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2491 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2492 } else {
b4d8c36b 2493 rdata->num_rx_desc = nrxd;
bdca134f
SZ		 2494 }
2495
2496 /*
2497 * Allocate Receive Descriptor ring
2498 */
235b9d30 2499 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2500 EMX_DBA_ALIGN);
235b9d30 2501 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2502 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ		 2503 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2504 &rdata->rx_desc_paddr);
235b9d30 2505 if (rdata->rx_desc == NULL) {
bdca134f 2506 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2507 return ENOMEM;
bdca134f 2508 }
5330213c 2509
323e5ecd
SZ		 2510 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2511 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ		 2512
2513 /*
2514 * Create DMA tag for rx buffers
2515 */
2516 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2517 1, 0, /* alignment, bounds */
2518 BUS_SPACE_MAXADDR, /* lowaddr */
2519 BUS_SPACE_MAXADDR, /* highaddr */
2520 NULL, NULL, /* filter, filterarg */
2521 MCLBYTES, /* maxsize */
2522 1, /* nsegments */
2523 MCLBYTES, /* maxsegsize */
2524 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2525 &rdata->rxtag);
5330213c
SZ		 2526 if (error) {
2527 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ		 2528 kfree(rdata->rx_buf, M_DEVBUF);
2529 rdata->rx_buf = NULL;
5330213c
SZ		 2530 return error;
2531 }
2532
2533 /*
2534 * Create spare DMA map for rx buffers
2535 */
c39e3a1f
SZ		 2536 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2537 &rdata->rx_sparemap);
5330213c
SZ		 2538 if (error) {
2539 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2540 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ		 2541 kfree(rdata->rx_buf, M_DEVBUF);
2542 rdata->rx_buf = NULL;
5330213c
SZ		 2543 return error;
2544 }
2545
2546 /*
2547 * Create DMA maps for rx buffers
2548 */
c39e3a1f 2549 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2550 rx_buffer = &rdata->rx_buf[i];
5330213c 2551
c39e3a1f 2552 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ		 2553 &rx_buffer->map);
2554 if (error) {
2555 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2556 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ		 2557 return error;
2558 }
2559 }
2560 return (0);
2561}
2562
c39e3a1f
SZ		 2563static void
2564emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2565{
2566 int i;
2567
2568 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2569 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ		 2570
2571 if (rx_buffer->m_head != NULL) {
2572 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2573 m_freem(rx_buffer->m_head);
2574 rx_buffer->m_head = NULL;
2575 }
2576 }
2577
2578 if (rdata->fmp != NULL)
2579 m_freem(rdata->fmp);
2580 rdata->fmp = NULL;
2581 rdata->lmp = NULL;
2582}
2583
5330213c 2584static int
c39e3a1f 2585emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ		 2586{
2587 int i, error;
2588
2589 /* Reset descriptor ring */
235b9d30 2590 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ		 2591
2592 /* Allocate new ones. */
c39e3a1f
SZ		 2593 for (i = 0; i < rdata->num_rx_desc; i++) {
2594 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ		 2595 if (error)
2596 return (error);
2597 }
2598
2599 /* Setup our descriptor pointers */
c39e3a1f 2600 rdata->next_rx_desc_to_check = 0;
5330213c
SZ		 2601
2602 return (0);
2603}
2604
2605static void
2606emx_init_rx_unit(struct emx_softc *sc)
2607{
2608 struct ifnet *ifp = &sc->arpcom.ac_if;
2609 uint64_t bus_addr;
2d0e5700 2610 uint32_t rctl, itr, rfctl;
3f939c23 2611 int i;
5330213c
SZ		 2612
2613 /*
2614 * Make sure receives are disabled while setting
2615 * up the descriptor ring
2616 */
2617 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2618 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2619
2620 /*
2621 * Set the interrupt throttling rate. Value is calculated
2622 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2623 */
2d0e5700
SZ		 2624 if (sc->int_throttle_ceil)
2625 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2626 else
2627 itr = 0;
2628 emx_set_itr(sc, itr);
5330213c 2629
235b9d30
SZ		 2630 /* Use extended RX descriptor */
2631 rfctl = E1000_RFCTL_EXTEN;
2632
5330213c 2633 /* Disable accelerated ackknowledge */
235b9d30
SZ		 2634 if (sc->hw.mac.type == e1000_82574)
2635 rfctl |= E1000_RFCTL_ACK_DIS;
2636
2637 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2638
65c7a6af
SZ		 2639 /*
2640 * Receive Checksum Offload for TCP and UDP
2641 *
2642 * Checksum offloading is also enabled if multiple receive
2643 * queue is to be supported, since we need it to figure out
2644 * packet type.
2645 */
13890b61
SZ		 2646 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2647 sc->rx_ring_cnt > 1) {
2d0e5700
SZ		 2648 uint32_t rxcsum;
2649
5330213c 2650 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ		 2651
2652 /*
2653 * NOTE:
2654 * PCSD must be enabled to enable multiple
2655 * receive queues.
2656 */
2657 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2658 E1000_RXCSUM_PCSD;
5330213c
SZ		 2659 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2660 }
2661
2662 /*
65c7a6af 2663 * Configure multiple receive queue (RSS)
3f939c23 2664 */
13890b61 2665 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ		 2666 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2667 uint32_t reta;
2668
13890b61
SZ		 2669 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2670 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2671
65c7a6af
SZ		 2672 /*
2673 * NOTE:
2674 * When we reach here, RSS has already been disabled
2675 * in emx_stop(), so we could safely configure RSS key
2676 * and redirect table.
2677 */
3f939c23 2678
65c7a6af
SZ		 2679 /*
2680 * Configure RSS key
2681 */
89d8e73d
SZ		 2682 toeplitz_get_key(key, sizeof(key));
2683 for (i = 0; i < EMX_NRSSRK; ++i) {
2684 uint32_t rssrk;
2685
2686 rssrk = EMX_RSSRK_VAL(key, i);
2687 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2688
2689 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2690 }
3f939c23 2691
65c7a6af 2692 /*
89d8e73d
SZ		 2693 * Configure RSS redirect table in following fashion:
2694 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2695 */
89d8e73d
SZ		 2696 reta = 0;
2697 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2698 uint32_t q;
2699
13890b61 2700 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ		 2701 reta |= q << (8 * i);
2702 }
2703 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2704
65c7a6af
SZ		 2705 for (i = 0; i < EMX_NRETA; ++i)
2706 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2707
65c7a6af
SZ		 2708 /*
2709 * Enable multiple receive queues.
2710 * Enable IPv4 RSS standard hash functions.
2711 * Disable RSS interrupt.
2712 */
2713 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2714 E1000_MRQC_ENABLE_RSS_2Q |
2715 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2716 E1000_MRQC_RSS_FIELD_IPV4);
2717 }
3f939c23
SZ		 2718
2719 /*
5330213c
SZ		 2720 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2721 * long latencies are observed, like Lenovo X60. This
2722 * change eliminates the problem, but since having positive
2723 * values in RDTR is a known source of problems on other
2724 * platforms another solution is being sought.
2725 */
2726 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2727 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2728 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2729 }
2730
13890b61 2731 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ		 2732 struct emx_rxdata *rdata = &sc->rx_data[i];
2733
2734 /*
2735 * Setup the Base and Length of the Rx Descriptor Ring
2736 */
2737 bus_addr = rdata->rx_desc_paddr;
2738 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2739 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2740 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2741 (uint32_t)(bus_addr >> 32));
2742 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2743 (uint32_t)bus_addr);
2744
2745 /*
2746 * Setup the HW Rx Head and Tail Descriptor Pointers
2747 */
3f939c23
SZ		 2748 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2749 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2750 sc->rx_data[i].num_rx_desc - 1);
2751 }
2752
2d0e5700
SZ		 2753 /* Setup the Receive Control Register */
2754 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2755 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2756 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2757 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2758
2759 /* Make sure VLAN Filters are off */
2760 rctl &= ~E1000_RCTL_VFE;
2761
2762 /* Don't store bad paket */
2763 rctl &= ~E1000_RCTL_SBP;
2764
2765 /* MCLBYTES */
2766 rctl |= E1000_RCTL_SZ_2048;
2767
2768 if (ifp->if_mtu > ETHERMTU)
2769 rctl |= E1000_RCTL_LPE;
2770 else
2771 rctl &= ~E1000_RCTL_LPE;
2772
3f939c23
SZ		 2773 /* Enable Receives */
2774 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ		 2775}
2776
2777static void
c39e3a1f 2778emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2779{
323e5ecd 2780 struct emx_rxbuf *rx_buffer;
5330213c
SZ		 2781 int i;
2782
bdca134f 2783 /* Free Receive Descriptor ring */
235b9d30 2784 if (rdata->rx_desc) {
c39e3a1f 2785 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2786 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ		 2787 rdata->rx_desc_dmap);
2788 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2789
235b9d30 2790 rdata->rx_desc = NULL;
a596084c 2791 }
bdca134f 2792
323e5ecd 2793 if (rdata->rx_buf == NULL)
5330213c
SZ		 2794 return;
2795
2796 for (i = 0; i < ndesc; i++) {
323e5ecd 2797 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ		 2798
2799 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2800 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2801 }
c39e3a1f
SZ		 2802 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2803 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2804
323e5ecd
SZ		 2805 kfree(rdata->rx_buf, M_DEVBUF);
2806 rdata->rx_buf = NULL;
5330213c
SZ		 2807}
2808
2809static void
c39e3a1f 2810emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2811{
c39e3a1f 2812 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2813 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2814 uint32_t staterr;
235b9d30 2815 emx_rxdesc_t *current_desc;
5330213c
SZ		 2816 struct mbuf *mp;
2817 int i;
5330213c 2818
c39e3a1f 2819 i = rdata->next_rx_desc_to_check;
235b9d30
SZ		 2820 current_desc = &rdata->rx_desc[i];
2821 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2822
235b9d30 2823 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ		 2824 return;
2825
235b9d30 2826 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2827 struct pktinfo *pi = NULL, pi0;
235b9d30 2828 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2829 struct mbuf *m = NULL;
0acc29d6 2830 int eop, len;
5330213c
SZ		 2831
2832 logif(pkt_receive);
2833
235b9d30 2834 mp = rx_buf->m_head;
5330213c
SZ		 2835
2836 /*
2837 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2838 * needs to access the last received byte in the mbuf.
2839 */
235b9d30 2840 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ		 2841 BUS_DMASYNC_POSTREAD);
2842
0acc29d6 2843 len = le16toh(current_desc->rxd_length);
235b9d30 2844 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ		 2845 count--;
2846 eop = 1;
5330213c
SZ		 2847 } else {
2848 eop = 0;
5330213c
SZ		 2849 }
2850
235b9d30
SZ		 2851 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2852 uint16_t vlan = 0;
3f939c23 2853 uint32_t mrq, rss_hash;
235b9d30
SZ		 2854
2855 /*
2856 * Save several necessary information,
2857 * before emx_newbuf() destroy it.
2858 */
2859 if ((staterr & E1000_RXD_STAT_VP) && eop)
2860 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2861
3f939c23
SZ		 2862 mrq = le32toh(current_desc->rxd_mrq);
2863 rss_hash = le32toh(current_desc->rxd_rss);
2864
2865 EMX_RSS_DPRINTF(sc, 10,
2866 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2867 ring_idx, mrq, rss_hash);
2868
c39e3a1f 2869 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ		 2870 ifp->if_iqdrops++;
2871 goto discard;
2872 }
2873
2874 /* Assign correct length to the current fragment */
2875 mp->m_len = len;
2876
c39e3a1f 2877 if (rdata->fmp == NULL) {
5330213c 2878 mp->m_pkthdr.len = len;
c39e3a1f
SZ		 2879 rdata->fmp = mp; /* Store the first mbuf */
2880 rdata->lmp = mp;
5330213c
SZ		 2881 } else {
2882 /*
2883 * Chain mbuf's together
2884 */
c39e3a1f
SZ		 2885 rdata->lmp->m_next = mp;
2886 rdata->lmp = rdata->lmp->m_next;
2887 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ		 2888 }
2889
2890 if (eop) {
c39e3a1f 2891 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ		 2892 ifp->if_ipackets++;
2893
235b9d30
SZ		 2894 if (ifp->if_capenable & IFCAP_RXCSUM)
2895 emx_rxcsum(staterr, rdata->fmp);
5330213c 2896
235b9d30 2897 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2898 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2899 vlan;
c39e3a1f 2900 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2901 }
c39e3a1f
SZ		 2902 m = rdata->fmp;
2903 rdata->fmp = NULL;
2904 rdata->lmp = NULL;
3f939c23 2905
9cc86e17
SZ		 2906 if (ifp->if_capenable & IFCAP_RSS) {
2907 pi = emx_rssinfo(m, &pi0, mrq,
2908 rss_hash, staterr);
2909 }
3f939c23
SZ		 2910#ifdef EMX_RSS_DEBUG
2911 rdata->rx_pkts++;
2912#endif
5330213c
SZ		 2913 }
2914 } else {
2915 ifp->if_ierrors++;
2916discard:
235b9d30 2917 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ		 2918 if (rdata->fmp != NULL) {
2919 m_freem(rdata->fmp);
2920 rdata->fmp = NULL;
2921 rdata->lmp = NULL;
5330213c
SZ		 2922 }
2923 m = NULL;
2924 }
2925
5330213c 2926 if (m != NULL)
eda7db08 2927 ether_input_pkt(ifp, m, pi);
5330213c
SZ		 2928
2929 /* Advance our pointers to the next descriptor. */
c39e3a1f 2930 if (++i == rdata->num_rx_desc)
5330213c 2931 i = 0;
235b9d30
SZ		 2932
2933 current_desc = &rdata->rx_desc[i];
2934 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2935 }
c39e3a1f 2936 rdata->next_rx_desc_to_check = i;
5330213c 2937
3f939c23 2938 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2939 if (--i < 0)
c39e3a1f 2940 i = rdata->num_rx_desc - 1;
3f939c23 2941 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ		 2942}
2943
2944static void
5330213c
SZ		 2945emx_enable_intr(struct emx_softc *sc)
2946{
2d0e5700
SZ		 2947 uint32_t ims_mask = IMS_ENABLE_MASK;
2948
6d435846 2949 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ		 2950
2951#if 0
2952 if (sc->hw.mac.type == e1000_82574) {
2953 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2954 ims_mask |= EM_MSIX_MASK;
2955 }
2956#endif
2957 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ		 2958}
2959
2960static void
2961emx_disable_intr(struct emx_softc *sc)
2962{
2d0e5700
SZ		 2963 if (sc->hw.mac.type == e1000_82574)
2964 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 2965 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 2966
6d435846 2967 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ		 2968}
2969
2970/*
2971 * Bit of a misnomer, what this really means is
2972 * to enable OS management of the system... aka
2973 * to disable special hardware management features
2974 */
2975static void
2976emx_get_mgmt(struct emx_softc *sc)
2977{
2978 /* A shared code workaround */
2979 if (sc->has_manage) {
2980 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2981 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2982
2983 /* disable hardware interception of ARP */
2984 manc &= ~(E1000_MANC_ARP_EN);
2985
2986 /* enable receiving management packets to the host */
2987 manc |= E1000_MANC_EN_MNG2HOST;
2988#define E1000_MNG2HOST_PORT_623 (1 << 5)
2989#define E1000_MNG2HOST_PORT_664 (1 << 6)
2990 manc2h |= E1000_MNG2HOST_PORT_623;
2991 manc2h |= E1000_MNG2HOST_PORT_664;
2992 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2993
2994 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2995 }
2996}
2997
2998/*
2999 * Give control back to hardware management
3000 * controller if there is one.
3001 */
3002static void
3003emx_rel_mgmt(struct emx_softc *sc)
3004{
3005 if (sc->has_manage) {
3006 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3007
3008 /* re-enable hardware interception of ARP */
3009 manc |= E1000_MANC_ARP_EN;
3010 manc &= ~E1000_MANC_EN_MNG2HOST;
3011
3012 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3013 }
3014}
3015
3016/*
3017 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3018 * For ASF and Pass Through versions of f/w this means that
3019 * the driver is loaded. For AMT version (only with 82573)
3020 * of the f/w this means that the network i/f is open.
3021 */
3022static void
3023emx_get_hw_control(struct emx_softc *sc)
3024{
5330213c 3025 /* Let firmware know the driver has taken over */
2d0e5700
SZ		 3026 if (sc->hw.mac.type == e1000_82573) {
3027 uint32_t swsm;
3028
5330213c
SZ		 3029 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3030 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3031 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ		 3032 } else {
3033 uint32_t ctrl_ext;
5330213c 3034
5330213c
SZ		 3035 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3036 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3037 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3038 }
2d0e5700 3039 sc->control_hw = 1;
5330213c
SZ		 3040}
3041
3042/*
3043 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3044 * For ASF and Pass Through versions of f/w this means that the
3045 * driver is no longer loaded. For AMT version (only with 82573)
3046 * of the f/w this means that the network i/f is closed.
3047 */
3048static void
3049emx_rel_hw_control(struct emx_softc *sc)
3050{
2d0e5700
SZ		 3051 if (!sc->control_hw)
3052 return;
3053 sc->control_hw = 0;
5330213c
SZ		 3054
3055 /* Let firmware taken over control of h/w */
2d0e5700
SZ		 3056 if (sc->hw.mac.type == e1000_82573) {
3057 uint32_t swsm;
3058
5330213c
SZ		 3059 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3060 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3061 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ		 3062 } else {
3063 uint32_t ctrl_ext;
5330213c 3064
5330213c
SZ		 3065 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3066 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3067 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ		 3068 }
3069}
3070
3071static int
3072emx_is_valid_eaddr(const uint8_t *addr)
3073{
3074 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3075
3076 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3077 return (FALSE);
3078
3079 return (TRUE);
3080}
3081
3082/*
3083 * Enable PCI Wake On Lan capability
3084 */
3085void
3086emx_enable_wol(device_t dev)
3087{
3088 uint16_t cap, status;
3089 uint8_t id;
3090
3091 /* First find the capabilities pointer*/
3092 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3093
3094 /* Read the PM Capabilities */
3095 id = pci_read_config(dev, cap, 1);
3096 if (id != PCIY_PMG) /* Something wrong */
3097 return;
3098
3099 /*
3100 * OK, we have the power capabilities,
3101 * so now get the status register
3102 */
3103 cap += PCIR_POWER_STATUS;
3104 status = pci_read_config(dev, cap, 2);
3105 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3106 pci_write_config(dev, cap, status, 2);
3107}
3108
3109static void
3110emx_update_stats(struct emx_softc *sc)
3111{
3112 struct ifnet *ifp = &sc->arpcom.ac_if;
3113
3114 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3115 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3116 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3117 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3118 }
3119 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3120 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3121 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3122 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3123
3124 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3125 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3126 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3127 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3128 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3129 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3130 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3131 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3132 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3133 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3134 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3135 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3136 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3137 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3138 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3139 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3140 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3141 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3142 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3143 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3144
3145 /* For the 64-bit byte counters the low dword must be read first. */
3146 /* Both registers clear on the read of the high dword */
3147
3148 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3149 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3150
3151 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3152 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3153 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3154 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3155 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3156
3157 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3158 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3159
3160 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3161 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3162 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3163 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3164 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3165 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3166 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3167 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3168 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3169 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3170
3171 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3172 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3173 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3174 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3175 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3176 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3177
3178 ifp->if_collisions = sc->stats.colc;
3179
3180 /* Rx Errors */
3181 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3182 sc->stats.crcerrs + sc->stats.algnerrc +
3183 sc->stats.ruc + sc->stats.roc +
3184 sc->stats.mpc + sc->stats.cexterr;
3185
3186 /* Tx Errors */
3187 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3188 sc->watchdog_events;
3189}
3190
3191static void
3192emx_print_debug_info(struct emx_softc *sc)
3193{
3194 device_t dev = sc->dev;
3195 uint8_t *hw_addr = sc->hw.hw_addr;
3196
3197 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3198 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3199 E1000_READ_REG(&sc->hw, E1000_CTRL),
3200 E1000_READ_REG(&sc->hw, E1000_RCTL));
3201 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3202 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3203 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3204 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3205 sc->hw.fc.high_water, sc->hw.fc.low_water);
3206 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3207 E1000_READ_REG(&sc->hw, E1000_TIDV),
3208 E1000_READ_REG(&sc->hw, E1000_TADV));
3209 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3210 E1000_READ_REG(&sc->hw, E1000_RDTR),
3211 E1000_READ_REG(&sc->hw, E1000_RADV));
3212 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3213 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3214 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3215 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3216 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3217 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3218 device_printf(dev, "Num Tx descriptors avail = %d\n",
3219 sc->num_tx_desc_avail);
3220 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3221 sc->no_tx_desc_avail1);
3222 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3223 sc->no_tx_desc_avail2);
3224 device_printf(dev, "Std mbuf failed = %ld\n",
3225 sc->mbuf_alloc_failed);
3226 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3227 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ		 3228 device_printf(dev, "Driver dropped packets = %ld\n",
3229 sc->dropped_pkts);
3230 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3231 sc->no_tx_dma_setup);
5330213c
SZ		 3232}
3233
3234static void
3235emx_print_hw_stats(struct emx_softc *sc)
3236{
3237 device_t dev = sc->dev;
3238
3239 device_printf(dev, "Excessive collisions = %lld\n",
3240 (long long)sc->stats.ecol);
3241#if (DEBUG_HW > 0) /* Dont output these errors normally */
3242 device_printf(dev, "Symbol errors = %lld\n",
3243 (long long)sc->stats.symerrs);
3244#endif
3245 device_printf(dev, "Sequence errors = %lld\n",
3246 (long long)sc->stats.sec);
3247 device_printf(dev, "Defer count = %lld\n",
3248 (long long)sc->stats.dc);
3249 device_printf(dev, "Missed Packets = %lld\n",
3250 (long long)sc->stats.mpc);
3251 device_printf(dev, "Receive No Buffers = %lld\n",
3252 (long long)sc->stats.rnbc);
3253 /* RLEC is inaccurate on some hardware, calculate our own. */
3254 device_printf(dev, "Receive Length Errors = %lld\n",
3255 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3256 device_printf(dev, "Receive errors = %lld\n",
3257 (long long)sc->stats.rxerrc);
3258 device_printf(dev, "Crc errors = %lld\n",
3259 (long long)sc->stats.crcerrs);
3260 device_printf(dev, "Alignment errors = %lld\n",
3261 (long long)sc->stats.algnerrc);
3262 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3263 (long long)sc->stats.cexterr);
3264 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3265 device_printf(dev, "watchdog timeouts = %ld\n",
3266 sc->watchdog_events);
3267 device_printf(dev, "XON Rcvd = %lld\n",
3268 (long long)sc->stats.xonrxc);
3269 device_printf(dev, "XON Xmtd = %lld\n",
3270 (long long)sc->stats.xontxc);
3271 device_printf(dev, "XOFF Rcvd = %lld\n",
3272 (long long)sc->stats.xoffrxc);
3273 device_printf(dev, "XOFF Xmtd = %lld\n",
3274 (long long)sc->stats.xofftxc);
3275 device_printf(dev, "Good Packets Rcvd = %lld\n",
3276 (long long)sc->stats.gprc);
3277 device_printf(dev, "Good Packets Xmtd = %lld\n",
3278 (long long)sc->stats.gptc);
3279}
3280
3281static void
3282emx_print_nvm_info(struct emx_softc *sc)
3283{
3284 uint16_t eeprom_data;
3285 int i, j, row = 0;
3286
3287 /* Its a bit crude, but it gets the job done */
3288 kprintf("\nInterface EEPROM Dump:\n");
3289 kprintf("Offset\n0x0000 ");
3290 for (i = 0, j = 0; i < 32; i++, j++) {
3291 if (j == 8) { /* Make the offset block */
3292 j = 0; ++row;
3293 kprintf("\n0x00%x0 ",row);
3294 }
3295 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3296 kprintf("%04x ", eeprom_data);
3297 }
3298 kprintf("\n");
3299}
3300
3301static int
3302emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3303{
3304 struct emx_softc *sc;
3305 struct ifnet *ifp;
3306 int error, result;
3307
3308 result = -1;
3309 error = sysctl_handle_int(oidp, &result, 0, req);
3310 if (error || !req->newptr)
3311 return (error);
3312
3313 sc = (struct emx_softc *)arg1;
3314 ifp = &sc->arpcom.ac_if;
3315
6d435846 3316 ifnet_serialize_all(ifp);
5330213c
SZ		 3317
3318 if (result == 1)
3319 emx_print_debug_info(sc);
3320
3321 /*
3322 * This value will cause a hex dump of the
3323 * first 32 16-bit words of the EEPROM to
3324 * the screen.
3325 */
3326 if (result == 2)
3327 emx_print_nvm_info(sc);
3328
6d435846 3329 ifnet_deserialize_all(ifp);
5330213c
SZ		 3330
3331 return (error);
3332}
3333
3334static int
3335emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3336{
3337 int error, result;
3338
3339 result = -1;
3340 error = sysctl_handle_int(oidp, &result, 0, req);
3341 if (error || !req->newptr)
3342 return (error);
3343
3344 if (result == 1) {
3345 struct emx_softc *sc = (struct emx_softc *)arg1;
3346 struct ifnet *ifp = &sc->arpcom.ac_if;
3347
6d435846 3348 ifnet_serialize_all(ifp);
5330213c 3349 emx_print_hw_stats(sc);
6d435846 3350 ifnet_deserialize_all(ifp);
5330213c
SZ		 3351 }
3352 return (error);
3353}
3354
3355static void
3356emx_add_sysctl(struct emx_softc *sc)
3357{
3f939c23
SZ		 3358#ifdef EMX_RSS_DEBUG
3359 char rx_pkt[32];
3360 int i;
3361#endif
5330213c
SZ		 3362
3363 sysctl_ctx_init(&sc->sysctl_ctx);
3364 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3365 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3366 device_get_nameunit(sc->dev),
3367 CTLFLAG_RD, 0, "");
3368 if (sc->sysctl_tree == NULL) {
3369 device_printf(sc->dev, "can't add sysctl node\n");
3370 return;
3371 }
3372
3373 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3374 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3375 emx_sysctl_debug_info, "I", "Debug Information");
3376
3377 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3378 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3379 emx_sysctl_stats, "I", "Statistics");
3380
3381 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ		 3382 OID_AUTO, "rxd", CTLFLAG_RD,
3383 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3384 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3385 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3386
5330213c
SZ		 3387 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3388 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3389 sc, 0, emx_sysctl_int_throttle, "I",
3390 "interrupt throttling rate");
3391 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3392 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3393 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3394 "# segments per TX interrupt");
3f939c23 3395
8434a83b 3396 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ		 3397 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3398 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3399
3f939c23
SZ		 3400#ifdef EMX_RSS_DEBUG
3401 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3402 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3403 0, "RSS debug level");
65c7a6af 3404 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3405 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3406 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3407 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3408 rx_pkt, CTLFLAG_RW,
3f939c23
SZ		 3409 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3410 }
3411#endif
5330213c
SZ		 3412}
3413
3414static int
3415emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3416{
3417 struct emx_softc *sc = (void *)arg1;
3418 struct ifnet *ifp = &sc->arpcom.ac_if;
3419 int error, throttle;
3420
3421 throttle = sc->int_throttle_ceil;
3422 error = sysctl_handle_int(oidp, &throttle, 0, req);
3423 if (error || req->newptr == NULL)
3424 return error;
3425 if (throttle < 0 || throttle > 1000000000 / 256)
3426 return EINVAL;
3427
3428 if (throttle) {
3429 /*
3430 * Set the interrupt throttling rate in 256ns increments,
3431 * recalculate sysctl value assignment to get exact frequency.
3432 */
3433 throttle = 1000000000 / 256 / throttle;
3434
3435 /* Upper 16bits of ITR is reserved and should be zero */
3436 if (throttle & 0xffff0000)
3437 return EINVAL;
3438 }
3439
6d435846 3440 ifnet_serialize_all(ifp);
5330213c
SZ		 3441
3442 if (throttle)
3443 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3444 else
3445 sc->int_throttle_ceil = 0;
3446
3447 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3448 emx_set_itr(sc, throttle);
5330213c 3449
6d435846 3450 ifnet_deserialize_all(ifp);
5330213c
SZ		 3451
3452 if (bootverbose) {
3453 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3454 sc->int_throttle_ceil);
3455 }
3456 return 0;
3457}
3458
3459static int
3460emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3461{
3462 struct emx_softc *sc = (void *)arg1;
3463 struct ifnet *ifp = &sc->arpcom.ac_if;
3464 int error, segs;
3465
3466 segs = sc->tx_int_nsegs;
3467 error = sysctl_handle_int(oidp, &segs, 0, req);
3468 if (error || req->newptr == NULL)
3469 return error;
3470 if (segs <= 0)
3471 return EINVAL;
3472
6d435846 3473 ifnet_serialize_all(ifp);
5330213c
SZ		 3474
3475 /*
3476 * Don't allow int_tx_nsegs to become:
3477 * o Less the oact_tx_desc
3478 * o Too large that no TX desc will cause TX interrupt to
3479 * be generated (OACTIVE will never recover)
3480 * o Too small that will cause tx_dd[] overflow
3481 */
3482 if (segs < sc->oact_tx_desc ||
3483 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3484 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3485 error = EINVAL;
3486 } else {
3487 error = 0;
3488 sc->tx_int_nsegs = segs;
3489 }
3490
6d435846 3491 ifnet_deserialize_all(ifp);
5330213c
SZ		 3492
3493 return error;
3494}
071699f8
SZ		 3495
3496static int
3497emx_dma_alloc(struct emx_softc *sc)
3498{
3f939c23 3499 int error, i;
071699f8
SZ		 3500
3501 /*
3502 * Create top level busdma tag
3503 */
3504 error = bus_dma_tag_create(NULL, 1, 0,
3505 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3506 NULL, NULL,
3507 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3508 0, &sc->parent_dtag);
3509 if (error) {
3510 device_printf(sc->dev, "could not create top level DMA tag\n");
3511 return error;
3512 }
3513
3514 /*
3515 * Allocate transmit descriptors ring and buffers
3516 */
3517 error = emx_create_tx_ring(sc);
3518 if (error) {
3519 device_printf(sc->dev, "Could not setup transmit structures\n");
3520 return error;
3521 }
3522
3523 /*
3524 * Allocate receive descriptors ring and buffers
3525 */
65c7a6af 3526 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3527 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3528 if (error) {
3529 device_printf(sc->dev,
3530 "Could not setup receive structures\n");
3531 return error;
3532 }
071699f8
SZ		 3533 }
3534 return 0;
3535}
3536
3537static void
3538emx_dma_free(struct emx_softc *sc)
3539{
3f939c23
SZ		 3540 int i;
3541
071699f8 3542 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3543
65c7a6af 3544 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3545 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3546 sc->rx_data[i].num_rx_desc);
3547 }
071699f8
SZ		 3548
3549 /* Free top level busdma tag */
3550 if (sc->parent_dtag != NULL)
3551 bus_dma_tag_destroy(sc->parent_dtag);
3552}
6d435846
SZ		 3553
3554static void
3555emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3556{
3557 struct emx_softc *sc = ifp->if_softc;
6d435846 3558
8f594b38
SZ		 3559 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3560 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ		 3561}
3562
3563static void
3564emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3565{
3566 struct emx_softc *sc = ifp->if_softc;
6d435846 3567
8f594b38
SZ		 3568 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3569 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ		 3570}
3571
3572static int
3573emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3574{
3575 struct emx_softc *sc = ifp->if_softc;
6d435846 3576
8f594b38
SZ		 3577 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3578 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846 3579}
bca7c435
SZ		 3580
3581static void
3582emx_serialize_skipmain(struct emx_softc *sc)
3583{
3584 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3585}
3586
3587static void
3588emx_deserialize_skipmain(struct emx_softc *sc)
3589{
3590 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3591}
2c9effcf
SZ		 3592
3593#ifdef INVARIANTS
3594
3595static void
3596emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
8f594b38 3597 boolean_t serialized)
2c9effcf
SZ		 3598{
3599 struct emx_softc *sc = ifp->if_softc;
2c9effcf 3600
8f594b38
SZ		 3601 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3602 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
2c9effcf
SZ		 3603}
3604
3605#endif /* INVARIANTS */
b3a7093f
SZ		 3606
3607#ifdef IFPOLL_ENABLE
3608
3609static void
3610emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3611{
3612 struct emx_softc *sc = ifp->if_softc;
3613 uint32_t reg_icr;
3614
3615 ASSERT_SERIALIZED(&sc->main_serialize);
3616
3617 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3618 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3cbe4103
SZ		 3619 emx_serialize_skipmain(sc);
3620
3621 callout_stop(&sc->timer);
3622 sc->hw.mac.get_link_status = 1;
3623 emx_update_link_status(sc);
3624 callout_reset(&sc->timer, hz, emx_timer, sc);
3625
3626 emx_deserialize_skipmain(sc);
b3a7093f
SZ		 3627 }
3628}
3629
3630static void
3631emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3632{
3633 struct emx_softc *sc = ifp->if_softc;
3634
3635 ASSERT_SERIALIZED(&sc->tx_serialize);
3636
3637 emx_txeof(sc);
3638 if (!ifq_is_empty(&ifp->if_snd))
3639 if_devstart(ifp);
3640}
3641
3642static void
3643emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3644{
3645 struct emx_softc *sc = ifp->if_softc;
3646 struct emx_rxdata *rdata = arg;
3647
3648 ASSERT_SERIALIZED(&rdata->rx_serialize);
3649
3650 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3651}
3652
3653static void
3654emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3655{
3656 struct emx_softc *sc = ifp->if_softc;
3657
3658 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3659
3660 if (info) {
3661 int i;
3662
3663 info->ifpi_status.status_func = emx_qpoll_status;
3664 info->ifpi_status.serializer = &sc->main_serialize;
3665
3666 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3667 info->ifpi_tx[0].arg = NULL;
3668 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3669
3670 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3671 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3672 info->ifpi_rx[i].arg = &sc->rx_data[i];
3673 info->ifpi_rx[i].serializer =
3674 &sc->rx_data[i].rx_serialize;
3675 }
3676
3677 if (ifp->if_flags & IFF_RUNNING)
3678 emx_disable_intr(sc);
3679 } else if (ifp->if_flags & IFF_RUNNING) {
3680 emx_enable_intr(sc);
3681 }
3682}
3683
3684#endif /* IFPOLL_ENABLE */
2d0e5700
SZ		 3685
3686static void
3687emx_set_itr(struct emx_softc *sc, uint32_t itr)
3688{
3689 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3690 if (sc->hw.mac.type == e1000_82574) {
3691 int i;
3692
3693 /*
3694 * When using MSIX interrupts we need to
3695 * throttle using the EITR register
3696 */
3697 for (i = 0; i < 4; ++i)
3698 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3699 }
3700}
6d5e2922
SZ		 3701
3702/*
3703 * Disable the L0s, 82574L Errata #20
3704 */
3705static void
3706emx_disable_aspm(struct emx_softc *sc)
3707{
04eb0cef 3708 uint16_t link_cap, link_ctrl, disable;
6d5e2922
SZ		 3709 uint8_t pcie_ptr, reg;
3710 device_t dev = sc->dev;
3711
3712 switch (sc->hw.mac.type) {
04eb0cef
SZ		 3713 case e1000_82571:
3714 case e1000_82572:
6d5e2922