ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath / if_ath_pci.c
CommitLineData
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1/*-
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
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28 */
29
572ff6f6 30#include <sys/cdefs.h>
572ff6f6 31
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32/*
33 * PCI/Cardbus front-end for the Atheros Wireless LAN controller driver.
34 */
572ff6f6 35#include "opt_ath.h"
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36
37#include <sys/param.h>
38#include <sys/systm.h>
572ff6f6 39#include <sys/malloc.h>
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40#include <sys/module.h>
41#include <sys/kernel.h>
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42#include <sys/lock.h>
43#include <sys/mutex.h>
193b341d 44#include <sys/errno.h>
572ff6f6 45
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46#include <sys/bus.h>
47#include <sys/rman.h>
48
49#include <sys/socket.h>
50
51#include <net/if.h>
52#include <net/if_media.h>
53#include <net/if_arp.h>
572ff6f6 54#include <net/ethernet.h>
193b341d 55
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56#include <netproto/802_11/ieee80211_var.h>
57
5cd80a8c 58#include <dev/netif/ath/ath/if_athvar.h>
193b341d 59
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60#include <bus/pci/pcivar.h>
61#include <bus/pci/pcireg.h>
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62
63/* For EEPROM firmware */
64#ifdef ATH_EEPROM_FIRMWARE
65#include <sys/linker.h>
66#include <sys/firmware.h>
67#endif /* ATH_EEPROM_FIRMWARE */
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68
69/*
70 * PCI glue.
71 */
72
73struct ath_pci_softc {
74 struct ath_softc sc_sc;
75 struct resource *sc_sr; /* memory resource */
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76 struct resource *sc_irq; /* irq resource */
77 void *sc_ih; /* interrupt handler */
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78};
79
80#define BS_BAR 0x10
81#define PCIR_RETRY_TIMEOUT 0x41
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82#define PCIR_CFG_PMCSR 0x48
83
84#define DEFAULT_CACHESIZE 32
85
86static void
87ath_pci_setup(device_t dev)
88{
89 uint8_t cz;
90
91 /* XXX TODO: need to override the _system_ saved copies of this */
92
93 /*
94 * If the cache line size is 0, force it to a reasonable
95 * value.
96 */
97 cz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
98 if (cz == 0) {
99 pci_write_config(dev, PCIR_CACHELNSZ,
100 DEFAULT_CACHESIZE / 4, 1);
101 }
102
103 /* Override the system latency timer */
104 pci_write_config(dev, PCIR_LATTIMER, 0xa8, 1);
105
106 /* If a PCI NIC, force wakeup */
107#ifdef ATH_PCI_WAKEUP_WAR
108 /* XXX TODO: don't do this for non-PCI (ie, PCIe, Cardbus!) */
109 if (1) {
110 uint16_t pmcsr;
111 pmcsr = pci_read_config(dev, PCIR_CFG_PMCSR, 2);
112 pmcsr |= 3;
113 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
114 pmcsr &= ~3;
115 pci_write_config(dev, PCIR_CFG_PMCSR, pmcsr, 2);
116 }
117#endif
118
119 /*
120 * Disable retry timeout to keep PCI Tx retries from
121 * interfering with C3 CPU state.
122 */
123 pci_write_config(dev, PCIR_RETRY_TIMEOUT, 0, 1);
124}
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125
126static int
127ath_pci_probe(device_t dev)
128{
129 const char* devname;
130
131 devname = ath_hal_probe(pci_get_vendor(dev), pci_get_device(dev));
132 if (devname != NULL) {
133 device_set_desc(dev, devname);
86877dfb 134 return BUS_PROBE_DEFAULT;
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135 }
136 return ENXIO;
137}
138
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139static int
140ath_pci_attach(device_t dev)
193b341d 141{
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142 struct ath_pci_softc *psc = device_get_softc(dev);
143 struct ath_softc *sc = &psc->sc_sc;
144 int error = ENXIO;
145 int rid;
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146#ifdef ATH_EEPROM_FIRMWARE
147 const struct firmware *fw = NULL;
148 const char *buf;
149#endif
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150
151 sc->sc_dev = dev;
152
193b341d 153 /*
86877dfb 154 * Enable bus mastering.
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155 */
156 pci_enable_busmaster(dev);
157
158 /*
572ff6f6 159 * Setup other PCI bus configuration parameters.
193b341d 160 */
572ff6f6 161 ath_pci_setup(dev);
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162
163 /*
164 * Setup memory-mapping of PCI registers.
165 */
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166 rid = BS_BAR;
167 psc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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168 RF_ACTIVE);
169 if (psc->sc_sr == NULL) {
170 device_printf(dev, "cannot map register space\n");
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171 goto bad;
172 }
173 /* XXX uintptr_t is a bandaid for ia64; to be fixed */
174 sc->sc_st = (HAL_BUS_TAG)(uintptr_t) rman_get_bustag(psc->sc_sr);
175 sc->sc_sh = (HAL_BUS_HANDLE) rman_get_bushandle(psc->sc_sr);
176 /*
177 * Mark device invalid so any interrupts (shared or otherwise)
178 * that arrive before the HAL is setup are discarded.
179 */
180 sc->sc_invalid = 1;
181
182 /*
183 * Arrange interrupt line.
184 */
185 rid = 0;
186 psc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
187 RF_SHAREABLE|RF_ACTIVE);
188 if (psc->sc_irq == NULL) {
189 device_printf(dev, "could not map interrupt\n");
190 goto bad1;
191 }
192 if (bus_setup_intr(dev, psc->sc_irq,
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193 INTR_MPSAFE,
194 ath_intr, sc, &psc->sc_ih,
195 &wlan_global_serializer)) {
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196 device_printf(dev, "could not establish interrupt\n");
197 goto bad2;
193b341d 198 }
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199
200 /*
201 * Setup DMA descriptor area.
202 */
572ff6f6 203 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
3133c5e3 204 4, 0, /* alignment, bounds */
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205 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
206 BUS_SPACE_MAXADDR, /* highaddr */
207 NULL, NULL, /* filter, filterarg */
208 0x3ffff, /* maxsize XXX */
209 ATH_MAX_SCATTER, /* nsegments */
210 0x3ffff, /* maxsegsize XXX */
211 BUS_DMA_ALLOCNOW, /* flags */
212 &sc->sc_dmat)) {
193b341d 213 device_printf(dev, "cannot allocate DMA tag\n");
86877dfb 214 goto bad3;
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215 }
216
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217#ifdef ATH_EEPROM_FIRMWARE
218 /*
219 * If there's an EEPROM firmware image, load that in.
220 */
221 if (resource_string_value(device_get_name(dev), device_get_unit(dev),
222 "eeprom_firmware", &buf) == 0) {
223 if (bootverbose)
224 device_printf(dev, "%s: looking up firmware @ '%s'\n",
225 __func__, buf);
226
227 fw = firmware_get(buf);
228 if (fw == NULL) {
229 device_printf(dev, "%s: couldn't find firmware\n",
230 __func__);
231 goto bad3;
232 }
233
234 device_printf(dev, "%s: EEPROM firmware @ %p\n",
235 __func__, fw->data);
236 sc->sc_eepromdata =
3133c5e3 237 kmalloc(fw->datasize, M_TEMP, M_WAITOK | M_ZERO);
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238 if (! sc->sc_eepromdata) {
239 device_printf(dev, "%s: can't malloc eepromdata\n",
240 __func__);
241 goto bad3;
242 }
243 memcpy(sc->sc_eepromdata, fw->data, fw->datasize);
244 firmware_put(fw, 0);
245 }
246#endif /* ATH_EEPROM_FIRMWARE */
247
248 ATH_LOCK_INIT(sc);
249 ATH_PCU_LOCK_INIT(sc);
250 ATH_RX_LOCK_INIT(sc);
251 ATH_TX_LOCK_INIT(sc);
252 ATH_TX_IC_LOCK_INIT(sc);
253 ATH_TXSTATUS_LOCK_INIT(sc);
254
193b341d 255 error = ath_attach(pci_get_device(dev), sc);
572ff6f6 256 if (error == 0) /* success */
86877dfb 257 return 0;
193b341d 258
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259 ATH_TXSTATUS_LOCK_DESTROY(sc);
260 ATH_PCU_LOCK_DESTROY(sc);
261 ATH_RX_LOCK_DESTROY(sc);
262 ATH_TX_IC_LOCK_DESTROY(sc);
263 ATH_TX_LOCK_DESTROY(sc);
264 ATH_LOCK_DESTROY(sc);
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265 bus_dma_tag_destroy(sc->sc_dmat);
266bad3:
267 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
268bad2:
269 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
270bad1:
271 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
272bad:
273 return (error);
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274}
275
276static int
277ath_pci_detach(device_t dev)
278{
279 struct ath_pci_softc *psc = device_get_softc(dev);
280 struct ath_softc *sc = &psc->sc_sc;
281
86877dfb 282 /* check if device was removed */
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283 sc->sc_invalid = !bus_child_present(dev);
284
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285 /*
286 * Do a config read to clear pre-existing pci error status.
287 */
288 (void) pci_read_config(dev, PCIR_COMMAND, 4);
289
86877dfb 290 ath_detach(sc);
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291
292 bus_generic_detach(dev);
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293 bus_teardown_intr(dev, psc->sc_irq, psc->sc_ih);
294 bus_release_resource(dev, SYS_RES_IRQ, 0, psc->sc_irq);
193b341d 295
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296 bus_dma_tag_destroy(sc->sc_dmat);
297 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, psc->sc_sr);
193b341d 298
572ff6f6 299 if (sc->sc_eepromdata)
3133c5e3 300 kfree(sc->sc_eepromdata, M_TEMP);
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301
302 ATH_TXSTATUS_LOCK_DESTROY(sc);
303 ATH_PCU_LOCK_DESTROY(sc);
304 ATH_RX_LOCK_DESTROY(sc);
305 ATH_TX_IC_LOCK_DESTROY(sc);
306 ATH_TX_LOCK_DESTROY(sc);
307 ATH_LOCK_DESTROY(sc);
308
86877dfb 309 return (0);
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310}
311
312static int
313ath_pci_shutdown(device_t dev)
314{
315 struct ath_pci_softc *psc = device_get_softc(dev);
316
317 ath_shutdown(&psc->sc_sc);
318 return (0);
319}
320
321static int
322ath_pci_suspend(device_t dev)
323{
324 struct ath_pci_softc *psc = device_get_softc(dev);
325
326 ath_suspend(&psc->sc_sc);
86877dfb 327
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328 return (0);
329}
330
331static int
332ath_pci_resume(device_t dev)
333{
334 struct ath_pci_softc *psc = device_get_softc(dev);
335
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336 /*
337 * Suspend/resume resets the PCI configuration space.
338 */
339 ath_pci_setup(dev);
340
193b341d 341 ath_resume(&psc->sc_sc);
86877dfb 342
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343 return (0);
344}
345
346static device_method_t ath_pci_methods[] = {
347 /* Device interface */
348 DEVMETHOD(device_probe, ath_pci_probe),
349 DEVMETHOD(device_attach, ath_pci_attach),
350 DEVMETHOD(device_detach, ath_pci_detach),
351 DEVMETHOD(device_shutdown, ath_pci_shutdown),
352 DEVMETHOD(device_suspend, ath_pci_suspend),
353 DEVMETHOD(device_resume, ath_pci_resume),
354
572ff6f6 355 { 0,0 }
193b341d 356};
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357static driver_t ath_pci_driver = {
358 "ath",
359 ath_pci_methods,
360 sizeof (struct ath_pci_softc)
361};
193b341d 362static devclass_t ath_devclass;
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363DRIVER_MODULE(ath_pci, pci, ath_pci_driver, ath_devclass, 0, 0);
364MODULE_VERSION(ath_pci, 1);
365MODULE_DEPEND(ath_pci, wlan, 1, 1, 1); /* 802.11 media layer */
366MODULE_DEPEND(ath_pci, if_ath, 1, 1, 1); /* if_ath driver */
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367MODULE_DEPEND(ath_pci, ath_hal, 1, 1, 1); /* Atheros HAL */
368MODULE_DEPEND(ath_pci, ath_rate, 1, 1, 1); /* rate control alg */
369MODULE_DEPEND(ath_pci, ath_dfs, 1, 1, 1); /* wtf */