ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath / if_ath_rx.c
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1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
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31
32/*
33 * Driver for the Atheros Wireless LAN controller.
34 *
35 * This software is derived from work of Atsushi Onoe; his contribution
36 * is greatly appreciated.
37 */
38
39#include "opt_inet.h"
40#include "opt_ath.h"
41/*
42 * This is needed for register operations which are performed
43 * by the driver - eg, calls to ath_hal_gettsf32().
44 *
45 * It's also required for any AH_DEBUG checks in here, eg the
46 * module dependencies.
47 */
48#include "opt_ah.h"
49#include "opt_wlan.h"
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/sysctl.h>
54#include <sys/mbuf.h>
55#include <sys/malloc.h>
56#include <sys/lock.h>
57#include <sys/mutex.h>
58#include <sys/kernel.h>
59#include <sys/socket.h>
60#include <sys/sockio.h>
61#include <sys/errno.h>
62#include <sys/callout.h>
63#include <sys/bus.h>
64#include <sys/endian.h>
65#include <sys/kthread.h>
66#include <sys/taskqueue.h>
67#include <sys/priv.h>
68#include <sys/module.h>
69#include <sys/ktr.h>
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70
71#include <net/if.h>
72#include <net/if_var.h>
73#include <net/if_dl.h>
74#include <net/if_media.h>
75#include <net/if_types.h>
76#include <net/if_arp.h>
77#include <net/ethernet.h>
78#include <net/if_llc.h>
3133c5e3 79#include <net/ifq_var.h>
572ff6f6 80
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81#include <netproto/802_11/ieee80211_var.h>
82#include <netproto/802_11/ieee80211_regdomain.h>
572ff6f6 83#ifdef IEEE80211_SUPPORT_SUPERG
5cd80a8c 84#include <netproto/802_11/ieee80211_superg.h>
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85#endif
86#ifdef IEEE80211_SUPPORT_TDMA
5cd80a8c 87#include <netproto/802_11/ieee80211_tdma.h>
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88#endif
89
90#include <net/bpf.h>
91
92#ifdef INET
93#include <netinet/in.h>
94#include <netinet/if_ether.h>
95#endif
96
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97#include <dev/netif/ath/ath/if_athvar.h>
98#include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
99#include <dev/netif/ath/ath_hal/ah_diagcodes.h>
572ff6f6 100
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101#include <dev/netif/ath/ath/if_ath_debug.h>
102#include <dev/netif/ath/ath/if_ath_misc.h>
103#include <dev/netif/ath/ath/if_ath_tsf.h>
104#include <dev/netif/ath/ath/if_ath_tx.h>
105#include <dev/netif/ath/ath/if_ath_sysctl.h>
106#include <dev/netif/ath/ath/if_ath_led.h>
107#include <dev/netif/ath/ath/if_ath_keycache.h>
108#include <dev/netif/ath/ath/if_ath_rx.h>
109#include <dev/netif/ath/ath/if_ath_beacon.h>
110#include <dev/netif/ath/ath/if_athdfs.h>
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111
112#ifdef ATH_TX99_DIAG
5cd80a8c 113#include <dev/netif/ath/ath_tx99/ath_tx99.h>
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114#endif
115
116#ifdef ATH_DEBUG_ALQ
5cd80a8c 117#include <dev/netif/ath/ath/if_ath_alq.h>
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118#endif
119
5cd80a8c 120#include <dev/netif/ath/ath/if_ath_lna_div.h>
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121
122/*
123 * Calculate the receive filter according to the
124 * operating mode and state:
125 *
126 * o always accept unicast, broadcast, and multicast traffic
127 * o accept PHY error frames when hardware doesn't have MIB support
128 * to count and we need them for ANI (sta mode only until recently)
129 * and we are not scanning (ANI is disabled)
130 * NB: older hal's add rx filter bits out of sight and we need to
131 * blindly preserve them
132 * o probe request frames are accepted only when operating in
133 * hostap, adhoc, mesh, or monitor modes
134 * o enable promiscuous mode
135 * - when in monitor mode
136 * - if interface marked PROMISC (assumes bridge setting is filtered)
137 * o accept beacons:
138 * - when operating in station mode for collecting rssi data when
139 * the station is otherwise quiet, or
140 * - when operating in adhoc mode so the 802.11 layer creates
141 * node table entries for peers,
142 * - when scanning
143 * - when doing s/w beacon miss (e.g. for ap+sta)
144 * - when operating in ap mode in 11g to detect overlapping bss that
145 * require protection
146 * - when operating in mesh mode to detect neighbors
147 * o accept control frames:
148 * - when in monitor mode
149 * XXX HT protection for 11n
150 */
151u_int32_t
152ath_calcrxfilter(struct ath_softc *sc)
153{
154 struct ifnet *ifp = sc->sc_ifp;
155 struct ieee80211com *ic = ifp->if_l2com;
156 u_int32_t rfilt;
157
158 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
159 if (!sc->sc_needmib && !sc->sc_scanning)
160 rfilt |= HAL_RX_FILTER_PHYERR;
161 if (ic->ic_opmode != IEEE80211_M_STA)
162 rfilt |= HAL_RX_FILTER_PROBEREQ;
163 /* XXX ic->ic_monvaps != 0? */
164 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
165 rfilt |= HAL_RX_FILTER_PROM;
166 if (ic->ic_opmode == IEEE80211_M_STA ||
167 ic->ic_opmode == IEEE80211_M_IBSS ||
168 sc->sc_swbmiss || sc->sc_scanning)
169 rfilt |= HAL_RX_FILTER_BEACON;
170 /*
171 * NB: We don't recalculate the rx filter when
172 * ic_protmode changes; otherwise we could do
173 * this only when ic_protmode != NONE.
174 */
175 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
176 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
177 rfilt |= HAL_RX_FILTER_BEACON;
178
179 /*
180 * Enable hardware PS-POLL RX only for hostap mode;
181 * STA mode sends PS-POLL frames but never
182 * receives them.
183 */
184 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
185 0, NULL) == HAL_OK &&
186 ic->ic_opmode == IEEE80211_M_HOSTAP)
187 rfilt |= HAL_RX_FILTER_PSPOLL;
188
189 if (sc->sc_nmeshvaps) {
190 rfilt |= HAL_RX_FILTER_BEACON;
191 if (sc->sc_hasbmatch)
192 rfilt |= HAL_RX_FILTER_BSSID;
193 else
194 rfilt |= HAL_RX_FILTER_PROM;
195 }
196 if (ic->ic_opmode == IEEE80211_M_MONITOR)
197 rfilt |= HAL_RX_FILTER_CONTROL;
198
199 /*
200 * Enable RX of compressed BAR frames only when doing
201 * 802.11n. Required for A-MPDU.
202 */
203 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
204 rfilt |= HAL_RX_FILTER_COMPBAR;
205
206 /*
207 * Enable radar PHY errors if requested by the
208 * DFS module.
209 */
210 if (sc->sc_dodfs)
211 rfilt |= HAL_RX_FILTER_PHYRADAR;
212
213 /*
214 * Enable spectral PHY errors if requested by the
215 * spectral module.
216 */
217 if (sc->sc_dospectral)
218 rfilt |= HAL_RX_FILTER_PHYRADAR;
219
220 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
221 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
222 return rfilt;
223}
224
225static int
226ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
227{
228 struct ath_hal *ah = sc->sc_ah;
229 int error;
230 struct mbuf *m;
231 struct ath_desc *ds;
232
233 m = bf->bf_m;
234 if (m == NULL) {
235 /*
236 * NB: by assigning a page to the rx dma buffer we
237 * implicitly satisfy the Atheros requirement that
238 * this buffer be cache-line-aligned and sized to be
239 * multiple of the cache line size. Not doing this
240 * causes weird stuff to happen (for the 5210 at least).
241 */
242 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
243 if (m == NULL) {
244 DPRINTF(sc, ATH_DEBUG_ANY,
245 "%s: no mbuf/cluster\n", __func__);
246 sc->sc_stats.ast_rx_nombuf++;
247 return ENOMEM;
248 }
249 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
250
3133c5e3 251 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
572ff6f6 252 bf->bf_dmamap, m,
3133c5e3 253 bf->bf_segs, 1, &bf->bf_nseg,
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254 BUS_DMA_NOWAIT);
255 if (error != 0) {
256 DPRINTF(sc, ATH_DEBUG_ANY,
257 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
258 __func__, error);
259 sc->sc_stats.ast_rx_busdma++;
260 m_freem(m);
261 return error;
262 }
263 KASSERT(bf->bf_nseg == 1,
264 ("multi-segment packet; nseg %u", bf->bf_nseg));
265 bf->bf_m = m;
266 }
267 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
268
269 /*
270 * Setup descriptors. For receive we always terminate
271 * the descriptor list with a self-linked entry so we'll
272 * not get overrun under high load (as can happen with a
273 * 5212 when ANI processing enables PHY error frames).
274 *
275 * To insure the last descriptor is self-linked we create
276 * each descriptor as self-linked and add it to the end. As
277 * each additional descriptor is added the previous self-linked
278 * entry is ``fixed'' naturally. This should be safe even
279 * if DMA is happening. When processing RX interrupts we
280 * never remove/process the last, self-linked, entry on the
281 * descriptor list. This insures the hardware always has
282 * someplace to write a new frame.
283 */
284 /*
285 * 11N: we can no longer afford to self link the last descriptor.
286 * MAC acknowledges BA status as long as it copies frames to host
287 * buffer (or rx fifo). This can incorrectly acknowledge packets
288 * to a sender if last desc is self-linked.
289 */
290 ds = bf->bf_desc;
291 if (sc->sc_rxslink)
292 ds->ds_link = bf->bf_daddr; /* link to self */
293 else
294 ds->ds_link = 0; /* terminate the list */
295 ds->ds_data = bf->bf_segs[0].ds_addr;
296 ath_hal_setuprxdesc(ah, ds
297 , m->m_len /* buffer size */
298 , 0
299 );
300
301 if (sc->sc_rxlink != NULL)
302 *sc->sc_rxlink = bf->bf_daddr;
303 sc->sc_rxlink = &ds->ds_link;
304 return 0;
305}
306
307/*
308 * Intercept management frames to collect beacon rssi data
309 * and to do ibss merges.
310 */
311void
312ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
313 int subtype, int rssi, int nf)
314{
315 struct ieee80211vap *vap = ni->ni_vap;
316 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
317
318 /*
319 * Call up first so subsequent work can use information
320 * potentially stored in the node (e.g. for ibss merge).
321 */
322 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
323 switch (subtype) {
324 case IEEE80211_FC0_SUBTYPE_BEACON:
325 /* update rssi statistics for use by the hal */
326 /* XXX unlocked check against vap->iv_bss? */
327 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
328 if (sc->sc_syncbeacon &&
329 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
330 /*
331 * Resync beacon timers using the tsf of the beacon
332 * frame we just received.
333 */
334 ath_beacon_config(sc, vap);
335 }
336 /* fall thru... */
337 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
338 if (vap->iv_opmode == IEEE80211_M_IBSS &&
339 vap->iv_state == IEEE80211_S_RUN) {
340 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
341 uint64_t tsf = ath_extend_tsf(sc, rstamp,
342 ath_hal_gettsf64(sc->sc_ah));
343 /*
344 * Handle ibss merge as needed; check the tsf on the
345 * frame before attempting the merge. The 802.11 spec
346 * says the station should change it's bssid to match
347 * the oldest station with the same ssid, where oldest
348 * is determined by the tsf. Note that hardware
349 * reconfiguration happens through callback to
350 * ath_newstate as the state machine will go from
351 * RUN -> RUN when this happens.
352 */
353 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
354 DPRINTF(sc, ATH_DEBUG_STATE,
355 "ibss merge, rstamp %u tsf %ju "
356 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
357 (uintmax_t)ni->ni_tstamp.tsf);
358 (void) ieee80211_ibss_merge(ni);
359 }
360 }
361 break;
362 }
363}
364
365#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
366static void
367ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m,
368 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
369{
370 struct ath_softc *sc = ifp->if_softc;
371
372 /* Fill in the extension bitmap */
373 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
374
375 /* Fill in the vendor header */
376 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
377 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
378 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
379
380 /* XXX what should this be? */
381 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
382 sc->sc_rx_th.wr_vh.vh_skip_len =
383 htole16(sizeof(struct ath_radiotap_vendor_hdr));
384
385 /* General version info */
386 sc->sc_rx_th.wr_v.vh_version = 1;
387
388 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
389
390 /* rssi */
391 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
392 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
393 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
394 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
395 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
396 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
397
398 /* evm */
399 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
400 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
401 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
402 /* These are only populated from the AR9300 or later */
403 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
404 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
405
406 /* direction */
407 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX;
408
409 /* RX rate */
410 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate;
411
412 /* RX flags */
413 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags;
414
415 if (rs->rs_isaggr)
416 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR;
417 if (rs->rs_moreaggr)
418 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR;
419
420 /* phyerr info */
421 if (rs->rs_status & HAL_RXERR_PHY) {
422 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
423 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR;
424 } else {
425 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
426 }
427 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
428 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
429}
430#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
431
432static void
433ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
434 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
435{
436#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
437#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
438#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
439#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
440 struct ath_softc *sc = ifp->if_softc;
441 const HAL_RATE_TABLE *rt;
442 uint8_t rix;
443
444 rt = sc->sc_currates;
445 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
446 rix = rt->rateCodeToIndex[rs->rs_rate];
447 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
448 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
449#ifdef AH_SUPPORT_AR5416
450 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
451 if (rs->rs_status & HAL_RXERR_PHY) {
452 /*
453 * PHY error - make sure the channel flags
454 * reflect the actual channel configuration,
455 * not the received frame.
456 */
457 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
458 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
459 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
460 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
461 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
462 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
463 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
464 struct ieee80211com *ic = ifp->if_l2com;
465
466 if ((rs->rs_flags & HAL_RX_2040) == 0)
467 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
468 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
469 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
470 else
471 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
472 if ((rs->rs_flags & HAL_RX_GI) == 0)
473 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
474 }
475
476#endif
477 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
478 if (rs->rs_status & HAL_RXERR_CRC)
479 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
480 /* XXX propagate other error flags from descriptor */
481 sc->sc_rx_th.wr_antnoise = nf;
482 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
483 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
484#undef CHAN_HT
485#undef CHAN_HT20
486#undef CHAN_HT40U
487#undef CHAN_HT40D
488}
489
490static void
491ath_handle_micerror(struct ieee80211com *ic,
492 struct ieee80211_frame *wh, int keyix)
493{
494 struct ieee80211_node *ni;
495
496 /* XXX recheck MIC to deal w/ chips that lie */
497 /* XXX discard MIC errors on !data frames */
498 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
499 if (ni != NULL) {
500 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
501 ieee80211_free_node(ni);
502 }
503}
504
505/*
506 * Process a single packet.
507 *
508 * The mbuf must already be synced, unmapped and removed from bf->bf_m
509 * by this stage.
510 *
511 * The mbuf must be consumed by this routine - either passed up the
512 * net80211 stack, put on the holding queue, or freed.
513 */
514int
515ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
516 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf,
517 struct mbuf *m)
518{
519 uint64_t rstamp;
520 int len, type;
521 struct ifnet *ifp = sc->sc_ifp;
522 struct ieee80211com *ic = ifp->if_l2com;
523 struct ieee80211_node *ni;
524 int is_good = 0;
525 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
526
527 /*
528 * Calculate the correct 64 bit TSF given
529 * the TSF64 register value and rs_tstamp.
530 */
531 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
532
533 /* These aren't specifically errors */
534#ifdef AH_SUPPORT_AR5416
535 if (rs->rs_flags & HAL_RX_GI)
536 sc->sc_stats.ast_rx_halfgi++;
537 if (rs->rs_flags & HAL_RX_2040)
538 sc->sc_stats.ast_rx_2040++;
539 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
540 sc->sc_stats.ast_rx_pre_crc_err++;
541 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
542 sc->sc_stats.ast_rx_post_crc_err++;
543 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
544 sc->sc_stats.ast_rx_decrypt_busy_err++;
545 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
546 sc->sc_stats.ast_rx_hi_rx_chain++;
547 if (rs->rs_flags & HAL_RX_STBC)
548 sc->sc_stats.ast_rx_stbc++;
549#endif /* AH_SUPPORT_AR5416 */
550
551 if (rs->rs_status != 0) {
552 if (rs->rs_status & HAL_RXERR_CRC)
553 sc->sc_stats.ast_rx_crcerr++;
554 if (rs->rs_status & HAL_RXERR_FIFO)
555 sc->sc_stats.ast_rx_fifoerr++;
556 if (rs->rs_status & HAL_RXERR_PHY) {
557 sc->sc_stats.ast_rx_phyerr++;
558 /* Process DFS radar events */
559 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
560 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
561 /* Now pass it to the radar processing code */
562 ath_dfs_process_phy_err(sc, m, rstamp, rs);
563 }
564
565 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
566 if (rs->rs_phyerr < 64)
567 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
568 goto rx_error; /* NB: don't count in ierrors */
569 }
570 if (rs->rs_status & HAL_RXERR_DECRYPT) {
571 /*
572 * Decrypt error. If the error occurred
573 * because there was no hardware key, then
574 * let the frame through so the upper layers
575 * can process it. This is necessary for 5210
576 * parts which have no way to setup a ``clear''
577 * key cache entry.
578 *
579 * XXX do key cache faulting
580 */
581 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
582 goto rx_accept;
583 sc->sc_stats.ast_rx_badcrypt++;
584 }
585 /*
586 * Similar as above - if the failure was a keymiss
587 * just punt it up to the upper layers for now.
588 */
589 if (rs->rs_status & HAL_RXERR_KEYMISS) {
590 sc->sc_stats.ast_rx_keymiss++;
591 goto rx_accept;
592 }
593 if (rs->rs_status & HAL_RXERR_MIC) {
594 sc->sc_stats.ast_rx_badmic++;
595 /*
596 * Do minimal work required to hand off
597 * the 802.11 header for notification.
598 */
599 /* XXX frag's and qos frames */
600 len = rs->rs_datalen;
601 if (len >= sizeof (struct ieee80211_frame)) {
602 ath_handle_micerror(ic,
603 mtod(m, struct ieee80211_frame *),
604 sc->sc_splitmic ?
605 rs->rs_keyix-32 : rs->rs_keyix);
606 }
607 }
608 ifp->if_ierrors++;
609rx_error:
610 /*
611 * Cleanup any pending partial frame.
612 */
613 if (re->m_rxpending != NULL) {
614 m_freem(re->m_rxpending);
615 re->m_rxpending = NULL;
616 }
617 /*
618 * When a tap is present pass error frames
619 * that have been requested. By default we
620 * pass decrypt+mic errors but others may be
621 * interesting (e.g. crc).
622 */
623 if (ieee80211_radiotap_active(ic) &&
624 (rs->rs_status & sc->sc_monpass)) {
625 /* NB: bpf needs the mbuf length setup */
626 len = rs->rs_datalen;
627 m->m_pkthdr.len = m->m_len = len;
628 ath_rx_tap(ifp, m, rs, rstamp, nf);
629#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
630 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
631#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
632 ieee80211_radiotap_rx_all(ic, m);
633 }
634 /* XXX pass MIC errors up for s/w reclaculation */
635 m_freem(m); m = NULL;
636 goto rx_next;
637 }
638rx_accept:
639 len = rs->rs_datalen;
640 m->m_len = len;
641
642 if (rs->rs_more) {
643 /*
644 * Frame spans multiple descriptors; save
645 * it for the next completed descriptor, it
646 * will be used to construct a jumbogram.
647 */
648 if (re->m_rxpending != NULL) {
649 /* NB: max frame size is currently 2 clusters */
650 sc->sc_stats.ast_rx_toobig++;
651 m_freem(re->m_rxpending);
652 }
653 m->m_pkthdr.rcvif = ifp;
654 m->m_pkthdr.len = len;
655 re->m_rxpending = m;
656 m = NULL;
657 goto rx_next;
658 } else if (re->m_rxpending != NULL) {
659 /*
660 * This is the second part of a jumbogram,
661 * chain it to the first mbuf, adjust the
662 * frame length, and clear the rxpending state.
663 */
664 re->m_rxpending->m_next = m;
665 re->m_rxpending->m_pkthdr.len += len;
666 m = re->m_rxpending;
667 re->m_rxpending = NULL;
668 } else {
669 /*
670 * Normal single-descriptor receive; setup
671 * the rcvif and packet length.
672 */
673 m->m_pkthdr.rcvif = ifp;
674 m->m_pkthdr.len = len;
675 }
676
677 /*
678 * Validate rs->rs_antenna.
679 *
680 * Some users w/ AR9285 NICs have reported crashes
681 * here because rs_antenna field is bogusly large.
682 * Let's enforce the maximum antenna limit of 8
683 * (and it shouldn't be hard coded, but that's a
684 * separate problem) and if there's an issue, print
685 * out an error and adjust rs_antenna to something
686 * sensible.
687 *
688 * This code should be removed once the actual
689 * root cause of the issue has been identified.
690 * For example, it may be that the rs_antenna
691 * field is only valid for the lsat frame of
692 * an aggregate and it just happens that it is
693 * "mostly" right. (This is a general statement -
694 * the majority of the statistics are only valid
695 * for the last frame in an aggregate.
696 */
697 if (rs->rs_antenna > 7) {
698 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
699 __func__, rs->rs_antenna);
700#ifdef ATH_DEBUG
701 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
702#endif /* ATH_DEBUG */
703 rs->rs_antenna = 0; /* XXX better than nothing */
704 }
705
706 /*
707 * If this is an AR9285/AR9485, then the receive and LNA
708 * configuration is stored in RSSI[2] / EXTRSSI[2].
709 * We can extract this out to build a much better
710 * receive antenna profile.
711 *
712 * Yes, this just blurts over the above RX antenna field
713 * for now. It's fine, the AR9285 doesn't really use
714 * that.
715 *
716 * Later on we should store away the fine grained LNA
717 * information and keep separate counters just for
718 * that. It'll help when debugging the AR9285/AR9485
719 * combined diversity code.
720 */
721 if (sc->sc_rx_lnamixer) {
722 rs->rs_antenna = 0;
723
724 /* Bits 0:1 - the LNA configuration used */
725 rs->rs_antenna |=
726 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED)
727 >> HAL_RX_LNA_CFG_USED_S);
728
729 /* Bit 2 - the external RX antenna switch */
730 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG)
731 rs->rs_antenna |= 0x4;
732 }
733
734 ifp->if_ipackets++;
735 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
736
737 /*
738 * Populate the rx status block. When there are bpf
739 * listeners we do the additional work to provide
740 * complete status. Otherwise we fill in only the
741 * material required by ieee80211_input. Note that
742 * noise setting is filled in above.
743 */
744 if (ieee80211_radiotap_active(ic)) {
745 ath_rx_tap(ifp, m, rs, rstamp, nf);
746#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
747 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf);
748#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
749 }
750
751 /*
752 * From this point on we assume the frame is at least
753 * as large as ieee80211_frame_min; verify that.
754 */
755 if (len < IEEE80211_MIN_LEN) {
756 if (!ieee80211_radiotap_active(ic)) {
757 DPRINTF(sc, ATH_DEBUG_RECV,
758 "%s: short packet %d\n", __func__, len);
759 sc->sc_stats.ast_rx_tooshort++;
760 } else {
761 /* NB: in particular this captures ack's */
762 ieee80211_radiotap_rx_all(ic, m);
763 }
764 m_freem(m); m = NULL;
765 goto rx_next;
766 }
767
768 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
769 const HAL_RATE_TABLE *rt = sc->sc_currates;
770 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
771
772 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
773 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
774 }
775
776 m_adj(m, -IEEE80211_CRC_LEN);
777
778 /*
779 * Locate the node for sender, track state, and then
780 * pass the (referenced) node up to the 802.11 layer
781 * for its use.
782 */
783 ni = ieee80211_find_rxnode_withkey(ic,
784 mtod(m, const struct ieee80211_frame_min *),
785 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
786 IEEE80211_KEYIX_NONE : rs->rs_keyix);
787 sc->sc_lastrs = rs;
788
789#ifdef AH_SUPPORT_AR5416
790 if (rs->rs_isaggr)
791 sc->sc_stats.ast_rx_agg++;
792#endif /* AH_SUPPORT_AR5416 */
793
794 if (ni != NULL) {
795 /*
796 * Only punt packets for ampdu reorder processing for
797 * 11n nodes; net80211 enforces that M_AMPDU is only
798 * set for 11n nodes.
799 */
800 if (ni->ni_flags & IEEE80211_NODE_HT)
801 m->m_flags |= M_AMPDU;
802
803 /*
804 * Sending station is known, dispatch directly.
805 */
806 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
807 ieee80211_free_node(ni);
808 m = NULL;
809 /*
810 * Arrange to update the last rx timestamp only for
811 * frames from our ap when operating in station mode.
812 * This assumes the rx key is always setup when
813 * associated.
814 */
815 if (ic->ic_opmode == IEEE80211_M_STA &&
816 rs->rs_keyix != HAL_RXKEYIX_INVALID)
817 is_good = 1;
818 } else {
819 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
820 m = NULL;
821 }
822
823 /*
824 * At this point we have passed the frame up the stack; thus
825 * the mbuf is no longer ours.
826 */
827
828 /*
829 * Track rx rssi and do any rx antenna management.
830 */
831 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
832 if (sc->sc_diversity) {
833 /*
834 * When using fast diversity, change the default rx
835 * antenna if diversity chooses the other antenna 3
836 * times in a row.
837 */
838 if (sc->sc_defant != rs->rs_antenna) {
839 if (++sc->sc_rxotherant >= 3)
840 ath_setdefantenna(sc, rs->rs_antenna);
841 } else
842 sc->sc_rxotherant = 0;
843 }
844
845 /* Handle slow diversity if enabled */
846 if (sc->sc_dolnadiv) {
847 ath_lna_rx_comb_scan(sc, rs, ticks, hz);
848 }
849
850 if (sc->sc_softled) {
851 /*
852 * Blink for any data frame. Otherwise do a
853 * heartbeat-style blink when idle. The latter
854 * is mainly for station mode where we depend on
855 * periodic beacon frames to trigger the poll event.
856 */
857 if (type == IEEE80211_FC0_TYPE_DATA) {
858 const HAL_RATE_TABLE *rt = sc->sc_currates;
859 ath_led_event(sc,
860 rt->rateCodeToIndex[rs->rs_rate]);
861 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
862 ath_led_event(sc, 0);
863 }
864rx_next:
865 /*
866 * Debugging - complain if we didn't NULL the mbuf pointer
867 * here.
868 */
869 if (m != NULL) {
870 device_printf(sc->sc_dev,
871 "%s: mbuf %p should've been freed!\n",
872 __func__,
873 m);
874 }
875 return (is_good);
876}
877
878#define ATH_RX_MAX 128
879
880static void
881ath_rx_proc(struct ath_softc *sc, int resched)
882{
883#define PA2DESC(_sc, _pa) \
884 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
885 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
886 struct ath_buf *bf;
887 struct ifnet *ifp = sc->sc_ifp;
888 struct ath_hal *ah = sc->sc_ah;
889#ifdef IEEE80211_SUPPORT_SUPERG
890 struct ieee80211com *ic = ifp->if_l2com;
891#endif
892 struct ath_desc *ds;
893 struct ath_rx_status *rs;
894 struct mbuf *m;
895 int ngood;
896 HAL_STATUS status;
897 int16_t nf;
898 u_int64_t tsf;
899 int npkts = 0;
900 int kickpcu = 0;
901
902 /* XXX we must not hold the ATH_LOCK here */
903 ATH_UNLOCK_ASSERT(sc);
904 ATH_PCU_UNLOCK_ASSERT(sc);
905
906 ATH_PCU_LOCK(sc);
907 sc->sc_rxproc_cnt++;
908 kickpcu = sc->sc_kickpcu;
909 ATH_PCU_UNLOCK(sc);
910
911 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
912 ngood = 0;
913 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
914 sc->sc_stats.ast_rx_noise = nf;
915 tsf = ath_hal_gettsf64(ah);
916 do {
917 /*
918 * Don't process too many packets at a time; give the
919 * TX thread time to also run - otherwise the TX
920 * latency can jump by quite a bit, causing throughput
921 * degredation.
922 */
923 if (!kickpcu && npkts >= ATH_RX_MAX)
924 break;
925
926 bf = TAILQ_FIRST(&sc->sc_rxbuf);
927 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
928 if_printf(ifp, "%s: no buffer!\n", __func__);
929 break;
930 } else if (bf == NULL) {
931 /*
932 * End of List:
933 * this can happen for non-self-linked RX chains
934 */
935 sc->sc_stats.ast_rx_hitqueueend++;
936 break;
937 }
938 m = bf->bf_m;
939 if (m == NULL) { /* NB: shouldn't happen */
940 /*
941 * If mbuf allocation failed previously there
942 * will be no mbuf; try again to re-populate it.
943 */
944 /* XXX make debug msg */
945 if_printf(ifp, "%s: no mbuf!\n", __func__);
946 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
947 goto rx_proc_next;
948 }
949 ds = bf->bf_desc;
950 if (ds->ds_link == bf->bf_daddr) {
951 /* NB: never process the self-linked entry at the end */
952 sc->sc_stats.ast_rx_hitqueueend++;
953 break;
954 }
955 /* XXX sync descriptor memory */
956 /*
957 * Must provide the virtual address of the current
958 * descriptor, the physical address, and the virtual
959 * address of the next descriptor in the h/w chain.
960 * This allows the HAL to look ahead to see if the
961 * hardware is done with a descriptor by checking the
962 * done bit in the following descriptor and the address
963 * of the current descriptor the DMA engine is working
964 * on. All this is necessary because of our use of
965 * a self-linked list to avoid rx overruns.
966 */
967 rs = &bf->bf_status.ds_rxstat;
968 status = ath_hal_rxprocdesc(ah, ds,
969 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
970#ifdef ATH_DEBUG
971 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
972 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
973#endif
974
975#ifdef ATH_DEBUG_ALQ
976 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
977 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
978 sc->sc_rx_statuslen, (char *) ds);
979#endif /* ATH_DEBUG_ALQ */
980
981 if (status == HAL_EINPROGRESS)
982 break;
983
984 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
985 npkts++;
986
987 /*
988 * Process a single frame.
989 */
990 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
991 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
992 bf->bf_m = NULL;
993 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m))
994 ngood++;
995rx_proc_next:
996 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
997 } while (ath_rxbuf_init(sc, bf) == 0);
998
999 /* rx signal state monitoring */
1000 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
1001 if (ngood)
1002 sc->sc_lastrx = tsf;
1003
1004 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
1005 /* Queue DFS tasklet if needed */
1006 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
1007 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
1008
1009 /*
1010 * Now that all the RX frames were handled that
1011 * need to be handled, kick the PCU if there's
1012 * been an RXEOL condition.
1013 */
1014 if (resched && kickpcu) {
1015 ATH_PCU_LOCK(sc);
1016 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
1017 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
1018 __func__, npkts);
1019
1020 /*
1021 * Go through the process of fully tearing down
1022 * the RX buffers and reinitialising them.
1023 *
1024 * There's a hardware bug that causes the RX FIFO
1025 * to get confused under certain conditions and
1026 * constantly write over the same frame, leading
1027 * the RX driver code here to get heavily confused.
1028 */
1029#if 1
1030 ath_startrecv(sc);
1031#else
1032 /*
1033 * Disabled for now - it'd be nice to be able to do
1034 * this in order to limit the amount of CPU time spent
1035 * reinitialising the RX side (and thus minimise RX
1036 * drops) however there's a hardware issue that
1037 * causes things to get too far out of whack.
1038 */
1039 /*
1040 * XXX can we hold the PCU lock here?
1041 * Are there any net80211 buffer calls involved?
1042 */
1043 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1044 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1045 ath_hal_rxena(ah); /* enable recv descriptors */
1046 ath_mode_init(sc); /* set filters, etc. */
1047 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1048#endif
1049
1050 ath_hal_intrset(ah, sc->sc_imask);
1051 sc->sc_kickpcu = 0;
1052 ATH_PCU_UNLOCK(sc);
1053 }
1054
1055 /* XXX check this inside of IF_LOCK? */
3133c5e3 1056 if (resched && !ifq_is_oactive(&ifp->if_snd)) {
572ff6f6
MD
1057#ifdef IEEE80211_SUPPORT_SUPERG
1058 ieee80211_ff_age_all(ic, 100);
1059#endif
3133c5e3 1060 if (!ifq_is_empty(&ifp->if_snd))
572ff6f6
MD
1061 ath_tx_kick(sc);
1062 }
1063#undef PA2DESC
1064
1065 /*
1066 * If we hit the maximum number of frames in this round,
1067 * reschedule for another immediate pass. This gives
1068 * the TX and TX completion routines time to run, which
1069 * will reduce latency.
1070 */
1071 if (npkts >= ATH_RX_MAX)
1072 sc->sc_rx.recv_sched(sc, resched);
1073
1074 ATH_PCU_LOCK(sc);
1075 sc->sc_rxproc_cnt--;
1076 ATH_PCU_UNLOCK(sc);
1077}
1078
1079#undef ATH_RX_MAX
1080
1081/*
1082 * Only run the RX proc if it's not already running.
1083 * Since this may get run as part of the reset/flush path,
1084 * the task can't clash with an existing, running tasklet.
1085 */
1086static void
1087ath_legacy_rx_tasklet(void *arg, int npending)
1088{
1089 struct ath_softc *sc = arg;
1090
1091 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1092 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1093 ATH_PCU_LOCK(sc);
1094 if (sc->sc_inreset_cnt > 0) {
1095 device_printf(sc->sc_dev,
1096 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1097 ATH_PCU_UNLOCK(sc);
1098 return;
1099 }
1100 ATH_PCU_UNLOCK(sc);
1101
1102 ath_rx_proc(sc, 1);
1103}
1104
1105static void
1106ath_legacy_flushrecv(struct ath_softc *sc)
1107{
1108
1109 ath_rx_proc(sc, 0);
1110}
1111
1112/*
1113 * Disable the receive h/w in preparation for a reset.
1114 */
1115static void
1116ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1117{
1118#define PA2DESC(_sc, _pa) \
1119 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1120 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1121 struct ath_hal *ah = sc->sc_ah;
1122
1123 ath_hal_stoppcurecv(ah); /* disable PCU */
1124 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1125 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1126 /*
1127 * TODO: see if this particular DELAY() is required; it may be
1128 * masking some missing FIFO flush or DMA sync.
1129 */
1130#if 0
1131 if (dodelay)
1132#endif
1133 DELAY(3000); /* 3ms is long enough for 1 frame */
1134#ifdef ATH_DEBUG
1135 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1136 struct ath_buf *bf;
1137 u_int ix;
1138
1139 device_printf(sc->sc_dev,
1140 "%s: rx queue %p, link %p\n",
1141 __func__,
1142 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1143 sc->sc_rxlink);
1144 ix = 0;
1145 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1146 struct ath_desc *ds = bf->bf_desc;
1147 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1148 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1149 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1150 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1151 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1152 ix++;
1153 }
1154 }
1155#endif
1156 /*
1157 * Free both high/low RX pending, just in case.
1158 */
1159 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1160 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1161 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1162 }
1163 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1164 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1165 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1166 }
1167 sc->sc_rxlink = NULL; /* just in case */
1168#undef PA2DESC
1169}
1170
1171/*
1172 * Enable the receive h/w following a reset.
1173 */
1174static int
1175ath_legacy_startrecv(struct ath_softc *sc)
1176{
1177 struct ath_hal *ah = sc->sc_ah;
1178 struct ath_buf *bf;
1179
1180 sc->sc_rxlink = NULL;
1181 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1182 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1183 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1184 int error = ath_rxbuf_init(sc, bf);
1185 if (error != 0) {
1186 DPRINTF(sc, ATH_DEBUG_RECV,
1187 "%s: ath_rxbuf_init failed %d\n",
1188 __func__, error);
1189 return error;
1190 }
1191 }
1192
1193 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1194 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1195 ath_hal_rxena(ah); /* enable recv descriptors */
1196 ath_mode_init(sc); /* set filters, etc. */
1197 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1198 return 0;
1199}
1200
1201static int
1202ath_legacy_dma_rxsetup(struct ath_softc *sc)
1203{
1204 int error;
1205
1206 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1207 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1208 if (error != 0)
1209 return (error);
1210
1211 return (0);
1212}
1213
1214static int
1215ath_legacy_dma_rxteardown(struct ath_softc *sc)
1216{
1217
1218 if (sc->sc_rxdma.dd_desc_len != 0)
1219 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1220 return (0);
1221}
1222
1223static void
1224ath_legacy_recv_sched(struct ath_softc *sc, int dosched)
1225{
1226
1227 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1228}
1229
1230static void
1231ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q,
1232 int dosched)
1233{
1234
1235 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1236}
1237
1238void
1239ath_recv_setup_legacy(struct ath_softc *sc)
1240{
1241
1242 /* Sensible legacy defaults */
1243 /*
1244 * XXX this should be changed to properly support the
1245 * exact RX descriptor size for each HAL.
1246 */
1247 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1248
1249 sc->sc_rx.recv_start = ath_legacy_startrecv;
1250 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1251 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1252 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1253 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1254
1255 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1256 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1257 sc->sc_rx.recv_sched = ath_legacy_recv_sched;
1258 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue;
1259}