ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath / if_ath_rx_edma.c
CommitLineData
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1/*-
2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30#include <sys/cdefs.h>
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31
32/*
33 * Driver for the Atheros Wireless LAN controller.
34 *
35 * This software is derived from work of Atsushi Onoe; his contribution
36 * is greatly appreciated.
37 */
38
39#include "opt_inet.h"
40#include "opt_ath.h"
41/*
42 * This is needed for register operations which are performed
43 * by the driver - eg, calls to ath_hal_gettsf32().
44 *
45 * It's also required for any AH_DEBUG checks in here, eg the
46 * module dependencies.
47 */
48#include "opt_ah.h"
49#include "opt_wlan.h"
50
51#include <sys/param.h>
52#include <sys/systm.h>
53#include <sys/sysctl.h>
54#include <sys/mbuf.h>
55#include <sys/malloc.h>
56#include <sys/lock.h>
57#include <sys/mutex.h>
58#include <sys/kernel.h>
59#include <sys/socket.h>
60#include <sys/sockio.h>
61#include <sys/errno.h>
62#include <sys/callout.h>
63#include <sys/bus.h>
64#include <sys/endian.h>
65#include <sys/kthread.h>
66#include <sys/taskqueue.h>
67#include <sys/priv.h>
68#include <sys/module.h>
69#include <sys/ktr.h>
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70
71#include <net/if.h>
72#include <net/if_var.h>
73#include <net/if_dl.h>
74#include <net/if_media.h>
75#include <net/if_types.h>
76#include <net/if_arp.h>
77#include <net/ethernet.h>
78#include <net/if_llc.h>
3133c5e3 79#include <net/ifq_var.h>
572ff6f6 80
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81#include <netproto/802_11/ieee80211_var.h>
82#include <netproto/802_11/ieee80211_regdomain.h>
572ff6f6 83#ifdef IEEE80211_SUPPORT_SUPERG
5cd80a8c 84#include <netproto/802_11/ieee80211_superg.h>
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85#endif
86#ifdef IEEE80211_SUPPORT_TDMA
5cd80a8c 87#include <netproto/802_11/ieee80211_tdma.h>
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88#endif
89
90#include <net/bpf.h>
91
92#ifdef INET
93#include <netinet/in.h>
94#include <netinet/if_ether.h>
95#endif
96
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97#include <dev/netif/ath/ath/if_athvar.h>
98#include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
99#include <dev/netif/ath/ath_hal/ah_diagcodes.h>
100
101#include <dev/netif/ath/ath/if_ath_debug.h>
102#include <dev/netif/ath/ath/if_ath_misc.h>
103#include <dev/netif/ath/ath/if_ath_tsf.h>
104#include <dev/netif/ath/ath/if_ath_tx.h>
105#include <dev/netif/ath/ath/if_ath_sysctl.h>
106#include <dev/netif/ath/ath/if_ath_led.h>
107#include <dev/netif/ath/ath/if_ath_keycache.h>
108#include <dev/netif/ath/ath/if_ath_rx.h>
109#include <dev/netif/ath/ath/if_ath_beacon.h>
110#include <dev/netif/ath/ath/if_athdfs.h>
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111
112#ifdef ATH_TX99_DIAG
5cd80a8c 113#include <dev/netif/ath/ath_tx99/ath_tx99.h>
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114#endif
115
5cd80a8c 116#include <dev/netif/ath/ath/if_ath_rx_edma.h>
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117
118#ifdef ATH_DEBUG_ALQ
5cd80a8c 119#include <dev/netif/ath/ath/if_ath_alq.h>
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120#endif
121
122/*
123 * some general macros
124 */
125#define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
126#define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
127
128MALLOC_DECLARE(M_ATHDEV);
129
130/*
131 * XXX TODO:
132 *
133 * + Make sure the FIFO is correctly flushed and reinitialised
134 * through a reset;
135 * + Verify multi-descriptor frames work!
136 * + There's a "memory use after free" which needs to be tracked down
137 * and fixed ASAP. I've seen this in the legacy path too, so it
138 * may be a generic RX path issue.
139 */
140
141/*
142 * XXX shuffle the function orders so these pre-declarations aren't
143 * required!
144 */
145static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
146 int nbufs);
147static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
148static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
149static void ath_edma_recv_proc_queue(struct ath_softc *sc,
150 HAL_RX_QUEUE qtype, int dosched);
151static int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
152 HAL_RX_QUEUE qtype, int dosched);
153
154static void
155ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
156{
157 struct ath_hal *ah = sc->sc_ah;
158
159 ATH_RX_LOCK(sc);
160 ath_hal_stoppcurecv(ah);
161 ath_hal_setrxfilter(ah, 0);
162 ath_hal_stopdmarecv(ah);
163
164 DELAY(3000);
165
166 /* Flush RX pending for each queue */
167 /* XXX should generic-ify this */
168 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
169 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
170 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
171 }
172
173 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
174 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
175 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
176 }
177 ATH_RX_UNLOCK(sc);
178}
179
180/*
181 * Re-initialise the FIFO given the current buffer contents.
182 * Specifically, walk from head -> tail, pushing the FIFO contents
183 * back into the FIFO.
184 */
185static void
186ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
187{
188 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
189 struct ath_buf *bf;
190 int i, j;
191
192 ATH_RX_LOCK_ASSERT(sc);
193
194 i = re->m_fifo_head;
195 for (j = 0; j < re->m_fifo_depth; j++) {
196 bf = re->m_fifo[i];
197 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
198 "%s: Q%d: pos=%i, addr=0x%jx\n",
199 __func__,
200 qtype,
201 i,
202 (uintmax_t)bf->bf_daddr);
203 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
204 INCR(i, re->m_fifolen);
205 }
206
207 /* Ensure this worked out right */
208 if (i != re->m_fifo_tail) {
209 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
210 __func__,
211 i,
212 re->m_fifo_tail);
213 }
214}
215
216/*
217 * Start receive.
218 *
219 * XXX TODO: this needs to reallocate the FIFO entries when a reset
220 * occurs, in case the FIFO is filled up and no new descriptors get
221 * thrown into the FIFO.
222 */
223static int
224ath_edma_startrecv(struct ath_softc *sc)
225{
226 struct ath_hal *ah = sc->sc_ah;
227
228 ATH_RX_LOCK(sc);
229
230 /* Enable RX FIFO */
231 ath_hal_rxena(ah);
232
233 /*
234 * Entries should only be written out if the
235 * FIFO is empty.
236 *
237 * XXX This isn't correct. I should be looking
238 * at the value of AR_RXDP_SIZE (0x0070) to determine
239 * how many entries are in here.
240 *
241 * A warm reset will clear the registers but not the FIFO.
242 *
243 * And I believe this is actually the address of the last
244 * handled buffer rather than the current FIFO pointer.
245 * So if no frames have been (yet) seen, we'll reinit the
246 * FIFO.
247 *
248 * I'll chase that up at some point.
249 */
250 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
251 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
252 "%s: Re-initing HP FIFO\n", __func__);
253 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
254 }
255 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
256 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
257 "%s: Re-initing LP FIFO\n", __func__);
258 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
259 }
260
261 /* Add up to m_fifolen entries in each queue */
262 /*
263 * These must occur after the above write so the FIFO buffers
264 * are pushed/tracked in the same order as the hardware will
265 * process them.
266 */
267 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
268 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
269
270 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
271 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
272
273 ath_mode_init(sc);
274 ath_hal_startpcurecv(ah);
275
276 ATH_RX_UNLOCK(sc);
277
278 return (0);
279}
280
281static void
282ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
283 int dosched)
284{
285
286 ath_edma_recv_proc_queue(sc, qtype, dosched);
287 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
288}
289
290static void
291ath_edma_recv_sched(struct ath_softc *sc, int dosched)
292{
293
294 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
295 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
296 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
297}
298
299static void
300ath_edma_recv_flush(struct ath_softc *sc)
301{
302
303 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
304
305 ATH_PCU_LOCK(sc);
306 sc->sc_rxproc_cnt++;
307 ATH_PCU_UNLOCK(sc);
308
309 /*
310 * Flush any active frames from FIFO -> deferred list
311 */
312 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
313 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
314
315 /*
316 * Process what's in the deferred queue
317 */
318 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
319 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
320
321 ATH_PCU_LOCK(sc);
322 sc->sc_rxproc_cnt--;
323 ATH_PCU_UNLOCK(sc);
324}
325
326/*
327 * Process frames from the current queue into the deferred queue.
328 */
329static void
330ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
331 int dosched)
332{
333 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
334 struct ath_rx_status *rs;
335 struct ath_desc *ds;
336 struct ath_buf *bf;
337 struct mbuf *m;
338 struct ath_hal *ah = sc->sc_ah;
339 uint64_t tsf;
340 uint16_t nf;
341 int npkts = 0;
342
343 tsf = ath_hal_gettsf64(ah);
344 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
345 sc->sc_stats.ast_rx_noise = nf;
346
347 ATH_RX_LOCK(sc);
348
349 do {
350 bf = re->m_fifo[re->m_fifo_head];
351 /* This shouldn't occur! */
352 if (bf == NULL) {
353 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
354 __func__,
355 qtype);
356 break;
357 }
358 m = bf->bf_m;
359 ds = bf->bf_desc;
360
361 /*
362 * Sync descriptor memory - this also syncs the buffer for us.
363 * EDMA descriptors are in cached memory.
364 */
365 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
366 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
367 rs = &bf->bf_status.ds_rxstat;
368 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
369 NULL, rs);
370#ifdef ATH_DEBUG
371 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
372 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
373#endif /* ATH_DEBUG */
374#ifdef ATH_DEBUG_ALQ
375 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
376 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
377 sc->sc_rx_statuslen, (char *) ds);
378#endif /* ATH_DEBUG */
379 if (bf->bf_rxstatus == HAL_EINPROGRESS)
380 break;
381
382 /*
383 * Completed descriptor.
384 */
385 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
386 "%s: Q%d: completed!\n", __func__, qtype);
387 npkts++;
388
389 /*
390 * We've been synced already, so unmap.
391 */
392 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
393
394 /*
395 * Remove the FIFO entry and place it on the completion
396 * queue.
397 */
398 re->m_fifo[re->m_fifo_head] = NULL;
399 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist[qtype], bf, bf_list);
400
401 /* Bump the descriptor FIFO stats */
402 INCR(re->m_fifo_head, re->m_fifolen);
403 re->m_fifo_depth--;
404 /* XXX check it doesn't fall below 0 */
405 } while (re->m_fifo_depth > 0);
406
407 /* Append some more fresh frames to the FIFO */
408 if (dosched)
409 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
410
411 ATH_RX_UNLOCK(sc);
412
413 /* rx signal state monitoring */
414 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
415
416 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
417 "ath edma rx proc: npkts=%d\n",
418 npkts);
419
420 /* Handle resched and kickpcu appropriately */
421 ATH_PCU_LOCK(sc);
422 if (dosched && sc->sc_kickpcu) {
423 ATH_KTR(sc, ATH_KTR_ERROR, 0,
424 "ath_edma_recv_proc_queue(): kickpcu");
425 if (npkts > 0)
426 device_printf(sc->sc_dev,
427 "%s: handled npkts %d\n",
428 __func__, npkts);
429
430 /*
431 * XXX TODO: what should occur here? Just re-poke and
432 * re-enable the RX FIFO?
433 */
434 sc->sc_kickpcu = 0;
435 }
436 ATH_PCU_UNLOCK(sc);
437
438 return;
439}
440
441/*
442 * Flush the deferred queue.
443 *
444 * This destructively flushes the deferred queue - it doesn't
445 * call the wireless stack on each mbuf.
446 */
447static void
448ath_edma_flush_deferred_queue(struct ath_softc *sc)
449{
3133c5e3 450 struct ath_buf *bf;
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451
452 ATH_RX_LOCK_ASSERT(sc);
453
454 /* Free in one set, inside the lock */
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455 while ((bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP])) != NULL) {
456 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP], bf, bf_list);
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457 ath_edma_rxbuf_free(sc, bf);
458 }
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459 while ((bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP])) != NULL) {
460 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP], bf, bf_list);
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461 ath_edma_rxbuf_free(sc, bf);
462 }
463}
464
465static int
466ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
467 int dosched)
468{
469 int ngood = 0;
470 uint64_t tsf;
3133c5e3 471 struct ath_buf *bf;
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472 struct ath_rx_status *rs;
473 int16_t nf;
474 ath_bufhead rxlist;
475 struct mbuf *m;
476
477 TAILQ_INIT(&rxlist);
478
479 nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
480 /*
481 * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
482 * otherwise we may end up adding in the wrong values if this
483 * is delayed too far..
484 */
485 tsf = ath_hal_gettsf64(sc->sc_ah);
486
487 /* Copy the list over */
488 ATH_RX_LOCK(sc);
489 TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist[qtype], bf_list);
490 ATH_RX_UNLOCK(sc);
491
492 /* Handle the completed descriptors */
3133c5e3 493 TAILQ_FOREACH(bf, &rxlist, bf_list) {
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494 /*
495 * Skip the RX descriptor status - start at the data offset
496 */
497 m_adj(bf->bf_m, sc->sc_rx_statuslen);
498
499 /* Handle the frame */
500
501 rs = &bf->bf_status.ds_rxstat;
502 m = bf->bf_m;
503 bf->bf_m = NULL;
504 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf, m))
505 ngood++;
506 }
507
508 if (ngood) {
509 sc->sc_lastrx = tsf;
510 }
511
512 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
513 "ath edma rx deferred proc: ngood=%d\n",
514 ngood);
515
516 /* Free in one set, inside the lock */
517 ATH_RX_LOCK(sc);
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518
519 while ((bf = TAILQ_FIRST(&rxlist)) != NULL) {
572ff6f6 520 /* Free the buffer/mbuf */
3133c5e3 521 TAILQ_REMOVE(&rxlist, bf, bf_list);
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522 ath_edma_rxbuf_free(sc, bf);
523 }
524 ATH_RX_UNLOCK(sc);
525
526 return (ngood);
527}
528
529static void
530ath_edma_recv_tasklet(void *arg, int npending)
531{
532 struct ath_softc *sc = (struct ath_softc *) arg;
533 struct ifnet *ifp = sc->sc_ifp;
534#ifdef IEEE80211_SUPPORT_SUPERG
535 struct ieee80211com *ic = ifp->if_l2com;
536#endif
537
538 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
539 __func__,
540 npending);
541
542 ATH_PCU_LOCK(sc);
543 if (sc->sc_inreset_cnt > 0) {
544 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
545 __func__);
546 ATH_PCU_UNLOCK(sc);
547 return;
548 }
549 sc->sc_rxproc_cnt++;
550 ATH_PCU_UNLOCK(sc);
551
552 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
553 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
554
555 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
556 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
557
558 /* XXX inside IF_LOCK ? */
3133c5e3 559 if (!ifq_is_oactive(&ifp->if_snd)) {
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560#ifdef IEEE80211_SUPPORT_SUPERG
561 ieee80211_ff_age_all(ic, 100);
562#endif
3133c5e3 563 if (!ifq_is_empty(&ifp->if_snd))
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564 ath_tx_kick(sc);
565 }
566 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
567 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
568
569 ATH_PCU_LOCK(sc);
570 sc->sc_rxproc_cnt--;
571 ATH_PCU_UNLOCK(sc);
572}
573
574/*
575 * Allocate an RX mbuf for the given ath_buf and initialise
576 * it for EDMA.
577 *
578 * + Allocate a 4KB mbuf;
579 * + Setup the DMA map for the given buffer;
580 * + Return that.
581 */
582static int
583ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
584{
585
586 struct mbuf *m;
587 int error;
588 int len;
589
590 ATH_RX_LOCK_ASSERT(sc);
591
592 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
593 if (! m)
594 return (ENOBUFS); /* XXX ?*/
595
596 /* XXX warn/enforce alignment */
597
598 len = m->m_ext.ext_size;
599#if 0
600 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
601 __func__,
602 m,
603 len,
604 mtod(m, char *));
605#endif
606
607 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
608
609 /*
610 * Populate ath_buf fields.
611 */
612 bf->bf_desc = mtod(m, struct ath_desc *);
613 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
614 bf->bf_m = m;
615
616 /*
617 * Zero the descriptor and ensure it makes it out to the
618 * bounce buffer if one is required.
619 *
620 * XXX PREWRITE will copy the whole buffer; we only needed it
621 * to sync the first 32 DWORDS. Oh well.
622 */
623 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
624
625 /*
626 * Create DMA mapping.
627 */
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628 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
629 bf->bf_dmamap, m, bf->bf_segs, 1, &bf->bf_nseg, BUS_DMA_NOWAIT);
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630
631 if (error != 0) {
632 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
633 __func__,
634 error);
635 m_freem(m);
636 return (error);
637 }
638
639 /*
640 * Set daddr to the physical mapping page.
641 */
642 bf->bf_daddr = bf->bf_segs[0].ds_addr;
643
644 /*
645 * Prepare for the upcoming read.
646 *
647 * We need to both sync some data into the buffer (the zero'ed
648 * descriptor payload) and also prepare for the read that's going
649 * to occur.
650 */
651 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
653
654 /* Finish! */
655 return (0);
656}
657
658/*
659 * Allocate a RX buffer.
660 */
661static struct ath_buf *
662ath_edma_rxbuf_alloc(struct ath_softc *sc)
663{
664 struct ath_buf *bf;
665 int error;
666
667 ATH_RX_LOCK_ASSERT(sc);
668
669 /* Allocate buffer */
670 bf = TAILQ_FIRST(&sc->sc_rxbuf);
671 /* XXX shouldn't happen upon startup? */
672 if (bf == NULL) {
673 device_printf(sc->sc_dev, "%s: nothing on rxbuf?!\n",
674 __func__);
675 return (NULL);
676 }
677
678 /* Remove it from the free list */
679 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
680
681 /* Assign RX mbuf to it */
682 error = ath_edma_rxbuf_init(sc, bf);
683 if (error != 0) {
684 device_printf(sc->sc_dev,
685 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
686 __func__,
687 bf,
688 error);
689 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
690 return (NULL);
691 }
692
693 return (bf);
694}
695
696static void
697ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
698{
699
700 ATH_RX_LOCK_ASSERT(sc);
701
702 /*
703 * Only unload the frame if we haven't consumed
704 * the mbuf via ath_rx_pkt().
705 */
706 if (bf->bf_m) {
707 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
708 m_freem(bf->bf_m);
709 bf->bf_m = NULL;
710 }
711
712 /* XXX lock? */
713 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
714}
715
716/*
717 * Allocate up to 'n' entries and push them onto the hardware FIFO.
718 *
719 * Return how many entries were successfully pushed onto the
720 * FIFO.
721 */
722static int
723ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
724{
725 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
726 struct ath_buf *bf;
727 int i;
728
729 ATH_RX_LOCK_ASSERT(sc);
730
731 /*
732 * Allocate buffers until the FIFO is full or nbufs is reached.
733 */
734 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
735 /* Ensure the FIFO is already blank, complain loudly! */
736 if (re->m_fifo[re->m_fifo_tail] != NULL) {
737 device_printf(sc->sc_dev,
738 "%s: Q%d: fifo[%d] != NULL (%p)\n",
739 __func__,
740 qtype,
741 re->m_fifo_tail,
742 re->m_fifo[re->m_fifo_tail]);
743
744 /* Free the slot */
745 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
746 re->m_fifo_depth--;
747 /* XXX check it's not < 0 */
748 re->m_fifo[re->m_fifo_tail] = NULL;
749 }
750
751 bf = ath_edma_rxbuf_alloc(sc);
752 /* XXX should ensure the FIFO is not NULL? */
753 if (bf == NULL) {
754 device_printf(sc->sc_dev,
755 "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
756 __func__,
757 qtype,
758 i,
759 nbufs);
760 break;
761 }
762
763 re->m_fifo[re->m_fifo_tail] = bf;
764
765 /* Write to the RX FIFO */
766 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
767 "%s: Q%d: putrxbuf=%p (0x%jx)\n",
768 __func__,
769 qtype,
770 bf->bf_desc,
771 (uintmax_t) bf->bf_daddr);
772 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
773
774 re->m_fifo_depth++;
775 INCR(re->m_fifo_tail, re->m_fifolen);
776 }
777
778 /*
779 * Return how many were allocated.
780 */
781 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
782 __func__,
783 qtype,
784 nbufs,
785 i);
786 return (i);
787}
788
789static int
790ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
791{
792 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
793 int i;
794
795 ATH_RX_LOCK_ASSERT(sc);
796
797 for (i = 0; i < re->m_fifolen; i++) {
798 if (re->m_fifo[i] != NULL) {
799#ifdef ATH_DEBUG
800 struct ath_buf *bf = re->m_fifo[i];
801
802 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
803 ath_printrxbuf(sc, bf, 0, HAL_OK);
804#endif
805 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
806 re->m_fifo[i] = NULL;
807 re->m_fifo_depth--;
808 }
809 }
810
811 if (re->m_rxpending != NULL) {
812 m_freem(re->m_rxpending);
813 re->m_rxpending = NULL;
814 }
815 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
816
817 return (0);
818}
819
820/*
821 * Setup the initial RX FIFO structure.
822 */
823static int
824ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
825{
826 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
827
828 ATH_RX_LOCK_ASSERT(sc);
829
830 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
831 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
832 __func__,
833 qtype);
834 return (-EINVAL);
835 }
836 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
837 __func__,
838 qtype,
839 re->m_fifolen);
840
841 /* Allocate ath_buf FIFO array, pre-zero'ed */
3133c5e3 842 re->m_fifo = kmalloc(sizeof(struct ath_buf *) * re->m_fifolen,
572ff6f6 843 M_ATHDEV,
3133c5e3 844 M_INTWAIT | M_ZERO);
572ff6f6
MD
845 if (re->m_fifo == NULL) {
846 device_printf(sc->sc_dev, "%s: malloc failed\n",
847 __func__);
848 return (-ENOMEM);
849 }
850
851 /*
852 * Set initial "empty" state.
853 */
854 re->m_rxpending = NULL;
855 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
856
857 return (0);
858}
859
860static int
861ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
862{
863 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
864
865 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
866 __func__,
867 qtype);
868
3133c5e3 869 kfree(re->m_fifo, M_ATHDEV);
572ff6f6
MD
870
871 return (0);
872}
873
874static int
875ath_edma_dma_rxsetup(struct ath_softc *sc)
876{
877 int error;
878
879 /*
880 * Create RX DMA tag and buffers.
881 */
882 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
883 "rx", ath_rxbuf, sc->sc_rx_statuslen);
884 if (error != 0)
885 return error;
886
887 ATH_RX_LOCK(sc);
888 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
889 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
890 ATH_RX_UNLOCK(sc);
891
892 return (0);
893}
894
895static int
896ath_edma_dma_rxteardown(struct ath_softc *sc)
897{
898
899 ATH_RX_LOCK(sc);
900 ath_edma_flush_deferred_queue(sc);
901 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
902 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
903
904 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
905 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
906 ATH_RX_UNLOCK(sc);
907
908 /* Free RX ath_buf */
909 /* Free RX DMA tag */
910 if (sc->sc_rxdma.dd_desc_len != 0)
911 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
912
913 return (0);
914}
915
916void
917ath_recv_setup_edma(struct ath_softc *sc)
918{
919
920 /* Set buffer size to 4k */
921 sc->sc_edma_bufsize = 4096;
922
923 /* Fetch EDMA field and buffer sizes */
924 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
925
926 /* Configure the hardware with the RX buffer size */
927 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
928 sc->sc_rx_statuslen);
929
930 device_printf(sc->sc_dev, "RX status length: %d\n",
931 sc->sc_rx_statuslen);
932 device_printf(sc->sc_dev, "RX buffer size: %d\n",
933 sc->sc_edma_bufsize);
934
935 sc->sc_rx.recv_stop = ath_edma_stoprecv;
936 sc->sc_rx.recv_start = ath_edma_startrecv;
937 sc->sc_rx.recv_flush = ath_edma_recv_flush;
938 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
939 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
940
941 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
942 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
943
944 sc->sc_rx.recv_sched = ath_edma_recv_sched;
945 sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;
946}