ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath / if_ath_tx.c
CommitLineData
572ff6f6
MD
1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
14 * redistribution must be conditioned upon including a substantially
15 * similar Disclaimer requirement for further binary redistribution.
16 *
17 * NO WARRANTY
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGES.
29 */
30
31#include <sys/cdefs.h>
572ff6f6
MD
32
33/*
34 * Driver for the Atheros Wireless LAN controller.
35 *
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
38 */
39
40#include "opt_inet.h"
41#include "opt_ath.h"
42#include "opt_wlan.h"
43
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/sysctl.h>
47#include <sys/mbuf.h>
48#include <sys/malloc.h>
49#include <sys/lock.h>
50#include <sys/mutex.h>
51#include <sys/kernel.h>
52#include <sys/socket.h>
53#include <sys/sockio.h>
54#include <sys/errno.h>
55#include <sys/callout.h>
56#include <sys/bus.h>
57#include <sys/endian.h>
58#include <sys/kthread.h>
59#include <sys/taskqueue.h>
60#include <sys/priv.h>
61#include <sys/ktr.h>
62
572ff6f6
MD
63#include <net/if.h>
64#include <net/if_var.h>
65#include <net/if_dl.h>
66#include <net/if_media.h>
67#include <net/if_types.h>
68#include <net/if_arp.h>
69#include <net/ethernet.h>
70#include <net/if_llc.h>
71
5cd80a8c
MD
72#include <netproto/802_11/ieee80211_var.h>
73#include <netproto/802_11/ieee80211_regdomain.h>
572ff6f6 74#ifdef IEEE80211_SUPPORT_SUPERG
5cd80a8c 75#include <netproto/802_11/ieee80211_superg.h>
572ff6f6
MD
76#endif
77#ifdef IEEE80211_SUPPORT_TDMA
5cd80a8c 78#include <netproto/802_11/ieee80211_tdma.h>
572ff6f6 79#endif
5cd80a8c 80#include <netproto/802_11/ieee80211_ht.h>
572ff6f6
MD
81
82#include <net/bpf.h>
83
84#ifdef INET
85#include <netinet/in.h>
86#include <netinet/if_ether.h>
87#endif
88
5cd80a8c
MD
89#include <dev/netif/ath/ath/if_athvar.h>
90#include <dev/netif/ath/ath_hal/ah_devid.h> /* XXX for softled */
91#include <dev/netif/ath/ath_hal/ah_diagcodes.h>
572ff6f6 92
5cd80a8c 93#include <dev/netif/ath/ath/if_ath_debug.h>
572ff6f6
MD
94
95#ifdef ATH_TX99_DIAG
5cd80a8c 96#include <dev/netif/ath/ath_tx99/ath_tx99.h>
572ff6f6
MD
97#endif
98
5cd80a8c
MD
99#include <dev/netif/ath/ath/if_ath_misc.h>
100#include <dev/netif/ath/ath/if_ath_tx.h>
101#include <dev/netif/ath/ath/if_ath_tx_ht.h>
572ff6f6
MD
102
103#ifdef ATH_DEBUG_ALQ
5cd80a8c 104#include <dev/netif/ath/ath/if_ath_alq.h>
572ff6f6
MD
105#endif
106
107/*
108 * How many retries to perform in software
109 */
110#define SWMAX_RETRIES 10
111
112/*
113 * What queue to throw the non-QoS TID traffic into
114 */
115#define ATH_NONQOS_TID_AC WME_AC_VO
116
117#if 0
118static int ath_tx_node_is_asleep(struct ath_softc *sc, struct ath_node *an);
119#endif
120static int ath_tx_ampdu_pending(struct ath_softc *sc, struct ath_node *an,
121 int tid);
122static int ath_tx_ampdu_running(struct ath_softc *sc, struct ath_node *an,
123 int tid);
124static ieee80211_seq ath_tx_tid_seqno_assign(struct ath_softc *sc,
125 struct ieee80211_node *ni, struct ath_buf *bf, struct mbuf *m0);
126static int ath_tx_action_frame_override_queue(struct ath_softc *sc,
127 struct ieee80211_node *ni, struct mbuf *m0, int *tid);
128static struct ath_buf *
129ath_tx_retry_clone(struct ath_softc *sc, struct ath_node *an,
130 struct ath_tid *tid, struct ath_buf *bf);
131
132#ifdef ATH_DEBUG_ALQ
133void
134ath_tx_alq_post(struct ath_softc *sc, struct ath_buf *bf_first)
135{
136 struct ath_buf *bf;
137 int i, n;
138 const char *ds;
139
140 /* XXX we should skip out early if debugging isn't enabled! */
141 bf = bf_first;
142
143 while (bf != NULL) {
144 /* XXX should ensure bf_nseg > 0! */
145 if (bf->bf_nseg == 0)
146 break;
147 n = ((bf->bf_nseg - 1) / sc->sc_tx_nmaps) + 1;
148 for (i = 0, ds = (const char *) bf->bf_desc;
149 i < n;
150 i++, ds += sc->sc_tx_desclen) {
151 if_ath_alq_post(&sc->sc_alq,
152 ATH_ALQ_EDMA_TXDESC,
153 sc->sc_tx_desclen,
154 ds);
155 }
156 bf = bf->bf_next;
157 }
158}
159#endif /* ATH_DEBUG_ALQ */
160
161/*
162 * Whether to use the 11n rate scenario functions or not
163 */
164static inline int
165ath_tx_is_11n(struct ath_softc *sc)
166{
167 return ((sc->sc_ah->ah_magic == 0x20065416) ||
168 (sc->sc_ah->ah_magic == 0x19741014));
169}
170
171/*
172 * Obtain the current TID from the given frame.
173 *
174 * Non-QoS frames need to go into TID 16 (IEEE80211_NONQOS_TID.)
175 * This has implications for which AC/priority the packet is placed
176 * in.
177 */
178static int
179ath_tx_gettid(struct ath_softc *sc, const struct mbuf *m0)
180{
181 const struct ieee80211_frame *wh;
182 int pri = M_WME_GETAC(m0);
183
184 wh = mtod(m0, const struct ieee80211_frame *);
185 if (! IEEE80211_QOS_HAS_SEQ(wh))
186 return IEEE80211_NONQOS_TID;
187 else
188 return WME_AC_TO_TID(pri);
189}
190
191static void
192ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
193{
194 struct ieee80211_frame *wh;
195
196 wh = mtod(bf->bf_m, struct ieee80211_frame *);
197 /* Only update/resync if needed */
198 if (bf->bf_state.bfs_isretried == 0) {
199 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
200 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
201 BUS_DMASYNC_PREWRITE);
202 }
203 bf->bf_state.bfs_isretried = 1;
204 bf->bf_state.bfs_retries ++;
205}
206
207/*
208 * Determine what the correct AC queue for the given frame
209 * should be.
210 *
211 * This code assumes that the TIDs map consistently to
212 * the underlying hardware (or software) ath_txq.
213 * Since the sender may try to set an AC which is
214 * arbitrary, non-QoS TIDs may end up being put on
215 * completely different ACs. There's no way to put a
216 * TID into multiple ath_txq's for scheduling, so
217 * for now we override the AC/TXQ selection and set
218 * non-QOS TID frames into the BE queue.
219 *
220 * This may be completely incorrect - specifically,
221 * some management frames may end up out of order
222 * compared to the QoS traffic they're controlling.
223 * I'll look into this later.
224 */
225static int
226ath_tx_getac(struct ath_softc *sc, const struct mbuf *m0)
227{
228 const struct ieee80211_frame *wh;
229 int pri = M_WME_GETAC(m0);
230 wh = mtod(m0, const struct ieee80211_frame *);
231 if (IEEE80211_QOS_HAS_SEQ(wh))
232 return pri;
233
234 return ATH_NONQOS_TID_AC;
235}
236
237void
238ath_txfrag_cleanup(struct ath_softc *sc,
239 ath_bufhead *frags, struct ieee80211_node *ni)
240{
3133c5e3 241 struct ath_buf *bf;
572ff6f6
MD
242
243 ATH_TXBUF_LOCK_ASSERT(sc);
244
3133c5e3 245 while ((bf = TAILQ_FIRST(frags)) != NULL) {
572ff6f6
MD
246 /* NB: bf assumed clean */
247 TAILQ_REMOVE(frags, bf, bf_list);
248 ath_returnbuf_head(sc, bf);
249 ieee80211_node_decref(ni);
250 }
251}
252
253/*
254 * Setup xmit of a fragmented frame. Allocate a buffer
255 * for each frag and bump the node reference count to
256 * reflect the held reference to be setup by ath_tx_start.
257 */
258int
259ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
260 struct mbuf *m0, struct ieee80211_node *ni)
261{
262 struct mbuf *m;
263 struct ath_buf *bf;
264
265 ATH_TXBUF_LOCK(sc);
266 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
267 /* XXX non-management? */
268 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
269 if (bf == NULL) { /* out of buffers, cleanup */
270 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: no buffer?\n",
271 __func__);
272 ath_txfrag_cleanup(sc, frags, ni);
273 break;
274 }
275 ieee80211_node_incref(ni);
276 TAILQ_INSERT_TAIL(frags, bf, bf_list);
277 }
278 ATH_TXBUF_UNLOCK(sc);
279
280 return !TAILQ_EMPTY(frags);
281}
282
283/*
284 * Reclaim mbuf resources. For fragmented frames we
285 * need to claim each frag chained with m_nextpkt.
286 */
287void
288ath_freetx(struct mbuf *m)
289{
290 struct mbuf *next;
291
292 do {
293 next = m->m_nextpkt;
294 m->m_nextpkt = NULL;
295 m_freem(m);
296 } while ((m = next) != NULL);
297}
298
299static int
300ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
301{
302 struct mbuf *m;
303 int error;
304
305 /*
306 * Load the DMA map so any coalescing is done. This
307 * also calculates the number of descriptors we need.
308 */
3133c5e3
MD
309 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat, bf->bf_dmamap, m0,
310 bf->bf_segs, 1, &bf->bf_nseg,
572ff6f6
MD
311 BUS_DMA_NOWAIT);
312 if (error == EFBIG) {
313 /* XXX packet requires too many descriptors */
314 bf->bf_nseg = ATH_MAX_SCATTER + 1;
315 } else if (error != 0) {
316 sc->sc_stats.ast_tx_busdma++;
317 ath_freetx(m0);
318 return error;
319 }
320 /*
321 * Discard null packets and check for packets that
322 * require too many TX descriptors. We try to convert
323 * the latter to a cluster.
324 */
325 if (bf->bf_nseg > ATH_MAX_SCATTER) { /* too many desc's, linearize */
326 sc->sc_stats.ast_tx_linear++;
3133c5e3
MD
327
328 /* scrap for now */
329#if 0
572ff6f6 330 m = m_collapse(m0, M_NOWAIT, ATH_MAX_SCATTER);
3133c5e3
MD
331#else
332 m = NULL;
333#endif
334
572ff6f6
MD
335 if (m == NULL) {
336 ath_freetx(m0);
337 sc->sc_stats.ast_tx_nombuf++;
338 return ENOMEM;
339 }
340 m0 = m;
3133c5e3
MD
341 error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
342 bf->bf_dmamap, m0,
343 bf->bf_segs, 1, &bf->bf_nseg,
572ff6f6
MD
344 BUS_DMA_NOWAIT);
345 if (error != 0) {
346 sc->sc_stats.ast_tx_busdma++;
347 ath_freetx(m0);
348 return error;
349 }
350 KASSERT(bf->bf_nseg <= ATH_MAX_SCATTER,
351 ("too many segments after defrag; nseg %u", bf->bf_nseg));
352 } else if (bf->bf_nseg == 0) { /* null packet, discard */
353 sc->sc_stats.ast_tx_nodata++;
354 ath_freetx(m0);
355 return EIO;
356 }
357 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
358 __func__, m0, m0->m_pkthdr.len);
359 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
360 bf->bf_m = m0;
361
362 return 0;
363}
364
365/*
366 * Chain together segments+descriptors for a frame - 11n or otherwise.
367 *
368 * For aggregates, this is called on each frame in the aggregate.
369 */
370static void
371ath_tx_chaindesclist(struct ath_softc *sc, struct ath_desc *ds0,
372 struct ath_buf *bf, int is_aggr, int is_first_subframe,
373 int is_last_subframe)
374{
375 struct ath_hal *ah = sc->sc_ah;
376 char *ds;
377 int i, bp, dsp;
378 HAL_DMA_ADDR bufAddrList[4];
379 uint32_t segLenList[4];
380 int numTxMaps = 1;
381 int isFirstDesc = 1;
382
383 /*
384 * XXX There's txdma and txdma_mgmt; the descriptor
385 * sizes must match.
386 */
387 struct ath_descdma *dd = &sc->sc_txdma;
388
389 /*
390 * Fillin the remainder of the descriptor info.
391 */
392
393 /*
394 * We need the number of TX data pointers in each descriptor.
395 * EDMA and later chips support 4 TX buffers per descriptor;
396 * previous chips just support one.
397 */
398 numTxMaps = sc->sc_tx_nmaps;
399
400 /*
401 * For EDMA and later chips ensure the TX map is fully populated
402 * before advancing to the next descriptor.
403 */
404 ds = (char *) bf->bf_desc;
405 bp = dsp = 0;
406 bzero(bufAddrList, sizeof(bufAddrList));
407 bzero(segLenList, sizeof(segLenList));
408 for (i = 0; i < bf->bf_nseg; i++) {
409 bufAddrList[bp] = bf->bf_segs[i].ds_addr;
410 segLenList[bp] = bf->bf_segs[i].ds_len;
411 bp++;
412
413 /*
414 * Go to the next segment if this isn't the last segment
415 * and there's space in the current TX map.
416 */
417 if ((i != bf->bf_nseg - 1) && (bp < numTxMaps))
418 continue;
419
420 /*
421 * Last segment or we're out of buffer pointers.
422 */
423 bp = 0;
424
425 if (i == bf->bf_nseg - 1)
426 ath_hal_settxdesclink(ah, (struct ath_desc *) ds, 0);
427 else
428 ath_hal_settxdesclink(ah, (struct ath_desc *) ds,
429 bf->bf_daddr + dd->dd_descsize * (dsp + 1));
430
431 /*
432 * XXX This assumes that bfs_txq is the actual destination
433 * hardware queue at this point. It may not have been
434 * assigned, it may actually be pointing to the multicast
435 * software TXQ id. These must be fixed!
436 */
437 ath_hal_filltxdesc(ah, (struct ath_desc *) ds
438 , bufAddrList
439 , segLenList
440 , bf->bf_descid /* XXX desc id */
441 , bf->bf_state.bfs_tx_queue
442 , isFirstDesc /* first segment */
443 , i == bf->bf_nseg - 1 /* last segment */
444 , (struct ath_desc *) ds0 /* first descriptor */
445 );
446
447 /*
448 * Make sure the 11n aggregate fields are cleared.
449 *
450 * XXX TODO: this doesn't need to be called for
451 * aggregate frames; as it'll be called on all
452 * sub-frames. Since the descriptors are in
453 * non-cacheable memory, this leads to some
454 * rather slow writes on MIPS/ARM platforms.
455 */
456 if (ath_tx_is_11n(sc))
457 ath_hal_clr11n_aggr(sc->sc_ah, (struct ath_desc *) ds);
458
459 /*
460 * If 11n is enabled, set it up as if it's an aggregate
461 * frame.
462 */
463 if (is_last_subframe) {
464 ath_hal_set11n_aggr_last(sc->sc_ah,
465 (struct ath_desc *) ds);
466 } else if (is_aggr) {
467 /*
468 * This clears the aggrlen field; so
469 * the caller needs to call set_aggr_first()!
470 *
471 * XXX TODO: don't call this for the first
472 * descriptor in the first frame in an
473 * aggregate!
474 */
475 ath_hal_set11n_aggr_middle(sc->sc_ah,
476 (struct ath_desc *) ds,
477 bf->bf_state.bfs_ndelim);
478 }
479 isFirstDesc = 0;
480 bf->bf_lastds = (struct ath_desc *) ds;
481
482 /*
483 * Don't forget to skip to the next descriptor.
484 */
485 ds += sc->sc_tx_desclen;
486 dsp++;
487
488 /*
489 * .. and don't forget to blank these out!
490 */
491 bzero(bufAddrList, sizeof(bufAddrList));
492 bzero(segLenList, sizeof(segLenList));
493 }
494 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
495}
496
497/*
498 * Set the rate control fields in the given descriptor based on
499 * the bf_state fields and node state.
500 *
501 * The bfs fields should already be set with the relevant rate
502 * control information, including whether MRR is to be enabled.
503 *
504 * Since the FreeBSD HAL currently sets up the first TX rate
505 * in ath_hal_setuptxdesc(), this will setup the MRR
506 * conditionally for the pre-11n chips, and call ath_buf_set_rate
507 * unconditionally for 11n chips. These require the 11n rate
508 * scenario to be set if MCS rates are enabled, so it's easier
509 * to just always call it. The caller can then only set rates 2, 3
510 * and 4 if multi-rate retry is needed.
511 */
512static void
513ath_tx_set_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
514 struct ath_buf *bf)
515{
516 struct ath_rc_series *rc = bf->bf_state.bfs_rc;
517
518 /* If mrr is disabled, blank tries 1, 2, 3 */
519 if (! bf->bf_state.bfs_ismrr)
520 rc[1].tries = rc[2].tries = rc[3].tries = 0;
521
522#if 0
523 /*
524 * If NOACK is set, just set ntries=1.
525 */
526 else if (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) {
527 rc[1].tries = rc[2].tries = rc[3].tries = 0;
528 rc[0].tries = 1;
529 }
530#endif
531
532 /*
533 * Always call - that way a retried descriptor will
534 * have the MRR fields overwritten.
535 *
536 * XXX TODO: see if this is really needed - setting up
537 * the first descriptor should set the MRR fields to 0
538 * for us anyway.
539 */
540 if (ath_tx_is_11n(sc)) {
541 ath_buf_set_rate(sc, ni, bf);
542 } else {
543 ath_hal_setupxtxdesc(sc->sc_ah, bf->bf_desc
544 , rc[1].ratecode, rc[1].tries
545 , rc[2].ratecode, rc[2].tries
546 , rc[3].ratecode, rc[3].tries
547 );
548 }
549}
550
551/*
552 * Setup segments+descriptors for an 11n aggregate.
553 * bf_first is the first buffer in the aggregate.
554 * The descriptor list must already been linked together using
555 * bf->bf_next.
556 */
557static void
558ath_tx_setds_11n(struct ath_softc *sc, struct ath_buf *bf_first)
559{
560 struct ath_buf *bf, *bf_prev = NULL;
561 struct ath_desc *ds0 = bf_first->bf_desc;
562
563 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: nframes=%d, al=%d\n",
564 __func__, bf_first->bf_state.bfs_nframes,
565 bf_first->bf_state.bfs_al);
566
567 bf = bf_first;
568
569 if (bf->bf_state.bfs_txrate0 == 0)
570 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: bf=%p, txrate0=%d\n",
571 __func__, bf, 0);
572 if (bf->bf_state.bfs_rc[0].ratecode == 0)
573 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: bf=%p, rix0=%d\n",
574 __func__, bf, 0);
575
576 /*
577 * Setup all descriptors of all subframes - this will
578 * call ath_hal_set11naggrmiddle() on every frame.
579 */
580 while (bf != NULL) {
581 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
582 "%s: bf=%p, nseg=%d, pktlen=%d, seqno=%d\n",
583 __func__, bf, bf->bf_nseg, bf->bf_state.bfs_pktlen,
584 SEQNO(bf->bf_state.bfs_seqno));
585
586 /*
587 * Setup the initial fields for the first descriptor - all
588 * the non-11n specific stuff.
589 */
590 ath_hal_setuptxdesc(sc->sc_ah, bf->bf_desc
591 , bf->bf_state.bfs_pktlen /* packet length */
592 , bf->bf_state.bfs_hdrlen /* header length */
593 , bf->bf_state.bfs_atype /* Atheros packet type */
594 , bf->bf_state.bfs_txpower /* txpower */
595 , bf->bf_state.bfs_txrate0
596 , bf->bf_state.bfs_try0 /* series 0 rate/tries */
597 , bf->bf_state.bfs_keyix /* key cache index */
598 , bf->bf_state.bfs_txantenna /* antenna mode */
599 , bf->bf_state.bfs_txflags | HAL_TXDESC_INTREQ /* flags */
600 , bf->bf_state.bfs_ctsrate /* rts/cts rate */
601 , bf->bf_state.bfs_ctsduration /* rts/cts duration */
602 );
603
604 /*
605 * First descriptor? Setup the rate control and initial
606 * aggregate header information.
607 */
608 if (bf == bf_first) {
609 /*
610 * setup first desc with rate and aggr info
611 */
612 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
613 }
614
615 /*
616 * Setup the descriptors for a multi-descriptor frame.
617 * This is both aggregate and non-aggregate aware.
618 */
619 ath_tx_chaindesclist(sc, ds0, bf,
620 1, /* is_aggr */
621 !! (bf == bf_first), /* is_first_subframe */
622 !! (bf->bf_next == NULL) /* is_last_subframe */
623 );
624
625 if (bf == bf_first) {
626 /*
627 * Initialise the first 11n aggregate with the
628 * aggregate length and aggregate enable bits.
629 */
630 ath_hal_set11n_aggr_first(sc->sc_ah,
631 ds0,
632 bf->bf_state.bfs_al,
633 bf->bf_state.bfs_ndelim);
634 }
635
636 /*
637 * Link the last descriptor of the previous frame
638 * to the beginning descriptor of this frame.
639 */
640 if (bf_prev != NULL)
641 ath_hal_settxdesclink(sc->sc_ah, bf_prev->bf_lastds,
642 bf->bf_daddr);
643
644 /* Save a copy so we can link the next descriptor in */
645 bf_prev = bf;
646 bf = bf->bf_next;
647 }
648
649 /*
650 * Set the first descriptor bf_lastds field to point to
651 * the last descriptor in the last subframe, that's where
652 * the status update will occur.
653 */
654 bf_first->bf_lastds = bf_prev->bf_lastds;
655
656 /*
657 * And bf_last in the first descriptor points to the end of
658 * the aggregate list.
659 */
660 bf_first->bf_last = bf_prev;
661
662 /*
663 * For non-AR9300 NICs, which require the rate control
664 * in the final descriptor - let's set that up now.
665 *
666 * This is because the filltxdesc() HAL call doesn't
667 * populate the last segment with rate control information
668 * if firstSeg is also true. For non-aggregate frames
669 * that is fine, as the first frame already has rate control
670 * info. But if the last frame in an aggregate has one
671 * descriptor, both firstseg and lastseg will be true and
672 * the rate info isn't copied.
673 *
674 * This is inefficient on MIPS/ARM platforms that have
675 * non-cachable memory for TX descriptors, but we'll just
676 * make do for now.
677 *
678 * As to why the rate table is stashed in the last descriptor
679 * rather than the first descriptor? Because proctxdesc()
680 * is called on the final descriptor in an MPDU or A-MPDU -
681 * ie, the one that gets updated by the hardware upon
682 * completion. That way proctxdesc() doesn't need to know
683 * about the first _and_ last TX descriptor.
684 */
685 ath_hal_setuplasttxdesc(sc->sc_ah, bf_prev->bf_lastds, ds0);
686
687 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR, "%s: end\n", __func__);
688}
689
690/*
691 * Hand-off a frame to the multicast TX queue.
692 *
693 * This is a software TXQ which will be appended to the CAB queue
694 * during the beacon setup code.
695 *
696 * XXX TODO: since the AR9300 EDMA TX queue support wants the QCU ID
697 * as part of the TX descriptor, bf_state.bfs_tx_queue must be updated
698 * with the actual hardware txq, or all of this will fall apart.
699 *
700 * XXX It may not be a bad idea to just stuff the QCU ID into bf_state
701 * and retire bfs_tx_queue; then make sure the CABQ QCU ID is populated
702 * correctly.
703 */
704static void
705ath_tx_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
706 struct ath_buf *bf)
707{
708 ATH_TX_LOCK_ASSERT(sc);
709
710 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
711 ("%s: busy status 0x%x", __func__, bf->bf_flags));
712
713 /*
714 * Ensure that the tx queue is the cabq, so things get
715 * mapped correctly.
716 */
717 if (bf->bf_state.bfs_tx_queue != sc->sc_cabq->axq_qnum) {
718 DPRINTF(sc, ATH_DEBUG_XMIT,
719 "%s: bf=%p, bfs_tx_queue=%d, axq_qnum=%d\n",
720 __func__, bf, bf->bf_state.bfs_tx_queue,
721 txq->axq_qnum);
722 }
723
724 ATH_TXQ_LOCK(txq);
725 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) {
726 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
727 struct ieee80211_frame *wh;
728
729 /* mark previous frame */
730 wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
731 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
732 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
733 BUS_DMASYNC_PREWRITE);
734
735 /* link descriptor */
736 ath_hal_settxdesclink(sc->sc_ah,
737 bf_last->bf_lastds,
738 bf->bf_daddr);
739 }
740 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
741 ATH_TXQ_UNLOCK(txq);
742}
743
744/*
745 * Hand-off packet to a hardware queue.
746 */
747static void
748ath_tx_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
749 struct ath_buf *bf)
750{
751 struct ath_hal *ah = sc->sc_ah;
752 struct ath_buf *bf_first;
753
754 /*
755 * Insert the frame on the outbound list and pass it on
756 * to the hardware. Multicast frames buffered for power
757 * save stations and transmit from the CAB queue are stored
758 * on a s/w only queue and loaded on to the CAB queue in
759 * the SWBA handler since frames only go out on DTIM and
760 * to avoid possible races.
761 */
762 ATH_TX_LOCK_ASSERT(sc);
763 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
764 ("%s: busy status 0x%x", __func__, bf->bf_flags));
765 KASSERT(txq->axq_qnum != ATH_TXQ_SWQ,
766 ("ath_tx_handoff_hw called for mcast queue"));
767
768 /*
769 * XXX racy, should hold the PCU lock when checking this,
770 * and also should ensure that the TX counter is >0!
771 */
772 KASSERT((sc->sc_inreset_cnt == 0),
773 ("%s: TX during reset?\n", __func__));
774
775#if 0
776 /*
777 * This causes a LOR. Find out where the PCU lock is being
778 * held whilst the TXQ lock is grabbed - that shouldn't
779 * be occuring.
780 */
781 ATH_PCU_LOCK(sc);
782 if (sc->sc_inreset_cnt) {
783 ATH_PCU_UNLOCK(sc);
784 DPRINTF(sc, ATH_DEBUG_RESET,
785 "%s: called with sc_in_reset != 0\n",
786 __func__);
787 DPRINTF(sc, ATH_DEBUG_XMIT,
788 "%s: queued: TXDP[%u] = %p (%p) depth %d\n",
789 __func__, txq->axq_qnum,
790 (caddr_t)bf->bf_daddr, bf->bf_desc,
791 txq->axq_depth);
792 /* XXX axq_link needs to be set and updated! */
793 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
794 if (bf->bf_state.bfs_aggr)
795 txq->axq_aggr_depth++;
796 return;
797 }
798 ATH_PCU_UNLOCK(sc);
799#endif
800
801 ATH_TXQ_LOCK(txq);
802
803 /*
804 * XXX TODO: if there's a holdingbf, then
805 * ATH_TXQ_PUTRUNNING should be clear.
806 *
807 * If there is a holdingbf and the list is empty,
808 * then axq_link should be pointing to the holdingbf.
809 *
810 * Otherwise it should point to the last descriptor
811 * in the last ath_buf.
812 *
813 * In any case, we should really ensure that we
814 * update the previous descriptor link pointer to
815 * this descriptor, regardless of all of the above state.
816 *
817 * For now this is captured by having axq_link point
818 * to either the holdingbf (if the TXQ list is empty)
819 * or the end of the list (if the TXQ list isn't empty.)
820 * I'd rather just kill axq_link here and do it as above.
821 */
822
823 /*
824 * Append the frame to the TX queue.
825 */
826 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
827 ATH_KTR(sc, ATH_KTR_TX, 3,
828 "ath_tx_handoff: non-tdma: txq=%u, add bf=%p "
829 "depth=%d",
830 txq->axq_qnum,
831 bf,
832 txq->axq_depth);
833
834 /*
835 * If there's a link pointer, update it.
836 *
837 * XXX we should replace this with the above logic, just
838 * to kill axq_link with fire.
839 */
840 if (txq->axq_link != NULL) {
841 *txq->axq_link = bf->bf_daddr;
842 DPRINTF(sc, ATH_DEBUG_XMIT,
843 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
844 txq->axq_qnum, txq->axq_link,
845 (caddr_t)bf->bf_daddr, bf->bf_desc,
846 txq->axq_depth);
847 ATH_KTR(sc, ATH_KTR_TX, 5,
848 "ath_tx_handoff: non-tdma: link[%u](%p)=%p (%p) "
849 "lastds=%d",
850 txq->axq_qnum, txq->axq_link,
851 (caddr_t)bf->bf_daddr, bf->bf_desc,
852 bf->bf_lastds);
853 }
854
855 /*
856 * If we've not pushed anything into the hardware yet,
857 * push the head of the queue into the TxDP.
858 *
859 * Once we've started DMA, there's no guarantee that
860 * updating the TxDP with a new value will actually work.
861 * So we just don't do that - if we hit the end of the list,
862 * we keep that buffer around (the "holding buffer") and
863 * re-start DMA by updating the link pointer of _that_
864 * descriptor and then restart DMA.
865 */
866 if (! (txq->axq_flags & ATH_TXQ_PUTRUNNING)) {
867 bf_first = TAILQ_FIRST(&txq->axq_q);
868 txq->axq_flags |= ATH_TXQ_PUTRUNNING;
869 ath_hal_puttxbuf(ah, txq->axq_qnum, bf_first->bf_daddr);
870 DPRINTF(sc, ATH_DEBUG_XMIT,
871 "%s: TXDP[%u] = %p (%p) depth %d\n",
872 __func__, txq->axq_qnum,
873 (caddr_t)bf_first->bf_daddr, bf_first->bf_desc,
874 txq->axq_depth);
875 ATH_KTR(sc, ATH_KTR_TX, 5,
876 "ath_tx_handoff: TXDP[%u] = %p (%p) "
877 "lastds=%p depth %d",
878 txq->axq_qnum,
879 (caddr_t)bf_first->bf_daddr, bf_first->bf_desc,
880 bf_first->bf_lastds,
881 txq->axq_depth);
882 }
883
884 /*
885 * Ensure that the bf TXQ matches this TXQ, so later
886 * checking and holding buffer manipulation is sane.
887 */
888 if (bf->bf_state.bfs_tx_queue != txq->axq_qnum) {
889 DPRINTF(sc, ATH_DEBUG_XMIT,
890 "%s: bf=%p, bfs_tx_queue=%d, axq_qnum=%d\n",
891 __func__, bf, bf->bf_state.bfs_tx_queue,
892 txq->axq_qnum);
893 }
894
895 /*
896 * Track aggregate queue depth.
897 */
898 if (bf->bf_state.bfs_aggr)
899 txq->axq_aggr_depth++;
900
901 /*
902 * Update the link pointer.
903 */
904 ath_hal_gettxdesclinkptr(ah, bf->bf_lastds, &txq->axq_link);
905
906 /*
907 * Start DMA.
908 *
909 * If we wrote a TxDP above, DMA will start from here.
910 *
911 * If DMA is running, it'll do nothing.
912 *
913 * If the DMA engine hit the end of the QCU list (ie LINK=NULL,
914 * or VEOL) then it stops at the last transmitted write.
915 * We then append a new frame by updating the link pointer
916 * in that descriptor and then kick TxE here; it will re-read
917 * that last descriptor and find the new descriptor to transmit.
918 *
919 * This is why we keep the holding descriptor around.
920 */
921 ath_hal_txstart(ah, txq->axq_qnum);
922 ATH_TXQ_UNLOCK(txq);
923 ATH_KTR(sc, ATH_KTR_TX, 1,
924 "ath_tx_handoff: txq=%u, txstart", txq->axq_qnum);
925}
926
927/*
928 * Restart TX DMA for the given TXQ.
929 *
930 * This must be called whether the queue is empty or not.
931 */
932static void
933ath_legacy_tx_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
934{
935 struct ath_buf *bf, *bf_last;
936
937 ATH_TXQ_LOCK_ASSERT(txq);
938
939 /* XXX make this ATH_TXQ_FIRST */
940 bf = TAILQ_FIRST(&txq->axq_q);
941 bf_last = ATH_TXQ_LAST(txq, axq_q_s);
942
943 if (bf == NULL)
944 return;
945
946 DPRINTF(sc, ATH_DEBUG_RESET,
947 "%s: Q%d: bf=%p, bf_last=%p, daddr=0x%08x\n",
948 __func__,
949 txq->axq_qnum,
950 bf,
951 bf_last,
952 (uint32_t) bf->bf_daddr);
953
954#ifdef ATH_DEBUG
955 if (sc->sc_debug & ATH_DEBUG_RESET)
956 ath_tx_dump(sc, txq);
957#endif
958
959 /*
960 * This is called from a restart, so DMA is known to be
961 * completely stopped.
962 */
963 KASSERT((!(txq->axq_flags & ATH_TXQ_PUTRUNNING)),
964 ("%s: Q%d: called with PUTRUNNING=1\n",
965 __func__,
966 txq->axq_qnum));
967
968 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
969 txq->axq_flags |= ATH_TXQ_PUTRUNNING;
970
971 ath_hal_gettxdesclinkptr(sc->sc_ah, bf_last->bf_lastds,
972 &txq->axq_link);
973 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
974}
975
976/*
977 * Hand off a packet to the hardware (or mcast queue.)
978 *
979 * The relevant hardware txq should be locked.
980 */
981static void
982ath_legacy_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
983 struct ath_buf *bf)
984{
985 ATH_TX_LOCK_ASSERT(sc);
986
987#ifdef ATH_DEBUG_ALQ
988 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
989 ath_tx_alq_post(sc, bf);
990#endif
991
992 if (txq->axq_qnum == ATH_TXQ_SWQ)
993 ath_tx_handoff_mcast(sc, txq, bf);
994 else
995 ath_tx_handoff_hw(sc, txq, bf);
996}
997
998static int
999ath_tx_tag_crypto(struct ath_softc *sc, struct ieee80211_node *ni,
1000 struct mbuf *m0, int iswep, int isfrag, int *hdrlen, int *pktlen,
1001 int *keyix)
1002{
1003 DPRINTF(sc, ATH_DEBUG_XMIT,
1004 "%s: hdrlen=%d, pktlen=%d, isfrag=%d, iswep=%d, m0=%p\n",
1005 __func__,
1006 *hdrlen,
1007 *pktlen,
1008 isfrag,
1009 iswep,
1010 m0);
1011
1012 if (iswep) {
1013 const struct ieee80211_cipher *cip;
1014 struct ieee80211_key *k;
1015
1016 /*
1017 * Construct the 802.11 header+trailer for an encrypted
1018 * frame. The only reason this can fail is because of an
1019 * unknown or unsupported cipher/key type.
1020 */
1021 k = ieee80211_crypto_encap(ni, m0);
1022 if (k == NULL) {
1023 /*
1024 * This can happen when the key is yanked after the
1025 * frame was queued. Just discard the frame; the
1026 * 802.11 layer counts failures and provides
1027 * debugging/diagnostics.
1028 */
1029 return (0);
1030 }
1031 /*
1032 * Adjust the packet + header lengths for the crypto
1033 * additions and calculate the h/w key index. When
1034 * a s/w mic is done the frame will have had any mic
1035 * added to it prior to entry so m0->m_pkthdr.len will
1036 * account for it. Otherwise we need to add it to the
1037 * packet length.
1038 */
1039 cip = k->wk_cipher;
1040 (*hdrlen) += cip->ic_header;
1041 (*pktlen) += cip->ic_header + cip->ic_trailer;
1042 /* NB: frags always have any TKIP MIC done in s/w */
1043 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
1044 (*pktlen) += cip->ic_miclen;
1045 (*keyix) = k->wk_keyix;
1046 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
1047 /*
1048 * Use station key cache slot, if assigned.
1049 */
1050 (*keyix) = ni->ni_ucastkey.wk_keyix;
1051 if ((*keyix) == IEEE80211_KEYIX_NONE)
1052 (*keyix) = HAL_TXKEYIX_INVALID;
1053 } else
1054 (*keyix) = HAL_TXKEYIX_INVALID;
1055
1056 return (1);
1057}
1058
1059/*
1060 * Calculate whether interoperability protection is required for
1061 * this frame.
1062 *
1063 * This requires the rate control information be filled in,
1064 * as the protection requirement depends upon the current
1065 * operating mode / PHY.
1066 */
1067static void
1068ath_tx_calc_protection(struct ath_softc *sc, struct ath_buf *bf)
1069{
1070 struct ieee80211_frame *wh;
1071 uint8_t rix;
1072 uint16_t flags;
1073 int shortPreamble;
1074 const HAL_RATE_TABLE *rt = sc->sc_currates;
1075 struct ifnet *ifp = sc->sc_ifp;
1076 struct ieee80211com *ic = ifp->if_l2com;
1077
1078 flags = bf->bf_state.bfs_txflags;
1079 rix = bf->bf_state.bfs_rc[0].rix;
1080 shortPreamble = bf->bf_state.bfs_shpream;
1081 wh = mtod(bf->bf_m, struct ieee80211_frame *);
1082
1083 /*
1084 * If 802.11g protection is enabled, determine whether
1085 * to use RTS/CTS or just CTS. Note that this is only
1086 * done for OFDM unicast frames.
1087 */
1088 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1089 rt->info[rix].phy == IEEE80211_T_OFDM &&
1090 (flags & HAL_TXDESC_NOACK) == 0) {
1091 bf->bf_state.bfs_doprot = 1;
1092 /* XXX fragments must use CCK rates w/ protection */
1093 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1094 flags |= HAL_TXDESC_RTSENA;
1095 } else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1096 flags |= HAL_TXDESC_CTSENA;
1097 }
1098 /*
1099 * For frags it would be desirable to use the
1100 * highest CCK rate for RTS/CTS. But stations
1101 * farther away may detect it at a lower CCK rate
1102 * so use the configured protection rate instead
1103 * (for now).
1104 */
1105 sc->sc_stats.ast_tx_protect++;
1106 }
1107
1108 /*
1109 * If 11n protection is enabled and it's a HT frame,
1110 * enable RTS.
1111 *
1112 * XXX ic_htprotmode or ic_curhtprotmode?
1113 * XXX should it_htprotmode only matter if ic_curhtprotmode
1114 * XXX indicates it's not a HT pure environment?
1115 */
1116 if ((ic->ic_htprotmode == IEEE80211_PROT_RTSCTS) &&
1117 rt->info[rix].phy == IEEE80211_T_HT &&
1118 (flags & HAL_TXDESC_NOACK) == 0) {
1119 flags |= HAL_TXDESC_RTSENA;
1120 sc->sc_stats.ast_tx_htprotect++;
1121 }
1122 bf->bf_state.bfs_txflags = flags;
1123}
1124
1125/*
1126 * Update the frame duration given the currently selected rate.
1127 *
1128 * This also updates the frame duration value, so it will require
1129 * a DMA flush.
1130 */
1131static void
1132ath_tx_calc_duration(struct ath_softc *sc, struct ath_buf *bf)
1133{
1134 struct ieee80211_frame *wh;
1135 uint8_t rix;
1136 uint16_t flags;
1137 int shortPreamble;
1138 struct ath_hal *ah = sc->sc_ah;
1139 const HAL_RATE_TABLE *rt = sc->sc_currates;
1140 int isfrag = bf->bf_m->m_flags & M_FRAG;
1141
1142 flags = bf->bf_state.bfs_txflags;
1143 rix = bf->bf_state.bfs_rc[0].rix;
1144 shortPreamble = bf->bf_state.bfs_shpream;
1145 wh = mtod(bf->bf_m, struct ieee80211_frame *);
1146
1147 /*
1148 * Calculate duration. This logically belongs in the 802.11
1149 * layer but it lacks sufficient information to calculate it.
1150 */
1151 if ((flags & HAL_TXDESC_NOACK) == 0 &&
1152 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
1153 u_int16_t dur;
1154 if (shortPreamble)
1155 dur = rt->info[rix].spAckDuration;
1156 else
1157 dur = rt->info[rix].lpAckDuration;
1158 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
1159 dur += dur; /* additional SIFS+ACK */
1160 /*
1161 * Include the size of next fragment so NAV is
1162 * updated properly. The last fragment uses only
1163 * the ACK duration
1164 *
1165 * XXX TODO: ensure that the rate lookup for each
1166 * fragment is the same as the rate used by the
1167 * first fragment!
1168 */
1169 dur += ath_hal_computetxtime(ah,
1170 rt,
1171 bf->bf_nextfraglen,
1172 rix, shortPreamble);
1173 }
1174 if (isfrag) {
1175 /*
1176 * Force hardware to use computed duration for next
1177 * fragment by disabling multi-rate retry which updates
1178 * duration based on the multi-rate duration table.
1179 */
1180 bf->bf_state.bfs_ismrr = 0;
1181 bf->bf_state.bfs_try0 = ATH_TXMGTTRY;
1182 /* XXX update bfs_rc[0].try? */
1183 }
1184
1185 /* Update the duration field itself */
1186 *(u_int16_t *)wh->i_dur = htole16(dur);
1187 }
1188}
1189
1190static uint8_t
1191ath_tx_get_rtscts_rate(struct ath_hal *ah, const HAL_RATE_TABLE *rt,
1192 int cix, int shortPreamble)
1193{
1194 uint8_t ctsrate;
1195
1196 /*
1197 * CTS transmit rate is derived from the transmit rate
1198 * by looking in the h/w rate table. We must also factor
1199 * in whether or not a short preamble is to be used.
1200 */
1201 /* NB: cix is set above where RTS/CTS is enabled */
1202 KASSERT(cix != 0xff, ("cix not setup"));
1203 ctsrate = rt->info[cix].rateCode;
1204
1205 /* XXX this should only matter for legacy rates */
1206 if (shortPreamble)
1207 ctsrate |= rt->info[cix].shortPreamble;
1208
1209 return (ctsrate);
1210}
1211
1212/*
1213 * Calculate the RTS/CTS duration for legacy frames.
1214 */
1215static int
1216ath_tx_calc_ctsduration(struct ath_hal *ah, int rix, int cix,
1217 int shortPreamble, int pktlen, const HAL_RATE_TABLE *rt,
1218 int flags)
1219{
1220 int ctsduration = 0;
1221
1222 /* This mustn't be called for HT modes */
1223 if (rt->info[cix].phy == IEEE80211_T_HT) {
3133c5e3 1224 kprintf("%s: HT rate where it shouldn't be (0x%x)\n",
572ff6f6
MD
1225 __func__, rt->info[cix].rateCode);
1226 return (-1);
1227 }
1228
1229 /*
1230 * Compute the transmit duration based on the frame
1231 * size and the size of an ACK frame. We call into the
1232 * HAL to do the computation since it depends on the
1233 * characteristics of the actual PHY being used.
1234 *
1235 * NB: CTS is assumed the same size as an ACK so we can
1236 * use the precalculated ACK durations.
1237 */
1238 if (shortPreamble) {
1239 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1240 ctsduration += rt->info[cix].spAckDuration;
1241 ctsduration += ath_hal_computetxtime(ah,
1242 rt, pktlen, rix, AH_TRUE);
1243 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1244 ctsduration += rt->info[rix].spAckDuration;
1245 } else {
1246 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1247 ctsduration += rt->info[cix].lpAckDuration;
1248 ctsduration += ath_hal_computetxtime(ah,
1249 rt, pktlen, rix, AH_FALSE);
1250 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1251 ctsduration += rt->info[rix].lpAckDuration;
1252 }
1253
1254 return (ctsduration);
1255}
1256
1257/*
1258 * Update the given ath_buf with updated rts/cts setup and duration
1259 * values.
1260 *
1261 * To support rate lookups for each software retry, the rts/cts rate
1262 * and cts duration must be re-calculated.
1263 *
1264 * This function assumes the RTS/CTS flags have been set as needed;
1265 * mrr has been disabled; and the rate control lookup has been done.
1266 *
1267 * XXX TODO: MRR need only be disabled for the pre-11n NICs.
1268 * XXX The 11n NICs support per-rate RTS/CTS configuration.
1269 */
1270static void
1271ath_tx_set_rtscts(struct ath_softc *sc, struct ath_buf *bf)
1272{
1273 uint16_t ctsduration = 0;
1274 uint8_t ctsrate = 0;
1275 uint8_t rix = bf->bf_state.bfs_rc[0].rix;
1276 uint8_t cix = 0;
1277 const HAL_RATE_TABLE *rt = sc->sc_currates;
1278
1279 /*
1280 * No RTS/CTS enabled? Don't bother.
1281 */
1282 if ((bf->bf_state.bfs_txflags &
1283 (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) == 0) {
1284 /* XXX is this really needed? */
1285 bf->bf_state.bfs_ctsrate = 0;
1286 bf->bf_state.bfs_ctsduration = 0;
1287 return;
1288 }
1289
1290 /*
1291 * If protection is enabled, use the protection rix control
1292 * rate. Otherwise use the rate0 control rate.
1293 */
1294 if (bf->bf_state.bfs_doprot)
1295 rix = sc->sc_protrix;
1296 else
1297 rix = bf->bf_state.bfs_rc[0].rix;
1298
1299 /*
1300 * If the raw path has hard-coded ctsrate0 to something,
1301 * use it.
1302 */
1303 if (bf->bf_state.bfs_ctsrate0 != 0)
1304 cix = ath_tx_findrix(sc, bf->bf_state.bfs_ctsrate0);
1305 else
1306 /* Control rate from above */
1307 cix = rt->info[rix].controlRate;
1308
1309 /* Calculate the rtscts rate for the given cix */
1310 ctsrate = ath_tx_get_rtscts_rate(sc->sc_ah, rt, cix,
1311 bf->bf_state.bfs_shpream);
1312
1313 /* The 11n chipsets do ctsduration calculations for you */
1314 if (! ath_tx_is_11n(sc))
1315 ctsduration = ath_tx_calc_ctsduration(sc->sc_ah, rix, cix,
1316 bf->bf_state.bfs_shpream, bf->bf_state.bfs_pktlen,
1317 rt, bf->bf_state.bfs_txflags);
1318
1319 /* Squirrel away in ath_buf */
1320 bf->bf_state.bfs_ctsrate = ctsrate;
1321 bf->bf_state.bfs_ctsduration = ctsduration;
1322
1323 /*
1324 * Must disable multi-rate retry when using RTS/CTS.
1325 */
1326 if (!sc->sc_mrrprot) {
1327 bf->bf_state.bfs_ismrr = 0;
1328 bf->bf_state.bfs_try0 =
1329 bf->bf_state.bfs_rc[0].tries = ATH_TXMGTTRY; /* XXX ew */
1330 }
1331}
1332
1333/*
1334 * Setup the descriptor chain for a normal or fast-frame
1335 * frame.
1336 *
1337 * XXX TODO: extend to include the destination hardware QCU ID.
1338 * Make sure that is correct. Make sure that when being added
1339 * to the mcastq, the CABQ QCUID is set or things will get a bit
1340 * odd.
1341 */
1342static void
1343ath_tx_setds(struct ath_softc *sc, struct ath_buf *bf)
1344{
1345 struct ath_desc *ds = bf->bf_desc;
1346 struct ath_hal *ah = sc->sc_ah;
1347
1348 if (bf->bf_state.bfs_txrate0 == 0)
1349 DPRINTF(sc, ATH_DEBUG_XMIT,
1350 "%s: bf=%p, txrate0=%d\n", __func__, bf, 0);
1351
1352 ath_hal_setuptxdesc(ah, ds
1353 , bf->bf_state.bfs_pktlen /* packet length */
1354 , bf->bf_state.bfs_hdrlen /* header length */
1355 , bf->bf_state.bfs_atype /* Atheros packet type */
1356 , bf->bf_state.bfs_txpower /* txpower */
1357 , bf->bf_state.bfs_txrate0
1358 , bf->bf_state.bfs_try0 /* series 0 rate/tries */
1359 , bf->bf_state.bfs_keyix /* key cache index */
1360 , bf->bf_state.bfs_txantenna /* antenna mode */
1361 , bf->bf_state.bfs_txflags /* flags */
1362 , bf->bf_state.bfs_ctsrate /* rts/cts rate */
1363 , bf->bf_state.bfs_ctsduration /* rts/cts duration */
1364 );
1365
1366 /*
1367 * This will be overriden when the descriptor chain is written.
1368 */
1369 bf->bf_lastds = ds;
1370 bf->bf_last = bf;
1371
1372 /* Set rate control and descriptor chain for this frame */
1373 ath_tx_set_ratectrl(sc, bf->bf_node, bf);
1374 ath_tx_chaindesclist(sc, ds, bf, 0, 0, 0);
1375}
1376
1377/*
1378 * Do a rate lookup.
1379 *
1380 * This performs a rate lookup for the given ath_buf only if it's required.
1381 * Non-data frames and raw frames don't require it.
1382 *
1383 * This populates the primary and MRR entries; MRR values are
1384 * then disabled later on if something requires it (eg RTS/CTS on
1385 * pre-11n chipsets.
1386 *
1387 * This needs to be done before the RTS/CTS fields are calculated
1388 * as they may depend upon the rate chosen.
1389 */
1390static void
1391ath_tx_do_ratelookup(struct ath_softc *sc, struct ath_buf *bf)
1392{
1393 uint8_t rate, rix;
1394 int try0;
1395
1396 if (! bf->bf_state.bfs_doratelookup)
1397 return;
1398
1399 /* Get rid of any previous state */
1400 bzero(bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1401
1402 ATH_NODE_LOCK(ATH_NODE(bf->bf_node));
1403 ath_rate_findrate(sc, ATH_NODE(bf->bf_node), bf->bf_state.bfs_shpream,
1404 bf->bf_state.bfs_pktlen, &rix, &try0, &rate);
1405
1406 /* In case MRR is disabled, make sure rc[0] is setup correctly */
1407 bf->bf_state.bfs_rc[0].rix = rix;
1408 bf->bf_state.bfs_rc[0].ratecode = rate;
1409 bf->bf_state.bfs_rc[0].tries = try0;
1410
1411 if (bf->bf_state.bfs_ismrr && try0 != ATH_TXMAXTRY)
1412 ath_rate_getxtxrates(sc, ATH_NODE(bf->bf_node), rix,
1413 bf->bf_state.bfs_rc);
1414 ATH_NODE_UNLOCK(ATH_NODE(bf->bf_node));
1415
1416 sc->sc_txrix = rix; /* for LED blinking */
1417 sc->sc_lastdatarix = rix; /* for fast frames */
1418 bf->bf_state.bfs_try0 = try0;
1419 bf->bf_state.bfs_txrate0 = rate;
1420}
1421
1422/*
1423 * Update the CLRDMASK bit in the ath_buf if it needs to be set.
1424 */
1425static void
1426ath_tx_update_clrdmask(struct ath_softc *sc, struct ath_tid *tid,
1427 struct ath_buf *bf)
1428{
1429 struct ath_node *an = ATH_NODE(bf->bf_node);
1430
1431 ATH_TX_LOCK_ASSERT(sc);
1432
1433 if (an->clrdmask == 1) {
1434 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
1435 an->clrdmask = 0;
1436 }
1437}
1438
1439/*
1440 * Return whether this frame should be software queued or
1441 * direct dispatched.
1442 *
1443 * When doing powersave, BAR frames should be queued but other management
1444 * frames should be directly sent.
1445 *
1446 * When not doing powersave, stick BAR frames into the hardware queue
1447 * so it goes out even though the queue is paused.
1448 *
1449 * For now, management frames are also software queued by default.
1450 */
1451static int
1452ath_tx_should_swq_frame(struct ath_softc *sc, struct ath_node *an,
1453 struct mbuf *m0, int *queue_to_head)
1454{
1455 struct ieee80211_node *ni = &an->an_node;
1456 struct ieee80211_frame *wh;
1457 uint8_t type, subtype;
1458
1459 wh = mtod(m0, struct ieee80211_frame *);
1460 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1461 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1462
1463 (*queue_to_head) = 0;
1464
1465 /* If it's not in powersave - direct-dispatch BAR */
1466 if ((ATH_NODE(ni)->an_is_powersave == 0)
1467 && type == IEEE80211_FC0_TYPE_CTL &&
1468 subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1469 DPRINTF(sc, ATH_DEBUG_SW_TX,
1470 "%s: BAR: TX'ing direct\n", __func__);
1471 return (0);
1472 } else if ((ATH_NODE(ni)->an_is_powersave == 1)
1473 && type == IEEE80211_FC0_TYPE_CTL &&
1474 subtype == IEEE80211_FC0_SUBTYPE_BAR) {
1475 /* BAR TX whilst asleep; queue */
1476 DPRINTF(sc, ATH_DEBUG_SW_TX,
1477 "%s: swq: TX'ing\n", __func__);
1478 (*queue_to_head) = 1;
1479 return (1);
1480 } else if ((ATH_NODE(ni)->an_is_powersave == 1)
1481 && (type == IEEE80211_FC0_TYPE_MGT ||
1482 type == IEEE80211_FC0_TYPE_CTL)) {
1483 /*
1484 * Other control/mgmt frame; bypass software queuing
1485 * for now!
1486 */
1487 DPRINTF(sc, ATH_DEBUG_XMIT,
1488 "%s: %6D: Node is asleep; sending mgmt "
1489 "(type=%d, subtype=%d)\n",
1490 __func__, ni->ni_macaddr, ":", type, subtype);
1491 return (0);
1492 } else {
1493 return (1);
1494 }
1495}
1496
1497
1498/*
1499 * Transmit the given frame to the hardware.
1500 *
1501 * The frame must already be setup; rate control must already have
1502 * been done.
1503 *
1504 * XXX since the TXQ lock is being held here (and I dislike holding
1505 * it for this long when not doing software aggregation), later on
1506 * break this function into "setup_normal" and "xmit_normal". The
1507 * lock only needs to be held for the ath_tx_handoff call.
1508 *
1509 * XXX we don't update the leak count here - if we're doing
1510 * direct frame dispatch, we need to be able to do it without
1511 * decrementing the leak count (eg multicast queue frames.)
1512 */
1513static void
1514ath_tx_xmit_normal(struct ath_softc *sc, struct ath_txq *txq,
1515 struct ath_buf *bf)
1516{
1517 struct ath_node *an = ATH_NODE(bf->bf_node);
1518 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
1519
1520 ATH_TX_LOCK_ASSERT(sc);
1521
1522 /*
1523 * For now, just enable CLRDMASK. ath_tx_xmit_normal() does
1524 * set a completion handler however it doesn't (yet) properly
1525 * handle the strict ordering requirements needed for normal,
1526 * non-aggregate session frames.
1527 *
1528 * Once this is implemented, only set CLRDMASK like this for
1529 * frames that must go out - eg management/raw frames.
1530 */
1531 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
1532
1533 /* Setup the descriptor before handoff */
1534 ath_tx_do_ratelookup(sc, bf);
1535 ath_tx_calc_duration(sc, bf);
1536 ath_tx_calc_protection(sc, bf);
1537 ath_tx_set_rtscts(sc, bf);
1538 ath_tx_rate_fill_rcflags(sc, bf);
1539 ath_tx_setds(sc, bf);
1540
1541 /* Track per-TID hardware queue depth correctly */
1542 tid->hwq_depth++;
1543
1544 /* Assign the completion handler */
1545 bf->bf_comp = ath_tx_normal_comp;
1546
1547 /* Hand off to hardware */
1548 ath_tx_handoff(sc, txq, bf);
1549}
1550
1551/*
1552 * Do the basic frame setup stuff that's required before the frame
1553 * is added to a software queue.
1554 *
1555 * All frames get mostly the same treatment and it's done once.
1556 * Retransmits fiddle with things like the rate control setup,
1557 * setting the retransmit bit in the packet; doing relevant DMA/bus
1558 * syncing and relinking it (back) into the hardware TX queue.
1559 *
1560 * Note that this may cause the mbuf to be reallocated, so
1561 * m0 may not be valid.
1562 */
1563static int
1564ath_tx_normal_setup(struct ath_softc *sc, struct ieee80211_node *ni,
1565 struct ath_buf *bf, struct mbuf *m0, struct ath_txq *txq)
1566{
1567 struct ieee80211vap *vap = ni->ni_vap;
1568 struct ath_hal *ah = sc->sc_ah;
1569 struct ifnet *ifp = sc->sc_ifp;
1570 struct ieee80211com *ic = ifp->if_l2com;
1571 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
1572 int error, iswep, ismcast, isfrag, ismrr;
1573 int keyix, hdrlen, pktlen, try0 = 0;
1574 u_int8_t rix = 0, txrate = 0;
1575 struct ath_desc *ds;
1576 struct ieee80211_frame *wh;
1577 u_int subtype, flags;
1578 HAL_PKT_TYPE atype;
1579 const HAL_RATE_TABLE *rt;
1580 HAL_BOOL shortPreamble;
1581 struct ath_node *an;
1582 u_int pri;
1583
1584 /*
1585 * To ensure that both sequence numbers and the CCMP PN handling
1586 * is "correct", make sure that the relevant TID queue is locked.
1587 * Otherwise the CCMP PN and seqno may appear out of order, causing
1588 * re-ordered frames to have out of order CCMP PN's, resulting
1589 * in many, many frame drops.
1590 */
1591 ATH_TX_LOCK_ASSERT(sc);
1592
1593 wh = mtod(m0, struct ieee80211_frame *);
1594 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1595 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1596 isfrag = m0->m_flags & M_FRAG;
1597 hdrlen = ieee80211_anyhdrsize(wh);
1598 /*
1599 * Packet length must not include any
1600 * pad bytes; deduct them here.
1601 */
1602 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
1603
1604 /* Handle encryption twiddling if needed */
1605 if (! ath_tx_tag_crypto(sc, ni, m0, iswep, isfrag, &hdrlen,
1606 &pktlen, &keyix)) {
1607 ath_freetx(m0);
1608 return EIO;
1609 }
1610
1611 /* packet header may have moved, reset our local pointer */
1612 wh = mtod(m0, struct ieee80211_frame *);
1613
1614 pktlen += IEEE80211_CRC_LEN;
1615
1616 /*
1617 * Load the DMA map so any coalescing is done. This
1618 * also calculates the number of descriptors we need.
1619 */
1620 error = ath_tx_dmasetup(sc, bf, m0);
1621 if (error != 0)
1622 return error;
1623 bf->bf_node = ni; /* NB: held reference */
1624 m0 = bf->bf_m; /* NB: may have changed */
1625 wh = mtod(m0, struct ieee80211_frame *);
1626
1627 /* setup descriptors */
1628 ds = bf->bf_desc;
1629 rt = sc->sc_currates;
1630 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
1631
1632 /*
1633 * NB: the 802.11 layer marks whether or not we should
1634 * use short preamble based on the current mode and
1635 * negotiated parameters.
1636 */
1637 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1638 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
1639 shortPreamble = AH_TRUE;
1640 sc->sc_stats.ast_tx_shortpre++;
1641 } else {
1642 shortPreamble = AH_FALSE;
1643 }
1644
1645 an = ATH_NODE(ni);
1646 //flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
1647 flags = 0;
1648 ismrr = 0; /* default no multi-rate retry*/
1649 pri = M_WME_GETAC(m0); /* honor classification */
1650 /* XXX use txparams instead of fixed values */
1651 /*
1652 * Calculate Atheros packet type from IEEE80211 packet header,
1653 * setup for rate calculations, and select h/w transmit queue.
1654 */
1655 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1656 case IEEE80211_FC0_TYPE_MGT:
1657 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1658 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
1659 atype = HAL_PKT_TYPE_BEACON;
1660 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1661 atype = HAL_PKT_TYPE_PROBE_RESP;
1662 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1663 atype = HAL_PKT_TYPE_ATIM;
1664 else
1665 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
1666 rix = an->an_mgmtrix;
1667 txrate = rt->info[rix].rateCode;
1668 if (shortPreamble)
1669 txrate |= rt->info[rix].shortPreamble;
1670 try0 = ATH_TXMGTTRY;
1671 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1672 break;
1673 case IEEE80211_FC0_TYPE_CTL:
1674 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
1675 rix = an->an_mgmtrix;
1676 txrate = rt->info[rix].rateCode;
1677 if (shortPreamble)
1678 txrate |= rt->info[rix].shortPreamble;
1679 try0 = ATH_TXMGTTRY;
1680 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
1681 break;
1682 case IEEE80211_FC0_TYPE_DATA:
1683 atype = HAL_PKT_TYPE_NORMAL; /* default */
1684 /*
1685 * Data frames: multicast frames go out at a fixed rate,
1686 * EAPOL frames use the mgmt frame rate; otherwise consult
1687 * the rate control module for the rate to use.
1688 */
1689 if (ismcast) {
1690 rix = an->an_mcastrix;
1691 txrate = rt->info[rix].rateCode;
1692 if (shortPreamble)
1693 txrate |= rt->info[rix].shortPreamble;
1694 try0 = 1;
1695 } else if (m0->m_flags & M_EAPOL) {
1696 /* XXX? maybe always use long preamble? */
1697 rix = an->an_mgmtrix;
1698 txrate = rt->info[rix].rateCode;
1699 if (shortPreamble)
1700 txrate |= rt->info[rix].shortPreamble;
1701 try0 = ATH_TXMAXTRY; /* XXX?too many? */
1702 } else {
1703 /*
1704 * Do rate lookup on each TX, rather than using
1705 * the hard-coded TX information decided here.
1706 */
1707 ismrr = 1;
1708 bf->bf_state.bfs_doratelookup = 1;
1709 }
1710 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
1711 flags |= HAL_TXDESC_NOACK;
1712 break;
1713 default:
1714 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
1715 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
1716 /* XXX statistic */
1717 /* XXX free tx dmamap */
1718 ath_freetx(m0);
1719 return EIO;
1720 }
1721
1722 /*
1723 * There are two known scenarios where the frame AC doesn't match
1724 * what the destination TXQ is.
1725 *
1726 * + non-QoS frames (eg management?) that the net80211 stack has
1727 * assigned a higher AC to, but since it's a non-QoS TID, it's
1728 * being thrown into TID 16. TID 16 gets the AC_BE queue.
1729 * It's quite possible that management frames should just be
1730 * direct dispatched to hardware rather than go via the software
1731 * queue; that should be investigated in the future. There are
1732 * some specific scenarios where this doesn't make sense, mostly
1733 * surrounding ADDBA request/response - hence why that is special
1734 * cased.
1735 *
1736 * + Multicast frames going into the VAP mcast queue. That shows up
1737 * as "TXQ 11".
1738 *
1739 * This driver should eventually support separate TID and TXQ locking,
1740 * allowing for arbitrary AC frames to appear on arbitrary software
1741 * queues, being queued to the "correct" hardware queue when needed.
1742 */
1743#if 0
1744 if (txq != sc->sc_ac2q[pri]) {
1745 DPRINTF(sc, ATH_DEBUG_XMIT,
1746 "%s: txq=%p (%d), pri=%d, pri txq=%p (%d)\n",
1747 __func__,
1748 txq,
1749 txq->axq_qnum,
1750 pri,
1751 sc->sc_ac2q[pri],
1752 sc->sc_ac2q[pri]->axq_qnum);
1753 }
1754#endif
1755
1756 /*
1757 * Calculate miscellaneous flags.
1758 */
1759 if (ismcast) {
1760 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
1761 } else if (pktlen > vap->iv_rtsthreshold &&
1762 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
1763 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
1764 sc->sc_stats.ast_tx_rts++;
1765 }
1766 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
1767 sc->sc_stats.ast_tx_noack++;
1768#ifdef IEEE80211_SUPPORT_TDMA
1769 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
1770 DPRINTF(sc, ATH_DEBUG_TDMA,
1771 "%s: discard frame, ACK required w/ TDMA\n", __func__);
1772 sc->sc_stats.ast_tdma_ack++;
1773 /* XXX free tx dmamap */
1774 ath_freetx(m0);
1775 return EIO;
1776 }
1777#endif
1778
1779 /*
1780 * Determine if a tx interrupt should be generated for
1781 * this descriptor. We take a tx interrupt to reap
1782 * descriptors when the h/w hits an EOL condition or
1783 * when the descriptor is specifically marked to generate
1784 * an interrupt. We periodically mark descriptors in this
1785 * way to insure timely replenishing of the supply needed
1786 * for sending frames. Defering interrupts reduces system
1787 * load and potentially allows more concurrent work to be
1788 * done but if done to aggressively can cause senders to
1789 * backup.
1790 *
1791 * NB: use >= to deal with sc_txintrperiod changing
1792 * dynamically through sysctl.
1793 */
1794 if (flags & HAL_TXDESC_INTREQ) {
1795 txq->axq_intrcnt = 0;
1796 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
1797 flags |= HAL_TXDESC_INTREQ;
1798 txq->axq_intrcnt = 0;
1799 }
1800
1801 /* This point forward is actual TX bits */
1802
1803 /*
1804 * At this point we are committed to sending the frame
1805 * and we don't need to look at m_nextpkt; clear it in
1806 * case this frame is part of frag chain.
1807 */
1808 m0->m_nextpkt = NULL;
1809
1810 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
1811 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
1812 sc->sc_hwmap[rix].ieeerate, -1);
1813
1814 if (ieee80211_radiotap_active_vap(vap)) {
1815 u_int64_t tsf = ath_hal_gettsf64(ah);
1816
1817 sc->sc_tx_th.wt_tsf = htole64(tsf);
1818 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
1819 if (iswep)
1820 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
1821 if (isfrag)
1822 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
1823 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
1824 sc->sc_tx_th.wt_txpower = ieee80211_get_node_txpower(ni);
1825 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
1826
1827 ieee80211_radiotap_tx(vap, m0);
1828 }
1829
1830 /* Blank the legacy rate array */
1831 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
1832
1833 /*
1834 * ath_buf_set_rate needs at least one rate/try to setup
1835 * the rate scenario.
1836 */
1837 bf->bf_state.bfs_rc[0].rix = rix;
1838 bf->bf_state.bfs_rc[0].tries = try0;
1839 bf->bf_state.bfs_rc[0].ratecode = txrate;
1840
1841 /* Store the decided rate index values away */
1842 bf->bf_state.bfs_pktlen = pktlen;
1843 bf->bf_state.bfs_hdrlen = hdrlen;
1844 bf->bf_state.bfs_atype = atype;
1845 bf->bf_state.bfs_txpower = ieee80211_get_node_txpower(ni);
1846 bf->bf_state.bfs_txrate0 = txrate;
1847 bf->bf_state.bfs_try0 = try0;
1848 bf->bf_state.bfs_keyix = keyix;
1849 bf->bf_state.bfs_txantenna = sc->sc_txantenna;
1850 bf->bf_state.bfs_txflags = flags;
1851 bf->bf_state.bfs_shpream = shortPreamble;
1852
1853 /* XXX this should be done in ath_tx_setrate() */
1854 bf->bf_state.bfs_ctsrate0 = 0; /* ie, no hard-coded ctsrate */
1855 bf->bf_state.bfs_ctsrate = 0; /* calculated later */
1856 bf->bf_state.bfs_ctsduration = 0;
1857 bf->bf_state.bfs_ismrr = ismrr;
1858
1859 return 0;
1860}
1861
1862/*
1863 * Queue a frame to the hardware or software queue.
1864 *
1865 * This can be called by the net80211 code.
1866 *
1867 * XXX what about locking? Or, push the seqno assign into the
1868 * XXX aggregate scheduler so its serialised?
1869 *
1870 * XXX When sending management frames via ath_raw_xmit(),
1871 * should CLRDMASK be set unconditionally?
1872 */
1873int
1874ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
1875 struct ath_buf *bf, struct mbuf *m0)
1876{
1877 struct ieee80211vap *vap = ni->ni_vap;
1878 struct ath_vap *avp = ATH_VAP(vap);
1879 int r = 0;
1880 u_int pri;
1881 int tid;
1882 struct ath_txq *txq;
1883 int ismcast;
1884 const struct ieee80211_frame *wh;
1885 int is_ampdu, is_ampdu_tx, is_ampdu_pending;
1886 ieee80211_seq seqno;
1887 uint8_t type, subtype;
1888 int queue_to_head;
1889
1890 ATH_TX_LOCK_ASSERT(sc);
1891
1892 /*
1893 * Determine the target hardware queue.
1894 *
1895 * For multicast frames, the txq gets overridden appropriately
1896 * depending upon the state of PS.
1897 *
1898 * For any other frame, we do a TID/QoS lookup inside the frame
1899 * to see what the TID should be. If it's a non-QoS frame, the
1900 * AC and TID are overridden. The TID/TXQ code assumes the
1901 * TID is on a predictable hardware TXQ, so we don't support
1902 * having a node TID queued to multiple hardware TXQs.
1903 * This may change in the future but would require some locking
1904 * fudgery.
1905 */
1906 pri = ath_tx_getac(sc, m0);
1907 tid = ath_tx_gettid(sc, m0);
1908
1909 txq = sc->sc_ac2q[pri];
1910 wh = mtod(m0, struct ieee80211_frame *);
1911 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1912 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1913 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1914
1915 /*
1916 * Enforce how deep the multicast queue can grow.
1917 *
1918 * XXX duplicated in ath_raw_xmit().
1919 */
1920 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1921 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth
1922 > sc->sc_txq_mcastq_maxdepth) {
1923 sc->sc_stats.ast_tx_mcastq_overflow++;
1924 m_freem(m0);
1925 return (ENOBUFS);
1926 }
1927 }
1928
1929 /*
1930 * Enforce how deep the unicast queue can grow.
1931 *
1932 * If the node is in power save then we don't want
1933 * the software queue to grow too deep, or a node may
1934 * end up consuming all of the ath_buf entries.
1935 *
1936 * For now, only do this for DATA frames.
1937 *
1938 * We will want to cap how many management/control
1939 * frames get punted to the software queue so it doesn't
1940 * fill up. But the correct solution isn't yet obvious.
1941 * In any case, this check should at least let frames pass
1942 * that we are direct-dispatching.
1943 *
1944 * XXX TODO: duplicate this to the raw xmit path!
1945 */
1946 if (type == IEEE80211_FC0_TYPE_DATA &&
1947 ATH_NODE(ni)->an_is_powersave &&
1948 ATH_NODE(ni)->an_swq_depth >
1949 sc->sc_txq_node_psq_maxdepth) {
1950 sc->sc_stats.ast_tx_node_psq_overflow++;
1951 m_freem(m0);
1952 return (ENOBUFS);
1953 }
1954
1955 /* A-MPDU TX */
1956 is_ampdu_tx = ath_tx_ampdu_running(sc, ATH_NODE(ni), tid);
1957 is_ampdu_pending = ath_tx_ampdu_pending(sc, ATH_NODE(ni), tid);
1958 is_ampdu = is_ampdu_tx | is_ampdu_pending;
1959
1960 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: tid=%d, ac=%d, is_ampdu=%d\n",
1961 __func__, tid, pri, is_ampdu);
1962
1963 /* Set local packet state, used to queue packets to hardware */
1964 bf->bf_state.bfs_tid = tid;
1965 bf->bf_state.bfs_tx_queue = txq->axq_qnum;
1966 bf->bf_state.bfs_pri = pri;
1967
1968#if 1
1969 /*
1970 * When servicing one or more stations in power-save mode
1971 * (or) if there is some mcast data waiting on the mcast
1972 * queue (to prevent out of order delivery) multicast frames
1973 * must be bufferd until after the beacon.
1974 *
1975 * TODO: we should lock the mcastq before we check the length.
1976 */
1977 if (sc->sc_cabq_enable && ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth)) {
1978 txq = &avp->av_mcastq;
1979 /*
1980 * Mark the frame as eventually belonging on the CAB
1981 * queue, so the descriptor setup functions will
1982 * correctly initialise the descriptor 'qcuId' field.
1983 */
1984 bf->bf_state.bfs_tx_queue = sc->sc_cabq->axq_qnum;
1985 }
1986#endif
1987
1988 /* Do the generic frame setup */
1989 /* XXX should just bzero the bf_state? */
1990 bf->bf_state.bfs_dobaw = 0;
1991
1992 /* A-MPDU TX? Manually set sequence number */
1993 /*
1994 * Don't do it whilst pending; the net80211 layer still
1995 * assigns them.
1996 */
1997 if (is_ampdu_tx) {
1998 /*
1999 * Always call; this function will
2000 * handle making sure that null data frames
2001 * don't get a sequence number from the current
2002 * TID and thus mess with the BAW.
2003 */
2004 seqno = ath_tx_tid_seqno_assign(sc, ni, bf, m0);
2005
2006 /*
2007 * Don't add QoS NULL frames to the BAW.
2008 */
2009 if (IEEE80211_QOS_HAS_SEQ(wh) &&
2010 subtype != IEEE80211_FC0_SUBTYPE_QOS_NULL) {
2011 bf->bf_state.bfs_dobaw = 1;
2012 }
2013 }
2014
2015 /*
2016 * If needed, the sequence number has been assigned.
2017 * Squirrel it away somewhere easy to get to.
2018 */
2019 bf->bf_state.bfs_seqno = M_SEQNO_GET(m0) << IEEE80211_SEQ_SEQ_SHIFT;
2020
2021 /* Is ampdu pending? fetch the seqno and print it out */
2022 if (is_ampdu_pending)
2023 DPRINTF(sc, ATH_DEBUG_SW_TX,
2024 "%s: tid %d: ampdu pending, seqno %d\n",
2025 __func__, tid, M_SEQNO_GET(m0));
2026
2027 /* This also sets up the DMA map */
2028 r = ath_tx_normal_setup(sc, ni, bf, m0, txq);
2029
2030 if (r != 0)
2031 goto done;
2032
2033 /* At this point m0 could have changed! */
2034 m0 = bf->bf_m;
2035
2036#if 1
2037 /*
2038 * If it's a multicast frame, do a direct-dispatch to the
2039 * destination hardware queue. Don't bother software
2040 * queuing it.
2041 */
2042 /*
2043 * If it's a BAR frame, do a direct dispatch to the
2044 * destination hardware queue. Don't bother software
2045 * queuing it, as the TID will now be paused.
2046 * Sending a BAR frame can occur from the net80211 txa timer
2047 * (ie, retries) or from the ath txtask (completion call.)
2048 * It queues directly to hardware because the TID is paused
2049 * at this point (and won't be unpaused until the BAR has
2050 * either been TXed successfully or max retries has been
2051 * reached.)
2052 */
2053 /*
2054 * Until things are better debugged - if this node is asleep
2055 * and we're sending it a non-BAR frame, direct dispatch it.
2056 * Why? Because we need to figure out what's actually being
2057 * sent - eg, during reassociation/reauthentication after
2058 * the node (last) disappeared whilst asleep, the driver should
2059 * have unpaused/unsleep'ed the node. So until that is
2060 * sorted out, use this workaround.
2061 */
2062 if (txq == &avp->av_mcastq) {
2063 DPRINTF(sc, ATH_DEBUG_SW_TX,
2064 "%s: bf=%p: mcastq: TX'ing\n", __func__, bf);
2065 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2066 ath_tx_xmit_normal(sc, txq, bf);
2067 } else if (ath_tx_should_swq_frame(sc, ATH_NODE(ni), m0,
2068 &queue_to_head)) {
2069 ath_tx_swq(sc, ni, txq, queue_to_head, bf);
2070 } else {
2071 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2072 ath_tx_xmit_normal(sc, txq, bf);
2073 }
2074#else
2075 /*
2076 * For now, since there's no software queue,
2077 * direct-dispatch to the hardware.
2078 */
2079 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2080 /*
2081 * Update the current leak count if
2082 * we're leaking frames; and set the
2083 * MORE flag as appropriate.
2084 */
2085 ath_tx_leak_count_update(sc, tid, bf);
2086 ath_tx_xmit_normal(sc, txq, bf);
2087#endif
2088done:
2089 return 0;
2090}
2091
2092static int
2093ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
2094 struct ath_buf *bf, struct mbuf *m0,
2095 const struct ieee80211_bpf_params *params)
2096{
2097 struct ifnet *ifp = sc->sc_ifp;
2098 struct ieee80211com *ic = ifp->if_l2com;
2099 struct ath_hal *ah = sc->sc_ah;
2100 struct ieee80211vap *vap = ni->ni_vap;
2101 int error, ismcast, ismrr;
2102 int keyix, hdrlen, pktlen, try0, txantenna;
2103 u_int8_t rix, txrate;
2104 struct ieee80211_frame *wh;
2105 u_int flags;
2106 HAL_PKT_TYPE atype;
2107 const HAL_RATE_TABLE *rt;
2108 struct ath_desc *ds;
2109 u_int pri;
2110 int o_tid = -1;
2111 int do_override;
2112 uint8_t type, subtype;
2113 int queue_to_head;
2114
2115 ATH_TX_LOCK_ASSERT(sc);
2116
2117 wh = mtod(m0, struct ieee80211_frame *);
2118 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2119 hdrlen = ieee80211_anyhdrsize(wh);
2120 /*
2121 * Packet length must not include any
2122 * pad bytes; deduct them here.
2123 */
2124 /* XXX honor IEEE80211_BPF_DATAPAD */
2125 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
2126
2127 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2128 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2129
2130 ATH_KTR(sc, ATH_KTR_TX, 2,
2131 "ath_tx_raw_start: ni=%p, bf=%p, raw", ni, bf);
2132
2133 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: ismcast=%d\n",
2134 __func__, ismcast);
2135
2136 pri = params->ibp_pri & 3;
2137 /* Override pri if the frame isn't a QoS one */
2138 if (! IEEE80211_QOS_HAS_SEQ(wh))
2139 pri = ath_tx_getac(sc, m0);
2140
2141 /* XXX If it's an ADDBA, override the correct queue */
2142 do_override = ath_tx_action_frame_override_queue(sc, ni, m0, &o_tid);
2143
2144 /* Map ADDBA to the correct priority */
2145 if (do_override) {
2146#if 0
2147 DPRINTF(sc, ATH_DEBUG_XMIT,
2148 "%s: overriding tid %d pri %d -> %d\n",
2149 __func__, o_tid, pri, TID_TO_WME_AC(o_tid));
2150#endif
2151 pri = TID_TO_WME_AC(o_tid);
2152 }
2153
2154 /* Handle encryption twiddling if needed */
2155 if (! ath_tx_tag_crypto(sc, ni,
2156 m0, params->ibp_flags & IEEE80211_BPF_CRYPTO, 0,
2157 &hdrlen, &pktlen, &keyix)) {
2158 ath_freetx(m0);
2159 return EIO;
2160 }
2161 /* packet header may have moved, reset our local pointer */
2162 wh = mtod(m0, struct ieee80211_frame *);
2163
2164 /* Do the generic frame setup */
2165 /* XXX should just bzero the bf_state? */
2166 bf->bf_state.bfs_dobaw = 0;
2167
2168 error = ath_tx_dmasetup(sc, bf, m0);
2169 if (error != 0)
2170 return error;
2171 m0 = bf->bf_m; /* NB: may have changed */
2172 wh = mtod(m0, struct ieee80211_frame *);
2173 bf->bf_node = ni; /* NB: held reference */
2174
2175 /* Always enable CLRDMASK for raw frames for now.. */
2176 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
2177 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
2178 if (params->ibp_flags & IEEE80211_BPF_RTS)
2179 flags |= HAL_TXDESC_RTSENA;
2180 else if (params->ibp_flags & IEEE80211_BPF_CTS) {
2181 /* XXX assume 11g/11n protection? */
2182 bf->bf_state.bfs_doprot = 1;
2183 flags |= HAL_TXDESC_CTSENA;
2184 }
2185 /* XXX leave ismcast to injector? */
2186 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
2187 flags |= HAL_TXDESC_NOACK;
2188
2189 rt = sc->sc_currates;
2190 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
2191 rix = ath_tx_findrix(sc, params->ibp_rate0);
2192 txrate = rt->info[rix].rateCode;
2193 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
2194 txrate |= rt->info[rix].shortPreamble;
2195 sc->sc_txrix = rix;
2196 try0 = params->ibp_try0;
2197 ismrr = (params->ibp_try1 != 0);
2198 txantenna = params->ibp_pri >> 2;
2199 if (txantenna == 0) /* XXX? */
2200 txantenna = sc->sc_txantenna;
2201
2202 /*
2203 * Since ctsrate is fixed, store it away for later
2204 * use when the descriptor fields are being set.
2205 */
2206 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA))
2207 bf->bf_state.bfs_ctsrate0 = params->ibp_ctsrate;
2208
2209 /*
2210 * NB: we mark all packets as type PSPOLL so the h/w won't
2211 * set the sequence number, duration, etc.
2212 */
2213 atype = HAL_PKT_TYPE_PSPOLL;
2214
2215 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
2216 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
2217 sc->sc_hwmap[rix].ieeerate, -1);
2218
2219 if (ieee80211_radiotap_active_vap(vap)) {
2220 u_int64_t tsf = ath_hal_gettsf64(ah);
2221
2222 sc->sc_tx_th.wt_tsf = htole64(tsf);
2223 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
2224 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
2225 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2226 if (m0->m_flags & M_FRAG)
2227 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
2228 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
2229 sc->sc_tx_th.wt_txpower = MIN(params->ibp_power,
2230 ieee80211_get_node_txpower(ni));
2231 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
2232
2233 ieee80211_radiotap_tx(vap, m0);
2234 }
2235
2236 /*
2237 * Formulate first tx descriptor with tx controls.
2238 */
2239 ds = bf->bf_desc;
2240 /* XXX check return value? */
2241
2242 /* Store the decided rate index values away */
2243 bf->bf_state.bfs_pktlen = pktlen;
2244 bf->bf_state.bfs_hdrlen = hdrlen;
2245 bf->bf_state.bfs_atype = atype;
2246 bf->bf_state.bfs_txpower = MIN(params->ibp_power,
2247 ieee80211_get_node_txpower(ni));
2248 bf->bf_state.bfs_txrate0 = txrate;
2249 bf->bf_state.bfs_try0 = try0;
2250 bf->bf_state.bfs_keyix = keyix;
2251 bf->bf_state.bfs_txantenna = txantenna;
2252 bf->bf_state.bfs_txflags = flags;
2253 bf->bf_state.bfs_shpream =
2254 !! (params->ibp_flags & IEEE80211_BPF_SHORTPRE);
2255
2256 /* Set local packet state, used to queue packets to hardware */
2257 bf->bf_state.bfs_tid = WME_AC_TO_TID(pri);
2258 bf->bf_state.bfs_tx_queue = sc->sc_ac2q[pri]->axq_qnum;
2259 bf->bf_state.bfs_pri = pri;
2260
2261 /* XXX this should be done in ath_tx_setrate() */
2262 bf->bf_state.bfs_ctsrate = 0;
2263 bf->bf_state.bfs_ctsduration = 0;
2264 bf->bf_state.bfs_ismrr = ismrr;
2265
2266 /* Blank the legacy rate array */
2267 bzero(&bf->bf_state.bfs_rc, sizeof(bf->bf_state.bfs_rc));
2268
2269 bf->bf_state.bfs_rc[0].rix =
2270 ath_tx_findrix(sc, params->ibp_rate0);
2271 bf->bf_state.bfs_rc[0].tries = try0;
2272 bf->bf_state.bfs_rc[0].ratecode = txrate;
2273
2274 if (ismrr) {
2275 int rix;
2276
2277 rix = ath_tx_findrix(sc, params->ibp_rate1);
2278 bf->bf_state.bfs_rc[1].rix = rix;
2279 bf->bf_state.bfs_rc[1].tries = params->ibp_try1;
2280
2281 rix = ath_tx_findrix(sc, params->ibp_rate2);
2282 bf->bf_state.bfs_rc[2].rix = rix;
2283 bf->bf_state.bfs_rc[2].tries = params->ibp_try2;
2284
2285 rix = ath_tx_findrix(sc, params->ibp_rate3);
2286 bf->bf_state.bfs_rc[3].rix = rix;
2287 bf->bf_state.bfs_rc[3].tries = params->ibp_try3;
2288 }
2289 /*
2290 * All the required rate control decisions have been made;
2291 * fill in the rc flags.
2292 */
2293 ath_tx_rate_fill_rcflags(sc, bf);
2294
2295 /* NB: no buffered multicast in power save support */
2296
2297 /*
2298 * If we're overiding the ADDBA destination, dump directly
2299 * into the hardware queue, right after any pending
2300 * frames to that node are.
2301 */
2302 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: dooverride=%d\n",
2303 __func__, do_override);
2304
2305#if 1
2306 /*
2307 * Put addba frames in the right place in the right TID/HWQ.
2308 */
2309 if (do_override) {
2310 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2311 /*
2312 * XXX if it's addba frames, should we be leaking
2313 * them out via the frame leak method?
2314 * XXX for now let's not risk it; but we may wish
2315 * to investigate this later.
2316 */
2317 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
2318 } else if (ath_tx_should_swq_frame(sc, ATH_NODE(ni), m0,
2319 &queue_to_head)) {
2320 /* Queue to software queue */
2321 ath_tx_swq(sc, ni, sc->sc_ac2q[pri], queue_to_head, bf);
2322 } else {
2323 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2324 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
2325 }
2326#else
2327 /* Direct-dispatch to the hardware */
2328 bf->bf_state.bfs_txflags |= HAL_TXDESC_CLRDMASK;
2329 /*
2330 * Update the current leak count if
2331 * we're leaking frames; and set the
2332 * MORE flag as appropriate.
2333 */
2334 ath_tx_leak_count_update(sc, tid, bf);
2335 ath_tx_xmit_normal(sc, sc->sc_ac2q[pri], bf);
2336#endif
2337 return 0;
2338}
2339
2340/*
2341 * Send a raw frame.
2342 *
2343 * This can be called by net80211.
2344 */
2345int
2346ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2347 const struct ieee80211_bpf_params *params)
2348{
2349 struct ieee80211com *ic = ni->ni_ic;
2350 struct ifnet *ifp = ic->ic_ifp;
2351 struct ath_softc *sc = ifp->if_softc;
2352 struct ath_buf *bf;
2353 struct ieee80211_frame *wh = mtod(m, struct ieee80211_frame *);
2354 int error = 0;
2355
2356 ATH_PCU_LOCK(sc);
2357 if (sc->sc_inreset_cnt > 0) {
2358 DPRINTF(sc, ATH_DEBUG_XMIT,
2359 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
2360 error = EIO;
2361 ATH_PCU_UNLOCK(sc);
2362 goto bad0;
2363 }
2364 sc->sc_txstart_cnt++;
2365 ATH_PCU_UNLOCK(sc);
2366
2367 ATH_TX_LOCK(sc);
2368
3133c5e3 2369 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid) {
572ff6f6 2370 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
3133c5e3 2371 (ifp->if_flags & IFF_RUNNING) == 0 ?
572ff6f6
MD
2372 "!running" : "invalid");
2373 m_freem(m);
2374 error = ENETDOWN;
2375 goto bad;
2376 }
2377
2378 /*
2379 * Enforce how deep the multicast queue can grow.
2380 *
2381 * XXX duplicated in ath_tx_start().
2382 */
2383 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2384 if (sc->sc_cabq->axq_depth + sc->sc_cabq->fifo.axq_depth
2385 > sc->sc_txq_mcastq_maxdepth) {
2386 sc->sc_stats.ast_tx_mcastq_overflow++;
2387 error = ENOBUFS;
2388 }
2389
2390 if (error != 0) {
2391 m_freem(m);
2392 goto bad;
2393 }
2394 }
2395
2396 /*
2397 * Grab a TX buffer and associated resources.
2398 */
2399 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
2400 if (bf == NULL) {
2401 sc->sc_stats.ast_tx_nobuf++;
2402 m_freem(m);
2403 error = ENOBUFS;
2404 goto bad;
2405 }
2406 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: m=%p, params=%p, bf=%p\n",
2407 m, params, bf);
2408
2409 if (params == NULL) {
2410 /*
2411 * Legacy path; interpret frame contents to decide
2412 * precisely how to send the frame.
2413 */
2414 if (ath_tx_start(sc, ni, bf, m)) {
2415 error = EIO; /* XXX */
2416 goto bad2;
2417 }
2418 } else {
2419 /*
2420 * Caller supplied explicit parameters to use in
2421 * sending the frame.
2422 */
2423 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
2424 error = EIO; /* XXX */
2425 goto bad2;
2426 }
2427 }
2428 sc->sc_wd_timer = 5;
2429 ifp->if_opackets++;
2430 sc->sc_stats.ast_tx_raw++;
2431
2432 /*
2433 * Update the TIM - if there's anything queued to the
2434 * software queue and power save is enabled, we should
2435 * set the TIM.
2436 */
2437 ath_tx_update_tim(sc, ni, 1);
2438
2439 ATH_TX_UNLOCK(sc);
2440
2441 ATH_PCU_LOCK(sc);
2442 sc->sc_txstart_cnt--;
2443 ATH_PCU_UNLOCK(sc);
2444
2445 return 0;
2446bad2:
2447 ATH_KTR(sc, ATH_KTR_TX, 3, "ath_raw_xmit: bad2: m=%p, params=%p, "
2448 "bf=%p",
2449 m,
2450 params,
2451 bf);
2452 ATH_TXBUF_LOCK(sc);
2453 ath_returnbuf_head(sc, bf);
2454 ATH_TXBUF_UNLOCK(sc);
2455bad:
2456
2457 ATH_TX_UNLOCK(sc);
2458
2459 ATH_PCU_LOCK(sc);
2460 sc->sc_txstart_cnt--;
2461 ATH_PCU_UNLOCK(sc);
2462bad0:
2463 ATH_KTR(sc, ATH_KTR_TX, 2, "ath_raw_xmit: bad0: m=%p, params=%p",
2464 m, params);
2465 ifp->if_oerrors++;
2466 sc->sc_stats.ast_tx_raw_fail++;
2467 ieee80211_free_node(ni);
2468
2469 return error;
2470}
2471
2472/* Some helper functions */
2473
2474/*
2475 * ADDBA (and potentially others) need to be placed in the same
2476 * hardware queue as the TID/node it's relating to. This is so
2477 * it goes out after any pending non-aggregate frames to the
2478 * same node/TID.
2479 *
2480 * If this isn't done, the ADDBA can go out before the frames
2481 * queued in hardware. Even though these frames have a sequence
2482 * number -earlier- than the ADDBA can be transmitted (but
2483 * no frames whose sequence numbers are after the ADDBA should
2484 * be!) they'll arrive after the ADDBA - and the receiving end
2485 * will simply drop them as being out of the BAW.
2486 *
2487 * The frames can't be appended to the TID software queue - it'll
2488 * never be sent out. So these frames have to be directly
2489 * dispatched to the hardware, rather than queued in software.
2490 * So if this function returns true, the TXQ has to be
2491 * overridden and it has to be directly dispatched.
2492 *
2493 * It's a dirty hack, but someone's gotta do it.
2494 */
2495
2496/*
2497 * XXX doesn't belong here!
2498 */
2499static int
2500ieee80211_is_action(struct ieee80211_frame *wh)
2501{
2502 /* Type: Management frame? */
2503 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) !=
2504 IEEE80211_FC0_TYPE_MGT)
2505 return 0;
2506
2507 /* Subtype: Action frame? */
2508 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) !=
2509 IEEE80211_FC0_SUBTYPE_ACTION)
2510 return 0;
2511
2512 return 1;
2513}
2514
2515#define MS(_v, _f) (((_v) & _f) >> _f##_S)
2516/*
2517 * Return an alternate TID for ADDBA request frames.
2518 *
2519 * Yes, this likely should be done in the net80211 layer.
2520 */
2521static int
2522ath_tx_action_frame_override_queue(struct ath_softc *sc,
2523 struct ieee80211_node *ni,
2524 struct mbuf *m0, int *tid)
2525{
2526 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
2527 struct ieee80211_action_ba_addbarequest *ia;
2528 uint8_t *frm;
2529 uint16_t baparamset;
2530
2531 /* Not action frame? Bail */
2532 if (! ieee80211_is_action(wh))
2533 return 0;
2534
2535 /* XXX Not needed for frames we send? */
2536#if 0
2537 /* Correct length? */
2538 if (! ieee80211_parse_action(ni, m))
2539 return 0;
2540#endif
2541
2542 /* Extract out action frame */
2543 frm = (u_int8_t *)&wh[1];
2544 ia = (struct ieee80211_action_ba_addbarequest *) frm;
2545
2546 /* Not ADDBA? Bail */
2547 if (ia->rq_header.ia_category != IEEE80211_ACTION_CAT_BA)
2548 return 0;
2549 if (ia->rq_header.ia_action != IEEE80211_ACTION_BA_ADDBA_REQUEST)
2550 return 0;
2551
2552 /* Extract TID, return it */
2553 baparamset = le16toh(ia->rq_baparamset);
2554 *tid = (int) MS(baparamset, IEEE80211_BAPS_TID);
2555
2556 return 1;
2557}
2558#undef MS
2559
2560/* Per-node software queue operations */
2561
2562/*
2563 * Add the current packet to the given BAW.
2564 * It is assumed that the current packet
2565 *
2566 * + fits inside the BAW;
2567 * + already has had a sequence number allocated.
2568 *
2569 * Since the BAW status may be modified by both the ath task and
2570 * the net80211/ifnet contexts, the TID must be locked.
2571 */
2572void
2573ath_tx_addto_baw(struct ath_softc *sc, struct ath_node *an,
2574 struct ath_tid *tid, struct ath_buf *bf)
2575{
2576 int index, cindex;
2577 struct ieee80211_tx_ampdu *tap;
2578
2579 ATH_TX_LOCK_ASSERT(sc);
2580
2581 if (bf->bf_state.bfs_isretried)
2582 return;
2583
2584 tap = ath_tx_get_tx_tid(an, tid->tid);
2585
2586 if (! bf->bf_state.bfs_dobaw) {
2587 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2588 "%s: dobaw=0, seqno=%d, window %d:%d\n",
2589 __func__, SEQNO(bf->bf_state.bfs_seqno),
2590 tap->txa_start, tap->txa_wnd);
2591 }
2592
2593 if (bf->bf_state.bfs_addedbaw)
2594 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2595 "%s: re-added? tid=%d, seqno %d; window %d:%d; "
2596 "baw head=%d tail=%d\n",
2597 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2598 tap->txa_start, tap->txa_wnd, tid->baw_head,
2599 tid->baw_tail);
2600
2601 /*
2602 * Verify that the given sequence number is not outside of the
2603 * BAW. Complain loudly if that's the case.
2604 */
2605 if (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2606 SEQNO(bf->bf_state.bfs_seqno))) {
2607 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2608 "%s: bf=%p: outside of BAW?? tid=%d, seqno %d; window %d:%d; "
2609 "baw head=%d tail=%d\n",
2610 __func__, bf, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2611 tap->txa_start, tap->txa_wnd, tid->baw_head,
2612 tid->baw_tail);
2613 }
2614
2615 /*
2616 * ni->ni_txseqs[] is the currently allocated seqno.
2617 * the txa state contains the current baw start.
2618 */
2619 index = ATH_BA_INDEX(tap->txa_start, SEQNO(bf->bf_state.bfs_seqno));
2620 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2621 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2622 "%s: tid=%d, seqno %d; window %d:%d; index=%d cindex=%d "
2623 "baw head=%d tail=%d\n",
2624 __func__, tid->tid, SEQNO(bf->bf_state.bfs_seqno),
2625 tap->txa_start, tap->txa_wnd, index, cindex, tid->baw_head,
2626 tid->baw_tail);
2627
2628
2629#if 0
2630 assert(tid->tx_buf[cindex] == NULL);
2631#endif
2632 if (tid->tx_buf[cindex] != NULL) {
2633 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2634 "%s: ba packet dup (index=%d, cindex=%d, "
2635 "head=%d, tail=%d)\n",
2636 __func__, index, cindex, tid->baw_head, tid->baw_tail);
2637 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2638 "%s: BA bf: %p; seqno=%d ; new bf: %p; seqno=%d\n",
2639 __func__,
2640 tid->tx_buf[cindex],
2641 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno),
2642 bf,
2643 SEQNO(bf->bf_state.bfs_seqno)
2644 );
2645 }
2646 tid->tx_buf[cindex] = bf;
2647
2648 if (index >= ((tid->baw_tail - tid->baw_head) &
2649 (ATH_TID_MAX_BUFS - 1))) {
2650 tid->baw_tail = cindex;
2651 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
2652 }
2653}
2654
2655/*
2656 * Flip the BAW buffer entry over from the existing one to the new one.
2657 *
2658 * When software retransmitting a (sub-)frame, it is entirely possible that
2659 * the frame ath_buf is marked as BUSY and can't be immediately reused.
2660 * In that instance the buffer is cloned and the new buffer is used for
2661 * retransmit. We thus need to update the ath_buf slot in the BAW buf
2662 * tracking array to maintain consistency.
2663 */
2664static void
2665ath_tx_switch_baw_buf(struct ath_softc *sc, struct ath_node *an,
2666 struct ath_tid *tid, struct ath_buf *old_bf, struct ath_buf *new_bf)
2667{
2668 int index, cindex;
2669 struct ieee80211_tx_ampdu *tap;
2670 int seqno = SEQNO(old_bf->bf_state.bfs_seqno);
2671
2672 ATH_TX_LOCK_ASSERT(sc);
2673
2674 tap = ath_tx_get_tx_tid(an, tid->tid);
2675 index = ATH_BA_INDEX(tap->txa_start, seqno);
2676 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2677
2678 /*
2679 * Just warn for now; if it happens then we should find out
2680 * about it. It's highly likely the aggregation session will
2681 * soon hang.
2682 */
2683 if (old_bf->bf_state.bfs_seqno != new_bf->bf_state.bfs_seqno) {
2684 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2685 "%s: retransmitted buffer"
2686 " has mismatching seqno's, BA session may hang.\n",
2687 __func__);
2688 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2689 "%s: old seqno=%d, new_seqno=%d\n", __func__,
2690 old_bf->bf_state.bfs_seqno, new_bf->bf_state.bfs_seqno);
2691 }
2692
2693 if (tid->tx_buf[cindex] != old_bf) {
2694 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2695 "%s: ath_buf pointer incorrect; "
2696 " has m BA session may hang.\n", __func__);
2697 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2698 "%s: old bf=%p, new bf=%p\n", __func__, old_bf, new_bf);
2699 }
2700
2701 tid->tx_buf[cindex] = new_bf;
2702}
2703
2704/*
2705 * seq_start - left edge of BAW
2706 * seq_next - current/next sequence number to allocate
2707 *
2708 * Since the BAW status may be modified by both the ath task and
2709 * the net80211/ifnet contexts, the TID must be locked.
2710 */
2711static void
2712ath_tx_update_baw(struct ath_softc *sc, struct ath_node *an,
2713 struct ath_tid *tid, const struct ath_buf *bf)
2714{
2715 int index, cindex;
2716 struct ieee80211_tx_ampdu *tap;
2717 int seqno = SEQNO(bf->bf_state.bfs_seqno);
2718
2719 ATH_TX_LOCK_ASSERT(sc);
2720
2721 tap = ath_tx_get_tx_tid(an, tid->tid);
2722 index = ATH_BA_INDEX(tap->txa_start, seqno);
2723 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
2724
2725 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2726 "%s: tid=%d, baw=%d:%d, seqno=%d, index=%d, cindex=%d, "
2727 "baw head=%d, tail=%d\n",
2728 __func__, tid->tid, tap->txa_start, tap->txa_wnd, seqno, index,
2729 cindex, tid->baw_head, tid->baw_tail);
2730
2731 /*
2732 * If this occurs then we have a big problem - something else
2733 * has slid tap->txa_start along without updating the BAW
2734 * tracking start/end pointers. Thus the TX BAW state is now
2735 * completely busted.
2736 *
2737 * But for now, since I haven't yet fixed TDMA and buffer cloning,
2738 * it's quite possible that a cloned buffer is making its way
2739 * here and causing it to fire off. Disable TDMA for now.
2740 */
2741 if (tid->tx_buf[cindex] != bf) {
2742 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2743 "%s: comp bf=%p, seq=%d; slot bf=%p, seqno=%d\n",
2744 __func__, bf, SEQNO(bf->bf_state.bfs_seqno),
2745 tid->tx_buf[cindex],
2746 (tid->tx_buf[cindex] != NULL) ?
2747 SEQNO(tid->tx_buf[cindex]->bf_state.bfs_seqno) : -1);
2748 }
2749
2750 tid->tx_buf[cindex] = NULL;
2751
2752 while (tid->baw_head != tid->baw_tail &&
2753 !tid->tx_buf[tid->baw_head]) {
2754 INCR(tap->txa_start, IEEE80211_SEQ_RANGE);
2755 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
2756 }
2757 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW,
2758 "%s: baw is now %d:%d, baw head=%d\n",
2759 __func__, tap->txa_start, tap->txa_wnd, tid->baw_head);
2760}
2761
2762static void
2763ath_tx_leak_count_update(struct ath_softc *sc, struct ath_tid *tid,
2764 struct ath_buf *bf)
2765{
2766 struct ieee80211_frame *wh;
2767
2768 ATH_TX_LOCK_ASSERT(sc);
2769
2770 if (tid->an->an_leak_count > 0) {
2771 wh = mtod(bf->bf_m, struct ieee80211_frame *);
2772
2773 /*
2774 * Update MORE based on the software/net80211 queue states.
2775 */
2776 if ((tid->an->an_stack_psq > 0)
2777 || (tid->an->an_swq_depth > 0))
2778 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
2779 else
2780 wh->i_fc[1] &= ~IEEE80211_FC1_MORE_DATA;
2781
2782 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
2783 "%s: %6D: leak count = %d, psq=%d, swq=%d, MORE=%d\n",
2784 __func__,
2785 tid->an->an_node.ni_macaddr,
2786 ":",
2787 tid->an->an_leak_count,
2788 tid->an->an_stack_psq,
2789 tid->an->an_swq_depth,
2790 !! (wh->i_fc[1] & IEEE80211_FC1_MORE_DATA));
2791
2792 /*
2793 * Re-sync the underlying buffer.
2794 */
2795 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2796 BUS_DMASYNC_PREWRITE);
2797
2798 tid->an->an_leak_count --;
2799 }
2800}
2801
2802static int
2803ath_tx_tid_can_tx_or_sched(struct ath_softc *sc, struct ath_tid *tid)
2804{
2805
2806 ATH_TX_LOCK_ASSERT(sc);
2807
2808 if (tid->an->an_leak_count > 0) {
2809 return (1);
2810 }
2811 if (tid->paused)
2812 return (0);
2813 return (1);
2814}
2815
2816/*
2817 * Mark the current node/TID as ready to TX.
2818 *
2819 * This is done to make it easy for the software scheduler to
2820 * find which nodes have data to send.
2821 *
2822 * The TXQ lock must be held.
2823 */
2824void
2825ath_tx_tid_sched(struct ath_softc *sc, struct ath_tid *tid)
2826{
2827 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2828
2829 ATH_TX_LOCK_ASSERT(sc);
2830
2831 /*
2832 * If we are leaking out a frame to this destination
2833 * for PS-POLL, ensure that we allow scheduling to
2834 * occur.
2835 */
2836 if (! ath_tx_tid_can_tx_or_sched(sc, tid))
2837 return; /* paused, can't schedule yet */
2838
2839 if (tid->sched)
2840 return; /* already scheduled */
2841
2842 tid->sched = 1;
2843
2844#if 0
2845 /*
2846 * If this is a sleeping node we're leaking to, given
2847 * it a higher priority. This is so bad for QoS it hurts.
2848 */
2849 if (tid->an->an_leak_count) {
2850 TAILQ_INSERT_HEAD(&txq->axq_tidq, tid, axq_qelem);
2851 } else {
2852 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2853 }
2854#endif
2855
2856 /*
2857 * We can't do the above - it'll confuse the TXQ software
2858 * scheduler which will keep checking the _head_ TID
2859 * in the list to see if it has traffic. If we queue
2860 * a TID to the head of the list and it doesn't transmit,
2861 * we'll check it again.
2862 *
2863 * So, get the rest of this leaking frames support working
2864 * and reliable first and _then_ optimise it so they're
2865 * pushed out in front of any other pending software
2866 * queued nodes.
2867 */
2868 TAILQ_INSERT_TAIL(&txq->axq_tidq, tid, axq_qelem);
2869}
2870
2871/*
2872 * Mark the current node as no longer needing to be polled for
2873 * TX packets.
2874 *
2875 * The TXQ lock must be held.
2876 */
2877static void
2878ath_tx_tid_unsched(struct ath_softc *sc, struct ath_tid *tid)
2879{
2880 struct ath_txq *txq = sc->sc_ac2q[tid->ac];
2881
2882 ATH_TX_LOCK_ASSERT(sc);
2883
2884 if (tid->sched == 0)
2885 return;
2886
2887 tid->sched = 0;
2888 TAILQ_REMOVE(&txq->axq_tidq, tid, axq_qelem);
2889}
2890
2891/*
2892 * Assign a sequence number manually to the given frame.
2893 *
2894 * This should only be called for A-MPDU TX frames.
2895 */
2896static ieee80211_seq
2897ath_tx_tid_seqno_assign(struct ath_softc *sc, struct ieee80211_node *ni,
2898 struct ath_buf *bf, struct mbuf *m0)
2899{
2900 struct ieee80211_frame *wh;
2901 int tid, pri;
2902 ieee80211_seq seqno;
2903 uint8_t subtype;
2904
2905 /* TID lookup */
2906 wh = mtod(m0, struct ieee80211_frame *);
2907 pri = M_WME_GETAC(m0); /* honor classification */
2908 tid = WME_AC_TO_TID(pri);
2909 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pri=%d, tid=%d, qos has seq=%d\n",
2910 __func__, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
2911
2912 /* XXX Is it a control frame? Ignore */
2913
2914 /* Does the packet require a sequence number? */
2915 if (! IEEE80211_QOS_HAS_SEQ(wh))
2916 return -1;
2917
2918 ATH_TX_LOCK_ASSERT(sc);
2919
2920 /*
2921 * Is it a QOS NULL Data frame? Give it a sequence number from
2922 * the default TID (IEEE80211_NONQOS_TID.)
2923 *
2924 * The RX path of everything I've looked at doesn't include the NULL
2925 * data frame sequence number in the aggregation state updates, so
2926 * assigning it a sequence number there will cause a BAW hole on the
2927 * RX side.
2928 */
2929 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
2930 if (subtype == IEEE80211_FC0_SUBTYPE_QOS_NULL) {
2931 /* XXX no locking for this TID? This is a bit of a problem. */
2932 seqno = ni->ni_txseqs[IEEE80211_NONQOS_TID];
2933 INCR(ni->ni_txseqs[IEEE80211_NONQOS_TID], IEEE80211_SEQ_RANGE);
2934 } else {
2935 /* Manually assign sequence number */
2936 seqno = ni->ni_txseqs[tid];
2937 INCR(ni->ni_txseqs[tid], IEEE80211_SEQ_RANGE);
2938 }
2939 *(uint16_t *)&wh->i_seq[0] = htole16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
2940 M_SEQNO_SET(m0, seqno);
2941
2942 /* Return so caller can do something with it if needed */
2943 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: -> seqno=%d\n", __func__, seqno);
2944 return seqno;
2945}
2946
2947/*
2948 * Attempt to direct dispatch an aggregate frame to hardware.
2949 * If the frame is out of BAW, queue.
2950 * Otherwise, schedule it as a single frame.
2951 */
2952static void
2953ath_tx_xmit_aggr(struct ath_softc *sc, struct ath_node *an,
2954 struct ath_txq *txq, struct ath_buf *bf)
2955{
2956 struct ath_tid *tid = &an->an_tid[bf->bf_state.bfs_tid];
2957 struct ieee80211_tx_ampdu *tap;
2958
2959 ATH_TX_LOCK_ASSERT(sc);
2960
2961 tap = ath_tx_get_tx_tid(an, tid->tid);
2962
2963 /* paused? queue */
2964 if (! ath_tx_tid_can_tx_or_sched(sc, tid)) {
2965 ATH_TID_INSERT_HEAD(tid, bf, bf_list);
2966 /* XXX don't sched - we're paused! */
2967 return;
2968 }
2969
2970 /* outside baw? queue */
2971 if (bf->bf_state.bfs_dobaw &&
2972 (! BAW_WITHIN(tap->txa_start, tap->txa_wnd,
2973 SEQNO(bf->bf_state.bfs_seqno)))) {
2974 ATH_TID_INSERT_HEAD(tid, bf, bf_list);
2975 ath_tx_tid_sched(sc, tid);
2976 return;
2977 }
2978
2979 /*
2980 * This is a temporary check and should be removed once
2981 * all the relevant code paths have been fixed.
2982 *
2983 * During aggregate retries, it's possible that the head
2984 * frame will fail (which has the bfs_aggr and bfs_nframes
2985 * fields set for said aggregate) and will be retried as
2986 * a single frame. In this instance, the values should
2987 * be reset or the completion code will get upset with you.
2988 */
2989 if (bf->bf_state.bfs_aggr != 0 || bf->bf_state.bfs_nframes > 1) {
2990 DPRINTF(sc, ATH_DEBUG_SW_TX_AGGR,
2991 "%s: bfs_aggr=%d, bfs_nframes=%d\n", __func__,
2992 bf->bf_state.bfs_aggr, bf->bf_state.bfs_nframes);
2993 bf->bf_state.bfs_aggr = 0;
2994 bf->bf_state.bfs_nframes = 1;
2995 }
2996
2997 /* Update CLRDMASK just before this frame is queued */
2998 ath_tx_update_clrdmask(sc, tid, bf);
2999
3000 /* Direct dispatch to hardware */
3001 ath_tx_do_ratelookup(sc, bf);
3002 ath_tx_calc_duration(sc, bf);
3003 ath_tx_calc_protection(sc, bf);
3004 ath_tx_set_rtscts(sc, bf);
3005 ath_tx_rate_fill_rcflags(sc, bf);
3006 ath_tx_setds(sc, bf);
3007
3008 /* Statistics */
3009 sc->sc_aggr_stats.aggr_low_hwq_single_pkt++;
3010
3011 /* Track per-TID hardware queue depth correctly */
3012 tid->hwq_depth++;
3013
3014 /* Add to BAW */
3015 if (bf->bf_state.bfs_dobaw) {
3016 ath_tx_addto_baw(sc, an, tid, bf);
3017 bf->bf_state.bfs_addedbaw = 1;
3018 }
3019
3020 /* Set completion handler, multi-frame aggregate or not */
3021 bf->bf_comp = ath_tx_aggr_comp;
3022
3023 /*
3024 * Update the current leak count if
3025 * we're leaking frames; and set the
3026 * MORE flag as appropriate.
3027 */
3028 ath_tx_leak_count_update(sc, tid, bf);
3029
3030 /* Hand off to hardware */
3031 ath_tx_handoff(sc, txq, bf);
3032}
3033
3034/*
3035 * Attempt to send the packet.
3036 * If the queue isn't busy, direct-dispatch.
3037 * If the queue is busy enough, queue the given packet on the
3038 * relevant software queue.
3039 */
3040void
3041ath_tx_swq(struct ath_softc *sc, struct ieee80211_node *ni,
3042 struct ath_txq *txq, int queue_to_head, struct ath_buf *bf)
3043{
3044 struct ath_node *an = ATH_NODE(ni);
3045 struct ieee80211_frame *wh;
3046 struct ath_tid *atid;
3047 int pri, tid;
3048 struct mbuf *m0 = bf->bf_m;
3049
3050 ATH_TX_LOCK_ASSERT(sc);
3051
3052 /* Fetch the TID - non-QoS frames get assigned to TID 16 */
3053 wh = mtod(m0, struct ieee80211_frame *);
3054 pri = ath_tx_getac(sc, m0);
3055 tid = ath_tx_gettid(sc, m0);
3056 atid = &an->an_tid[tid];
3057
3058 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: bf=%p, pri=%d, tid=%d, qos=%d\n",
3059 __func__, bf, pri, tid, IEEE80211_QOS_HAS_SEQ(wh));
3060
3061 /* Set local packet state, used to queue packets to hardware */
3062 /* XXX potentially duplicate info, re-check */
3063 bf->bf_state.bfs_tid = tid;
3064 bf->bf_state.bfs_tx_queue = txq->axq_qnum;
3065 bf->bf_state.bfs_pri = pri;
3066
3067 /*
3068 * If the hardware queue isn't busy, queue it directly.
3069 * If the hardware queue is busy, queue it.
3070 * If the TID is paused or the traffic it outside BAW, software
3071 * queue it.
3072 *
3073 * If the node is in power-save and we're leaking a frame,
3074 * leak a single frame.
3075 */
3076 if (! ath_tx_tid_can_tx_or_sched(sc, atid)) {
3077 /* TID is paused, queue */
3078 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: paused\n", __func__);
3079 /*
3080 * If the caller requested that it be sent at a high
3081 * priority, queue it at the head of the list.
3082 */
3083 if (queue_to_head)
3084 ATH_TID_INSERT_HEAD(atid, bf, bf_list);
3085 else
3086 ATH_TID_INSERT_TAIL(atid, bf, bf_list);
3087 } else if (ath_tx_ampdu_pending(sc, an, tid)) {
3088 /* AMPDU pending; queue */
3089 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: pending\n", __func__);
3090 ATH_TID_INSERT_TAIL(atid, bf, bf_list);
3091 /* XXX sched? */
3092 } else if (ath_tx_ampdu_running(sc, an, tid)) {
3093 /* AMPDU running, attempt direct dispatch if possible */
3094
3095 /*
3096 * Always queue the frame to the tail of the list.
3097 */
3098 ATH_TID_INSERT_TAIL(atid, bf, bf_list);
3099
3100 /*
3101 * If the hardware queue isn't busy, direct dispatch
3102 * the head frame in the list. Don't schedule the
3103 * TID - let it build some more frames first?
3104 *
3105 * When running A-MPDU, always just check the hardware
3106 * queue depth against the aggregate frame limit.
3107 * We don't want to burst a large number of single frames
3108 * out to the hardware; we want to aggressively hold back.
3109 *
3110 * Otherwise, schedule the TID.
3111 */
3112 /* XXX TXQ locking */
3113 if (txq->axq_depth + txq->fifo.axq_depth < sc->sc_hwq_limit_aggr) {
3114 bf = ATH_TID_FIRST(atid);
3115 ATH_TID_REMOVE(atid, bf, bf_list);
3116
3117 /*
3118 * Ensure it's definitely treated as a non-AMPDU
3119 * frame - this information may have been left
3120 * over from a previous attempt.
3121 */
3122 bf->bf_state.bfs_aggr = 0;
3123 bf->bf_state.bfs_nframes = 1;
3124
3125 /* Queue to the hardware */
3126 ath_tx_xmit_aggr(sc, an, txq, bf);
3127 DPRINTF(sc, ATH_DEBUG_SW_TX,
3128 "%s: xmit_aggr\n",
3129 __func__);
3130 } else {
3131 DPRINTF(sc, ATH_DEBUG_SW_TX,
3132 "%s: ampdu; swq'ing\n",
3133 __func__);
3134
3135 ath_tx_tid_sched(sc, atid);
3136 }
3137 /*
3138 * If we're not doing A-MPDU, be prepared to direct dispatch
3139 * up to both limits if possible. This particular corner
3140 * case may end up with packet starvation between aggregate
3141 * traffic and non-aggregate traffic: we wnat to ensure
3142 * that non-aggregate stations get a few frames queued to the
3143 * hardware before the aggregate station(s) get their chance.
3144 *
3145 * So if you only ever see a couple of frames direct dispatched
3146 * to the hardware from a non-AMPDU client, check both here
3147 * and in the software queue dispatcher to ensure that those
3148 * non-AMPDU stations get a fair chance to transmit.
3149 */
3150 /* XXX TXQ locking */
3151 } else if ((txq->axq_depth + txq->fifo.axq_depth < sc->sc_hwq_limit_nonaggr) &&
3152 (txq->axq_aggr_depth < sc->sc_hwq_limit_aggr)) {
3153 /* AMPDU not running, attempt direct dispatch */
3154 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: xmit_normal\n", __func__);
3155 /* See if clrdmask needs to be set */
3156 ath_tx_update_clrdmask(sc, atid, bf);
3157
3158 /*
3159 * Update the current leak count if
3160 * we're leaking frames; and set the
3161 * MORE flag as appropriate.
3162 */
3163 ath_tx_leak_count_update(sc, atid, bf);
3164
3165 /*
3166 * Dispatch the frame.
3167 */
3168 ath_tx_xmit_normal(sc, txq, bf);
3169 } else {
3170 /* Busy; queue */
3171 DPRINTF(sc, ATH_DEBUG_SW_TX, "%s: swq'ing\n", __func__);
3172 ATH_TID_INSERT_TAIL(atid, bf, bf_list);
3173 ath_tx_tid_sched(sc, atid);
3174 }
3175}
3176
3177/*
3178 * Only set the clrdmask bit if none of the nodes are currently
3179 * filtered.
3180 *
3181 * XXX TODO: go through all the callers and check to see
3182 * which are being called in the context of looping over all
3183 * TIDs (eg, if all tids are being paused, resumed, etc.)
3184 * That'll avoid O(n^2) complexity here.
3185 */
3186static void
3187ath_tx_set_clrdmask(struct ath_softc *sc, struct ath_node *an)
3188{
3189 int i;
3190
3191 ATH_TX_LOCK_ASSERT(sc);
3192
3193 for (i = 0; i < IEEE80211_TID_SIZE; i++) {
3194 if (an->an_tid[i].isfiltered == 1)
3195 return;
3196 }
3197 an->clrdmask = 1;
3198}
3199
3200/*
3201 * Configure the per-TID node state.
3202 *
3203 * This likely belongs in if_ath_node.c but I can't think of anywhere
3204 * else to put it just yet.
3205 *
3206 * This sets up the SLISTs and the mutex as appropriate.
3207 */
3208void
3209ath_tx_tid_init(struct ath_softc *sc, struct ath_node *an)
3210{
3211 int i, j;
3212 struct ath_tid *atid;
3213
3214 for (i = 0; i < IEEE80211_TID_SIZE; i++) {
3215 atid = &an->an_tid[i];
3216
3217 /* XXX now with this bzer(), is the field 0'ing needed? */
3218 bzero(atid, sizeof(*atid));
3219
3220 TAILQ_INIT(&atid->tid_q);
3221 TAILQ_INIT(&atid->filtq.tid_q);
3222 atid->tid = i;
3223 atid->an = an;
3224 for (j = 0; j < ATH_TID_MAX_BUFS; j++)
3225 atid->tx_buf[j] = NULL;
3226 atid->baw_head = atid->baw_tail = 0;
3227 atid->paused = 0;
3228 atid->sched = 0;
3229 atid->hwq_depth = 0;
3230 atid->cleanup_inprogress = 0;
3231 if (i == IEEE80211_NONQOS_TID)
3232 atid->ac = ATH_NONQOS_TID_AC;
3233 else
3234 atid->ac = TID_TO_WME_AC(i);
3235 }
3236 an->clrdmask = 1; /* Always start by setting this bit */
3237}
3238
3239/*
3240 * Pause the current TID. This stops packets from being transmitted
3241 * on it.
3242 *
3243 * Since this is also called from upper layers as well as the driver,
3244 * it will get the TID lock.
3245 */
3246static void
3247ath_tx_tid_pause(struct ath_softc *sc, struct ath_tid *tid)
3248{
3249
3250 ATH_TX_LOCK_ASSERT(sc);
3251 tid->paused++;
3252 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: paused = %d\n",
3253 __func__, tid->paused);
3254}
3255
3256/*
3257 * Unpause the current TID, and schedule it if needed.
3258 */
3259static void
3260ath_tx_tid_resume(struct ath_softc *sc, struct ath_tid *tid)
3261{
3262 ATH_TX_LOCK_ASSERT(sc);
3263
3264 /*
3265 * There's some odd places where ath_tx_tid_resume() is called
3266 * when it shouldn't be; this works around that particular issue
3267 * until it's actually resolved.
3268 */
3269 if (tid->paused == 0) {
3270 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3271 "%s: %6D: paused=0?\n", __func__,
3272 tid->an->an_node.ni_macaddr, ":");
3273 } else {
3274 tid->paused--;
3275 }
3276
3277 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: unpaused = %d\n",
3278 __func__, tid->paused);
3279
3280 if (tid->paused)
3281 return;
3282
3283 /*
3284 * Override the clrdmask configuration for the next frame
3285 * from this TID, just to get the ball rolling.
3286 */
3287 ath_tx_set_clrdmask(sc, tid->an);
3288
3289 if (tid->axq_depth == 0)
3290 return;
3291
3292 /* XXX isfiltered shouldn't ever be 0 at this point */
3293 if (tid->isfiltered == 1) {
3294 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL, "%s: filtered?!\n",
3295 __func__);
3296 return;
3297 }
3298
3299 ath_tx_tid_sched(sc, tid);
3300
3301 /*
3302 * Queue the software TX scheduler.
3303 */
3304 ath_tx_swq_kick(sc);
3305}
3306
3307/*
3308 * Add the given ath_buf to the TID filtered frame list.
3309 * This requires the TID be filtered.
3310 */
3311static void
3312ath_tx_tid_filt_addbuf(struct ath_softc *sc, struct ath_tid *tid,
3313 struct ath_buf *bf)
3314{
3315
3316 ATH_TX_LOCK_ASSERT(sc);
3317
3318 if (!tid->isfiltered)
3319 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: not filtered?!\n",
3320 __func__);
3321
3322 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: bf=%p\n", __func__, bf);
3323
3324 /* Set the retry bit and bump the retry counter */
3325 ath_tx_set_retry(sc, bf);
3326 sc->sc_stats.ast_tx_swfiltered++;
3327
3328 ATH_TID_FILT_INSERT_TAIL(tid, bf, bf_list);
3329}
3330
3331/*
3332 * Handle a completed filtered frame from the given TID.
3333 * This just enables/pauses the filtered frame state if required
3334 * and appends the filtered frame to the filtered queue.
3335 */
3336static void
3337ath_tx_tid_filt_comp_buf(struct ath_softc *sc, struct ath_tid *tid,
3338 struct ath_buf *bf)
3339{
3340
3341 ATH_TX_LOCK_ASSERT(sc);
3342
3343 if (! tid->isfiltered) {
3344 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: filter transition\n",
3345 __func__);
3346 tid->isfiltered = 1;
3347 ath_tx_tid_pause(sc, tid);
3348 }
3349
3350 /* Add the frame to the filter queue */
3351 ath_tx_tid_filt_addbuf(sc, tid, bf);
3352}
3353
3354/*
3355 * Complete the filtered frame TX completion.
3356 *
3357 * If there are no more frames in the hardware queue, unpause/unfilter
3358 * the TID if applicable. Otherwise we will wait for a node PS transition
3359 * to unfilter.
3360 */
3361static void
3362ath_tx_tid_filt_comp_complete(struct ath_softc *sc, struct ath_tid *tid)
3363{
3364 struct ath_buf *bf;
3365
3366 ATH_TX_LOCK_ASSERT(sc);
3367
3368 if (tid->hwq_depth != 0)
3369 return;
3370
3371 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT, "%s: hwq=0, transition back\n",
3372 __func__);
3373 tid->isfiltered = 0;
3374 /* XXX ath_tx_tid_resume() also calls ath_tx_set_clrdmask()! */
3375 ath_tx_set_clrdmask(sc, tid->an);
3376
3377 /* XXX this is really quite inefficient */
3378 while ((bf = ATH_TID_FILT_LAST(tid, ath_bufhead_s)) != NULL) {
3379 ATH_TID_FILT_REMOVE(tid, bf, bf_list);
3380 ATH_TID_INSERT_HEAD(tid, bf, bf_list);
3381 }
3382
3383 ath_tx_tid_resume(sc, tid);
3384}
3385
3386/*
3387 * Called when a single (aggregate or otherwise) frame is completed.
3388 *
3389 * Returns 1 if the buffer could be added to the filtered list
3390 * (cloned or otherwise), 0 if the buffer couldn't be added to the
3391 * filtered list (failed clone; expired retry) and the caller should
3392 * free it and handle it like a failure (eg by sending a BAR.)
3393 */
3394static int
3395ath_tx_tid_filt_comp_single(struct ath_softc *sc, struct ath_tid *tid,
3396 struct ath_buf *bf)
3397{
3398 struct ath_buf *nbf;
3399 int retval;
3400
3401 ATH_TX_LOCK_ASSERT(sc);
3402
3403 /*
3404 * Don't allow a filtered frame to live forever.
3405 */
3406 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) {
3407 sc->sc_stats.ast_tx_swretrymax++;
3408 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3409 "%s: bf=%p, seqno=%d, exceeded retries\n",
3410 __func__,
3411 bf,
3412 bf->bf_state.bfs_seqno);
3413 return (0);
3414 }
3415
3416 /*
3417 * A busy buffer can't be added to the retry list.
3418 * It needs to be cloned.
3419 */
3420 if (bf->bf_flags & ATH_BUF_BUSY) {
3421 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf);
3422 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3423 "%s: busy buffer clone: %p -> %p\n",
3424 __func__, bf, nbf);
3425 } else {
3426 nbf = bf;
3427 }
3428
3429 if (nbf == NULL) {
3430 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3431 "%s: busy buffer couldn't be cloned (%p)!\n",
3432 __func__, bf);
3433 retval = 1;
3434 } else {
3435 ath_tx_tid_filt_comp_buf(sc, tid, nbf);
3436 retval = 0;
3437 }
3438 ath_tx_tid_filt_comp_complete(sc, tid);
3439
3440 return (retval);
3441}
3442
3443static void
3444ath_tx_tid_filt_comp_aggr(struct ath_softc *sc, struct ath_tid *tid,
3445 struct ath_buf *bf_first, ath_bufhead *bf_q)
3446{
3447 struct ath_buf *bf, *bf_next, *nbf;
3448
3449 ATH_TX_LOCK_ASSERT(sc);
3450
3451 bf = bf_first;
3452 while (bf) {
3453 bf_next = bf->bf_next;
3454 bf->bf_next = NULL; /* Remove it from the aggr list */
3455
3456 /*
3457 * Don't allow a filtered frame to live forever.
3458 */
3459 if (bf->bf_state.bfs_retries > SWMAX_RETRIES) {
3460 sc->sc_stats.ast_tx_swretrymax++;
3461 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3462 "%s: bf=%p, seqno=%d, exceeded retries\n",
3463 __func__,
3464 bf,
3465 bf->bf_state.bfs_seqno);
3466 TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3467 goto next;
3468 }
3469
3470 if (bf->bf_flags & ATH_BUF_BUSY) {
3471 nbf = ath_tx_retry_clone(sc, tid->an, tid, bf);
3472 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3473 "%s: busy buffer cloned: %p -> %p",
3474 __func__, bf, nbf);
3475 } else {
3476 nbf = bf;
3477 }
3478
3479 /*
3480 * If the buffer couldn't be cloned, add it to bf_q;
3481 * the caller will free the buffer(s) as required.
3482 */
3483 if (nbf == NULL) {
3484 DPRINTF(sc, ATH_DEBUG_SW_TX_FILT,
3485 "%s: buffer couldn't be cloned! (%p)\n",
3486 __func__, bf);
3487 TAILQ_INSERT_TAIL(bf_q, bf, bf_list);
3488 } else {
3489 ath_tx_tid_filt_comp_buf(sc, tid, nbf);
3490 }
3491next:
3492 bf = bf_next;
3493 }
3494
3495 ath_tx_tid_filt_comp_complete(sc, tid);
3496}
3497
3498/*
3499 * Suspend the queue because we need to TX a BAR.
3500 */
3501static void
3502ath_tx_tid_bar_suspend(struct ath_softc *sc, struct ath_tid *tid)
3503{
3504
3505 ATH_TX_LOCK_ASSERT(sc);
3506
3507 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3508 "%s: tid=%d, bar_wait=%d, bar_tx=%d, called\n",
3509 __func__,
3510 tid->tid,
3511 tid->bar_wait,
3512 tid->bar_tx);
3513
3514 /* We shouldn't be called when bar_tx is 1 */
3515 if (tid->bar_tx) {
3516 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3517 "%s: bar_tx is 1?!\n", __func__);
3518 }
3519
3520 /* If we've already been called, just be patient. */
3521 if (tid->bar_wait)
3522 return;
3523
3524 /* Wait! */
3525 tid->bar_wait = 1;
3526
3527 /* Only one pause, no matter how many frames fail */
3528 ath_tx_tid_pause(sc, tid);
3529}
3530
3531/*
3532 * We've finished with BAR handling - either we succeeded or
3533 * failed. Either way, unsuspend TX.
3534 */
3535static void
3536ath_tx_tid_bar_unsuspend(struct ath_softc *sc, struct ath_tid *tid)
3537{
3538
3539 ATH_TX_LOCK_ASSERT(sc);
3540
3541 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3542 "%s: %6D: TID=%d, called\n",
3543 __func__,
3544 tid->an->an_node.ni_macaddr,
3545 ":",
3546 tid->tid);
3547
3548 if (tid->bar_tx == 0 || tid->bar_wait == 0) {
3549 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3550 "%s: %6D: TID=%d, bar_tx=%d, bar_wait=%d: ?\n",
3551 __func__, tid->an->an_node.ni_macaddr, ":",
3552 tid->tid, tid->bar_tx, tid->bar_wait);
3553 }
3554
3555 tid->bar_tx = tid->bar_wait = 0;
3556 ath_tx_tid_resume(sc, tid);
3557}
3558
3559/*
3560 * Return whether we're ready to TX a BAR frame.
3561 *
3562 * Requires the TID lock be held.
3563 */
3564static int
3565ath_tx_tid_bar_tx_ready(struct ath_softc *sc, struct ath_tid *tid)
3566{
3567
3568 ATH_TX_LOCK_ASSERT(sc);
3569
3570 if (tid->bar_wait == 0 || tid->hwq_depth > 0)
3571 return (0);
3572
3573 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3574 "%s: %6D: TID=%d, bar ready\n",
3575 __func__,
3576 tid->an->an_node.ni_macaddr,
3577 ":",
3578 tid->tid);
3579
3580 return (1);
3581}
3582
3583/*
3584 * Check whether the current TID is ready to have a BAR
3585 * TXed and if so, do the TX.
3586 *
3587 * Since the TID/TXQ lock can't be held during a call to
3588 * ieee80211_send_bar(), we have to do the dirty thing of unlocking it,
3589 * sending the BAR and locking it again.
3590 *
3591 * Eventually, the code to send the BAR should be broken out
3592 * from this routine so the lock doesn't have to be reacquired
3593 * just to be immediately dropped by the caller.
3594 */
3595static void
3596ath_tx_tid_bar_tx(struct ath_softc *sc, struct ath_tid *tid)
3597{
3598 struct ieee80211_tx_ampdu *tap;
3599
3600 ATH_TX_LOCK_ASSERT(sc);
3601
3602 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3603 "%s: %6D: TID=%d, called\n",
3604 __func__,
3605 tid->an->an_node.ni_macaddr,
3606 ":",
3607 tid->tid);
3608
3609 tap = ath_tx_get_tx_tid(tid->an, tid->tid);
3610
3611 /*
3612 * This is an error condition!
3613 */
3614 if (tid->bar_wait == 0 || tid->bar_tx == 1) {
3615 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3616 "%s: %6D: TID=%d, bar_tx=%d, bar_wait=%d: ?\n",
3617 __func__, tid->an->an_node.ni_macaddr, ":",
3618 tid->tid, tid->bar_tx, tid->bar_wait);
3619 return;
3620 }
3621
3622 /* Don't do anything if we still have pending frames */
3623 if (tid->hwq_depth > 0) {
3624 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3625 "%s: %6D: TID=%d, hwq_depth=%d, waiting\n",
3626 __func__,
3627 tid->an->an_node.ni_macaddr,
3628 ":",
3629 tid->tid,
3630 tid->hwq_depth);
3631 return;
3632 }
3633
3634 /* We're now about to TX */
3635 tid->bar_tx = 1;
3636
3637 /*
3638 * Override the clrdmask configuration for the next frame,
3639 * just to get the ball rolling.
3640 */
3641 ath_tx_set_clrdmask(sc, tid->an);
3642
3643 /*
3644 * Calculate new BAW left edge, now that all frames have either
3645 * succeeded or failed.
3646 *
3647 * XXX verify this is _actually_ the valid value to begin at!
3648 */
3649 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3650 "%s: %6D: TID=%d, new BAW left edge=%d\n",
3651 __func__,
3652 tid->an->an_node.ni_macaddr,
3653 ":",
3654 tid->tid,
3655 tap->txa_start);
3656
3657 /* Try sending the BAR frame */
3658 /* We can't hold the lock here! */
3659
3660 ATH_TX_UNLOCK(sc);
3661 if (ieee80211_send_bar(&tid->an->an_node, tap, tap->txa_start) == 0) {
3662 /* Success? Now we wait for notification that it's done */
3663 ATH_TX_LOCK(sc);
3664 return;
3665 }
3666
3667 /* Failure? For now, warn loudly and continue */
3668 ATH_TX_LOCK(sc);
3669 DPRINTF(sc, ATH_DEBUG_SW_TX_BAR,
3670 "%s: %6D: TID=%d, failed to TX BAR, continue!\n",
3671 __func__, tid->an->an_node.ni_macaddr, ":",
3672 tid->tid);
3673 ath_tx_tid_bar_unsuspend(sc, tid);
3674}
3675
3676static void
3677ath_tx_tid_drain_pkt(struct ath_softc *sc, struct ath_node *an,
3678 struct ath_tid *tid, ath_bufhead *bf_cq, struct ath_buf *bf)
3679{
3680
3681 ATH_TX_LOCK_ASSERT(sc);
3682
3683 /*
3684 * If the current TID is running AMPDU, update
3685 * the BAW.
3686 */
3687 if (ath_tx_ampdu_running(sc, an, tid->tid) &&
3688 bf->bf_state.bfs_dobaw) {
3689 /*
3690 * Only remove the frame from the BAW if it's
3691 * been transmitted at least once; this means
3692 * the frame was in the BAW to begin with.
3693 */
3694 if (bf->bf_state.bfs_retries > 0) {
3695 ath_tx_update_baw(sc, an, tid, bf);
3696 bf->bf_state.bfs_dobaw = 0;
3697 }
3698#if 0
3699 /*
3700 * This has become a non-fatal error now
3701 */
3702 if (! bf->bf_state.bfs_addedbaw)
3703 DPRINTF(sc, ATH_DEBUG_SW_TX_BAW
3704 "%s: wasn't added: seqno %d\n",
3705 __func__, SEQNO(bf->bf_state.bfs_seqno));
3706#endif
3707 }
3708
3709 /* Strip it out of an aggregate list if it was in one */
3710 bf->bf_next = NULL;
3711
3712 /* Insert on the free queue to be freed by the caller */
3713 TAILQ_INSERT_TAIL(bf_cq, bf, bf_list);
3714}
3715
3716static void
3717ath_tx_tid_drain_print(struct ath_softc *sc, struct ath_node *an,
3718 const char *pfx, struct ath_tid *tid, struct ath_buf *bf)
3719{
3720 struct ieee80211_node *ni = &an->an_node;
3721 struct ath_txq *txq;
3722 struct ieee80211_tx_ampdu *tap;
3723
3724 txq = sc->sc_ac2q[tid->ac];
3725 tap = ath_tx_get_tx_tid(an, tid->tid);
3726
3727 DPRINTF(sc, ATH_DEBUG_SW_TX,
3728 "%s: %s: %6D: bf=%p: addbaw=%d, dobaw=%d, "
3729 "seqno=%d, retry=%d\n",
3730 __func__,
3731 pfx,
3732 ni->ni_macaddr,
3733 ":",
3734 bf,
3735 bf->bf_state.bfs_addedbaw,
3736 bf->bf_state.bfs_dobaw,
3737 SEQNO(bf->bf_state.bfs_seqno),
3738 bf->bf_state.bfs_retries);
3739 DPRINTF(sc, ATH_DEBUG_SW_TX,
3740 "%s: %s: %6D: bf=%p: txq[%d] axq_depth=%d, axq_aggr_depth=%d\n",
3741 __func__,
3742 pfx,
3743 ni->ni_macaddr,
3744 ":",
3745 bf,
3746 txq->axq_qnum,
3747 txq->axq_depth,
3748 txq->axq_aggr_depth);
3749 DPRINTF(sc, ATH_DEBUG_SW_TX,
3750 "%s: %s: %6D: bf=%p: tid txq_depth=%d hwq_depth=%d, bar_wait=%d, "
3751 "isfiltered=%d\n",
3752 __func__,
3753 pfx,
3754 ni->ni_macaddr,
3755 ":",
3756 bf,
3757 tid->axq_depth,
3758 tid->hwq_depth,
3759 tid->bar_wait,
3760 tid->isfiltered);
3761 DPRINTF(sc, ATH_DEBUG_SW_TX,
3762 "%s: %s: %6D: tid %d: "
3763 "sched=%d, paused=%d, "
3764 "incomp=%d, baw_head=%d, "
3765 "baw_tail=%d txa_start=%d, ni_txseqs=%d\n",
3766 __func__,
3767 pfx,
3768 ni->ni_macaddr,
3769 ":",
3770 tid->tid,
3771 tid->sched, tid->paused,
3772 tid->incomp, tid->baw_head,
3773 tid->baw_tail, tap == NULL ? -1 : tap->txa_start,
3774 ni->ni_txseqs[tid->tid]);
3775
3776 /* XXX Dump the frame, see what it is? */
3777 ieee80211_dump_pkt(ni->ni_ic,
3778 mtod(bf->bf_m, const uint8_t *),
3779 bf->bf_m->m_len, 0, -1);
3780}
3781
3782/*
3783 * Free any packets currently pending in the software TX queue.
3784 *
3785 * This will be called when a node is being deleted.
3786 *
3787 * It can also be called on an active node during an interface
3788 * reset or state transition.
3789 *
3790 * (From Linux/reference):
3791 *
3792 * TODO: For frame(s) that are in the retry state, we will reuse the
3793 * sequence number(s) without setting the retry bit. The
3794 * alternative is to give up on these and BAR the receiver's window
3795 * forward.
3796 */
3797static void
3798ath_tx_tid_drain(struct ath_softc *sc, struct ath_node *an,
3799 struct ath_tid *tid, ath_bufhead *bf_cq)
3800{
3801 struct ath_buf *bf;
3802 struct ieee80211_tx_ampdu *tap;
3803 struct ieee80211_node *ni = &an->an_node;
3804 int t;
3805
3806 tap = ath_tx_get_tx_tid(an, tid->tid);
3807
3808 ATH_TX_LOCK_ASSERT(sc);
3809
3810 /* Walk the queue, free frames */
3811 t = 0;
3812 for (;;) {
3813 bf = ATH_TID_FIRST(tid);
3814 if (bf == NULL) {
3815 break;
3816 }
3817
3818 if (t == 0) {
3819 ath_tx_tid_drain_print(sc, an, "norm", tid, bf);
3820 t = 1;
3821 }
3822
3823 ATH_TID_REMOVE(tid, bf, bf_list);
3824 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf);
3825 }
3826
3827 /* And now, drain the filtered frame queue */
3828 t = 0;
3829 for (;;) {
3830 bf = ATH_TID_FILT_FIRST(tid);
3831 if (bf == NULL)
3832 break;
3833
3834 if (t == 0) {
3835 ath_tx_tid_drain_print(sc, an, "filt", tid, bf);
3836 t = 1;
3837 }
3838
3839 ATH_TID_FILT_REMOVE(tid, bf, bf_list);
3840 ath_tx_tid_drain_pkt(sc, an, tid, bf_cq, bf);
3841 }
3842
3843 /*
3844 * Override the clrdmask configuration for the next frame
3845 * in case there is some future transmission, just to get
3846 * the ball rolling.
3847 *
3848 * This won't hurt things if the TID is about to be freed.
3849 */
3850 ath_tx_set_clrdmask(sc, tid->an);
3851
3852 /*
3853 * Now that it's completed, grab the TID lock and update
3854 * the sequence number and BAW window.
3855 * Because sequence numbers have been assigned to frames
3856 * that haven't been sent yet, it's entirely possible
3857 * we'll be called with some pending frames that have not
3858 * been transmitted.
3859 *
3860 * The cleaner solution is to do the sequence number allocation
3861 * when the packet is first transmitted - and thus the "retries"
3862 * check above would be enough to update the BAW/seqno.
3863 */
3864
3865 /* But don't do it for non-QoS TIDs */
3866 if (tap) {
3867#if 1
3868 DPRINTF(sc, ATH_DEBUG_SW_TX_CTRL,
3869 "%s: %6D: node %p: TID %d: sliding BAW left edge to %d\n",
3870 __func__,
3871 ni->ni_macaddr,
3872 ":",
3873 an,
3874 tid->tid,
3875 tap->txa_start);
3876#endif
3877 ni->ni_txseqs[tid->tid] = tap->txa_start;
3878 tid->baw_tail = tid->baw_head;
3879 }
3880}
3881
3882/*
3883 * Reset the TID state. This must be only called once the node has
3884 * had its frames flushed from this TID, to ensure that no other
3885 * pause / unpause logic can kick in.
3886 */
3887static void
3888ath_tx_tid_reset(struct ath_softc *sc, struct ath_tid *tid)
3889{
3890
3891#if 0
3892 tid->bar_wait = tid->bar_tx = tid->isfiltered = 0;
3893 tid->paused = tid->sched = tid->addba_tx_pending = 0;
3894 tid->incomp = tid->cleanup_inprogress = 0;
3895#endif
3896
3897 /*
3898 * If we have a bar_wait set, we need to unpause the TID
3899 * here. Otherwise once cleanup has finished, the TID won't
3900 * have the right paused counter.
3901 *
3902 * XXX I'm not going through resume here - I don't want the
3903 * node to be rescheuled just yet. This however should be
3904 * methodized!
3905 */
3906 if (tid->bar_wait) {
3907 if (tid->paused > 0) {
3908 tid->paused --;
3909 }
3910 }
3911
3912 /*
3913 * XXX same with a currently filtered TID.
3914 *
3915 * Since this is being called during a flush, we assume that
3916 * the filtered frame list is actually empty.
3917 *
3918 * XXX TODO: add in a check to ensure that the filtered queue
3919 * depth is actually 0!
3920 */
3921 if (tid->isfiltered) {
3922 if (tid->paused > 0) {
3923 tid->paused --;
3924 }
3925 }
3926
3927 /*
3928 * Clear BAR, filtered frames, scheduled and ADDBA pending.
3929 * The TID may be going through cleanup from the last association
3930 * where things in the BAW are still in the hardware queue.
3931 */
3932 tid->bar_wait = 0;
3933 tid->bar_tx = 0;
3934 tid->isfiltered = 0;
3935 tid->sched = 0;
3936 tid->addba_tx_pending = 0;
3937
3938 /*
3939 * XXX TODO: it may just be enough to walk the HWQs and mark
3940 * frames for that node as non-aggregate; or mark the ath_node
3941 * with something that indicates that aggregation is no longer
3942 * occuring. Then we can just toss the BAW complaints and
3943 * do a complete hard reset of state here - no pause, no
3944 * complete counter, etc.
3945 */
3946
3947}
3948
3949/*
3950 * Flush all software queued packets for the given node.
3951 *
3952 * This occurs when a completion handler frees the last buffer
3953 * for a node, and the node is thus freed. This causes the node
3954 * to be cleaned up, which ends up calling ath_tx_node_flush.
3955 */
3956void
3957ath_tx_node_flush(struct ath_softc *sc, struct ath_node *an)
3958{
3959 int tid;
3960 ath_bufhead bf_cq;
3961 struct ath_buf *bf;
3962
3963 TAILQ_INIT(&bf_cq);
3964
3965 ATH_KTR(sc, ATH_KTR_NODE, 1, "ath_tx_node_flush: flush node; ni=%p",
3966 &an->an_node);
3967
3968 ATH_TX_LOCK(sc);
3969 DPRINTF(sc, ATH_DEBUG_NODE,
3970 "%s: %6D: flush; is_powersave=%d, stack_psq=%d, tim=%d, "
3971 "swq_depth=%d, clrdmask=%d, leak_count=%d\n",
3972 __func__,
3973 an->an_node.ni_macaddr,
3974 ":",
3975 an->an_is_powersave,
3976 an->an_stack_psq,
3977 an->an_tim_set,
3978 an->an_swq_depth,
3979 an->clrdmask,
3980 an->an_leak_count);
3981
3982 for (tid = 0; tid < IEEE80211_TID_SIZE; tid++) {
3983 struct ath_tid *atid = &an->an_tid[tid];
3984
3985 /* Free packets */
3986 ath_tx_tid_drain(sc, an, atid, &bf_cq);
3987
3988 /* Remove this tid from the list of active tids */
3989 ath_tx_tid_unsched(sc, atid);
3990
3991 /* Reset the per-TID pause, BAR, etc state */
3992 ath_tx_tid_reset(sc, atid);
3993 }
3994
3995 /*
3996 * Clear global leak count
3997 */
3998 an->an_leak_count = 0;
3999 ATH_TX_UNLOCK(sc);
4000
4001 /* Handle completed frames */
4002 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
4003 TAILQ_REMOVE(&bf_cq, bf, bf_list);
4004 ath_tx_default_comp(sc, bf, 0);
4005 }
4006}
4007
4008/*
4009 * Drain all the software TXQs currently with traffic queued.
4010 */
4011void
4012ath_tx_txq_drain(struct ath_softc *sc, struct ath_txq *txq)
4013{
4014 struct ath_tid *tid;
4015 ath_bufhead bf_cq;
4016 struct ath_buf *bf;
4017
4018 TAILQ_INIT(&bf_cq);
4019 ATH_TX_LOCK(sc);
4020
4021 /*
4022 * Iterate over all active tids for the given txq,
4023 * flushing and unsched'ing them
4024 */
4025 while (! TAILQ_EMPTY(&txq->axq_tidq)) {
4026 tid = TAILQ_FIRST(&txq->axq_tidq);
4027 ath_tx_tid_drain(sc, tid->an, tid, &bf_cq);
4028 ath_tx_tid_unsched(sc, tid);
4029 }
4030
4031 ATH_TX_UNLOCK(sc);
4032
4033 while ((bf = TAILQ_FIRST(&bf_cq)) != NULL) {
4034 TAILQ_REMOVE(&bf_cq, bf, bf_list);
4035 ath_tx_default_comp(sc, bf, 0);
4036 }
4037}
4038
4039/*
4040 * Handle completion of non-aggregate session frames.
4041 *
4042 * This (currently) doesn't implement software retransmission of
4043 * non-aggregate frames!
4044 *