ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath / if_athvar.h
CommitLineData
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1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
572ff6f6 29 * $FreeBSD$
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30 */
31
32/*
33 * Defintions for the Atheros Wireless LAN controller driver.
34 */
35#ifndef _DEV_ATH_ATHVAR_H
36#define _DEV_ATH_ATHVAR_H
37
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38#include <machine/atomic.h>
39
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40#include <dev/netif/ath/ath_hal/ah.h>
41#include <dev/netif/ath/ath_hal/ah_desc.h>
42#include <netproto/802_11/ieee80211_radiotap.h>
43#include <dev/netif/ath/ath/if_athioctl.h>
44#include <dev/netif/ath/ath/if_athrate.h>
572ff6f6 45#ifdef ATH_DEBUG_ALQ
5cd80a8c 46#include <dev/netif/ath/ath/if_ath_alq.h>
572ff6f6 47#endif
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48
49#define ATH_TIMEOUT 1000
50
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51/*
52 * There is a separate TX ath_buf pool for management frames.
53 * This ensures that management frames such as probe responses
54 * and BAR frames can be transmitted during periods of high
55 * TX activity.
56 */
57#define ATH_MGMT_TXBUF 32
58
59/*
60 * 802.11n requires more TX and RX buffers to do AMPDU.
61 */
62#ifdef ATH_ENABLE_11N
63#define ATH_TXBUF 512
64#define ATH_RXBUF 512
65#endif
66
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67#ifndef ATH_RXBUF
68#define ATH_RXBUF 40 /* number of RX buffers */
69#endif
70#ifndef ATH_TXBUF
86877dfb 71#define ATH_TXBUF 200 /* number of TX buffers */
193b341d 72#endif
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73#define ATH_BCBUF 4 /* number of beacon buffers */
74
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75#define ATH_TXDESC 10 /* number of descriptors per buffer */
76#define ATH_TXMAXTRY 11 /* max number of transmit attempts */
77#define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
78#define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
79
572ff6f6 80#define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */
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81#define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
82#define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
83
84/*
85 * The key cache is used for h/w cipher state and also for
86 * tracking station state such as the current tx antenna.
87 * We also setup a mapping table between key cache slot indices
88 * and station state to short-circuit node lookups on rx.
89 * Different parts have different size key caches. We handle
90 * up to ATH_KEYMAX entries (could dynamically allocate state).
91 */
92#define ATH_KEYMAX 128 /* max key cache size we handle */
93#define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
94
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95struct taskqueue;
96struct kthread;
97struct ath_buf;
98
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99#define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX)
100
101/*
102 * Per-TID state
103 *
104 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
105 */
106struct ath_tid {
107 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */
108 struct ath_node *an; /* pointer to parent */
109 int tid; /* tid */
110 int ac; /* which AC gets this trafic */
111 int hwq_depth; /* how many buffers are on HW */
112 u_int axq_depth; /* SW queue depth */
113
114 struct {
115 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */
116 u_int axq_depth; /* SW queue depth */
117 } filtq;
118
119 /*
120 * Entry on the ath_txq; when there's traffic
121 * to send
122 */
123 TAILQ_ENTRY(ath_tid) axq_qelem;
124 int sched;
125 int paused; /* >0 if the TID has been paused */
126
127 /*
128 * These are flags - perhaps later collapse
129 * down to a single uint32_t ?
130 */
131 int addba_tx_pending; /* TX ADDBA pending */
132 int bar_wait; /* waiting for BAR */
133 int bar_tx; /* BAR TXed */
134 int isfiltered; /* is this node currently filtered */
135
136 /*
137 * Is the TID being cleaned up after a transition
138 * from aggregation to non-aggregation?
139 * When this is set to 1, this TID will be paused
140 * and no further traffic will be queued until all
141 * the hardware packets pending for this TID have been
142 * TXed/completed; at which point (non-aggregation)
143 * traffic will resume being TXed.
144 */
145 int cleanup_inprogress;
146 /*
147 * How many hardware-queued packets are
148 * waiting to be cleaned up.
149 * This is only valid if cleanup_inprogress is 1.
150 */
151 int incomp;
152
153 /*
154 * The following implements a ring representing
155 * the frames in the current BAW.
156 * To avoid copying the array content each time
157 * the BAW is moved, the baw_head/baw_tail point
158 * to the current BAW begin/end; when the BAW is
159 * shifted the head/tail of the array are also
160 * appropriately shifted.
161 */
162 /* active tx buffers, beginning at current BAW */
163 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
164 /* where the baw head is in the array */
165 int baw_head;
166 /* where the BAW tail is in the array */
167 int baw_tail;
168};
169
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170/* driver-specific node state */
171struct ath_node {
172 struct ieee80211_node an_node; /* base class */
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173 u_int8_t an_mgmtrix; /* min h/w rate index */
174 u_int8_t an_mcastrix; /* mcast h/w rate index */
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175 uint32_t an_is_powersave; /* node is sleeping */
176 uint32_t an_stack_psq; /* net80211 psq isn't empty */
177 uint32_t an_tim_set; /* TIM has been set */
86877dfb 178 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */
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179 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */
180 char an_name[32]; /* eg "wlan0_a1" */
3133c5e3 181#if 0
572ff6f6 182 struct mtx an_mtx; /* protecting the rate control state */
3133c5e3 183#endif
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184 uint32_t an_swq_depth; /* how many SWQ packets for this
185 node */
186 int clrdmask; /* has clrdmask been set */
187 uint32_t an_leak_count; /* How many frames to leak during pause */
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188 /* variable-length rate control state follows */
189};
190#define ATH_NODE(ni) ((struct ath_node *)(ni))
191#define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
192
193#define ATH_RSSI_LPF_LEN 10
194#define ATH_RSSI_DUMMY_MARKER 0x127
195#define ATH_EP_MUL(x, mul) ((x) * (mul))
196#define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
197#define ATH_LPF_RSSI(x, y, len) \
198 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
199#define ATH_RSSI_LPF(x, y) do { \
200 if ((y) >= -20) \
201 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
202} while (0)
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203#define ATH_EP_RND(x,mul) \
204 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
205#define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
193b341d 206
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207typedef enum {
208 ATH_BUFTYPE_NORMAL = 0,
209 ATH_BUFTYPE_MGMT = 1,
210} ath_buf_type_t;
211
193b341d 212struct ath_buf {
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213 TAILQ_ENTRY(ath_buf) bf_list;
214 struct ath_buf * bf_next; /* next buffer in the aggregate */
193b341d 215 int bf_nseg;
572ff6f6 216 HAL_STATUS bf_rxstatus;
86877dfb 217 uint16_t bf_flags; /* status flags (below) */
572ff6f6 218 uint16_t bf_descid; /* 16 bit descriptor ID */
193b341d 219 struct ath_desc *bf_desc; /* virtual addr of desc */
8982d733 220 struct ath_desc_status bf_status; /* tx/rx status */
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221 bus_addr_t bf_daddr; /* physical addr of desc */
222 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
223 struct mbuf *bf_m; /* mbuf for buf */
224 struct ieee80211_node *bf_node; /* pointer to the node */
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225 struct ath_desc *bf_lastds; /* last descriptor for comp status */
226 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */
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227 bus_size_t bf_mapsize;
228#define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
229 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
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230 uint32_t bf_nextfraglen; /* length of next fragment */
231
232 /* Completion function to call on TX complete (fail or not) */
233 /*
234 * "fail" here is set to 1 if the queue entries were removed
235 * through a call to ath_tx_draintxq().
236 */
237 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail);
238
239 /* This state is kept to support software retries and aggregation */
240 struct {
241 uint16_t bfs_seqno; /* sequence number of this packet */
242 uint16_t bfs_ndelim; /* number of delims for padding */
243
244 uint8_t bfs_retries; /* retry count */
245 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */
246 uint8_t bfs_nframes; /* number of frames in aggregate */
247 uint8_t bfs_pri; /* packet AC priority */
248 uint8_t bfs_tx_queue; /* destination hardware TX queue */
249
250 u_int32_t bfs_aggr:1, /* part of aggregate? */
251 bfs_aggrburst:1, /* part of aggregate burst? */
252 bfs_isretried:1, /* retried frame? */
253 bfs_dobaw:1, /* actually check against BAW? */
254 bfs_addedbaw:1, /* has been added to the BAW */
255 bfs_shpream:1, /* use short preamble */
256 bfs_istxfrag:1, /* is fragmented */
257 bfs_ismrr:1, /* do multi-rate TX retry */
258 bfs_doprot:1, /* do RTS/CTS based protection */
259 bfs_doratelookup:1; /* do rate lookup before each TX */
260
261 /*
262 * These fields are passed into the
263 * descriptor setup functions.
264 */
265
266 /* Make this an 8 bit value? */
267 HAL_PKT_TYPE bfs_atype; /* packet type */
268
269 uint32_t bfs_pktlen; /* length of this packet */
270
271 uint16_t bfs_hdrlen; /* length of this packet header */
272 uint16_t bfs_al; /* length of aggregate */
273
274 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */
275 uint8_t bfs_txrate0; /* first TX rate */
276 uint8_t bfs_try0; /* first try count */
277
278 uint16_t bfs_txpower; /* tx power */
279 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */
280 uint8_t bfs_ctsrate; /* CTS rate */
281
282 /* 16 bit? */
283 int32_t bfs_keyix; /* crypto key index */
284 int32_t bfs_txantenna; /* TX antenna config */
285
286 /* Make this an 8 bit value? */
287 enum ieee80211_protmode bfs_protmode;
288
289 /* 16 bit? */
290 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */
291 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */
292 } bf_state;
193b341d 293};
572ff6f6 294typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead;
193b341d 295
572ff6f6 296#define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */
86877dfb 297#define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */
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298#define ATH_BUF_FIFOEND 0x00000004
299#define ATH_BUF_FIFOPTR 0x00000008
300
301#define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT)
86877dfb 302
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303/*
304 * DMA state for tx/rx descriptors.
305 */
306struct ath_descdma {
307 const char* dd_name;
308 struct ath_desc *dd_desc; /* descriptors */
572ff6f6 309 int dd_descsize; /* size of single descriptor */
193b341d 310 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
ed33fa9f 311 bus_size_t dd_desc_len; /* size of dd_desc */
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312 bus_dma_segment_t dd_dseg;
313 bus_dma_tag_t dd_dmat; /* bus DMA tag */
314 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
315 struct ath_buf *dd_bufptr; /* associated buffers */
316};
317
318/*
319 * Data transmit queue state. One of these exists for each
320 * hardware transmit queue. Packets sent to us from above
321 * are assigned to queues based on their priority. Not all
322 * devices support a complete set of hardware transmit queues.
323 * For those devices the array sc_ac2q will map multiple
324 * priorities to fewer hardware queues (typically all to one
325 * hardware queue).
326 */
327struct ath_txq {
572ff6f6 328 struct ath_softc *axq_softc; /* Needed for scheduling */
193b341d 329 u_int axq_qnum; /* hardware q number */
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330#define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */
331 u_int axq_ac; /* WME AC */
332 u_int axq_flags;
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333//#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */
334#define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */
193b341d 335 u_int axq_depth; /* queue depth (stat only) */
572ff6f6 336 u_int axq_aggr_depth; /* how many aggregates are queued */
193b341d 337 u_int axq_intrcnt; /* interrupt count */
86877dfb 338 u_int32_t *axq_link; /* link ptr in last TX desc */
572ff6f6 339 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */
3133c5e3 340 struct lock axq_lock; /* lock on q and link */
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341
342 /*
343 * This is the FIFO staging buffer when doing EDMA.
344 *
345 * For legacy chips, we just push the head pointer to
346 * the hardware and we ignore this list.
347 *
348 * For EDMA, the staging buffer is treated as normal;
349 * when it's time to push a list of frames to the hardware
350 * we move that list here and we stamp buffers with
351 * flags to identify the beginning/end of that particular
352 * FIFO entry.
353 */
354 struct {
355 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q;
356 u_int axq_depth;
357 } fifo;
358 u_int axq_fifo_depth; /* depth of FIFO frames */
359
360 /*
361 * XXX the holdingbf field is protected by the TXBUF lock
362 * for now, NOT the TXQ lock.
363 *
364 * Architecturally, it would likely be better to move
365 * the holdingbf field to a separate array in ath_softc
366 * just to highlight that it's not protected by the normal
367 * TX path lock.
368 */
369 struct ath_buf *axq_holdingbf; /* holding TX buffer */
193b341d 370 char axq_name[12]; /* e.g. "ath0_txq4" */
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371
372 /* Per-TID traffic queue for software -> hardware TX */
373 /*
374 * This is protected by the general TX path lock, not (for now)
375 * by the TXQ lock.
376 */
377 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq;
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378};
379
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380#ifdef __DragonFly__
381/* already serialized by wlan_serializer */
382#define IF_LOCK(ifp)
383#define IF_UNLOCK(ifp)
384#define IEEE80211_LOCK_ASSERT(ic)
385#define IEEE80211_LOCK(ic)
386#define IEEE80211_UNLOCK(ic)
387#endif
388
389#define ATH_TXQ_LOCK_INIT(_sc, _tq)
390#define ATH_TXQ_LOCK_DESTROY(_tq)
391#define ATH_TXQ_LOCK(_tq)
392#define ATH_TXQ_UNLOCK(_tq)
393#define ATH_TXQ_LOCK_ASSERT(_tq)
394#define ATH_TXQ_UNLOCK_ASSERT(_tq)
395
396#define ATH_NODE_LOCK(_an)
397#define ATH_NODE_UNLOCK(_an)
398#define ATH_NODE_LOCK_ASSERT(_an)
399#define ATH_NODE_UNLOCK_ASSERT(_an)
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400
401/*
402 * These are for the hardware queue.
403 */
404#define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
405 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
406 (_tq)->axq_depth++; \
407} while (0)
193b341d 408#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
572ff6f6 409 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
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410 (_tq)->axq_depth++; \
411} while (0)
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412#define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
413 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
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414 (_tq)->axq_depth--; \
415} while (0)
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416#define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q)
417#define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field)
418
419/*
420 * These are for the TID software queue.
421 */
422#define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \
423 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
424 (_tq)->axq_depth++; \
425 (_tq)->an->an_swq_depth++; \
426} while (0)
427#define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \
428 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
429 (_tq)->axq_depth++; \
430 (_tq)->an->an_swq_depth++; \
431} while (0)
432#define ATH_TID_REMOVE(_tq, _elm, _field) do { \
433 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
434 (_tq)->axq_depth--; \
435 (_tq)->an->an_swq_depth--; \
436} while (0)
437#define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q)
438#define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field)
439
440/*
441 * These are for the TID filtered frame queue
442 */
443#define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \
444 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
445 (_tq)->axq_depth++; \
446 (_tq)->an->an_swq_depth++; \
447} while (0)
448#define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \
449 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
450 (_tq)->axq_depth++; \
451 (_tq)->an->an_swq_depth++; \
452} while (0)
453#define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \
454 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
455 (_tq)->axq_depth--; \
456 (_tq)->an->an_swq_depth--; \
457} while (0)
458#define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q)
459#define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
193b341d 460
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461struct ath_vap {
462 struct ieee80211vap av_vap; /* base class */
463 int av_bslot; /* beacon slot index */
464 struct ath_buf *av_bcbuf; /* beacon buffer */
465 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
466 struct ath_txq av_mcastq; /* buffered mcast s/w queue */
193b341d 467
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468 void (*av_recv_mgmt)(struct ieee80211_node *,
469 struct mbuf *, int, int, int);
470 int (*av_newstate)(struct ieee80211vap *,
471 enum ieee80211_state, int);
472 void (*av_bmiss)(struct ieee80211vap *);
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473 void (*av_node_ps)(struct ieee80211_node *, int);
474 int (*av_set_tim)(struct ieee80211_node *, int);
475 void (*av_recv_pspoll)(struct ieee80211_node *,
476 struct mbuf *);
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477};
478#define ATH_VAP(vap) ((struct ath_vap *)(vap))
193b341d 479
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480struct taskqueue;
481struct ath_tx99;
193b341d 482
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483/*
484 * Whether to reset the TX/RX queue with or without
485 * a queue flush.
486 */
487typedef enum {
488 ATH_RESET_DEFAULT = 0,
489 ATH_RESET_NOLOSS = 1,
490 ATH_RESET_FULL = 2,
491} ATH_RESET_TYPE;
492
493struct ath_rx_methods {
494 void (*recv_sched_queue)(struct ath_softc *sc,
495 HAL_RX_QUEUE q, int dosched);
496 void (*recv_sched)(struct ath_softc *sc, int dosched);
497 void (*recv_stop)(struct ath_softc *sc, int dodelay);
498 int (*recv_start)(struct ath_softc *sc);
499 void (*recv_flush)(struct ath_softc *sc);
500 void (*recv_tasklet)(void *arg, int npending);
501 int (*recv_rxbuf_init)(struct ath_softc *sc,
502 struct ath_buf *bf);
503 int (*recv_setup)(struct ath_softc *sc);
504 int (*recv_teardown)(struct ath_softc *sc);
505};
506
507/*
508 * Represent the current state of the RX FIFO.
509 */
510struct ath_rx_edma {
511 struct ath_buf **m_fifo;
512 int m_fifolen;
513 int m_fifo_head;
514 int m_fifo_tail;
515 int m_fifo_depth;
516 struct mbuf *m_rxpending;
517};
518
519struct ath_tx_edma_fifo {
520 struct ath_buf **m_fifo;
521 int m_fifolen;
522 int m_fifo_head;
523 int m_fifo_tail;
524 int m_fifo_depth;
525};
526
527struct ath_tx_methods {
528 int (*xmit_setup)(struct ath_softc *sc);
529 int (*xmit_teardown)(struct ath_softc *sc);
530 void (*xmit_attach_comp_func)(struct ath_softc *sc);
531
532 void (*xmit_dma_restart)(struct ath_softc *sc,
533 struct ath_txq *txq);
534 void (*xmit_handoff)(struct ath_softc *sc,
535 struct ath_txq *txq, struct ath_buf *bf);
536 void (*xmit_drain)(struct ath_softc *sc,
537 ATH_RESET_TYPE reset_type);
538};
539
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540struct ath_softc {
541 struct ifnet *sc_ifp; /* interface common */
193b341d 542 struct ath_stats sc_stats; /* interface statistics */
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543 struct ath_tx_aggr_stats sc_aggr_stats;
544 struct ath_intr_stats sc_intr_stats;
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545 struct sysctl_ctx_list sc_sysctl_ctx;
546 struct sysctl_oid *sc_sysctl_tree;
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547 uint64_t sc_debug;
548 uint64_t sc_ktrdebug;
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549 int sc_nvaps; /* # vaps */
550 int sc_nstavaps; /* # station vaps */
551 int sc_nmeshvaps; /* # mbss vaps */
552 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
553 u_int8_t sc_nbssid0; /* # vap's using base mac */
554 uint32_t sc_bssidmask; /* bssid mask */
555
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556 struct ath_rx_methods sc_rx;
557 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */
558 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */
559 struct ath_tx_methods sc_tx;
560 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES];
561
562 /*
563 * This is (currently) protected by the TX queue lock;
564 * it should migrate to a separate lock later
565 * so as to minimise contention.
566 */
567 ath_bufhead sc_txbuf_list;
568
569 int sc_rx_statuslen;
570 int sc_tx_desclen;
571 int sc_tx_statuslen;
572 int sc_tx_nmaps; /* Number of TX maps */
573 int sc_edma_bufsize;
574
575 void (*sc_node_cleanup)(struct ieee80211_node *);
193b341d
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576 void (*sc_node_free)(struct ieee80211_node *);
577 device_t sc_dev;
8982d733
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578 HAL_BUS_TAG sc_st; /* bus space tag */
579 HAL_BUS_HANDLE sc_sh; /* bus space handle */
193b341d 580 bus_dma_tag_t sc_dmat; /* bus DMA tag */
3133c5e3 581#if 0
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582 struct mtx sc_mtx; /* master lock (recursive) */
583 struct mtx sc_pcu_mtx; /* PCU access mutex */
584 char sc_pcu_mtx_name[32];
585 struct mtx sc_rx_mtx; /* RX access mutex */
586 char sc_rx_mtx_name[32];
587 struct mtx sc_tx_mtx; /* TX handling/comp mutex */
588 char sc_tx_mtx_name[32];
589 struct mtx sc_tx_ic_mtx; /* TX queue mutex */
590 char sc_tx_ic_mtx_name[32];
3133c5e3 591#endif
86877dfb 592 struct taskqueue *sc_tq; /* private task queue */
193b341d
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593 struct ath_hal *sc_ah; /* Atheros HAL */
594 struct ath_ratectrl *sc_rc; /* tx rate control support */
595 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
596 void (*sc_setdefantenna)(struct ath_softc *, u_int);
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597
598 /*
599 * First set of flags.
600 */
601 uint32_t sc_invalid : 1,/* disable hardware accesses */
86877dfb 602 sc_mrretry : 1,/* multi-rate retry support */
572ff6f6 603 sc_mrrprot : 1,/* MRR + protection support */
86877dfb 604 sc_softled : 1,/* enable LED gpio status */
572ff6f6 605 sc_hardled : 1,/* enable MAC LED status */
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606 sc_splitmic : 1,/* split TKIP MIC keys */
607 sc_needmib : 1,/* enable MIB stats intr */
608 sc_diversity: 1,/* enable rx diversity */
609 sc_hasveol : 1,/* tx VEOL support */
610 sc_ledstate : 1,/* LED on/off state */
611 sc_blinking : 1,/* LED blink operation active */
612 sc_mcastkey : 1,/* mcast key cache search */
613 sc_scanning : 1,/* scanning active */
193b341d 614 sc_syncbeacon:1,/* sync/resync beacon timers */
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615 sc_hasclrkey: 1,/* CLR key supported */
616 sc_xchanmode: 1,/* extended channel mode */
617 sc_outdoor : 1,/* outdoor operation */
618 sc_dturbo : 1,/* dynamic turbo in use */
619 sc_hasbmask : 1,/* bssid mask support */
620 sc_hasbmatch: 1,/* bssid match disable support*/
621 sc_hastsfadd: 1,/* tsf adjust support */
622 sc_beacons : 1,/* beacons running */
623 sc_swbmiss : 1,/* sta mode using sw bmiss */
624 sc_stagbeacons:1,/* use staggered beacons */
625 sc_wmetkipmic:1,/* can do WME+TKIP MIC */
626 sc_resume_up: 1,/* on resume, start all vaps */
627 sc_tdma : 1,/* TDMA in use */
628 sc_setcca : 1,/* set/clr CCA with TDMA */
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629 sc_resetcal : 1,/* reset cal state next trip */
630 sc_rxslink : 1,/* do self-linked final descriptor */
631 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */
632 sc_isedma : 1;/* supports EDMA */
633
634 /*
635 * Second set of flags.
636 */
637 u_int32_t sc_use_ent : 1,
638 sc_rx_stbc : 1,
639 sc_tx_stbc : 1,
640 sc_hasenforcetxop : 1, /* support enforce TxOP */
641 sc_hasdivcomb : 1, /* RX diversity combining */
642 sc_rx_lnamixer : 1; /* RX using LNA mixing */
643
644 int sc_cabq_enable; /* Enable cabq transmission */
645
646 /*
647 * Enterprise mode configuration for AR9380 and later chipsets.
648 */
649 uint32_t sc_ent_cfg;
650
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651 uint32_t sc_eerd; /* regdomain from EEPROM */
652 uint32_t sc_eecc; /* country code from EEPROM */
193b341d
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653 /* rate tables */
654 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
655 const HAL_RATE_TABLE *sc_currates; /* current rate table */
656 enum ieee80211_phymode sc_curmode; /* current phy mode */
657 HAL_OPMODE sc_opmode; /* current operating mode */
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658 u_int16_t sc_curtxpow; /* current tx power limit */
659 u_int16_t sc_curaid; /* current association id */
660 struct ieee80211_channel *sc_curchan; /* current installed channel */
661 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
662 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
193b341d 663 struct {
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664 u_int8_t ieeerate; /* IEEE rate */
665 u_int8_t rxflags; /* radiotap rx flags */
666 u_int8_t txflags; /* radiotap tx flags */
667 u_int16_t ledon; /* softled on time */
668 u_int16_t ledoff; /* softled off time */
193b341d 669 } sc_hwmap[32]; /* h/w rate ix mappings */
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670 u_int8_t sc_protrix; /* protection rate index */
671 u_int8_t sc_lastdatarix; /* last data frame rate index */
193b341d 672 u_int sc_mcastrate; /* ieee rate for mcastrateix */
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673 u_int sc_fftxqmin; /* min frames before staging */
674 u_int sc_fftxqmax; /* max frames before drop */
193b341d 675 u_int sc_txantenna; /* tx antenna (fixed or auto) */
572ff6f6 676
193b341d 677 HAL_INT sc_imask; /* interrupt mask copy */
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678
679 /*
680 * These are modified in the interrupt handler as well as
681 * the task queues and other contexts. Thus these must be
682 * protected by a mutex, or they could clash.
683 *
684 * For now, access to these is behind the ATH_LOCK,
685 * just to save time.
686 */
687 uint32_t sc_txq_active; /* bitmap of active TXQs */
688 uint32_t sc_kickpcu; /* whether to kick the PCU */
689 uint32_t sc_rxproc_cnt; /* In RX processing */
690 uint32_t sc_txproc_cnt; /* In TX processing */
691 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */
692 uint32_t sc_inreset_cnt; /* In active reset/chanchange */
693 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */
694 uint32_t sc_intr_cnt; /* refcount on interrupt handling */
695
193b341d 696 u_int sc_keymax; /* size of key cache */
86877dfb 697 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
193b341d 698
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699 /*
700 * Software based LED blinking
701 */
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702 u_int sc_ledpin; /* GPIO pin for driving LED */
703 u_int sc_ledon; /* pin setting for LED on */
704 u_int sc_ledidle; /* idle polling interval */
705 int sc_ledevent; /* time of last LED event */
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706 u_int8_t sc_txrix; /* current tx rate for LED */
707 u_int16_t sc_ledoff; /* off time for current blink */
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708 struct callout sc_ledtimer; /* led off timer */
709
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710 /*
711 * Hardware based LED blinking
712 */
713 int sc_led_pwr_pin; /* MAC power LED GPIO pin */
714 int sc_led_net_pin; /* MAC network LED GPIO pin */
715
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716 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
717 u_int sc_rfsilentpol; /* pin setting for rfkill on */
718
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719 struct ath_descdma sc_rxdma; /* RX descriptors */
720 ath_bufhead sc_rxbuf; /* receive buffer */
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721 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
722 struct task sc_rxtask; /* rx int processing */
723 u_int8_t sc_defant; /* current default antenna */
724 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
725 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
726 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */
727 struct ath_rx_radiotap_header sc_rx_th;
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728 int sc_rx_th_len;
729 u_int sc_monpass; /* frames to pass in mon.mode */
730
193b341d 731 struct ath_descdma sc_txdma; /* TX descriptors */
572ff6f6 732 uint16_t sc_txbuf_descid;
193b341d 733 ath_bufhead sc_txbuf; /* transmit buffer */
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734 int sc_txbuf_cnt; /* how many buffers avail */
735 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */
736 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */
737 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */
3133c5e3 738#if 0
572ff6f6 739 struct mtx sc_txbuflock; /* txbuf lock */
193b341d 740 char sc_txname[12]; /* e.g. "ath0_buf" */
3133c5e3 741#endif
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742 u_int sc_txqsetup; /* h/w queues setup */
743 u_int sc_txintrperiod;/* tx interrupt batching */
744 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
745 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
86877dfb 746 struct task sc_txtask; /* tx int processing */
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747 struct task sc_txqtask; /* tx proc processing */
748
749 struct ath_descdma sc_txcompdma; /* TX EDMA completion */
3133c5e3 750#if 0
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751 struct mtx sc_txcomplock; /* TX EDMA completion lock */
752 char sc_txcompname[12]; /* eg ath0_txcomp */
3133c5e3 753#endif
572ff6f6 754
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755 int sc_wd_timer; /* count down for wd timer */
756 struct callout sc_wd_ch; /* tx watchdog timer */
757 struct ath_tx_radiotap_header sc_tx_th;
758 int sc_tx_th_len;
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759
760 struct ath_descdma sc_bdma; /* beacon descriptors */
761 ath_bufhead sc_bbuf; /* beacon buffers */
762 u_int sc_bhalq; /* HAL q for outgoing beacons */
763 u_int sc_bmisscount; /* missed beacon transmits */
86877dfb 764 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
193b341d 765 struct ath_txq *sc_cabq; /* tx q for cab frames */
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766 struct task sc_bmisstask; /* bmiss int processing */
767 struct task sc_bstucktask; /* stuck beacon processing */
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768 struct task sc_resettask; /* interface reset task */
769 struct task sc_fataltask; /* fatal task */
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770 enum {
771 OK, /* no change needed */
772 UPDATE, /* update pending */
773 COMMIT /* beacon sent, commit change */
774 } sc_updateslot; /* slot time update fsm */
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775 int sc_slotupdate; /* slot to advance fsm */
776 struct ieee80211vap *sc_bslot[ATH_BCBUF];
777 int sc_nbcnvaps; /* # vaps with beacons */
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778
779 struct callout sc_cal_ch; /* callout handle for cals */
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780 int sc_lastlongcal; /* last long cal completed */
781 int sc_lastcalreset;/* last cal reset done */
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782 int sc_lastani; /* last ANI poll */
783 int sc_lastshortcal; /* last short calibration */
784 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */
193b341d 785 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
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786 u_int sc_tdmadbaprep; /* TDMA DBA prep time */
787 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */
788 u_int sc_tdmaswba; /* TDMA SWBA counter */
789 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */
790 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */
791 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */
792 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
793 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
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794 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
795 uint32_t sc_txchainmask; /* hardware TX chainmask */
796 uint32_t sc_rxchainmask; /* hardware RX chainmask */
797 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */
798 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */
799 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */
800 int sc_aggr_limit; /* TX limit on all aggregates */
801 int sc_delim_min_pad; /* Minimum delimiter count */
802
803 /* Queue limits */
804
805 /*
806 * To avoid queue starvation in congested conditions,
807 * these parameters tune the maximum number of frames
808 * queued to the data/mcastq before they're dropped.
809 *
810 * This is to prevent:
811 * + a single destination overwhelming everything, including
812 * management/multicast frames;
813 * + multicast frames overwhelming everything (when the
814 * air is sufficiently busy that cabq can't drain.)
815 * + A node in powersave shouldn't be allowed to exhaust
816 * all available mbufs;
817 *
818 * These implement:
819 * + data_minfree is the maximum number of free buffers
820 * overall to successfully allow a data frame.
821 *
822 * + mcastq_maxdepth is the maximum depth allowed of the cabq.
823 */
824 int sc_txq_node_maxdepth;
825 int sc_txq_data_minfree;
826 int sc_txq_mcastq_maxdepth;
827 int sc_txq_node_psq_maxdepth;
828
829 /*
830 * Software queue twiddles
831 *
832 * hwq_limit_nonaggr:
833 * when to begin limiting non-aggregate frames to the
834 * hardware queue, regardless of the TID.
835 * hwq_limit_aggr:
836 * when to begin limiting A-MPDU frames to the
837 * hardware queue, regardless of the TID.
838 * tid_hwq_lo: how low the per-TID hwq count has to be before the
839 * TID will be scheduled again
840 * tid_hwq_hi: how many frames to queue to the HWQ before the TID
841 * stops being scheduled.
842 */
843 int sc_hwq_limit_nonaggr;
844 int sc_hwq_limit_aggr;
845 int sc_tid_hwq_lo;
846 int sc_tid_hwq_hi;
847
848 /* DFS related state */
849 void *sc_dfs; /* Used by an optional DFS module */
850 int sc_dodfs; /* Whether to enable DFS rx filter bits */
851 struct task sc_dfstask; /* DFS processing task */
852
853 /* Spectral related state */
854 void *sc_spectral;
855 int sc_dospectral;
856
857 /* LNA diversity related state */
858 void *sc_lna_div;
859 int sc_dolnadiv;
860
861 /* ALQ */
862#ifdef ATH_DEBUG_ALQ
863 struct if_ath_alq sc_alq;
864#endif
865
866 /* TX AMPDU handling */
867 int (*sc_addba_request)(struct ieee80211_node *,
868 struct ieee80211_tx_ampdu *, int, int, int);
869 int (*sc_addba_response)(struct ieee80211_node *,
870 struct ieee80211_tx_ampdu *, int, int, int);
871 void (*sc_addba_stop)(struct ieee80211_node *,
872 struct ieee80211_tx_ampdu *);
873 void (*sc_addba_response_timeout)
874 (struct ieee80211_node *,
875 struct ieee80211_tx_ampdu *);
876 void (*sc_bar_response)(struct ieee80211_node *ni,
877 struct ieee80211_tx_ampdu *tap,
878 int status);
193b341d 879};
193b341d 880
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881#define ATH_LOCK_INIT(_sc)
882#define ATH_LOCK_DESTROY(_sc)
883#define ATH_LOCK(_sc)
884#define ATH_UNLOCK(_sc)
885#define ATH_LOCK_ASSERT(_sc)
886#define ATH_UNLOCK_ASSERT(_sc)
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887
888/*
889 * The TX lock is non-reentrant and serialises the TX frame send
890 * and completion operations.
891 */
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892#define ATH_TX_LOCK_INIT(_sc)
893#define ATH_TX_LOCK_DESTROY(_sc)
894#define ATH_TX_LOCK(_sc)
895#define ATH_TX_UNLOCK(_sc)
896#define ATH_TX_LOCK_ASSERT(_sc)
897#define ATH_TX_UNLOCK_ASSERT(_sc)
898/* #define ATH_TX_TRYLOCK(_sc) removed */
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899
900/*
901 * The IC TX lock is non-reentrant and serialises packet queuing from
902 * the upper layers.
903 */
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904#define ATH_TX_IC_LOCK_INIT(_sc)
905#define ATH_TX_IC_LOCK_DESTROY(_sc)
906#define ATH_TX_IC_LOCK(_sc)
907#define ATH_TX_IC_UNLOCK(_sc)
908#define ATH_TX_IC_LOCK_ASSERT(_sc)
909#define ATH_TX_IC_UNLOCK_ASSERT(_sc)
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910
911/*
912 * The PCU lock is non-recursive and should be treated as a spinlock.
913 * Although currently the interrupt code is run in netisr context and
914 * doesn't require this, this may change in the future.
915 * Please keep this in mind when protecting certain code paths
916 * with the PCU lock.
917 *
918 * The PCU lock is used to serialise access to the PCU so things such
919 * as TX, RX, state change (eg channel change), channel reset and updates
920 * from interrupt context (eg kickpcu, txqactive bits) do not clash.
921 *
922 * Although the current single-thread taskqueue mechanism protects the
923 * majority of these situations by simply serialising them, there are
924 * a few others which occur at the same time. These include the TX path
925 * (which only acquires ATH_LOCK when recycling buffers to the free list),
926 * ath_set_channel, the channel scanning API and perhaps quite a bit more.
927 */
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928#define ATH_PCU_LOCK_INIT(_sc)
929#define ATH_PCU_LOCK_DESTROY(_sc)
930#define ATH_PCU_LOCK(_sc)
931#define ATH_PCU_UNLOCK(_sc)
932#define ATH_PCU_LOCK_ASSERT(_sc)
933#define ATH_PCU_UNLOCK_ASSERT(_sc)
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MD
934
935/*
936 * The RX lock is primarily a(nother) workaround to ensure that the
937 * RX FIFO/list isn't modified by various execution paths.
938 * Even though RX occurs in a single context (the ath taskqueue), the
939 * RX path can be executed via various reset/channel change paths.
940 */
3133c5e3
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941#define ATH_RX_LOCK_INIT(_sc)
942#define ATH_RX_LOCK_DESTROY(_sc)
943#define ATH_RX_LOCK(_sc)
944#define ATH_RX_UNLOCK(_sc)
945#define ATH_RX_LOCK_ASSERT(_sc)
946#define ATH_RX_UNLOCK_ASSERT(_sc)
572ff6f6 947
86877dfb 948#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
193b341d 949
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950#define ATH_TXBUF_LOCK_INIT(_sc)
951#define ATH_TXBUF_LOCK_DESTROY(_sc)
952#define ATH_TXBUF_LOCK(_sc)
953#define ATH_TXBUF_UNLOCK(_sc)
954#define ATH_TXBUF_LOCK_ASSERT(_sc)
955#define ATH_TXBUF_UNLOCK_ASSERT(_sc)
956
957#define ATH_TXSTATUS_LOCK_INIT(_sc)
958#define ATH_TXSTATUS_LOCK_DESTROY(_sc)
959#define ATH_TXSTATUS_LOCK(_sc)
960#define ATH_TXSTATUS_UNLOCK(_sc)
961#define ATH_TXSTATUS_LOCK_ASSERT(_sc)
572ff6f6 962
86877dfb 963int ath_attach(u_int16_t, struct ath_softc *);
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964int ath_detach(struct ath_softc *);
965void ath_resume(struct ath_softc *);
966void ath_suspend(struct ath_softc *);
967void ath_shutdown(struct ath_softc *);
968void ath_intr(void *);
969
970/*
971 * HAL definitions to comply with local coding convention.
972 */
973#define ath_hal_detach(_ah) \
974 ((*(_ah)->ah_detach)((_ah)))
975#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
976 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
86877dfb
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977#define ath_hal_macversion(_ah) \
978 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
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979#define ath_hal_getratetable(_ah, _mode) \
980 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
981#define ath_hal_getmac(_ah, _mac) \
982 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
983#define ath_hal_setmac(_ah, _mac) \
984 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
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985#define ath_hal_getbssidmask(_ah, _mask) \
986 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
987#define ath_hal_setbssidmask(_ah, _mask) \
988 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
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989#define ath_hal_intrset(_ah, _mask) \
990 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
991#define ath_hal_intrget(_ah) \
992 ((*(_ah)->ah_getInterrupts)((_ah)))
993#define ath_hal_intrpend(_ah) \
994 ((*(_ah)->ah_isInterruptPending)((_ah)))
995#define ath_hal_getisr(_ah, _pmask) \
996 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
997#define ath_hal_updatetxtriglevel(_ah, _inc) \
998 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
999#define ath_hal_setpower(_ah, _mode) \
1000 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1001#define ath_hal_keycachesize(_ah) \
1002 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
1003#define ath_hal_keyreset(_ah, _ix) \
1004 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1005#define ath_hal_keyset(_ah, _ix, _pk, _mac) \
1006 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1007#define ath_hal_keyisvalid(_ah, _ix) \
1008 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1009#define ath_hal_keysetmac(_ah, _ix, _mac) \
1010 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1011#define ath_hal_getrxfilter(_ah) \
1012 ((*(_ah)->ah_getRxFilter)((_ah)))
1013#define ath_hal_setrxfilter(_ah, _filter) \
1014 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1015#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
1016 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1017#define ath_hal_waitforbeacon(_ah, _bf) \
1018 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
572ff6f6
MD
1019#define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \
1020 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
86877dfb
RP
1021/* NB: common across all chips */
1022#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
193b341d 1023#define ath_hal_gettsf32(_ah) \
86877dfb 1024 OS_REG_READ(_ah, AR_TSF_L32)
193b341d
SZ
1025#define ath_hal_gettsf64(_ah) \
1026 ((*(_ah)->ah_getTsf64)((_ah)))
572ff6f6
MD
1027#define ath_hal_settsf64(_ah, _val) \
1028 ((*(_ah)->ah_setTsf64)((_ah), (_val)))
193b341d
SZ
1029#define ath_hal_resettsf(_ah) \
1030 ((*(_ah)->ah_resetTsf)((_ah)))
1031#define ath_hal_rxena(_ah) \
1032 ((*(_ah)->ah_enableReceive)((_ah)))
1033#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
1034 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1035#define ath_hal_gettxbuf(_ah, _q) \
1036 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
1037#define ath_hal_numtxpending(_ah, _q) \
1038 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
572ff6f6
MD
1039#define ath_hal_getrxbuf(_ah, _rxq) \
1040 ((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
193b341d
SZ
1041#define ath_hal_txstart(_ah, _q) \
1042 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
1043#define ath_hal_setchannel(_ah, _chan) \
1044 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
1045#define ath_hal_calibrate(_ah, _chan, _iqcal) \
1046 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
86877dfb
RP
1047#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
1048 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1049#define ath_hal_calreset(_ah, _chan) \
1050 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
193b341d
SZ
1051#define ath_hal_setledstate(_ah, _state) \
1052 ((*(_ah)->ah_setLedState)((_ah), (_state)))
1053#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
1054 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1055#define ath_hal_beaconreset(_ah) \
1056 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
86877dfb
RP
1057#define ath_hal_beaconsettimers(_ah, _bt) \
1058 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
193b341d
SZ
1059#define ath_hal_beacontimers(_ah, _bs) \
1060 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
572ff6f6
MD
1061#define ath_hal_getnexttbtt(_ah) \
1062 ((*(_ah)->ah_getNextTBTT)((_ah)))
193b341d
SZ
1063#define ath_hal_setassocid(_ah, _bss, _associd) \
1064 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1065#define ath_hal_phydisable(_ah) \
1066 ((*(_ah)->ah_phyDisable)((_ah)))
1067#define ath_hal_setopmode(_ah) \
1068 ((*(_ah)->ah_setPCUConfig)((_ah)))
1069#define ath_hal_stoptxdma(_ah, _qnum) \
1070 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1071#define ath_hal_stoppcurecv(_ah) \
1072 ((*(_ah)->ah_stopPcuReceive)((_ah)))
1073#define ath_hal_startpcurecv(_ah) \
1074 ((*(_ah)->ah_startPcuReceive)((_ah)))
1075#define ath_hal_stopdmarecv(_ah) \
1076 ((*(_ah)->ah_stopDmaReceive)((_ah)))
1077#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
1078 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
1079 (_indata), (_insize), (_outdata), (_outsize)))
86877dfb
RP
1080#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
1081 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
193b341d
SZ
1082#define ath_hal_setuptxqueue(_ah, _type, _irq) \
1083 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1084#define ath_hal_resettxqueue(_ah, _q) \
1085 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1086#define ath_hal_releasetxqueue(_ah, _q) \
1087 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1088#define ath_hal_gettxqueueprops(_ah, _q, _qi) \
1089 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1090#define ath_hal_settxqueueprops(_ah, _q, _qi) \
1091 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
86877dfb
RP
1092/* NB: common across all chips */
1093#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
1094#define ath_hal_txqenabled(_ah, _qnum) \
1095 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
193b341d
SZ
1096#define ath_hal_getrfgain(_ah) \
1097 ((*(_ah)->ah_getRfGain)((_ah)))
1098#define ath_hal_getdefantenna(_ah) \
1099 ((*(_ah)->ah_getDefAntenna)((_ah)))
1100#define ath_hal_setdefantenna(_ah, _ant) \
1101 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1102#define ath_hal_rxmonitor(_ah, _arg, _chan) \
1103 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
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MD
1104#define ath_hal_ani_poll(_ah, _chan) \
1105 ((*(_ah)->ah_aniPoll)((_ah), (_chan)))
193b341d
SZ
1106#define ath_hal_mibevent(_ah, _stats) \
1107 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1108#define ath_hal_setslottime(_ah, _us) \
1109 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1110#define ath_hal_getslottime(_ah) \
1111 ((*(_ah)->ah_getSlotTime)((_ah)))
1112#define ath_hal_setacktimeout(_ah, _us) \
1113 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1114#define ath_hal_getacktimeout(_ah) \
1115 ((*(_ah)->ah_getAckTimeout)((_ah)))
1116#define ath_hal_setctstimeout(_ah, _us) \
1117 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1118#define ath_hal_getctstimeout(_ah) \
1119 ((*(_ah)->ah_getCTSTimeout)((_ah)))
1120#define ath_hal_getcapability(_ah, _cap, _param, _result) \
1121 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1122#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
1123 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1124#define ath_hal_ciphersupported(_ah, _cipher) \
1125 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
1126#define ath_hal_getregdomain(_ah, _prd) \
1127 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
1128#define ath_hal_setregdomain(_ah, _rd) \
86877dfb 1129 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
193b341d
SZ
1130#define ath_hal_getcountrycode(_ah, _pcc) \
1131 (*(_pcc) = (_ah)->ah_countryCode)
86877dfb
RP
1132#define ath_hal_gettkipmic(_ah) \
1133 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
1134#define ath_hal_settkipmic(_ah, _v) \
1135 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
8982d733 1136#define ath_hal_hastkipsplit(_ah) \
193b341d 1137 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
8982d733
SZ
1138#define ath_hal_gettkipsplit(_ah) \
1139 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
1140#define ath_hal_settkipsplit(_ah, _v) \
1141 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
86877dfb
RP
1142#define ath_hal_haswmetkipmic(_ah) \
1143 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
193b341d
SZ
1144#define ath_hal_hwphycounters(_ah) \
1145 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
1146#define ath_hal_hasdiversity(_ah) \
1147 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
1148#define ath_hal_getdiversity(_ah) \
1149 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
1150#define ath_hal_setdiversity(_ah, _v) \
1151 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
86877dfb
RP
1152#define ath_hal_getantennaswitch(_ah) \
1153 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
1154#define ath_hal_setantennaswitch(_ah, _v) \
1155 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
193b341d
SZ
1156#define ath_hal_getdiag(_ah, _pv) \
1157 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
1158#define ath_hal_setdiag(_ah, _v) \
1159 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
1160#define ath_hal_getnumtxqueues(_ah, _pv) \
1161 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
1162#define ath_hal_hasveol(_ah) \
1163 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
1164#define ath_hal_hastxpowlimit(_ah) \
1165 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
1166#define ath_hal_settxpowlimit(_ah, _pow) \
1167 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1168#define ath_hal_gettxpowlimit(_ah, _ppow) \
1169 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
1170#define ath_hal_getmaxtxpow(_ah, _ppow) \
1171 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
1172#define ath_hal_gettpscale(_ah, _scale) \
1173 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
1174#define ath_hal_settpscale(_ah, _v) \
1175 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
1176#define ath_hal_hastpc(_ah) \
1177 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
1178#define ath_hal_gettpc(_ah) \
1179 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
1180#define ath_hal_settpc(_ah, _v) \
1181 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
1182#define ath_hal_hasbursting(_ah) \
1183 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
86877dfb
RP
1184#define ath_hal_setmcastkeysearch(_ah, _v) \
1185 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
193b341d
SZ
1186#define ath_hal_hasmcastkeysearch(_ah) \
1187 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
1188#define ath_hal_getmcastkeysearch(_ah) \
1189 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
86877dfb
RP
1190#define ath_hal_hasfastframes(_ah) \
1191 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
1192#define ath_hal_hasbssidmask(_ah) \
1193 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
1194#define ath_hal_hasbssidmatch(_ah) \
1195 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
1196#define ath_hal_hastsfadjust(_ah) \
1197 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
1198#define ath_hal_gettsfadjust(_ah) \
1199 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
1200#define ath_hal_settsfadjust(_ah, _onoff) \
1201 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
193b341d
SZ
1202#define ath_hal_hasrfsilent(_ah) \
1203 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
1204#define ath_hal_getrfkill(_ah) \
1205 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
1206#define ath_hal_setrfkill(_ah, _onoff) \
1207 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
1208#define ath_hal_getrfsilent(_ah, _prfsilent) \
1209 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
1210#define ath_hal_setrfsilent(_ah, _rfsilent) \
1211 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
1212#define ath_hal_gettpack(_ah, _ptpack) \
1213 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
1214#define ath_hal_settpack(_ah, _tpack) \
1215 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
1216#define ath_hal_gettpcts(_ah, _ptpcts) \
1217 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
1218#define ath_hal_settpcts(_ah, _tpcts) \
1219 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
86877dfb 1220#define ath_hal_hasintmit(_ah) \
572ff6f6
MD
1221 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1222 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
86877dfb 1223#define ath_hal_getintmit(_ah) \
572ff6f6
MD
1224 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1225 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
86877dfb 1226#define ath_hal_setintmit(_ah, _v) \
572ff6f6
MD
1227 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
1228 HAL_CAP_INTMIT_ENABLE, _v, NULL)
1229
1230#define ath_hal_hasenforcetxop(_ah) \
1231 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK)
1232#define ath_hal_getenforcetxop(_ah) \
1233 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK)
1234#define ath_hal_setenforcetxop(_ah, _v) \
1235 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL)
1236
1237#define ath_hal_hasrxlnamixer(_ah) \
1238 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK)
1239
1240#define ath_hal_hasdivantcomb(_ah) \
1241 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK)
1242
1243/* EDMA definitions */
1244#define ath_hal_hasedma(_ah) \
1245 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \
1246 0, NULL) == HAL_OK)
1247#define ath_hal_getrxfifodepth(_ah, _qtype, _req) \
1248 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \
1249 == HAL_OK)
1250#define ath_hal_getntxmaps(_ah, _req) \
1251 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \
1252 == HAL_OK)
1253#define ath_hal_gettxdesclen(_ah, _req) \
1254 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \
1255 == HAL_OK)
1256#define ath_hal_gettxstatuslen(_ah, _req) \
1257 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \
1258 == HAL_OK)
1259#define ath_hal_getrxstatuslen(_ah, _req) \
1260 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \
1261 == HAL_OK)
1262#define ath_hal_setrxbufsize(_ah, _req) \
1263 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \
1264 == HAL_OK)
1265
193b341d
SZ
1266#define ath_hal_getchannoise(_ah, _c) \
1267 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
193b341d 1268
572ff6f6
MD
1269/* 802.11n HAL methods */
1270#define ath_hal_getrxchainmask(_ah, _prxchainmask) \
1271 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
1272#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \
1273 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
1274#define ath_hal_setrxchainmask(_ah, _rx) \
1275 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
1276#define ath_hal_settxchainmask(_ah, _tx) \
1277 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
1278#define ath_hal_split4ktrans(_ah) \
1279 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
1280 0, NULL) == HAL_OK)
1281#define ath_hal_self_linked_final_rxdesc(_ah) \
1282 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
1283 0, NULL) == HAL_OK)
1284#define ath_hal_gtxto_supported(_ah) \
1285 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
1286#define ath_hal_has_long_rxdesc_tsf(_ah) \
1287 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \
1288 0, NULL) == HAL_OK)
193b341d
SZ
1289#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
1290 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
8982d733
SZ
1291#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
1292 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
193b341d
SZ
1293#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
1294 _txr0, _txtr0, _keyix, _ant, _flags, \
1295 _rtsrate, _rtsdura) \
1296 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1297 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
1298 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
1299#define ath_hal_setupxtxdesc(_ah, _ds, \
1300 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
1301 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1302 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
572ff6f6
MD
1303#define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \
1304 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1305 (_first), (_last), (_ds0)))
8982d733
SZ
1306#define ath_hal_txprocdesc(_ah, _ds, _ts) \
1307 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
193b341d
SZ
1308#define ath_hal_gettxintrtxqs(_ah, _txqs) \
1309 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
572ff6f6
MD
1310#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
1311 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1312#define ath_hal_settxdesclink(_ah, _ds, _link) \
1313 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1314#define ath_hal_gettxdesclink(_ah, _ds, _link) \
1315 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1316#define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \
1317 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1318#define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \
1319 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1320 (_size)))
1321#define ath_hal_gettxrawtxdesc(_ah, _txstatus) \
1322 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1323
1324#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
1325 _txr0, _txtr0, _antm, _rcr, _rcd) \
1326 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1327 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
1328#define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \
1329 _keyix, _cipher, _delims, _first, _last, _lastaggr) \
1330 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1331 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \
1332 (_first), (_last), (_lastaggr)))
1333#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
1334 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1335
1336#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
1337 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1338 (_series), (_ns), (_flags)))
1339
1340#define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
1341 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1342#define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \
1343 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1344#define ath_hal_set11n_aggr_last(_ah, _ds) \
1345 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1346
1347#define ath_hal_set11nburstduration(_ah, _ds, _dur) \
1348 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1349#define ath_hal_clr11n_aggr(_ah, _ds) \
1350 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1351#define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \
1352 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
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1354#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
1355 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1356#define ath_hal_gpioset(_ah, _gpio, _b) \
1357 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1358#define ath_hal_gpioget(_ah, _gpio) \
1359 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1360#define ath_hal_gpiosetintr(_ah, _gpio, _b) \
1361 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
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1363/*
1364 * PCIe suspend/resume/poweron/poweroff related macros
1365 */
1366#define ath_hal_enablepcie(_ah, _restore, _poweroff) \
1367 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1368#define ath_hal_disablepcie(_ah) \
1369 ((*(_ah)->ah_disablePCIE)((_ah)))
1370
1371/*
1372 * This is badly-named; you need to set the correct parameters
1373 * to begin to receive useful radar events; and even then
1374 * it doesn't "enable" DFS. See the ath_dfs/null/ module for
1375 * more information.
1376 */
1377#define ath_hal_enabledfs(_ah, _param) \
1378 ((*(_ah)->ah_enableDfs)((_ah), (_param)))
1379#define ath_hal_getdfsthresh(_ah, _param) \
1380 ((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1381#define ath_hal_getdfsdefaultthresh(_ah, _param) \
1382 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1383#define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1384 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1385 (_buf), (_event)))
1386#define ath_hal_is_fast_clock_enabled(_ah) \
1387 ((*(_ah)->ah_isFastClockEnabled)((_ah)))
1388#define ath_hal_radar_wait(_ah, _chan) \
193b341d 1389 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
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1390#define ath_hal_get_mib_cycle_counts(_ah, _sample) \
1391 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1392#define ath_hal_get_chan_ext_busy(_ah) \
1393 ((*(_ah)->ah_get11nExtBusy)((_ah)))
1394#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
1395 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1396
1397#define ath_hal_spectral_supported(_ah) \
1398 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)
1399#define ath_hal_spectral_get_config(_ah, _p) \
1400 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1401#define ath_hal_spectral_configure(_ah, _p) \
1402 ((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1403#define ath_hal_spectral_start(_ah) \
1404 ((*(_ah)->ah_spectralStart)((_ah)))
1405#define ath_hal_spectral_stop(_ah) \
1406 ((*(_ah)->ah_spectralStop)((_ah)))
1407
1408#define ath_hal_btcoex_supported(_ah) \
1409 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK)
1410#define ath_hal_btcoex_set_info(_ah, _info) \
1411 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1412#define ath_hal_btcoex_set_config(_ah, _cfg) \
1413 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1414#define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \
1415 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1416#define ath_hal_btcoex_set_weights(_ah, _weight) \
1417 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1418#define ath_hal_btcoex_set_weights(_ah, _weight) \
1419 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1420#define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \
1421 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1422#define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \
1423 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1424#define ath_hal_btcoex_enable(_ah) \
1425 ((*(_ah)->ah_btCoexEnable)((_ah)))
1426#define ath_hal_btcoex_disable(_ah) \
1427 ((*(_ah)->ah_btCoexDisable)((_ah)))
1428
1429#define ath_hal_div_comb_conf_get(_ah, _conf) \
1430 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1431#define ath_hal_div_comb_conf_set(_ah, _conf) \
1432 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))
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1433
1434#endif /* _DEV_ATH_ATHVAR_H */