ath - Basic re-port, base code compile
[dragonfly.git] / sys / dev / netif / ath / ath_hal / ah_osdep.h
CommitLineData
8982d733 1/*-
818ddf01 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
572ff6f6 29 * $FreeBSD$
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30 */
31#ifndef _ATH_AH_OSDEP_H_
32#define _ATH_AH_OSDEP_H_
33/*
34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
35 */
572ff6f6 36#include <sys/cdefs.h>
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37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/endian.h>
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40#include <sys/bus.h>
41#include <sys/spinlock.h>
3f720b20 42#include <sys/linker_set.h>
8982d733 43
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44#include <sys/spinlock2.h>
45
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46/*
47 * Bus i/o type definitions.
48 */
49typedef void *HAL_SOFTC;
50typedef bus_space_tag_t HAL_BUS_TAG;
51typedef bus_space_handle_t HAL_BUS_HANDLE;
52
8982d733 53/*
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54 * Although the underlying hardware may support 64 bit DMA, the
55 * current Atheros hardware only supports 32 bit addressing.
56 */
57typedef uint32_t HAL_DMA_ADDR;
58
59/*
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60 * Linker set writearounds for chip and RF backend registration.
61 */
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62#define OS_DATA_SET(set, item) DATA_SET(set, item)
63#define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype)
64#define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set)
65
3f720b20 66/*
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67 * Delay n microseconds.
68 */
818ddf01 69#define OS_DELAY(_n) DELAY(_n)
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70
71#define OS_INLINE __inline
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72#define OS_MEMZERO(_a, _n) bzero((_a), (_n))
73#define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
572ff6f6 74#define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
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75
76#define abs(_a) __builtin_abs(_a)
77
78struct ath_hal;
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79
80/*
81 * The hardware registers are native little-endian byte order.
82 * Big-endian hosts are handled by enabling hardware byte-swap
83 * of register reads and writes at reset. But the PCI clock
84 * domain registers are not byte swapped! Thus, on big-endian
85 * platforms we have to explicitly byte-swap those registers.
86 * OS_REG_UNSWAPPED identifies the registers that need special handling.
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87 *
88 * This is not currently used by the FreeBSD HAL osdep code; the HAL
89 * currently does not configure hardware byteswapping for register space
90 * accesses and instead does it through the FreeBSD bus space code.
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91 */
92#if _BYTE_ORDER == _BIG_ENDIAN
93#define OS_REG_UNSWAPPED(_reg) \
94 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
95 ((_reg) >= 0x7000 && (_reg) < 0x8000))
96#else /* _BYTE_ORDER == _LITTLE_ENDIAN */
97#define OS_REG_UNSWAPPED(_reg) (0)
98#endif /* _BYTE_ORDER */
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99
100/*
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101 * For USB/SDIO support (where access latencies are quite high);
102 * some write accesses may be buffered and then flushed when
103 * either a read is done, or an explicit flush is done.
104 *
105 * These are simply placeholders for now.
106 */
107#define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
108 do { } while (0)
109#define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
110 do { } while (0)
111#define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
112 do { } while (0)
113
114/*
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115 * Register read/write operations are either handled through
116 * platform-dependent routines (or when debugging is enabled
117 * with AH_DEBUG); or they are inline expanded using the macros
818ddf01 118 * defined below.
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119 */
120#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
121#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
122#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
123
124extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
125extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
126#else
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127#define OS_REG_WRITE(_ah, _reg, _val) \
128 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
129 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
130#define OS_REG_READ(_ah, _reg) \
131 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
132 (bus_space_handle_t)(_ah)->ah_sh, (_reg))
572ff6f6 133#endif
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134
135#ifdef AH_DEBUG_ALQ
136extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
137#else
138#define OS_MARK(_ah, _id, _v)
139#endif
140
141#endif /* _ATH_AH_OSDEP_H_ */