[dragonfly.git] / sys / bus / pci / pcivar.h

/*-
 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice unmodified, this list of conditions, and the following
 *    disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
 *
 */

#ifndef _PCIVAR_H_
#define	_PCIVAR_H_

#ifndef _SYS_QUEUE_H_
#include <sys/queue.h>
#endif

/* some PCI bus constants */

#define	PCI_DOMAINMAX	65535	/* highest supported domain number */
#define	PCI_BUSMAX	255	/* highest supported bus number */
#define	PCI_SLOTMAX	31	/* highest supported slot number */
#define	PCI_FUNCMAX	7	/* highest supported function number */
#define	PCI_REGMAX	255	/* highest supported config register addr. */

#define	PCI_MAXMAPS_0	6	/* max. no. of memory/port maps */
#define	PCI_MAXMAPS_1	2	/* max. no. of maps for PCI to PCI bridge */
#define	PCI_MAXMAPS_2	1	/* max. no. of maps for CardBus bridge */

typedef uint64_t pci_addr_t;

/* Interesting values for PCI power management */
struct pcicfg_pp {
    uint16_t	pp_cap;		/* PCI power management capabilities */
    uint8_t	pp_status;	/* config space address of PCI power status reg */
    uint8_t	pp_pmcsr;	/* config space address of PMCSR reg */
    uint8_t	pp_data;	/* config space address of PCI power data reg */
};
 
struct vpd_readonly {
    char	keyword[2];
    char	*value;
};

struct vpd_write {
    char	keyword[2];
    char	*value;
    int 	start;
    int 	len;
};

struct pcicfg_vpd {
    uint8_t	vpd_reg;	/* base register, + 2 for addr, + 4 data */
    char	vpd_cached;
    char	*vpd_ident;	/* string identifier */
    int 	vpd_rocnt;
    struct vpd_readonly *vpd_ros;
    int 	vpd_wcnt;
    struct vpd_write *vpd_w;
};

/* Interesting values for PCI MSI */
struct pcicfg_msi {
    uint16_t	msi_ctrl;	/* Message Control */
    uint8_t	msi_location;	/* Offset of MSI capability registers. */
    uint8_t	msi_msgnum;	/* Number of messages */
    int		msi_alloc;	/* Number of allocated messages. */
    uint64_t	msi_addr;	/* Contents of address register. */
    uint16_t	msi_data;	/* Contents of data register. */
    u_int	msi_handlers;
};

/* Interesting values for PCI MSI-X */
struct msix_vector {
    uint64_t	mv_address;	/* Contents of address register. */
    uint32_t	mv_data;	/* Contents of data register. */
    int		mv_irq;
};

struct msix_table_entry {
    u_int	mte_vector;	/* 1-based index into msix_vectors array. */
    u_int	mte_handlers;
};

struct pcicfg_msix {
    uint16_t	msix_ctrl;	/* Message Control */
    uint16_t	msix_msgnum;	/* Number of messages */
    uint8_t	msix_location;	/* Offset of MSI-X capability registers. */
    uint8_t	msix_table_bar;	/* BAR containing vector table. */
    uint8_t	msix_pba_bar;	/* BAR containing PBA. */
    uint32_t	msix_table_offset;
    uint32_t	msix_pba_offset;
    int		msix_alloc;	/* Number of allocated vectors. */
    int		msix_table_len;	/* Length of virtual table. */
    struct msix_table_entry *msix_table; /* Virtual table. */
    struct msix_vector *msix_vectors;	/* Array of allocated vectors. */
    struct resource *msix_table_res;	/* Resource containing vector table. */
    struct resource *msix_pba_res;	/* Resource containing PBA. */
};

/* Interesting values for HyperTransport */
struct pcicfg_ht {
    uint8_t	ht_slave;	/* Non-zero if device is an HT slave. */
    uint8_t	ht_msimap;	/* Offset of MSI mapping cap registers. */
    uint16_t	ht_msictrl;	/* MSI mapping control */
    uint64_t	ht_msiaddr;	/* MSI mapping base address */
};

/* Interesting values for PCI Express capability */
struct pcicfg_expr {
    uint8_t	expr_ptr;	/* capability ptr */
    uint16_t	expr_cap;	/* capabilities */
    uint32_t	expr_slotcap;	/* slot capabilities */
};

/* Interesting values for PCI-X */
struct pcicfg_pcix {
    uint8_t	pcix_ptr;
};

/* config header information common to all header types */
typedef struct pcicfg {
    struct device *dev;		/* device which owns this */

    uint32_t	bar[PCI_MAXMAPS_0]; /* BARs */
    uint32_t	bios;		/* BIOS mapping */

    uint16_t	subvendor;	/* card vendor ID */
    uint16_t	subdevice;	/* card device ID, assigned by card vendor */
    uint16_t	vendor;		/* chip vendor ID */
    uint16_t	device;		/* chip device ID, assigned by chip vendor */

    uint16_t	cmdreg;		/* disable/enable chip and PCI options */
    uint16_t	statreg;	/* supported PCI features and error state */

    uint8_t	baseclass;	/* chip PCI class */
    uint8_t	subclass;	/* chip PCI subclass */
    uint8_t	progif;		/* chip PCI programming interface */
    uint8_t	revid;		/* chip revision ID */

    uint8_t	hdrtype;	/* chip config header type */
    uint8_t	cachelnsz;	/* cache line size in 4byte units */
    uint8_t	intpin;		/* PCI interrupt pin */
    uint8_t	intline;	/* interrupt line (IRQ for PC arch) */

    uint8_t	mingnt;		/* min. useful bus grant time in 250ns units */
    uint8_t	maxlat;		/* max. tolerated bus grant latency in 250ns */
    uint8_t	lattimer;	/* latency timer in units of 30ns bus cycles */

    uint8_t	mfdev;		/* multi-function device (from hdrtype reg) */
    uint8_t	nummaps;	/* actual number of PCI maps used */

    uint32_t	domain;		/* PCI domain */
    uint8_t	bus;		/* config space bus address */
    uint8_t	slot;		/* config space slot address */
    uint8_t	func;		/* config space function number */

#ifdef COMPAT_OLDPCI
    uint8_t	secondarybus;	/* bus on secondary side of bridge, if any */
#else
    uint8_t	dummy;
#endif

    struct pcicfg_pp pp;	/* pci power management */
    struct pcicfg_vpd vpd;	/* pci vital product data */
    struct pcicfg_msi msi;	/* pci msi */
    struct pcicfg_msix msix;	/* pci msi-x */
    struct pcicfg_ht ht;	/* HyperTransport */
    struct pcicfg_expr expr;	/* PCI Express */
    struct pcicfg_pcix pcix;	/* PCI-X */
} pcicfgregs;

/* additional type 1 device config header information (PCI to PCI bridge) */

#define	PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
#define	PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
#define	PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
#define	PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)

typedef struct {
    pci_addr_t	pmembase;	/* base address of prefetchable memory */
    pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */
    uint32_t	membase;	/* base address of memory window */
    uint32_t	memlimit;	/* topmost address of memory window */
    uint32_t	iobase;		/* base address of port window */
    uint32_t	iolimit;	/* topmost address of port window */
    uint16_t	secstat;	/* secondary bus status register */
    uint16_t	bridgectl;	/* bridge control register */
    uint8_t	seclat;		/* CardBus latency timer */
} pcih1cfgregs;

/* additional type 2 device config header information (CardBus bridge) */

typedef struct {
    uint32_t	membase0;	/* base address of memory window */
    uint32_t	memlimit0;	/* topmost address of memory window */
    uint32_t	membase1;	/* base address of memory window */
    uint32_t	memlimit1;	/* topmost address of memory window */
    uint32_t	iobase0;	/* base address of port window */
    uint32_t	iolimit0;	/* topmost address of port window */
    uint32_t	iobase1;	/* base address of port window */
    uint32_t	iolimit1;	/* topmost address of port window */
    uint32_t	pccardif;	/* PC Card 16bit IF legacy more base addr. */
    uint16_t	secstat;	/* secondary bus status register */
    uint16_t	bridgectl;	/* bridge control register */
    uint8_t	seclat;		/* CardBus latency timer */
} pcih2cfgregs;

extern uint32_t pci_numdevs;

/* Only if the prerequisites are present */
#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
struct pci_devinfo {
        STAILQ_ENTRY(pci_devinfo) pci_links;
	struct resource_list resources;
	pcicfgregs		cfg;
	struct pci_conf		conf;
};
#endif

#ifdef _SYS_BUS_H_

#include "pci_if.h"

/*
 * Define pci-specific resource flags for accessing memory via dense
 * or bwx memory spaces. These flags are ignored on i386.
 */
#define	PCI_RF_DENSE	0x10000
#define	PCI_RF_BWX	0x20000

enum pci_device_ivars {
    PCI_IVAR_SUBVENDOR,
    PCI_IVAR_SUBDEVICE,
    PCI_IVAR_VENDOR,
    PCI_IVAR_DEVICE,
    PCI_IVAR_DEVID,
    PCI_IVAR_CLASS,
    PCI_IVAR_SUBCLASS,
    PCI_IVAR_PROGIF,
    PCI_IVAR_REVID,
    PCI_IVAR_INTPIN,
    PCI_IVAR_IRQ,
    PCI_IVAR_DOMAIN,
    PCI_IVAR_BUS,
    PCI_IVAR_SLOT,
    PCI_IVAR_FUNCTION,
    PCI_IVAR_ETHADDR,
    PCI_IVAR_CMDREG,
    PCI_IVAR_CACHELNSZ,
    PCI_IVAR_MINGNT,
    PCI_IVAR_MAXLAT,
    PCI_IVAR_LATTIMER,
    PCI_IVAR_PCIXCAP_PTR,
    PCI_IVAR_PCIECAP_PTR,
    PCI_IVAR_VPDCAP_PTR
};

/*
 * Simplified accessors for pci devices
 */
#define	PCI_ACCESSOR(var, ivar, type)					\
	__BUS_ACCESSOR(pci, var, PCI, ivar, type)

PCI_ACCESSOR(subvendor,		SUBVENDOR,	uint16_t)
PCI_ACCESSOR(subdevice,		SUBDEVICE,	uint16_t)
PCI_ACCESSOR(vendor,		VENDOR,		uint16_t)
PCI_ACCESSOR(device,		DEVICE,		uint16_t)
PCI_ACCESSOR(devid,		DEVID,		uint32_t)
PCI_ACCESSOR(class,		CLASS,		uint8_t)
PCI_ACCESSOR(subclass,		SUBCLASS,	uint8_t)
PCI_ACCESSOR(progif,		PROGIF,		uint8_t)
PCI_ACCESSOR(revid,		REVID,		uint8_t)
PCI_ACCESSOR(intpin,		INTPIN,		uint8_t)
PCI_ACCESSOR(irq,		IRQ,		uint8_t)
PCI_ACCESSOR(domain,		DOMAIN,		uint32_t)
PCI_ACCESSOR(bus,		BUS,		uint8_t)
PCI_ACCESSOR(slot,		SLOT,		uint8_t)
PCI_ACCESSOR(function,		FUNCTION,	uint8_t)
PCI_ACCESSOR(ether,		ETHADDR,	uint8_t *)
PCI_ACCESSOR(cmdreg,		CMDREG,		uint8_t)
PCI_ACCESSOR(cachelnsz,		CACHELNSZ,	uint8_t)
PCI_ACCESSOR(mingnt,		MINGNT,		uint8_t)
PCI_ACCESSOR(maxlat,		MAXLAT,		uint8_t)
PCI_ACCESSOR(lattimer,		LATTIMER,	uint8_t)
PCI_ACCESSOR(pcixcap_ptr,	PCIXCAP_PTR,	uint8_t)
PCI_ACCESSOR(pciecap_ptr,	PCIECAP_PTR,	uint8_t)
PCI_ACCESSOR(vpdcap_ptr,	VPDCAP_PTR,	uint8_t)

#undef PCI_ACCESSOR

/*
 * Operations on configuration space.
 */
static __inline uint32_t
pci_read_config(device_t dev, int reg, int width)
{
    return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
}

static __inline void
pci_write_config(device_t dev, int reg, uint32_t val, int width)
{
    PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
}

/*
 * Ivars for pci bridges.
 */

/*typedef enum pci_device_ivars pcib_device_ivars;*/
enum pcib_device_ivars {
	PCIB_IVAR_DOMAIN,
	PCIB_IVAR_BUS
};

#define	PCIB_ACCESSOR(var, ivar, type)					 \
    __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)

PCIB_ACCESSOR(domain,		DOMAIN,		uint32_t)
PCIB_ACCESSOR(bus,		BUS,		uint32_t)

#undef PCIB_ACCESSOR

/*
 * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
 * on i386 or other platforms should be mapped out in the MD pcireadconf
 * code and not here, since the only MI invalid IRQ is 255.
 */
#define	PCI_INVALID_IRQ		255
#define	PCI_INTERRUPT_VALID(x)	((x) != PCI_INVALID_IRQ)

/*
 * Convenience functions.
 *
 * These should be used in preference to manually manipulating
 * configuration space.
 */
static __inline int
pci_enable_busmaster(device_t dev)
{
    return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
}

static __inline int
pci_disable_busmaster(device_t dev)
{
    return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
}

static __inline int
pci_enable_io(device_t dev, int space)
{
    return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
}

static __inline int
pci_disable_io(device_t dev, int space)
{
    return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
}

static __inline int
pci_get_vpd_ident(device_t dev, const char **identptr)
{
    return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
}

static __inline int
pci_get_vpd_readonly(device_t dev, const char *kw, const char **identptr)
{
    return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
}

/*
 * Check if the address range falls within the VGA defined address range(s)
 */
static __inline int
pci_is_vga_ioport_range(u_long start, u_long end)
{
 
	return (((start >= 0x3b0 && end <= 0x3bb) ||
	    (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
}

static __inline int
pci_is_vga_memory_range(u_long start, u_long end)
{

	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
}

int pcie_slot_implemented(device_t);
void pcie_set_max_readrq(device_t, uint16_t);
uint16_t pcie_get_max_readrq(device_t);

/*
 * PCI power states are as defined by ACPI:
 *
 * D0	State in which device is on and running.  It is receiving full
 *	power from the system and delivering full functionality to the user.
 * D1	Class-specific low-power state in which device context may or may not
 *	be lost.  Buses in D1 cannot do anything to the bus that would force
 *	devices on that bus to lose context.
 * D2	Class-specific low-power state in which device context may or may
 *	not be lost.  Attains greater power savings than D1.  Buses in D2
 *	can cause devices on that bus to lose some context.  Devices in D2
 *	must be prepared for the bus to be in D2 or higher.
 * D3	State in which the device is off and not running.  Device context is
 *	lost.  Power can be removed from the device.
 */
#define	PCI_POWERSTATE_D0	0
#define	PCI_POWERSTATE_D1	1
#define	PCI_POWERSTATE_D2	2
#define	PCI_POWERSTATE_D3	3
#define	PCI_POWERSTATE_UNKNOWN	-1

static __inline int
pci_set_powerstate(device_t dev, int state)
{
    return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
}

static __inline int
pci_get_powerstate(device_t dev)
{
    return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
}

static __inline int
pci_find_extcap(device_t dev, int capability, int *capreg)
{
    return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
}

static __inline int
pci_is_pcie(device_t dev)
{
	return (pci_get_pciecap_ptr(dev) != 0);
}

static __inline int
pci_is_pcix(device_t dev)
{
	return (pci_get_pcixcap_ptr(dev) != 0);
}

static __inline int
pci_alloc_msi(device_t dev, int *rid, int count, int cpuid)
{
    return (PCI_ALLOC_MSI(device_get_parent(dev), dev, rid, count, cpuid));
}

static __inline int
pci_alloc_msix(device_t dev, int *count)
{
    return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
}

static __inline int
pci_release_msi(device_t dev)
{
    return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
}

static __inline int
pci_msi_count(device_t dev)
{
    return (PCI_MSI_COUNT(device_get_parent(dev), dev));
}

static __inline int
pci_msix_count(device_t dev)
{
    return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
}

device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
device_t pci_find_device(uint16_t, uint16_t);

/* Can be used by drivers to manage the MSI-X table. */
int	pci_pending_msix_vector(device_t dev, u_int index);
int	pci_setup_msix(device_t dev);
void	pci_teardown_msix(device_t dev);

int	pci_msi_device_blacklisted(device_t dev);

void	pci_ht_map_msi(device_t dev, uint64_t addr);

/* Returns PCI_INTR_TYPE_ */
int	pci_alloc_1intr(device_t dev, int msi_enable, int *rid, u_int *flags);

#define PCI_INTR_TYPE_LEGACY	0
#define PCI_INTR_TYPE_MSI	1
#define PCI_INTR_TYPE_MSIX	2	/* not yet */

#endif	/* _SYS_BUS_H_ */

/*
 * cdev switch for control device, initialised in generic PCI code
 */
extern struct cdevsw pcicdev;

/*
 * List of all PCI devices, generation count for the list.
 */
STAILQ_HEAD(devlist, pci_devinfo);

extern struct devlist	pci_devq;
extern uint32_t	pci_generation;

/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */

#if defined(_KERNEL) && !defined(KLD_MODULE)
#include "opt_compat_oldpci.h"
#endif

#ifdef COMPAT_OLDPCI
/* all this is going some day */

typedef pcicfgregs *pcici_t;
typedef unsigned pcidi_t;
typedef void pci_inthand_t(void *arg);

#define pci_max_burst_len (3)

/* just copied from old PCI code for now ... */

struct pci_device {
    char*    pd_name;
    const char*  (*pd_probe ) (pcici_t tag, pcidi_t type);
    void   (*pd_attach) (pcici_t tag, int     unit);
    u_long  *pd_count;
    int    (*pd_shutdown) (int, int);
};

#ifdef __i386__
typedef u_short pci_port_t;
#else
typedef u_int pci_port_t;
#endif

u_long pci_conf_read (pcici_t tag, u_long reg);
void pci_conf_write (pcici_t tag, u_long reg, u_long data);
int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
int pci_map_int (pcici_t tag, pci_inthand_t *handler, void *arg);
int pci_map_int_right(pcici_t cfg, pci_inthand_t *handler, void *arg,
		      u_int flags);
int pci_unmap_int (pcici_t tag);

void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);

pcici_t pci_get_parent_from_tag(pcici_t tag);
int     pci_get_bus_from_tag(pcici_t tag);

pcicfgregs *pci_devlist_get_parent(pcicfgregs *cfg);

struct module;
int compat_pci_handler (struct module *, int, void *);
#define COMPAT_PCI_DRIVER(name, pcidata)				\
static moduledata_t name##_mod = {					\
	#name,								\
	compat_pci_handler,						\
	&pcidata							\
};									\
DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)

#endif /* COMPAT_OLDPCI */

#endif /* _PCIVAR_H_ */
Commit	Line	Data
4d28e78f	1	/*-
984263bc MD	2	* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions
	7	* are met:
	8	* 1. Redistributions of source code must retain the above copyright
	9	* notice unmodified, this list of conditions, and the following
	10	* disclaimer.
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	*
	15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
	16	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
	17	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	18	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	19	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	20	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	21	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	22	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	23	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	24	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	25	*
4d28e78f	26	* $FreeBSD: src/sys/dev/pci/pcivar.h,v 1.80.2.1.4.1 2009/04/15 03:14:26 kensmith Exp $
984263bc MD	27	*
	28	*/
	29
	30	#ifndef _PCIVAR_H_
4d28e78f	31	#define _PCIVAR_H_
984263bc	32
e2c4df7c	33	#ifndef _SYS_QUEUE_H_
984263bc	34	#include <sys/queue.h>
e2c4df7c SZ	35	#endif
e2c4df7c SZ	36
984263bc MD	37	/* some PCI bus constants */
984263bc MD	38
4d28e78f SZ	39	#define PCI_DOMAINMAX 65535 /* highest supported domain number */
	40	#define PCI_BUSMAX 255 /* highest supported bus number */
	41	#define PCI_SLOTMAX 31 /* highest supported slot number */
	42	#define PCI_FUNCMAX 7 /* highest supported function number */
	43	#define PCI_REGMAX 255 /* highest supported config register addr. */
984263bc	44
4d28e78f SZ	45	#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */
	46	#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */
	47	#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */
984263bc	48
4d28e78f	49	typedef uint64_t pci_addr_t;
984263bc	50
4d28e78f SZ	51	/* Interesting values for PCI power management */
	52	struct pcicfg_pp {
	53	uint16_t pp_cap; /* PCI power management capabilities */
	54	uint8_t pp_status; /* config space address of PCI power status reg */
	55	uint8_t pp_pmcsr; /* config space address of PMCSR reg */
	56	uint8_t pp_data; /* config space address of PCI power data reg */
1f7d9fe0	57	};
4d28e78f SZ	58
	59	struct vpd_readonly {
	60	char keyword[2];
	61	char *value;
b4c0a845 SZ	62	};
b4c0a845 SZ	63
4d28e78f SZ	64	struct vpd_write {
	65	char keyword[2];
	66	char *value;
	67	int start;
	68	int len;
	69	};
638744c5	70
4d28e78f SZ	71	struct pcicfg_vpd {
	72	uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */
	73	char vpd_cached;
	74	char vpd_ident; / string identifier */
	75	int vpd_rocnt;
	76	struct vpd_readonly *vpd_ros;
	77	int vpd_wcnt;
	78	struct vpd_write *vpd_w;
	79	};
984263bc	80
4d28e78f SZ	81	/* Interesting values for PCI MSI */
	82	struct pcicfg_msi {
	83	uint16_t msi_ctrl; /* Message Control */
	84	uint8_t msi_location; /* Offset of MSI capability registers. */
	85	uint8_t msi_msgnum; /* Number of messages */
	86	int msi_alloc; /* Number of allocated messages. */
	87	uint64_t msi_addr; /* Contents of address register. */
	88	uint16_t msi_data; /* Contents of data register. */
	89	u_int msi_handlers;
	90	};
984263bc	91
4d28e78f SZ	92	/* Interesting values for PCI MSI-X */
	93	struct msix_vector {
	94	uint64_t mv_address; /* Contents of address register. */
	95	uint32_t mv_data; /* Contents of data register. */
	96	int mv_irq;
	97	};
984263bc	98
4d28e78f SZ	99	struct msix_table_entry {
	100	u_int mte_vector; /* 1-based index into msix_vectors array. */
	101	u_int mte_handlers;
	102	};
984263bc	103
4d28e78f SZ	104	struct pcicfg_msix {
	105	uint16_t msix_ctrl; /* Message Control */
	106	uint16_t msix_msgnum; /* Number of messages */
	107	uint8_t msix_location; /* Offset of MSI-X capability registers. */
	108	uint8_t msix_table_bar; /* BAR containing vector table. */
	109	uint8_t msix_pba_bar; /* BAR containing PBA. */
	110	uint32_t msix_table_offset;
	111	uint32_t msix_pba_offset;
	112	int msix_alloc; /* Number of allocated vectors. */
	113	int msix_table_len; /* Length of virtual table. */
	114	struct msix_table_entry msix_table; / Virtual table. */
	115	struct msix_vector msix_vectors; / Array of allocated vectors. */
	116	struct resource msix_table_res; / Resource containing vector table. */
	117	struct resource msix_pba_res; / Resource containing PBA. */
	118	};
984263bc	119
4d28e78f SZ	120	/* Interesting values for HyperTransport */
4d28e78f SZ	121	struct pcicfg_ht {
941460da	122	uint8_t ht_slave; /* Non-zero if device is an HT slave. */
4d28e78f SZ	123	uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */
	124	uint16_t ht_msictrl; /* MSI mapping control */
	125	uint64_t ht_msiaddr; /* MSI mapping base address */
	126	};
984263bc	127
d85e7311 SZ	128	/* Interesting values for PCI Express capability */
	129	struct pcicfg_expr {
	130	uint8_t expr_ptr; /* capability ptr */
	131	uint16_t expr_cap; /* capabilities */
	132	uint32_t expr_slotcap; /* slot capabilities */
	133	};
	134
	135	/* Interesting values for PCI-X */
	136	struct pcicfg_pcix {
	137	uint8_t pcix_ptr;
	138	};
	139
4d28e78f SZ	140	/* config header information common to all header types */
	141	typedef struct pcicfg {
	142	struct device dev; / device which owns this */
984263bc	143
4d28e78f SZ	144	uint32_t bar[PCI_MAXMAPS_0]; /* BARs */
4d28e78f SZ	145	uint32_t bios; /* BIOS mapping */
984263bc	146
4d28e78f SZ	147	uint16_t subvendor; /* card vendor ID */
	148	uint16_t subdevice; /* card device ID, assigned by card vendor */
	149	uint16_t vendor; /* chip vendor ID */
	150	uint16_t device; /* chip device ID, assigned by chip vendor */
	151
	152	uint16_t cmdreg; /* disable/enable chip and PCI options */
	153	uint16_t statreg; /* supported PCI features and error state */
	154
	155	uint8_t baseclass; /* chip PCI class */
	156	uint8_t subclass; /* chip PCI subclass */
	157	uint8_t progif; /* chip PCI programming interface */
	158	uint8_t revid; /* chip revision ID */
	159
	160	uint8_t hdrtype; /* chip config header type */
	161	uint8_t cachelnsz; /* cache line size in 4byte units */
	162	uint8_t intpin; /* PCI interrupt pin */
	163	uint8_t intline; /* interrupt line (IRQ for PC arch) */
	164
	165	uint8_t mingnt; /* min. useful bus grant time in 250ns units */
	166	uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */
	167	uint8_t lattimer; /* latency timer in units of 30ns bus cycles */
	168
	169	uint8_t mfdev; /* multi-function device (from hdrtype reg) */
	170	uint8_t nummaps; /* actual number of PCI maps used */
	171
	172	uint32_t domain; /* PCI domain */
	173	uint8_t bus; /* config space bus address */
	174	uint8_t slot; /* config space slot address */
	175	uint8_t func; /* config space function number */
	176
6951547b SZ	177	#ifdef COMPAT_OLDPCI
	178	uint8_t secondarybus; /* bus on secondary side of bridge, if any */
	179	#else
	180	uint8_t dummy;
	181	#endif
	182
4d28e78f SZ	183	struct pcicfg_pp pp; /* pci power management */
	184	struct pcicfg_vpd vpd; /* pci vital product data */
	185	struct pcicfg_msi msi; /* pci msi */
	186	struct pcicfg_msix msix; /* pci msi-x */
	187	struct pcicfg_ht ht; /* HyperTransport */
d85e7311 SZ	188	struct pcicfg_expr expr; /* PCI Express */
d85e7311 SZ	189	struct pcicfg_pcix pcix; /* PCI-X */
984263bc MD	190	} pcicfgregs;
	191
	192	/* additional type 1 device config header information (PCI to PCI bridge) */
	193
4d28e78f SZ	194	#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
	195	#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) \| 0xfffff)
	196	#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff)
	197	#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) \| 0xfff)
984263bc MD	198
	199	typedef struct {
	200	pci_addr_t pmembase; /* base address of prefetchable memory */
	201	pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
4d28e78f SZ	202	uint32_t membase; /* base address of memory window */
	203	uint32_t memlimit; /* topmost address of memory window */
	204	uint32_t iobase; /* base address of port window */
	205	uint32_t iolimit; /* topmost address of port window */
	206	uint16_t secstat; /* secondary bus status register */
	207	uint16_t bridgectl; /* bridge control register */
	208	uint8_t seclat; /* CardBus latency timer */
984263bc MD	209	} pcih1cfgregs;
	210
	211	/* additional type 2 device config header information (CardBus bridge) */
	212
	213	typedef struct {
4d28e78f SZ	214	uint32_t membase0; /* base address of memory window */
	215	uint32_t memlimit0; /* topmost address of memory window */
	216	uint32_t membase1; /* base address of memory window */
	217	uint32_t memlimit1; /* topmost address of memory window */
	218	uint32_t iobase0; /* base address of port window */
	219	uint32_t iolimit0; /* topmost address of port window */
	220	uint32_t iobase1; /* base address of port window */
	221	uint32_t iolimit1; /* topmost address of port window */
	222	uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */
	223	uint16_t secstat; /* secondary bus status register */
	224	uint16_t bridgectl; /* bridge control register */
	225	uint8_t seclat; /* CardBus latency timer */
984263bc MD	226	} pcih2cfgregs;
984263bc MD	227
4d28e78f	228	extern uint32_t pci_numdevs;
984263bc	229
dc5a7bd2 JS	230	/* Only if the prerequisites are present */
	231	#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
	232	struct pci_devinfo {
	233	STAILQ_ENTRY(pci_devinfo) pci_links;
	234	struct resource_list resources;
	235	pcicfgregs cfg;
	236	struct pci_conf conf;
	237	};
	238	#endif
984263bc	239
984263bc MD	240	#ifdef _SYS_BUS_H_
	241
	242	#include "pci_if.h"
	243
	244	/*
	245	* Define pci-specific resource flags for accessing memory via dense
	246	* or bwx memory spaces. These flags are ignored on i386.
	247	*/
4d28e78f SZ	248	#define PCI_RF_DENSE 0x10000
4d28e78f SZ	249	#define PCI_RF_BWX 0x20000
984263bc MD	250
984263bc MD	251	enum pci_device_ivars {
4d28e78f SZ	252	PCI_IVAR_SUBVENDOR,
	253	PCI_IVAR_SUBDEVICE,
	254	PCI_IVAR_VENDOR,
	255	PCI_IVAR_DEVICE,
	256	PCI_IVAR_DEVID,
	257	PCI_IVAR_CLASS,
	258	PCI_IVAR_SUBCLASS,
	259	PCI_IVAR_PROGIF,
	260	PCI_IVAR_REVID,
	261	PCI_IVAR_INTPIN,
	262	PCI_IVAR_IRQ,
	263	PCI_IVAR_DOMAIN,
	264	PCI_IVAR_BUS,
	265	PCI_IVAR_SLOT,
	266	PCI_IVAR_FUNCTION,
	267	PCI_IVAR_ETHADDR,
	268	PCI_IVAR_CMDREG,
	269	PCI_IVAR_CACHELNSZ,
	270	PCI_IVAR_MINGNT,
	271	PCI_IVAR_MAXLAT,
	272	PCI_IVAR_LATTIMER,
d85e7311 SZ	273	PCI_IVAR_PCIXCAP_PTR,
	274	PCI_IVAR_PCIECAP_PTR,
	275	PCI_IVAR_VPDCAP_PTR
984263bc MD	276	};
	277
	278	/*
	279	* Simplified accessors for pci devices
	280	*/
4d28e78f SZ	281	#define PCI_ACCESSOR(var, ivar, type) \
	282	__BUS_ACCESSOR(pci, var, PCI, ivar, type)
	283
	284	PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t)
	285	PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t)
	286	PCI_ACCESSOR(vendor, VENDOR, uint16_t)
	287	PCI_ACCESSOR(device, DEVICE, uint16_t)
	288	PCI_ACCESSOR(devid, DEVID, uint32_t)
	289	PCI_ACCESSOR(class, CLASS, uint8_t)
	290	PCI_ACCESSOR(subclass, SUBCLASS, uint8_t)
	291	PCI_ACCESSOR(progif, PROGIF, uint8_t)
	292	PCI_ACCESSOR(revid, REVID, uint8_t)
	293	PCI_ACCESSOR(intpin, INTPIN, uint8_t)
	294	PCI_ACCESSOR(irq, IRQ, uint8_t)
	295	PCI_ACCESSOR(domain, DOMAIN, uint32_t)
	296	PCI_ACCESSOR(bus, BUS, uint8_t)
	297	PCI_ACCESSOR(slot, SLOT, uint8_t)
	298	PCI_ACCESSOR(function, FUNCTION, uint8_t)
f72d3d23	299	PCI_ACCESSOR(ether, ETHADDR, uint8_t *)
4d28e78f SZ	300	PCI_ACCESSOR(cmdreg, CMDREG, uint8_t)
	301	PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t)
	302	PCI_ACCESSOR(mingnt, MINGNT, uint8_t)
	303	PCI_ACCESSOR(maxlat, MAXLAT, uint8_t)
	304	PCI_ACCESSOR(lattimer, LATTIMER, uint8_t)
d85e7311 SZ	305	PCI_ACCESSOR(pcixcap_ptr, PCIXCAP_PTR, uint8_t)
	306	PCI_ACCESSOR(pciecap_ptr, PCIECAP_PTR, uint8_t)
	307	PCI_ACCESSOR(vpdcap_ptr, VPDCAP_PTR, uint8_t)
984263bc	308
27c23c6b JS	309	#undef PCI_ACCESSOR
27c23c6b JS	310
4d28e78f SZ	311	/*
	312	* Operations on configuration space.
	313	*/
	314	static __inline uint32_t
984263bc MD	315	pci_read_config(device_t dev, int reg, int width)
	316	{
	317	return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
	318	}
	319
	320	static __inline void
4d28e78f	321	pci_write_config(device_t dev, int reg, uint32_t val, int width)
984263bc MD	322	{
	323	PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
	324	}
	325
	326	/*
4d28e78f SZ	327	* Ivars for pci bridges.
	328	*/
	329
	330	/typedef enum pci_device_ivars pcib_device_ivars;/
	331	enum pcib_device_ivars {
	332	PCIB_IVAR_DOMAIN,
	333	PCIB_IVAR_BUS
	334	};
	335
	336	#define PCIB_ACCESSOR(var, ivar, type) \
	337	__BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
	338
	339	PCIB_ACCESSOR(domain, DOMAIN, uint32_t)
	340	PCIB_ACCESSOR(bus, BUS, uint32_t)
	341
	342	#undef PCIB_ACCESSOR
	343
	344	/*
	345	* PCI interrupt validation. Invalid interrupt values such as 0 or 128
	346	* on i386 or other platforms should be mapped out in the MD pcireadconf
	347	* code and not here, since the only MI invalid IRQ is 255.
	348	*/
	349	#define PCI_INVALID_IRQ 255
	350	#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ)
	351
	352	/*
984263bc MD	353	* Convenience functions.
	354	*
	355	* These should be used in preference to manually manipulating
	356	* configuration space.
	357	*/
4d28e78f	358	static __inline int
984263bc MD	359	pci_enable_busmaster(device_t dev)
984263bc MD	360	{
4d28e78f	361	return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
984263bc MD	362	}
984263bc MD	363
4d28e78f	364	static __inline int
984263bc MD	365	pci_disable_busmaster(device_t dev)
984263bc MD	366	{
4d28e78f	367	return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
984263bc MD	368	}
984263bc MD	369
4d28e78f	370	static __inline int
984263bc MD	371	pci_enable_io(device_t dev, int space)
984263bc MD	372	{
4d28e78f	373	return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
984263bc MD	374	}
984263bc MD	375
4d28e78f	376	static __inline int
984263bc MD	377	pci_disable_io(device_t dev, int space)
984263bc MD	378	{
4d28e78f	379	return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
984263bc MD	380	}
984263bc MD	381
c7e4e7eb	382	static __inline int
4d28e78f	383	pci_get_vpd_ident(device_t dev, const char **identptr)
c7e4e7eb	384	{
4d28e78f	385	return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
c7e4e7eb SZ	386	}
	387
	388	static __inline int
4d28e78f SZ	389	pci_get_vpd_readonly(device_t dev, const char kw, const char *identptr)
	390	{
	391	return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, identptr));
	392	}
	393
	394	/*
	395	* Check if the address range falls within the VGA defined address range(s)
	396	*/
	397	static __inline int
	398	pci_is_vga_ioport_range(u_long start, u_long end)
	399	{
	400
	401	return (((start >= 0x3b0 && end <= 0x3bb) \|\|
	402	(start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
	403	}
	404
	405	static __inline int
	406	pci_is_vga_memory_range(u_long start, u_long end)
c7e4e7eb	407	{
4d28e78f SZ	408
4d28e78f SZ	409	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
c7e4e7eb SZ	410	}
c7e4e7eb SZ	411
d85e7311	412	int pcie_slot_implemented(device_t);
4d28e78f	413	void pcie_set_max_readrq(device_t, uint16_t);
441580ca	414	uint16_t pcie_get_max_readrq(device_t);
d85e7311	415
984263bc MD	416	/*
	417	* PCI power states are as defined by ACPI:
	418	*
	419	* D0 State in which device is on and running. It is receiving full
	420	* power from the system and delivering full functionality to the user.
	421	* D1 Class-specific low-power state in which device context may or may not
	422	* be lost. Buses in D1 cannot do anything to the bus that would force
4d28e78f	423	* devices on that bus to lose context.
984263bc MD	424	* D2 Class-specific low-power state in which device context may or may
984263bc MD	425	* not be lost. Attains greater power savings than D1. Buses in D2
4d28e78f	426	* can cause devices on that bus to lose some context. Devices in D2
984263bc MD	427	* must be prepared for the bus to be in D2 or higher.
	428	* D3 State in which the device is off and not running. Device context is
	429	* lost. Power can be removed from the device.
	430	*/
4d28e78f SZ	431	#define PCI_POWERSTATE_D0 0
	432	#define PCI_POWERSTATE_D1 1
	433	#define PCI_POWERSTATE_D2 2
	434	#define PCI_POWERSTATE_D3 3
	435	#define PCI_POWERSTATE_UNKNOWN -1
984263bc MD	436
	437	static __inline int
	438	pci_set_powerstate(device_t dev, int state)
	439	{
	440	return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
	441	}
	442
	443	static __inline int
	444	pci_get_powerstate(device_t dev)
	445	{
	446	return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
	447	}
	448
4d28e78f SZ	449	static __inline int
	450	pci_find_extcap(device_t dev, int capability, int *capreg)
	451	{
	452	return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg);
	453	}
	454
	455	static __inline int
	456	pci_is_pcie(device_t dev)
	457	{
d85e7311	458	return (pci_get_pciecap_ptr(dev) != 0);
4d28e78f	459	}
984263bc	460
4d28e78f SZ	461	static __inline int
	462	pci_is_pcix(device_t dev)
	463	{
d85e7311	464	return (pci_get_pcixcap_ptr(dev) != 0);
4d28e78f	465	}
984263bc	466
4d28e78f	467	static __inline int
2c3d7ac8	468	pci_alloc_msi(device_t dev, int *rid, int count, int cpuid)
4d28e78f	469	{
2c3d7ac8	470	return (PCI_ALLOC_MSI(device_get_parent(dev), dev, rid, count, cpuid));
4d28e78f SZ	471	}
	472
	473	static __inline int
	474	pci_alloc_msix(device_t dev, int *count)
	475	{
	476	return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
	477	}
984263bc	478
4d28e78f	479	static __inline int
4d28e78f SZ	480	pci_release_msi(device_t dev)
	481	{
	482	return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
	483	}
984263bc	484
4d28e78f SZ	485	static __inline int
	486	pci_msi_count(device_t dev)
	487	{
	488	return (PCI_MSI_COUNT(device_get_parent(dev), dev));
	489	}
984263bc	490
4d28e78f SZ	491	static __inline int
	492	pci_msix_count(device_t dev)
	493	{
	494	return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
	495	}
984263bc	496
4d28e78f SZ	497	device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
	498	device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
	499	device_t pci_find_device(uint16_t, uint16_t);
	500
4d28e78f	501	/* Can be used by drivers to manage the MSI-X table. */
cf8f3133	502	int pci_pending_msix_vector(device_t dev, u_int index);
31646171 SZ	503	int pci_setup_msix(device_t dev);
31646171 SZ	504	void pci_teardown_msix(device_t dev);
4d28e78f SZ	505
	506	int pci_msi_device_blacklisted(device_t dev);
	507
	508	void pci_ht_map_msi(device_t dev, uint64_t addr);
	509
7fb43956 SZ	510	/* Returns PCI_INTR_TYPE_ */
	511	int pci_alloc_1intr(device_t dev, int msi_enable, int rid, u_int flags);
	512
	513	#define PCI_INTR_TYPE_LEGACY 0
	514	#define PCI_INTR_TYPE_MSI 1
	515	#define PCI_INTR_TYPE_MSIX 2 /* not yet */
	516
4d28e78f SZ	517	#endif /* _SYS_BUS_H_ */
	518
	519	/*
	520	* cdev switch for control device, initialised in generic PCI code
	521	*/
	522	extern struct cdevsw pcicdev;
	523
	524	/*
	525	* List of all PCI devices, generation count for the list.
	526	*/
	527	STAILQ_HEAD(devlist, pci_devinfo);
	528
	529	extern struct devlist pci_devq;
	530	extern uint32_t pci_generation;
984263bc	531
6951547b SZ	532	/* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
	533
	534	#if defined(_KERNEL) && !defined(KLD_MODULE)
	535	#include "opt_compat_oldpci.h"
	536	#endif
	537
	538	#ifdef COMPAT_OLDPCI
	539	/* all this is going some day */
	540
	541	typedef pcicfgregs *pcici_t;
	542	typedef unsigned pcidi_t;
	543	typedef void pci_inthand_t(void *arg);
	544
	545	#define pci_max_burst_len (3)
	546
	547	/* just copied from old PCI code for now ... */
	548
	549	struct pci_device {
	550	char* pd_name;
	551	const char* (*pd_probe ) (pcici_t tag, pcidi_t type);
	552	void (*pd_attach) (pcici_t tag, int unit);
	553	u_long *pd_count;
	554	int (*pd_shutdown) (int, int);
	555	};
	556
	557	#ifdef __i386__
	558	typedef u_short pci_port_t;
	559	#else
	560	typedef u_int pci_port_t;
	561	#endif
	562
	563	u_long pci_conf_read (pcici_t tag, u_long reg);
	564	void pci_conf_write (pcici_t tag, u_long reg, u_long data);
	565	int pci_map_port (pcici_t tag, u_long reg, pci_port_t* pa);
	566	int pci_map_mem (pcici_t tag, u_long reg, vm_offset_t* va, vm_offset_t* pa);
	567	int pci_map_int (pcici_t tag, pci_inthand_t handler, void arg);
	568	int pci_map_int_right(pcici_t cfg, pci_inthand_t handler, void arg,
	569	u_int flags);
	570	int pci_unmap_int (pcici_t tag);
	571
	572	void pci_cfgwrite (pcicfgregs *cfg, int reg, int data, int bytes);
	573
	574	pcici_t pci_get_parent_from_tag(pcici_t tag);
	575	int pci_get_bus_from_tag(pcici_t tag);
	576
	577	pcicfgregs pci_devlist_get_parent(pcicfgregs cfg);
	578
	579	struct module;
	580	int compat_pci_handler (struct module , int, void );
	581	#define COMPAT_PCI_DRIVER(name, pcidata) \
	582	static moduledata_t name##_mod = { \
	583	#name, \
	584	compat_pci_handler, \
	585	&pcidata \
	586	}; \
	587	DECLARE_MODULE(name, name##_mod, SI_SUB_DRIVERS, SI_ORDER_ANY)
	588
	589	#endif /* COMPAT_OLDPCI */
	590
984263bc	591	#endif /* _PCIVAR_H_ */