[dragonfly.git] / sys / dev / netif / emx / if_emx.h

/*
 * Copyright (c) 2001-2008, Intel Corporation
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright notice,
 *     this list of conditions and the following disclaimer.
 *
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
 *
 *  3. Neither the name of the Intel Corporation nor the names of its
 *     contributors may be used to endorse or promote products derived from
 *     this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _IF_EMX_H_
#define _IF_EMX_H_

/* Tunables */

/*
 * EMX_TXD: Maximum number of Transmit Descriptors
 * Valid Range: 256-4096 for others
 * Default Value: 512
 *   This value is the number of transmit descriptors allocated by the driver.
 *   Increasing this value allows the driver to queue more transmits. Each
 *   descriptor is 16 bytes.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define EMX_MIN_TXD			256
#define EMX_MAX_TXD			4096
#define EMX_DEFAULT_TXD			512

/*
 * EMX_RXD - Maximum number of receive Descriptors
 * Valid Range: 256-4096 for others
 * Default Value: 512
 *   This value is the number of receive descriptors allocated by the driver.
 *   Increasing this value allows the driver to buffer more incoming packets.
 *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
 *   descriptor. The maximum MTU size is 16110.
 *   Since TDLEN should be multiple of 128bytes, the number of transmit
 *   desscriptors should meet the following condition.
 *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
 */
#define EMX_MIN_RXD			256
#define EMX_MAX_RXD			4096
#define EMX_DEFAULT_RXD			512

/*
 * Receive Interrupt Delay Timer (Packet Timer)
 *
 * NOTE:
 * RDTR and RADV are deprecated; use ITR instead.  They are only used to
 * workaround hardware bug on certain 82573 based NICs.
 */
#define EMX_RDTR_82573			32

/*
 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
 *
 * NOTE:
 * RDTR and RADV are deprecated; use ITR instead.  They are only used to
 * workaround hardware bug on certain 82573 based NICs.
 */
#define EMX_RADV_82573			64

/*
 * This parameter controls the duration of transmit watchdog timer.
 */
#define EMX_TX_TIMEOUT			5

/* One for TX csum offloading desc, the other 2 are reserved */
#define EMX_TX_RESERVED			3

/* Large enough for 16K jumbo frame */
#define EMX_TX_SPARE			8

#define EMX_TX_OACTIVE_MAX		64

/* Interrupt throttle rate */
#define EMX_DEFAULT_ITR			6000

/*
 * This parameter controls whether or not autonegotation is enabled.
 *              0 - Disable autonegotiation
 *              1 - Enable  autonegotiation
 */
#define EMX_DO_AUTO_NEG			1

/* Tunables -- End */

#define EMX_AUTONEG_ADV_DEFAULT		(ADVERTISE_10_HALF | \
					 ADVERTISE_10_FULL | \
					 ADVERTISE_100_HALF | \
					 ADVERTISE_100_FULL | \
					 ADVERTISE_1000_FULL)

#define EMX_AUTO_ALL_MODES		0

/* PHY master/slave setting */
#define EMX_MASTER_SLAVE		e1000_ms_hw_default

/*
 * Micellaneous constants
 */
#define EMX_VENDOR_ID			0x8086

#define EMX_BAR_MEM			PCIR_BAR(0)

#define EMX_JUMBO_PBA			0x00000028
#define EMX_DEFAULT_PBA			0x00000030
#define EMX_SMARTSPEED_DOWNSHIFT	3
#define EMX_SMARTSPEED_MAX		15
#define EMX_MAX_INTR			10

#define EMX_MCAST_ADDR_MAX		128
#define EMX_FC_PAUSE_TIME		1000
#define EMX_EEPROM_APME			0x400;

/*
 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
 * also optimize cache line size effect. H/W supports up to cache line size 128.
 */
#define EMX_DBA_ALIGN			128

/*
 * Speed mode bit in TARC0/TARC1.
 * 82571EB/82572EI only, used to improve small packet transmit performance.
 */
#define EMX_TARC_SPEED_MODE		(1 << 21)

#define EMX_MAX_SCATTER			64
#define EMX_TSO_SIZE			(IP_MAXPACKET + \
					 sizeof(struct ether_vlan_header))
#define EMX_MAX_SEGSIZE			PAGE_SIZE
#define EMX_MSIX_MASK			0x01F00000 /* For 82574 use */

#define EMX_CSUM_FEATURES		(CSUM_IP | CSUM_TCP | CSUM_UDP)

/*
 * 82574 has a nonstandard address for EIAC
 * and since its only used in MSIX, and in
 * the em driver only 82574 uses MSIX we can
 * solve it just using this define.
 */
#define EMX_EIAC			0x000DC

#define EMX_NRSSRK			10
#define EMX_RSSRK_SIZE			4
#define EMX_RSSRK_VAL(key, i)		(key[(i) * EMX_RSSRK_SIZE] | \
					 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
					 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
					 key[(i) * EMX_RSSRK_SIZE + 3] << 24)

#define EMX_NRETA			32
#define EMX_RETA_SIZE			4
#define EMX_RETA_RINGIDX_SHIFT		7

#define EMX_NRX_RING			2
#define EMX_NSERIALIZE			4

typedef union e1000_rx_desc_extended	emx_rxdesc_t;

#define rxd_bufaddr	read.buffer_addr	/* 64bits */
#define rxd_length	wb.upper.length		/* 16bits */
#define rxd_vlan	wb.upper.vlan		/* 16bits */
#define rxd_staterr	wb.upper.status_error	/* 32bits */
#define rxd_mrq		wb.lower.mrq		/* 32bits */
#define rxd_rss		wb.lower.hi_dword.rss	/* 32bits */

#define EMX_RXDMRQ_RSSTYPE_MASK	0xf
#define EMX_RXDMRQ_NO_HASH	0
#define EMX_RXDMRQ_IPV4_TCP	1
#define EMX_RXDMRQ_IPV4		2
#define EMX_RXDMRQ_IPV6_TCP	3
#define EMX_RXDMRQ_IPV6		5

struct emx_rxdata {
	struct lwkt_serialize	rx_serialize;

	/*
	 * Receive definitions
	 *
	 * we have an array of num_rx_desc rx_desc (handled by the
	 * controller), and paired with an array of rx_buffers
	 * (at rx_buffer_area).
	 * The next pair to check on receive is at offset next_rx_desc_to_check
	 */
	emx_rxdesc_t		*rx_desc;
	uint32_t		next_rx_desc_to_check;
	int			num_rx_desc;
	struct emx_rxbuf	*rx_buf;
	bus_dma_tag_t		rxtag;
	bus_dmamap_t		rx_sparemap;

	/*
	 * First/last mbuf pointers, for
	 * collecting multisegment RX packets.
	 */
	struct mbuf		*fmp;
	struct mbuf		*lmp;

	/* RX statistics */
	unsigned long		rx_pkts;
	unsigned long		mbuf_cluster_failed;

	bus_dma_tag_t		rx_desc_dtag;
	bus_dmamap_t		rx_desc_dmap;
	bus_addr_t		rx_desc_paddr;
} __cachealign;

struct emx_softc {
	struct arpcom		arpcom;
	struct e1000_hw		hw;
	int			flags;
#define EMX_FLAG_SHARED_INTR	0x1
#define EMX_FLAG_TSO_PULLEX	0x2

	/* DragonFly operating-system-specific structures. */
	struct e1000_osdep	osdep;
	device_t		dev;

	bus_dma_tag_t		parent_dtag;

	bus_dma_tag_t		tx_desc_dtag;
	bus_dmamap_t		tx_desc_dmap;
	bus_addr_t		tx_desc_paddr;

	struct resource		*memory;
	int			memory_rid;

	struct resource		*intr_res;
	void			*intr_tag;
	int			intr_rid;
	int			intr_type;

	struct ifmedia		media;
	struct callout		timer;
	int			if_flags;
	int			max_frame_size;
	int			min_frame_size;

	/* Management and WOL features */
	int			wol;
	int			has_manage;
	int			has_amt;
	int			control_hw;

	/* Multicast array memory */
	uint8_t			*mta;

	/* Info about the board itself */
	uint8_t			link_active;
	uint16_t		link_speed;
	uint16_t		link_duplex;
	uint32_t		smartspeed;
	int			int_throttle_ceil;

	struct lwkt_serialize	main_serialize;
	struct lwkt_serialize	tx_serialize;
	struct lwkt_serialize	*serializes[EMX_NSERIALIZE];

	/*
	 * Transmit definitions
	 *
	 * We have an array of num_tx_desc descriptors (handled
	 * by the controller) paired with an array of tx_buffers
	 * (at tx_buffer_area).
	 * The index of the next available descriptor is next_avail_tx_desc.
	 * The number of remaining tx_desc is num_tx_desc_avail.
	 */
	struct e1000_tx_desc	*tx_desc_base;
	struct emx_txbuf	*tx_buf;
	uint32_t		next_avail_tx_desc;
	uint32_t		next_tx_to_clean;
	int			num_tx_desc_avail;
	int			num_tx_desc;
	bus_dma_tag_t		txtag;		/* dma tag for tx */
	int			spare_tx_desc;
	int			oact_tx_desc;

	/* Saved csum offloading context information */
	int			csum_flags;
	int			csum_lhlen;
	int			csum_iphlen;

	int			csum_thlen;	/* TSO */
	int			csum_mss;	/* TSO */
	int			csum_pktlen;	/* TSO */

	uint32_t		csum_txd_upper;
	uint32_t		csum_txd_lower;

	/*
	 * Variables used to reduce TX interrupt rate and
	 * number of device's TX ring write requests.
	 *
	 * tx_nsegs:
	 * Number of TX descriptors setup so far.
	 *
	 * tx_int_nsegs:
	 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
	 * in the last TX descriptor of the packet, and
	 * tx_nsegs will be reset to 0.  So TX interrupt and
	 * TX ring write request should be generated roughly
	 * every tx_int_nsegs TX descriptors.
	 *
	 * tx_dd[]:
	 * Index of the TX descriptors which have RS bit set,
	 * i.e. DD bit will be set on this TX descriptor after
	 * the data of the TX descriptor are transfered to
	 * hardware's internal packet buffer.  Only the TX
	 * descriptors listed in tx_dd[] will be checked upon
	 * TX interrupt.  This array is used as circular ring.
	 *
	 * tx_dd_tail, tx_dd_head:
	 * Tail and head index of valid elements in tx_dd[].
	 * tx_dd_tail == tx_dd_head means there is no valid
	 * elements in tx_dd[].  tx_dd_tail points to the position
	 * which is one beyond the last valid element in tx_dd[].
	 * tx_dd_head points to the first valid element in
	 * tx_dd[].
	 */
	int			tx_int_nsegs;
	int			tx_nsegs;
	int			tx_dd_tail;
	int			tx_dd_head;
#define EMX_TXDD_MAX	64
#define EMX_TXDD_SAFE	48 /* 48 <= val < EMX_TXDD_MAX */
	int			tx_dd[EMX_TXDD_MAX];

	int			rss_debug;
	int			rx_ring_cnt;
	struct emx_rxdata	rx_data[EMX_NRX_RING];

	/* Misc stats maintained by the driver */
	unsigned long		dropped_pkts;
	unsigned long		mbuf_alloc_failed;
	unsigned long		no_tx_desc_avail1;
	unsigned long		no_tx_desc_avail2;
	unsigned long		no_tx_map_avail;
	unsigned long		no_tx_dma_setup;
	unsigned long		watchdog_events;
	unsigned long		rx_overruns;
	unsigned long		rx_irq;
	unsigned long		tx_irq;
	unsigned long		link_irq;
	unsigned long		tso_segments;
	unsigned long		tso_ctx_reused;

	/* sysctl tree glue */
	struct sysctl_ctx_list	sysctl_ctx;
	struct sysctl_oid	*sysctl_tree;

	struct e1000_hw_stats	stats;
};

struct emx_txbuf {
	struct mbuf	*m_head;
	bus_dmamap_t	map;
};

struct emx_rxbuf {
	struct mbuf	*m_head;
	bus_dmamap_t	map;
	bus_addr_t	paddr;
};

#define EMX_IS_OACTIVE(sc)	((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc)

#define EMX_INC_TXDD_IDX(idx) \
do { \
	if (++(idx) == EMX_TXDD_MAX) \
		(idx) = 0; \
} while (0)

#endif /* !_IF_EMX_H_ */
Commit	Line	Data
5330213c SZ	1	/*
	2	* Copyright (c) 2001-2008, Intel Corporation
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions are met:
	7	*
	8	* 1. Redistributions of source code must retain the above copyright notice,
	9	* this list of conditions and the following disclaimer.
	10	*
	11	* 2. Redistributions in binary form must reproduce the above copyright
	12	* notice, this list of conditions and the following disclaimer in the
	13	* documentation and/or other materials provided with the distribution.
	14	*
	15	* 3. Neither the name of the Intel Corporation nor the names of its
	16	* contributors may be used to endorse or promote products derived from
	17	* this software without specific prior written permission.
	18	*
	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
	20	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	21	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	22	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
	23	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
	29	* POSSIBILITY OF SUCH DAMAGE.
	30	*/
	31
	32	#ifndef _IF_EMX_H_
	33	#define _IF_EMX_H_
	34
	35	/* Tunables */
	36
	37	/*
	38	* EMX_TXD: Maximum number of Transmit Descriptors
	39	* Valid Range: 256-4096 for others
	40	* Default Value: 512
	41	* This value is the number of transmit descriptors allocated by the driver.
	42	* Increasing this value allows the driver to queue more transmits. Each
	43	* descriptor is 16 bytes.
	44	* Since TDLEN should be multiple of 128bytes, the number of transmit
	45	* desscriptors should meet the following condition.
	46	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
	47	*/
	48	#define EMX_MIN_TXD 256
	49	#define EMX_MAX_TXD 4096
	50	#define EMX_DEFAULT_TXD 512
	51
	52	/*
	53	* EMX_RXD - Maximum number of receive Descriptors
	54	* Valid Range: 256-4096 for others
	55	* Default Value: 512
	56	* This value is the number of receive descriptors allocated by the driver.
	57	* Increasing this value allows the driver to buffer more incoming packets.
	58	* Each descriptor is 16 bytes. A receive buffer is also allocated for each
	59	* descriptor. The maximum MTU size is 16110.
	60	* Since TDLEN should be multiple of 128bytes, the number of transmit
	61	* desscriptors should meet the following condition.
	62	* (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
	63	*/
	64	#define EMX_MIN_RXD 256
65	#define EMX_MAX_RXD 4096
66	#define EMX_DEFAULT_RXD 512
67
68	/*
69	* Receive Interrupt Delay Timer (Packet Timer)
70	*
71	* NOTE:
72	* RDTR and RADV are deprecated; use ITR instead. They are only used to
73	* workaround hardware bug on certain 82573 based NICs.
74	*/
75	#define EMX_RDTR_82573 32
76
77	/*
78	* Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
79	*
80	* NOTE:
81	* RDTR and RADV are deprecated; use ITR instead. They are only used to
82	* workaround hardware bug on certain 82573 based NICs.
83	*/
84	#define EMX_RADV_82573 64
85
86	/*
87	* This parameter controls the duration of transmit watchdog timer.
88	*/
89	#define EMX_TX_TIMEOUT 5
90
dc07210e SZ	91	/* One for TX csum offloading desc, the other 2 are reserved */
dc07210e SZ	92	#define EMX_TX_RESERVED 3
5330213c SZ	93
	94	/* Large enough for 16K jumbo frame */
	95	#define EMX_TX_SPARE 8
	96
	97	#define EMX_TX_OACTIVE_MAX 64
	98
	99	/* Interrupt throttle rate */
3245f71e	100	#define EMX_DEFAULT_ITR 6000
5330213c SZ	101
	102	/*
	103	* This parameter controls whether or not autonegotation is enabled.
	104	* 0 - Disable autonegotiation
	105	* 1 - Enable autonegotiation
	106	*/
	107	#define EMX_DO_AUTO_NEG 1
	108
	109	/* Tunables -- End */
	110
	111	#define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF \| \
	112	ADVERTISE_10_FULL \| \
	113	ADVERTISE_100_HALF \| \
	114	ADVERTISE_100_FULL \| \
	115	ADVERTISE_1000_FULL)
	116
	117	#define EMX_AUTO_ALL_MODES 0
	118
	119	/* PHY master/slave setting */
	120	#define EMX_MASTER_SLAVE e1000_ms_hw_default
	121
	122	/*
	123	* Micellaneous constants
	124	*/
	125	#define EMX_VENDOR_ID 0x8086
	126
	127	#define EMX_BAR_MEM PCIR_BAR(0)
	128
	129	#define EMX_JUMBO_PBA 0x00000028
	130	#define EMX_DEFAULT_PBA 0x00000030
	131	#define EMX_SMARTSPEED_DOWNSHIFT 3
	132	#define EMX_SMARTSPEED_MAX 15
	133	#define EMX_MAX_INTR 10
	134
	135	#define EMX_MCAST_ADDR_MAX 128
	136	#define EMX_FC_PAUSE_TIME 1000
	137	#define EMX_EEPROM_APME 0x400;
	138
	139	/*
	140	* TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
	141	* multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
	142	* also optimize cache line size effect. H/W supports up to cache line size 128.
	143	*/
	144	#define EMX_DBA_ALIGN 128
	145
	146	/*
	147	* Speed mode bit in TARC0/TARC1.
	148	* 82571EB/82572EI only, used to improve small packet transmit performance.
	149	*/
	150	#define EMX_TARC_SPEED_MODE (1 << 21)
	151
	152	#define EMX_MAX_SCATTER 64
3eb0ea09	153	#define EMX_TSO_SIZE (IP_MAXPACKET + \
5330213c	154	sizeof(struct ether_vlan_header))
3eb0ea09	155	#define EMX_MAX_SEGSIZE PAGE_SIZE
5330213c SZ	156	#define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
	157
	158	#define EMX_CSUM_FEATURES (CSUM_IP \| CSUM_TCP \| CSUM_UDP)
5330213c SZ	159
	160	/*
	161	* 82574 has a nonstandard address for EIAC
	162	* and since its only used in MSIX, and in
	163	* the em driver only 82574 uses MSIX we can
	164	* solve it just using this define.
	165	*/
	166	#define EMX_EIAC 0x000DC
	167
3f939c23	168	#define EMX_NRSSRK 10
89d8e73d SZ	169	#define EMX_RSSRK_SIZE 4
	170	#define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] \| \
	171	key[(i) * EMX_RSSRK_SIZE + 1] << 8 \| \
	172	key[(i) * EMX_RSSRK_SIZE + 2] << 16 \| \
	173	key[(i) * EMX_RSSRK_SIZE + 3] << 24)
	174
3f939c23	175	#define EMX_NRETA 32
89d8e73d SZ	176	#define EMX_RETA_SIZE 4
89d8e73d SZ	177	#define EMX_RETA_RINGIDX_SHIFT 7
3f939c23	178
c39e3a1f	179	#define EMX_NRX_RING 2
6d435846	180	#define EMX_NSERIALIZE 4
c39e3a1f	181
235b9d30 SZ	182	typedef union e1000_rx_desc_extended emx_rxdesc_t;
	183
	184	#define rxd_bufaddr read.buffer_addr /* 64bits */
	185	#define rxd_length wb.upper.length /* 16bits */
	186	#define rxd_vlan wb.upper.vlan /* 16bits */
	187	#define rxd_staterr wb.upper.status_error /* 32bits */
3f939c23 SZ	188	#define rxd_mrq wb.lower.mrq /* 32bits */
3f939c23 SZ	189	#define rxd_rss wb.lower.hi_dword.rss /* 32bits */
235b9d30	190
9cc86e17 SZ	191	#define EMX_RXDMRQ_RSSTYPE_MASK 0xf
	192	#define EMX_RXDMRQ_NO_HASH 0
	193	#define EMX_RXDMRQ_IPV4_TCP 1
	194	#define EMX_RXDMRQ_IPV4 2
	195	#define EMX_RXDMRQ_IPV6_TCP 3
	196	#define EMX_RXDMRQ_IPV6 5
	197
c39e3a1f	198	struct emx_rxdata {
6d435846 SZ	199	struct lwkt_serialize rx_serialize;
6d435846 SZ	200
c39e3a1f SZ	201	/*
	202	* Receive definitions
	203	*
	204	* we have an array of num_rx_desc rx_desc (handled by the
	205	* controller), and paired with an array of rx_buffers
	206	* (at rx_buffer_area).
	207	* The next pair to check on receive is at offset next_rx_desc_to_check
	208	*/
235b9d30	209	emx_rxdesc_t *rx_desc;
c39e3a1f SZ	210	uint32_t next_rx_desc_to_check;
c39e3a1f SZ	211	int num_rx_desc;
323e5ecd	212	struct emx_rxbuf *rx_buf;
c39e3a1f SZ	213	bus_dma_tag_t rxtag;
	214	bus_dmamap_t rx_sparemap;
	215
	216	/*
	217	* First/last mbuf pointers, for
	218	* collecting multisegment RX packets.
	219	*/
	220	struct mbuf *fmp;
	221	struct mbuf *lmp;
	222
	223	/* RX statistics */
3f939c23	224	unsigned long rx_pkts;
c39e3a1f SZ	225	unsigned long mbuf_cluster_failed;
	226
	227	bus_dma_tag_t rx_desc_dtag;
	228	bus_dmamap_t rx_desc_dmap;
	229	bus_addr_t rx_desc_paddr;
d721525c	230	} __cachealign;
c39e3a1f	231
5330213c SZ	232	struct emx_softc {
	233	struct arpcom arpcom;
	234	struct e1000_hw hw;
4cb541ae SZ	235	int flags;
4cb541ae SZ	236	#define EMX_FLAG_SHARED_INTR 0x1
3eb0ea09	237	#define EMX_FLAG_TSO_PULLEX 0x2
5330213c SZ	238
	239	/* DragonFly operating-system-specific structures. */
	240	struct e1000_osdep osdep;
	241	device_t dev;
	242
	243	bus_dma_tag_t parent_dtag;
a596084c	244
a596084c SZ	245	bus_dma_tag_t tx_desc_dtag;
	246	bus_dmamap_t tx_desc_dmap;
	247	bus_addr_t tx_desc_paddr;
5330213c SZ	248
	249	struct resource *memory;
	250	int memory_rid;
	251
	252	struct resource *intr_res;
	253	void *intr_tag;
	254	int intr_rid;
704b6287	255	int intr_type;
5330213c SZ	256
	257	struct ifmedia media;
	258	struct callout timer;
	259	int if_flags;
	260	int max_frame_size;
	261	int min_frame_size;
	262
	263	/* Management and WOL features */
	264	int wol;
	265	int has_manage;
2d0e5700 SZ	266	int has_amt;
	267	int control_hw;
	268
	269	/* Multicast array memory */
	270	uint8_t *mta;
5330213c SZ	271
	272	/* Info about the board itself */
	273	uint8_t link_active;
	274	uint16_t link_speed;
	275	uint16_t link_duplex;
	276	uint32_t smartspeed;
	277	int int_throttle_ceil;
	278
6d435846 SZ	279	struct lwkt_serialize main_serialize;
	280	struct lwkt_serialize tx_serialize;
	281	struct lwkt_serialize *serializes[EMX_NSERIALIZE];
	282
5330213c SZ	283	/*
	284	* Transmit definitions
	285	*
	286	* We have an array of num_tx_desc descriptors (handled
	287	* by the controller) paired with an array of tx_buffers
	288	* (at tx_buffer_area).
	289	* The index of the next available descriptor is next_avail_tx_desc.
	290	* The number of remaining tx_desc is num_tx_desc_avail.
	291	*/
	292	struct e1000_tx_desc *tx_desc_base;
323e5ecd	293	struct emx_txbuf *tx_buf;
5330213c SZ	294	uint32_t next_avail_tx_desc;
	295	uint32_t next_tx_to_clean;
	296	int num_tx_desc_avail;
	297	int num_tx_desc;
	298	bus_dma_tag_t txtag; /* dma tag for tx */
	299	int spare_tx_desc;
	300	int oact_tx_desc;
	301
	302	/* Saved csum offloading context information */
	303	int csum_flags;
3eb0ea09	304	int csum_lhlen;
5330213c	305	int csum_iphlen;
3eb0ea09 SZ	306
	307	int csum_thlen; /* TSO */
	308	int csum_mss; /* TSO */
	309	int csum_pktlen; /* TSO */
	310
5330213c SZ	311	uint32_t csum_txd_upper;
	312	uint32_t csum_txd_lower;
	313
	314	/*
	315	* Variables used to reduce TX interrupt rate and
	316	* number of device's TX ring write requests.
	317	*
	318	* tx_nsegs:
	319	* Number of TX descriptors setup so far.
	320	*
	321	* tx_int_nsegs:
	322	* Once tx_nsegs > tx_int_nsegs, RS bit will be set
	323	* in the last TX descriptor of the packet, and
	324	* tx_nsegs will be reset to 0. So TX interrupt and
	325	* TX ring write request should be generated roughly
	326	* every tx_int_nsegs TX descriptors.
	327	*
	328	* tx_dd[]:
	329	* Index of the TX descriptors which have RS bit set,
	330	* i.e. DD bit will be set on this TX descriptor after
	331	* the data of the TX descriptor are transfered to
	332	* hardware's internal packet buffer. Only the TX
	333	* descriptors listed in tx_dd[] will be checked upon
	334	* TX interrupt. This array is used as circular ring.
	335	*
	336	* tx_dd_tail, tx_dd_head:
	337	* Tail and head index of valid elements in tx_dd[].
	338	* tx_dd_tail == tx_dd_head means there is no valid
	339	* elements in tx_dd[]. tx_dd_tail points to the position
	340	* which is one beyond the last valid element in tx_dd[].
	341	* tx_dd_head points to the first valid element in
	342	* tx_dd[].
	343	*/
	344	int tx_int_nsegs;
	345	int tx_nsegs;
	346	int tx_dd_tail;
	347	int tx_dd_head;
	348	#define EMX_TXDD_MAX 64
	349	#define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
	350	int tx_dd[EMX_TXDD_MAX];
	351
13890b61 SZ	352	int rss_debug;
13890b61 SZ	353	int rx_ring_cnt;
c39e3a1f	354	struct emx_rxdata rx_data[EMX_NRX_RING];
5330213c SZ	355
	356	/* Misc stats maintained by the driver */
	357	unsigned long dropped_pkts;
	358	unsigned long mbuf_alloc_failed;
5330213c SZ	359	unsigned long no_tx_desc_avail1;
	360	unsigned long no_tx_desc_avail2;
	361	unsigned long no_tx_map_avail;
	362	unsigned long no_tx_dma_setup;
	363	unsigned long watchdog_events;
	364	unsigned long rx_overruns;
	365	unsigned long rx_irq;
	366	unsigned long tx_irq;
	367	unsigned long link_irq;
0c0e1638 SZ	368	unsigned long tso_segments;
0c0e1638 SZ	369	unsigned long tso_ctx_reused;
5330213c SZ	370
	371	/* sysctl tree glue */
	372	struct sysctl_ctx_list sysctl_ctx;
	373	struct sysctl_oid *sysctl_tree;
	374
	375	struct e1000_hw_stats stats;
	376	};
	377
323e5ecd	378	struct emx_txbuf {
5330213c SZ	379	struct mbuf *m_head;
	380	bus_dmamap_t map;
	381	};
	382
323e5ecd SZ	383	struct emx_rxbuf {
	384	struct mbuf *m_head;
	385	bus_dmamap_t map;
	386	bus_addr_t paddr;
	387	};
	388
5330213c SZ	389	#define EMX_IS_OACTIVE(sc) ((sc)->num_tx_desc_avail <= (sc)->oact_tx_desc)
	390
	391	#define EMX_INC_TXDD_IDX(idx) \
	392	do { \
	393	if (++(idx) == EMX_TXDD_MAX) \
	394	(idx) = 0; \
	395	} while (0)
	396
	397	#endif /* !_IF_EMX_H_ */