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kernel - Misc fixes and debugging
[dragonfly.git] / sys / platform / pc32 / i386 / exception.s
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984263bc
MD		 1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/i386/i386/exception.s,v 1.65.2.3 2001/08/15 01:23:49 peter Exp $
c885c20e 34 * $DragonFly: src/sys/platform/pc32/i386/exception.s,v 1.32 2008/05/08 01:21:04 dillon Exp $
984263bc
MD		 35 */
36
1f2de5d4 37#include "use_npx.h"
984263bc
MD		 38
39#include <machine/asmacros.h>
bdc560a1 40#include <machine/segments.h>
984263bc
MD		 41#include <machine/lock.h>
42#include <machine/psl.h>
43#include <machine/trap.h>
984263bc
MD		 44
45#include "assym.s"
46
984263bc
MD		 47 .text
48
cc9b6223
MD		 49 .globl lwkt_switch_return
50
f7bc9806
MD		 51#ifdef DEBUG_INTERRUPTS
52 .globl Xrsvdary
53
54Xrsvdary:
55 .long Xrsvd0
56 .long Xrsvd1 , Xrsvd2 , Xrsvd3 , Xrsvd4 , Xrsvd5 , Xrsvd6 , Xrsvd7 , Xrsvd8
57 .long Xrsvd9 , Xrsvd10 , Xrsvd11 , Xrsvd12 , Xrsvd13 , Xrsvd14 , Xrsvd15 , Xrsvd16
58 .long Xrsvd17 , Xrsvd18 , Xrsvd19 , Xrsvd20 , Xrsvd21 , Xrsvd22 , Xrsvd23 , Xrsvd24
59 .long Xrsvd25 , Xrsvd26 , Xrsvd27 , Xrsvd28 , Xrsvd29 , Xrsvd30 , Xrsvd31 , Xrsvd32
60 .long Xrsvd33 , Xrsvd34 , Xrsvd35 , Xrsvd36 , Xrsvd37 , Xrsvd38 , Xrsvd39 , Xrsvd40
61 .long Xrsvd41 , Xrsvd42 , Xrsvd43 , Xrsvd44 , Xrsvd45 , Xrsvd46 , Xrsvd47 , Xrsvd48
62 .long Xrsvd49 , Xrsvd50 , Xrsvd51 , Xrsvd52 , Xrsvd53 , Xrsvd54 , Xrsvd55 , Xrsvd56
63 .long Xrsvd57 , Xrsvd58 , Xrsvd59 , Xrsvd60 , Xrsvd61 , Xrsvd62 , Xrsvd63 , Xrsvd64
64 .long Xrsvd65 , Xrsvd66 , Xrsvd67 , Xrsvd68 , Xrsvd69 , Xrsvd70 , Xrsvd71 , Xrsvd72
65 .long Xrsvd73 , Xrsvd74 , Xrsvd75 , Xrsvd76 , Xrsvd77 , Xrsvd78 , Xrsvd79 , Xrsvd80
66 .long Xrsvd81 , Xrsvd82 , Xrsvd83 , Xrsvd84 , Xrsvd85 , Xrsvd86 , Xrsvd87 , Xrsvd88
67 .long Xrsvd89 , Xrsvd90 , Xrsvd91 , Xrsvd92 , Xrsvd93 , Xrsvd94 , Xrsvd95 , Xrsvd96
68 .long Xrsvd97 , Xrsvd98 , Xrsvd99 , Xrsvd100, Xrsvd101, Xrsvd102, Xrsvd103, Xrsvd104
69 .long Xrsvd105, Xrsvd106, Xrsvd107, Xrsvd108, Xrsvd109, Xrsvd110, Xrsvd111, Xrsvd112
70 .long Xrsvd113, Xrsvd114, Xrsvd115, Xrsvd116, Xrsvd117, Xrsvd118, Xrsvd119, Xrsvd120
71 .long Xrsvd121, Xrsvd122, Xrsvd123, Xrsvd124, Xrsvd125, Xrsvd126, Xrsvd127, Xrsvd128
72 .long Xrsvd129, Xrsvd130, Xrsvd131, Xrsvd132, Xrsvd133, Xrsvd134, Xrsvd135, Xrsvd136
73 .long Xrsvd137, Xrsvd138, Xrsvd139, Xrsvd140, Xrsvd141, Xrsvd142, Xrsvd143, Xrsvd144
74 .long Xrsvd145, Xrsvd146, Xrsvd147, Xrsvd148, Xrsvd149, Xrsvd150, Xrsvd151, Xrsvd152
75 .long Xrsvd153, Xrsvd154, Xrsvd155, Xrsvd156, Xrsvd157, Xrsvd158, Xrsvd159, Xrsvd160
76 .long Xrsvd161, Xrsvd162, Xrsvd163, Xrsvd164, Xrsvd165, Xrsvd166, Xrsvd167, Xrsvd168
77 .long Xrsvd169, Xrsvd170, Xrsvd171, Xrsvd172, Xrsvd173, Xrsvd174, Xrsvd175, Xrsvd176
78 .long Xrsvd177, Xrsvd178, Xrsvd179, Xrsvd180, Xrsvd181, Xrsvd182, Xrsvd183, Xrsvd184
79 .long Xrsvd185, Xrsvd186, Xrsvd187, Xrsvd188, Xrsvd189, Xrsvd190, Xrsvd191, Xrsvd192
80 .long Xrsvd193, Xrsvd194, Xrsvd195, Xrsvd196, Xrsvd197, Xrsvd198, Xrsvd199, Xrsvd200
81 .long Xrsvd201, Xrsvd202, Xrsvd203, Xrsvd204, Xrsvd205, Xrsvd206, Xrsvd207, Xrsvd208
82 .long Xrsvd209, Xrsvd210, Xrsvd211, Xrsvd212, Xrsvd213, Xrsvd214, Xrsvd215, Xrsvd216
83 .long Xrsvd217, Xrsvd218, Xrsvd219, Xrsvd220, Xrsvd221, Xrsvd222, Xrsvd223, Xrsvd224
84 .long Xrsvd225, Xrsvd226, Xrsvd227, Xrsvd228, Xrsvd229, Xrsvd230, Xrsvd231, Xrsvd232
85 .long Xrsvd233, Xrsvd234, Xrsvd235, Xrsvd236, Xrsvd237, Xrsvd238, Xrsvd239, Xrsvd240
86 .long Xrsvd241, Xrsvd242, Xrsvd243, Xrsvd244, Xrsvd245, Xrsvd246, Xrsvd247, Xrsvd248
87 .long Xrsvd249, Xrsvd250, Xrsvd251, Xrsvd252, Xrsvd253, Xrsvd254, Xrsvd255
88
89#endif
90
984263bc
MD		 91/*****************************************************************************/
92/* Trap handling */
93/*****************************************************************************/
94/*
95 * Trap and fault vector routines.
96 *
97 * Most traps are 'trap gates', SDT_SYS386TGT. A trap gate pushes state on
98 * the stack that mostly looks like an interrupt, but does not disable
99 * interrupts. A few of the traps we are use are interrupt gates,
100 * SDT_SYS386IGT, which are nearly the same thing except interrupts are
101 * disabled on entry.
102 *
103 * The cpu will push a certain amount of state onto the kernel stack for
104 * the current process. The amount of state depends on the type of trap
105 * and whether the trap crossed rings or not. See i386/include/frame.h.
106 * At the very least the current EFLAGS (status register, which includes
107 * the interrupt disable state prior to the trap), the code segment register,
108 * and the return instruction pointer are pushed by the cpu. The cpu
109 * will also push an 'error' code for certain traps. We push a dummy
110 * error code for those traps where the cpu doesn't in order to maintain
111 * a consistent frame. We also push a contrived 'trap number'.
112 *
113 * The cpu does not push the general registers, we must do that, and we
114 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
4e7c41c5
MD		 115 * %ss segment registers, but does not mess with %ds, %es, %fs, or %gs.
116 * Thus we must load the ones we use (which is most of them) with appropriate
117 * values for supervisor mode operation.
984263bc
MD		 118 *
119 * On entry to a trap or interrupt WE DO NOT OWN THE MP LOCK. This means
120 * that we must be careful in regards to accessing global variables. We
121 * save (push) the current cpl (our software interrupt disable mask), call
2954c92f
MD		 122 * the trap function, then jump to doreti to restore the cpl and deal with
123 * ASTs (software interrupts). doreti will determine if the restoration
984263bc
MD		 124 * of the cpl unmasked any pending interrupts and will issue those interrupts
125 * synchronously prior to doing the iret.
984263bc 126 */
bdc560a1 127
2954c92f 128#define TRAP(a) pushl $(a) ; jmp alltraps
984263bc
MD		 129
130#ifdef BDE_DEBUGGER
131#define BDBTRAP(name) \
132 ss ; \
2954c92f 133 cmpb $0,bdb_exists ; \
984263bc
MD		 134 je 1f ; \
135 testb $SEL_RPL_MASK,4(%esp) ; \
136 jne 1f ; \
137 ss ; \
138 .globl __CONCAT(__CONCAT(bdb_,name),_ljmp); \
139__CONCAT(__CONCAT(bdb_,name),_ljmp): \
140 ljmp $0,$0 ; \
1411:
142#else
143#define BDBTRAP(name)
144#endif
145
146#define BPTTRAP(a) testl $PSL_I,4+8(%esp) ; je 1f ; sti ; 1: ; TRAP(a)
147
148MCOUNT_LABEL(user)
149MCOUNT_LABEL(btrap)
150
151IDTVEC(div)
152 pushl $0; TRAP(T_DIVIDE)
153IDTVEC(dbg)
154 BDBTRAP(dbg)
155 pushl $0; BPTTRAP(T_TRCTRAP)
156IDTVEC(nmi)
157 pushl $0; TRAP(T_NMI)
158IDTVEC(bpt)
159 BDBTRAP(bpt)
160 pushl $0; BPTTRAP(T_BPTFLT)
161IDTVEC(ofl)
162 pushl $0; TRAP(T_OFLOW)
163IDTVEC(bnd)
164 pushl $0; TRAP(T_BOUND)
165IDTVEC(ill)
166 pushl $0; TRAP(T_PRIVINFLT)
167IDTVEC(dna)
168 pushl $0; TRAP(T_DNA)
169IDTVEC(fpusegm)
170 pushl $0; TRAP(T_FPOPFLT)
171IDTVEC(tss)
172 TRAP(T_TSSFLT)
173IDTVEC(missing)
174 TRAP(T_SEGNPFLT)
175IDTVEC(stk)
176 TRAP(T_STKFLT)
177IDTVEC(prot)
178 TRAP(T_PROTFLT)
179IDTVEC(page)
180 TRAP(T_PAGEFLT)
181IDTVEC(mchk)
182 pushl $0; TRAP(T_MCHK)
f7bc9806
MD		 183
184IDTVEC(rsvd0)
984263bc
MD		 185 pushl $0; TRAP(T_RESERVED)
186
f7bc9806
MD		 187#ifdef DEBUG_INTERRUPTS
188
189IDTVEC(rsvd1)
190 pushl $1; TRAP(T_RESERVED)
191IDTVEC(rsvd2)
192 pushl $2; TRAP(T_RESERVED)
193IDTVEC(rsvd3)
194 pushl $3; TRAP(T_RESERVED)
195IDTVEC(rsvd4)
196 pushl $4; TRAP(T_RESERVED)
197IDTVEC(rsvd5)
198 pushl $5; TRAP(T_RESERVED)
199IDTVEC(rsvd6)
200 pushl $6; TRAP(T_RESERVED)
201IDTVEC(rsvd7)
202 pushl $7; TRAP(T_RESERVED)
203IDTVEC(rsvd8)
204 pushl $8; TRAP(T_RESERVED)
205IDTVEC(rsvd9)
206 pushl $9; TRAP(T_RESERVED)
207IDTVEC(rsvd10)
208 pushl $10; TRAP(T_RESERVED)
209IDTVEC(rsvd11)
210 pushl $11; TRAP(T_RESERVED)
211IDTVEC(rsvd12)
212 pushl $12; TRAP(T_RESERVED)
213IDTVEC(rsvd13)
214 pushl $13; TRAP(T_RESERVED)
215IDTVEC(rsvd14)
216 pushl $14; TRAP(T_RESERVED)
217IDTVEC(rsvd15)
218 pushl $15; TRAP(T_RESERVED)
219IDTVEC(rsvd16)
220 pushl $16; TRAP(T_RESERVED)
221IDTVEC(rsvd17)
222 pushl $17; TRAP(T_RESERVED)
223IDTVEC(rsvd18)
224 pushl $18; TRAP(T_RESERVED)
225IDTVEC(rsvd19)
226 pushl $19; TRAP(T_RESERVED)
227IDTVEC(rsvd20)
228 pushl $20; TRAP(T_RESERVED)
229IDTVEC(rsvd21)
230 pushl $21; TRAP(T_RESERVED)
231IDTVEC(rsvd22)
232 pushl $22; TRAP(T_RESERVED)
233IDTVEC(rsvd23)
234 pushl $23; TRAP(T_RESERVED)
235IDTVEC(rsvd24)
236 pushl $24; TRAP(T_RESERVED)
237IDTVEC(rsvd25)
238 pushl $25; TRAP(T_RESERVED)
239IDTVEC(rsvd26)
240 pushl $26; TRAP(T_RESERVED)
241IDTVEC(rsvd27)
242 pushl $27; TRAP(T_RESERVED)
243IDTVEC(rsvd28)
244 pushl $28; TRAP(T_RESERVED)
245IDTVEC(rsvd29)
246 pushl $29; TRAP(T_RESERVED)
247IDTVEC(rsvd30)
248 pushl $30; TRAP(T_RESERVED)
249IDTVEC(rsvd31)
250 pushl $31; TRAP(T_RESERVED)
251IDTVEC(rsvd32)
252 pushl $32; TRAP(T_RESERVED)
253IDTVEC(rsvd33)
254 pushl $33; TRAP(T_RESERVED)
255IDTVEC(rsvd34)
256 pushl $34; TRAP(T_RESERVED)
257IDTVEC(rsvd35)
258 pushl $35; TRAP(T_RESERVED)
259IDTVEC(rsvd36)
260 pushl $36; TRAP(T_RESERVED)
261IDTVEC(rsvd37)
262 pushl $37; TRAP(T_RESERVED)
263IDTVEC(rsvd38)
264 pushl $38; TRAP(T_RESERVED)
265IDTVEC(rsvd39)
266 pushl $39; TRAP(T_RESERVED)
267IDTVEC(rsvd40)
268 pushl $40; TRAP(T_RESERVED)
269IDTVEC(rsvd41)
270 pushl $41; TRAP(T_RESERVED)
271IDTVEC(rsvd42)
272 pushl $42; TRAP(T_RESERVED)
273IDTVEC(rsvd43)
274 pushl $43; TRAP(T_RESERVED)
275IDTVEC(rsvd44)
276 pushl $44; TRAP(T_RESERVED)
277IDTVEC(rsvd45)
278 pushl $45; TRAP(T_RESERVED)
279IDTVEC(rsvd46)
280 pushl $46; TRAP(T_RESERVED)
281IDTVEC(rsvd47)
282 pushl $47; TRAP(T_RESERVED)
283IDTVEC(rsvd48)
284 pushl $48; TRAP(T_RESERVED)
285IDTVEC(rsvd49)
286 pushl $49; TRAP(T_RESERVED)
287IDTVEC(rsvd50)
288 pushl $50; TRAP(T_RESERVED)
289IDTVEC(rsvd51)
290 pushl $51; TRAP(T_RESERVED)
291IDTVEC(rsvd52)
292 pushl $52; TRAP(T_RESERVED)
293IDTVEC(rsvd53)
294 pushl $53; TRAP(T_RESERVED)
295IDTVEC(rsvd54)
296 pushl $54; TRAP(T_RESERVED)
297IDTVEC(rsvd55)
298 pushl $55; TRAP(T_RESERVED)
299IDTVEC(rsvd56)
300 pushl $56; TRAP(T_RESERVED)
301IDTVEC(rsvd57)
302 pushl $57; TRAP(T_RESERVED)
303IDTVEC(rsvd58)
304 pushl $58; TRAP(T_RESERVED)
305IDTVEC(rsvd59)
306 pushl $59; TRAP(T_RESERVED)
307IDTVEC(rsvd60)
308 pushl $60; TRAP(T_RESERVED)
309IDTVEC(rsvd61)
310 pushl $61; TRAP(T_RESERVED)
311IDTVEC(rsvd62)
312 pushl $62; TRAP(T_RESERVED)
313IDTVEC(rsvd63)
314 pushl $63; TRAP(T_RESERVED)
315IDTVEC(rsvd64)
316 pushl $64; TRAP(T_RESERVED)
317IDTVEC(rsvd65)
318 pushl $65; TRAP(T_RESERVED)
319IDTVEC(rsvd66)
320 pushl $66; TRAP(T_RESERVED)
321IDTVEC(rsvd67)
322 pushl $67; TRAP(T_RESERVED)
323IDTVEC(rsvd68)
324 pushl $68; TRAP(T_RESERVED)
325IDTVEC(rsvd69)
326 pushl $69; TRAP(T_RESERVED)
327IDTVEC(rsvd70)
328 pushl $70; TRAP(T_RESERVED)
329IDTVEC(rsvd71)
330 pushl $71; TRAP(T_RESERVED)
331IDTVEC(rsvd72)
332 pushl $72; TRAP(T_RESERVED)
333IDTVEC(rsvd73)
334 pushl $73; TRAP(T_RESERVED)
335IDTVEC(rsvd74)
336 pushl $74; TRAP(T_RESERVED)
337IDTVEC(rsvd75)
338 pushl $75; TRAP(T_RESERVED)
339IDTVEC(rsvd76)
340 pushl $76; TRAP(T_RESERVED)
341IDTVEC(rsvd77)
342 pushl $77; TRAP(T_RESERVED)
343IDTVEC(rsvd78)
344 pushl $78; TRAP(T_RESERVED)
345IDTVEC(rsvd79)
346 pushl $79; TRAP(T_RESERVED)
347IDTVEC(rsvd80)
348 pushl $80; TRAP(T_RESERVED)
349IDTVEC(rsvd81)
350 pushl $81; TRAP(T_RESERVED)
351IDTVEC(rsvd82)
352 pushl $82; TRAP(T_RESERVED)
353IDTVEC(rsvd83)
354 pushl $83; TRAP(T_RESERVED)
355IDTVEC(rsvd84)
356 pushl $84; TRAP(T_RESERVED)
357IDTVEC(rsvd85)
358 pushl $85; TRAP(T_RESERVED)
359IDTVEC(rsvd86)
360 pushl $86; TRAP(T_RESERVED)
361IDTVEC(rsvd87)
362 pushl $87; TRAP(T_RESERVED)
363IDTVEC(rsvd88)
364 pushl $88; TRAP(T_RESERVED)
365IDTVEC(rsvd89)
366 pushl $89; TRAP(T_RESERVED)
367IDTVEC(rsvd90)
368 pushl $90; TRAP(T_RESERVED)
369IDTVEC(rsvd91)
370 pushl $91; TRAP(T_RESERVED)
371IDTVEC(rsvd92)
372 pushl $92; TRAP(T_RESERVED)
373IDTVEC(rsvd93)
374 pushl $93; TRAP(T_RESERVED)
375IDTVEC(rsvd94)
376 pushl $94; TRAP(T_RESERVED)
377IDTVEC(rsvd95)
378 pushl $95; TRAP(T_RESERVED)
379IDTVEC(rsvd96)
380 pushl $96; TRAP(T_RESERVED)
381IDTVEC(rsvd97)
382 pushl $97; TRAP(T_RESERVED)
383IDTVEC(rsvd98)
384 pushl $98; TRAP(T_RESERVED)
385IDTVEC(rsvd99)
386 pushl $99; TRAP(T_RESERVED)
387IDTVEC(rsvd100)
388 pushl $100; TRAP(T_RESERVED)
389IDTVEC(rsvd101)
390 pushl $101; TRAP(T_RESERVED)
391IDTVEC(rsvd102)
392 pushl $102; TRAP(T_RESERVED)
393IDTVEC(rsvd103)
394 pushl $103; TRAP(T_RESERVED)
395IDTVEC(rsvd104)
396 pushl $104; TRAP(T_RESERVED)
397IDTVEC(rsvd105)
398 pushl $105; TRAP(T_RESERVED)
399IDTVEC(rsvd106)
400 pushl $106; TRAP(T_RESERVED)
401IDTVEC(rsvd107)
402 pushl $107; TRAP(T_RESERVED)
403IDTVEC(rsvd108)
404 pushl $108; TRAP(T_RESERVED)
405IDTVEC(rsvd109)
406 pushl $109; TRAP(T_RESERVED)
407IDTVEC(rsvd110)
408 pushl $110; TRAP(T_RESERVED)
409IDTVEC(rsvd111)
410 pushl $111; TRAP(T_RESERVED)
411IDTVEC(rsvd112)
412 pushl $112; TRAP(T_RESERVED)
413IDTVEC(rsvd113)
414 pushl $113; TRAP(T_RESERVED)
415IDTVEC(rsvd114)
416 pushl $114; TRAP(T_RESERVED)
417IDTVEC(rsvd115)
418 pushl $115; TRAP(T_RESERVED)
419IDTVEC(rsvd116)
420 pushl $116; TRAP(T_RESERVED)
421IDTVEC(rsvd117)
422 pushl $117; TRAP(T_RESERVED)
423IDTVEC(rsvd118)
424 pushl $118; TRAP(T_RESERVED)
425IDTVEC(rsvd119)
426 pushl $119; TRAP(T_RESERVED)
427IDTVEC(rsvd120)
428 pushl $120; TRAP(T_RESERVED)
429IDTVEC(rsvd121)
430 pushl $121; TRAP(T_RESERVED)
431IDTVEC(rsvd122)
432 pushl $122; TRAP(T_RESERVED)
433IDTVEC(rsvd123)
434 pushl $123; TRAP(T_RESERVED)
435IDTVEC(rsvd124)
436 pushl $124; TRAP(T_RESERVED)
437IDTVEC(rsvd125)
438 pushl $125; TRAP(T_RESERVED)
439IDTVEC(rsvd126)
440 pushl $126; TRAP(T_RESERVED)
441IDTVEC(rsvd127)
442 pushl $127; TRAP(T_RESERVED)
443IDTVEC(rsvd128)
444 pushl $128; TRAP(T_RESERVED)
445IDTVEC(rsvd129)
446 pushl $129; TRAP(T_RESERVED)
447IDTVEC(rsvd130)
448 pushl $130; TRAP(T_RESERVED)
449IDTVEC(rsvd131)
450 pushl $131; TRAP(T_RESERVED)
451IDTVEC(rsvd132)
452 pushl $132; TRAP(T_RESERVED)
453IDTVEC(rsvd133)
454 pushl $133; TRAP(T_RESERVED)
455IDTVEC(rsvd134)
456 pushl $134; TRAP(T_RESERVED)
457IDTVEC(rsvd135)
458 pushl $135; TRAP(T_RESERVED)
459IDTVEC(rsvd136)
460 pushl $136; TRAP(T_RESERVED)
461IDTVEC(rsvd137)
462 pushl $137; TRAP(T_RESERVED)
463IDTVEC(rsvd138)
464 pushl $138; TRAP(T_RESERVED)
465IDTVEC(rsvd139)
466 pushl $139; TRAP(T_RESERVED)
467IDTVEC(rsvd140)
468 pushl $140; TRAP(T_RESERVED)
469IDTVEC(rsvd141)
470 pushl $141; TRAP(T_RESERVED)
471IDTVEC(rsvd142)
472 pushl $142; TRAP(T_RESERVED)
473IDTVEC(rsvd143)
474 pushl $143; TRAP(T_RESERVED)
475IDTVEC(rsvd144)
476 pushl $144; TRAP(T_RESERVED)
477IDTVEC(rsvd145)
478 pushl $145; TRAP(T_RESERVED)
479IDTVEC(rsvd146)
480 pushl $146; TRAP(T_RESERVED)
481IDTVEC(rsvd147)
482 pushl $147; TRAP(T_RESERVED)
483IDTVEC(rsvd148)
484 pushl $148; TRAP(T_RESERVED)
485IDTVEC(rsvd149)
486 pushl $149; TRAP(T_RESERVED)
487IDTVEC(rsvd150)
488 pushl $150; TRAP(T_RESERVED)
489IDTVEC(rsvd151)
490 pushl $151; TRAP(T_RESERVED)
491IDTVEC(rsvd152)
492 pushl $152; TRAP(T_RESERVED)
493IDTVEC(rsvd153)
494 pushl $153; TRAP(T_RESERVED)
495IDTVEC(rsvd154)
496 pushl $154; TRAP(T_RESERVED)
497IDTVEC(rsvd155)
498 pushl $155; TRAP(T_RESERVED)
499IDTVEC(rsvd156)
500 pushl $156; TRAP(T_RESERVED)
501IDTVEC(rsvd157)
502 pushl $157; TRAP(T_RESERVED)
503IDTVEC(rsvd158)
504 pushl $158; TRAP(T_RESERVED)
505IDTVEC(rsvd159)
506 pushl $159; TRAP(T_RESERVED)
507IDTVEC(rsvd160)
508 pushl $160; TRAP(T_RESERVED)
509IDTVEC(rsvd161)
510 pushl $161; TRAP(T_RESERVED)
511IDTVEC(rsvd162)
512 pushl $162; TRAP(T_RESERVED)
513IDTVEC(rsvd163)
514 pushl $163; TRAP(T_RESERVED)
515IDTVEC(rsvd164)
516 pushl $164; TRAP(T_RESERVED)
517IDTVEC(rsvd165)
518 pushl $165; TRAP(T_RESERVED)
519IDTVEC(rsvd166)
520 pushl $166; TRAP(T_RESERVED)
521IDTVEC(rsvd167)
522 pushl $167; TRAP(T_RESERVED)
523IDTVEC(rsvd168)
524 pushl $168; TRAP(T_RESERVED)
525IDTVEC(rsvd169)
526 pushl $169; TRAP(T_RESERVED)
527IDTVEC(rsvd170)
528 pushl $170; TRAP(T_RESERVED)
529IDTVEC(rsvd171)
530 pushl $171; TRAP(T_RESERVED)
531IDTVEC(rsvd172)
532 pushl $172; TRAP(T_RESERVED)
533IDTVEC(rsvd173)
534 pushl $173; TRAP(T_RESERVED)
535IDTVEC(rsvd174)
536 pushl $174; TRAP(T_RESERVED)
537IDTVEC(rsvd175)
538 pushl $175; TRAP(T_RESERVED)
539IDTVEC(rsvd176)
540 pushl $176; TRAP(T_RESERVED)
541IDTVEC(rsvd177)
542 pushl $177; TRAP(T_RESERVED)
543IDTVEC(rsvd178)
544 pushl $178; TRAP(T_RESERVED)
545IDTVEC(rsvd179)
546 pushl $179; TRAP(T_RESERVED)
547IDTVEC(rsvd180)
548 pushl $180; TRAP(T_RESERVED)
549IDTVEC(rsvd181)
550 pushl $181; TRAP(T_RESERVED)
551IDTVEC(rsvd182)
552 pushl $182; TRAP(T_RESERVED)
553IDTVEC(rsvd183)
554 pushl $183; TRAP(T_RESERVED)
555IDTVEC(rsvd184)
556 pushl $184; TRAP(T_RESERVED)
557IDTVEC(rsvd185)
558 pushl $185; TRAP(T_RESERVED)
559IDTVEC(rsvd186)
560 pushl $186; TRAP(T_RESERVED)
561IDTVEC(rsvd187)
562 pushl $187; TRAP(T_RESERVED)
563IDTVEC(rsvd188)
564 pushl $188; TRAP(T_RESERVED)
565IDTVEC(rsvd189)
566 pushl $189; TRAP(T_RESERVED)
567IDTVEC(rsvd190)
568 pushl $190; TRAP(T_RESERVED)
569IDTVEC(rsvd191)
570 pushl $191; TRAP(T_RESERVED)
571IDTVEC(rsvd192)
572 pushl $192; TRAP(T_RESERVED)
573IDTVEC(rsvd193)
574 pushl $193; TRAP(T_RESERVED)
575IDTVEC(rsvd194)
576 pushl $194; TRAP(T_RESERVED)
577IDTVEC(rsvd195)
578 pushl $195; TRAP(T_RESERVED)
579IDTVEC(rsvd196)
580 pushl $196; TRAP(T_RESERVED)
581IDTVEC(rsvd197)
582 pushl $197; TRAP(T_RESERVED)
583IDTVEC(rsvd198)
584 pushl $198; TRAP(T_RESERVED)
585IDTVEC(rsvd199)
586 pushl $199; TRAP(T_RESERVED)
587IDTVEC(rsvd200)
588 pushl $200; TRAP(T_RESERVED)
589IDTVEC(rsvd201)
590 pushl $201; TRAP(T_RESERVED)
591IDTVEC(rsvd202)
592 pushl $202; TRAP(T_RESERVED)
593IDTVEC(rsvd203)
594 pushl $203; TRAP(T_RESERVED)
595IDTVEC(rsvd204)
596 pushl $204; TRAP(T_RESERVED)
597IDTVEC(rsvd205)
598 pushl $205; TRAP(T_RESERVED)
599IDTVEC(rsvd206)
600 pushl $206; TRAP(T_RESERVED)
601IDTVEC(rsvd207)
602 pushl $207; TRAP(T_RESERVED)
603IDTVEC(rsvd208)
604 pushl $208; TRAP(T_RESERVED)
605IDTVEC(rsvd209)
606 pushl $209; TRAP(T_RESERVED)
607IDTVEC(rsvd210)
608 pushl $210; TRAP(T_RESERVED)
609IDTVEC(rsvd211)
610 pushl $211; TRAP(T_RESERVED)
611IDTVEC(rsvd212)
612 pushl $212; TRAP(T_RESERVED)
613IDTVEC(rsvd213)
614 pushl $213; TRAP(T_RESERVED)
615IDTVEC(rsvd214)
616 pushl $214; TRAP(T_RESERVED)
617IDTVEC(rsvd215)
618 pushl $215; TRAP(T_RESERVED)
619IDTVEC(rsvd216)
620 pushl $216; TRAP(T_RESERVED)
621IDTVEC(rsvd217)
622 pushl $217; TRAP(T_RESERVED)
623IDTVEC(rsvd218)
624 pushl $218; TRAP(T_RESERVED)
625IDTVEC(rsvd219)
626 pushl $219; TRAP(T_RESERVED)
627IDTVEC(rsvd220)
628 pushl $220; TRAP(T_RESERVED)
629IDTVEC(rsvd221)
630 pushl $221; TRAP(T_RESERVED)
631IDTVEC(rsvd222)
632 pushl $222; TRAP(T_RESERVED)
633IDTVEC(rsvd223)
634 pushl $223; TRAP(T_RESERVED)
635IDTVEC(rsvd224)
636 pushl $224; TRAP(T_RESERVED)
637IDTVEC(rsvd225)
638 pushl $225; TRAP(T_RESERVED)
639IDTVEC(rsvd226)
640 pushl $226; TRAP(T_RESERVED)
641IDTVEC(rsvd227)
642 pushl $227; TRAP(T_RESERVED)
643IDTVEC(rsvd228)
644 pushl $228; TRAP(T_RESERVED)
645IDTVEC(rsvd229)
646 pushl $229; TRAP(T_RESERVED)
647IDTVEC(rsvd230)
648 pushl $230; TRAP(T_RESERVED)
649IDTVEC(rsvd231)
650 pushl $231; TRAP(T_RESERVED)
651IDTVEC(rsvd232)
652 pushl $232; TRAP(T_RESERVED)
653IDTVEC(rsvd233)
654 pushl $233; TRAP(T_RESERVED)
655IDTVEC(rsvd234)
656 pushl $234; TRAP(T_RESERVED)
657IDTVEC(rsvd235)
658 pushl $235; TRAP(T_RESERVED)
659IDTVEC(rsvd236)
660 pushl $236; TRAP(T_RESERVED)
661IDTVEC(rsvd237)
662 pushl $237; TRAP(T_RESERVED)
663IDTVEC(rsvd238)
664 pushl $238; TRAP(T_RESERVED)
665IDTVEC(rsvd239)
666 pushl $239; TRAP(T_RESERVED)
667IDTVEC(rsvd240)
668 pushl $240; TRAP(T_RESERVED)
669IDTVEC(rsvd241)
670 pushl $241; TRAP(T_RESERVED)
671IDTVEC(rsvd242)
672 pushl $242; TRAP(T_RESERVED)
673IDTVEC(rsvd243)
674 pushl $243; TRAP(T_RESERVED)
675IDTVEC(rsvd244)
676 pushl $244; TRAP(T_RESERVED)
677IDTVEC(rsvd245)
678 pushl $245; TRAP(T_RESERVED)
679IDTVEC(rsvd246)
680 pushl $246; TRAP(T_RESERVED)
681IDTVEC(rsvd247)
682 pushl $247; TRAP(T_RESERVED)
683IDTVEC(rsvd248)
684 pushl $248; TRAP(T_RESERVED)
685IDTVEC(rsvd249)
686 pushl $249; TRAP(T_RESERVED)
687IDTVEC(rsvd250)
688 pushl $250; TRAP(T_RESERVED)
689IDTVEC(rsvd251)
690 pushl $251; TRAP(T_RESERVED)
691IDTVEC(rsvd252)
692 pushl $252; TRAP(T_RESERVED)
693IDTVEC(rsvd253)
694 pushl $253; TRAP(T_RESERVED)
695IDTVEC(rsvd254)
696 pushl $254; TRAP(T_RESERVED)
697IDTVEC(rsvd255)
698 pushl $255; TRAP(T_RESERVED)
699
700#endif
701
984263bc
MD		 702IDTVEC(fpu)
703#if NNPX > 0
704 /*
705 * Handle like an interrupt (except for accounting) so that we can
706 * call npx_intr to clear the error. It would be better to handle
707 * npx interrupts as traps. Nested interrupts would probably have
708 * to be converted to ASTs.
4e7c41c5
MD		 709 *
710 * Convert everything to a full trapframe
984263bc
MD		 711 */
712 pushl $0 /* dummy error code */
713 pushl $0 /* dummy trap type */
4e7c41c5 714 pushl $0 /* dummy xflags */
984263bc
MD		 715 pushal
716 pushl %ds
4e7c41c5 717 pushl %es
984263bc 718 pushl %fs
4e7c41c5 719 pushl %gs
c885c20e 720 cld
984263bc
MD		 721 mov $KDSEL,%ax
722 mov %ax,%ds
723 mov %ax,%es
4e7c41c5 724 mov %ax,%gs
12e4aaff 725 mov $KPSEL,%ax
984263bc 726 mov %ax,%fs
4e7c41c5 727 FAKE_MCOUNT(15*4(%esp))
984263bc 728
12e4aaff 729 incl PCPU(cnt)+V_TRAP
984263bc 730
bc588e93
MD		 731 /* additional dummy pushes to fake an interrupt frame */
732 pushl $0 /* ppl */
733 pushl $0 /* vector */
734
735 /* warning, trap frame dummy arg, no extra reg pushes */
2954c92f 736 call npx_intr /* note: call might mess w/ argument */
984263bc 737
bc588e93
MD		 738 /* convert back to a trapframe for doreti */
739 addl $4,%esp
38787eef 740 movl $0,(%esp) /* DUMMY CPL FOR DORETI */
984263bc 741 MEXITCOUNT
2954c92f 742 jmp doreti
984263bc
MD		 743#else /* NNPX > 0 */
744 pushl $0; TRAP(T_ARITHTRAP)
745#endif /* NNPX > 0 */
746
747IDTVEC(align)
748 TRAP(T_ALIGNFLT)
749
750IDTVEC(xmm)
751 pushl $0; TRAP(T_XMMFLT)
752
753 /*
754 * _alltraps entry point. Interrupts are enabled if this was a trap
755 * gate (TGT), else disabled if this was an interrupt gate (IGT).
756 * Note that int0x80_syscall is a trap gate. Only page faults
757 * use an interrupt gate.
758 *
8a8d5d85 759 * Note that we are MP through to the call to trap().
984263bc
MD		 760 */
761
762 SUPERALIGN_TEXT
2954c92f
MD		 763 .globl alltraps
764 .type alltraps,@function
765alltraps:
4e7c41c5 766 pushl $0 /* xflags (inherits hardware err on pagefault) */
984263bc
MD		 767 pushal
768 pushl %ds
769 pushl %es
770 pushl %fs
4e7c41c5 771 pushl %gs
bdc560a1 772 .globl alltraps_with_regs_pushed
984263bc
MD		 773alltraps_with_regs_pushed:
774 mov $KDSEL,%ax
775 mov %ax,%ds
776 mov %ax,%es
4e7c41c5 777 mov %ax,%gs
12e4aaff 778 mov $KPSEL,%ax
984263bc 779 mov %ax,%fs
4e7c41c5 780 FAKE_MCOUNT(15*4(%esp))
984263bc 781calltrap:
2954c92f 782 FAKE_MCOUNT(btrap) /* init "from" _btrap -> calltrap */
96728c05 783 incl PCPU(cnt)+V_TRAP
bc588e93 784 /* warning, trap frame dummy arg, no extra reg pushes */
3338cc67 785 cld
c7eb0589 786 pushl %esp /* pass frame by reference */
2954c92f 787 call trap
c7eb0589 788 addl $4,%esp
984263bc
MD		 789
790 /*
2954c92f 791 * Return via doreti to handle ASTs. Have to change trap frame
984263bc
MD		 792 * to interrupt frame.
793 */
38787eef 794 pushl $0 /* DUMMY CPL FOR DORETI */
984263bc 795 MEXITCOUNT
2954c92f 796 jmp doreti
984263bc
MD		 797
798/*
799 * SYSCALL CALL GATE (old entry point for a.out binaries)
800 *
801 * The intersegment call has been set up to specify one dummy parameter.
802 *
803 * This leaves a place to put eflags so that the call frame can be
804 * converted to a trap frame. Note that the eflags is (semi-)bogusly
805 * pushed into (what will be) tf_err and then copied later into the
806 * final spot. It has to be done this way because esp can't be just
807 * temporarily altered for the pushfl - an interrupt might come in
808 * and clobber the saved cs/eip.
809 *
810 * We do not obtain the MP lock, but the call to syscall2 might. If it
811 * does it will release the lock prior to returning.
812 */
813 SUPERALIGN_TEXT
814IDTVEC(syscall)
815 pushfl /* save eflags in tf_err for now */
4e7c41c5
MD		 816 pushl $T_SYSCALL80 /* tf_trapno */
817 pushl $0 /* tf_xflags */
984263bc
MD		 818 pushal
819 pushl %ds
820 pushl %es
821 pushl %fs
4e7c41c5 822 pushl %gs
c885c20e 823 cld
984263bc
MD		 824 mov $KDSEL,%ax /* switch to kernel segments */
825 mov %ax,%ds
826 mov %ax,%es
4e7c41c5 827 mov %ax,%gs
12e4aaff 828 mov $KPSEL,%ax
984263bc
MD		 829 mov %ax,%fs
830 movl TF_ERR(%esp),%eax /* copy saved eflags to final spot */
831 movl %eax,TF_EFLAGS(%esp)
832 movl $7,TF_ERR(%esp) /* sizeof "lcall 7,0" */
4e7c41c5 833 FAKE_MCOUNT(15*4(%esp))
12e4aaff 834 incl PCPU(cnt)+V_SYSCALL /* YYY per-cpu */
bc588e93 835 /* warning, trap frame dummy arg, no extra reg pushes */
c7eb0589 836 push %esp /* pass frame by reference */
2954c92f 837 call syscall2
c7eb0589 838 addl $4,%esp
984263bc 839 MEXITCOUNT
235957ed
MD		 840 cli /* atomic reqflags interlock w/iret */
841 cmpl $0,PCPU(reqflags)
984263bc 842 je doreti_syscall_ret
984263bc 843 pushl $0 /* cpl to restore */
2954c92f 844 jmp doreti
984263bc
MD		 845
846/*
a64ba182 847 * Trap gate entry for FreeBSD ELF and Linux/NetBSD syscall (int 0x80)
984263bc
MD		 848 *
849 * Even though the name says 'int0x80', this is actually a TGT (trap gate)
850 * rather then an IGT (interrupt gate). Thus interrupts are enabled on
851 * entry just as they are for a normal syscall.
852 *
853 * We do not obtain the MP lock, but the call to syscall2 might. If it
854 * does it will release the lock prior to returning.
855 */
856 SUPERALIGN_TEXT
857IDTVEC(int0x80_syscall)
4e7c41c5
MD		 858 pushl $0 /* tf_err */
859 pushl $T_SYSCALL80 /* tf_trapno */
860 pushl $0 /* tf_xflags */
984263bc
MD		 861 pushal
862 pushl %ds
863 pushl %es
864 pushl %fs
4e7c41c5 865 pushl %gs
c885c20e 866 cld
984263bc
MD		 867 mov $KDSEL,%ax /* switch to kernel segments */
868 mov %ax,%ds
869 mov %ax,%es
4e7c41c5 870 mov %ax,%gs
12e4aaff 871 mov $KPSEL,%ax
984263bc
MD		 872 mov %ax,%fs
873 movl $2,TF_ERR(%esp) /* sizeof "int 0x80" */
4e7c41c5 874 FAKE_MCOUNT(15*4(%esp))
a64ba182 875 incl PCPU(cnt)+V_SYSCALL
bc588e93 876 /* warning, trap frame dummy arg, no extra reg pushes */
c7eb0589 877 push %esp /* pass frame by reference */
2954c92f 878 call syscall2
c7eb0589 879 addl $4,%esp
984263bc 880 MEXITCOUNT
235957ed
MD		 881 cli /* atomic reqflags interlock w/irq */
882 cmpl $0,PCPU(reqflags)
984263bc 883 je doreti_syscall_ret
984263bc 884 pushl $0 /* cpl to restore */
2954c92f 885 jmp doreti
984263bc 886
a64ba182 887/*
26a0694b 888 * This function is what cpu_heavy_restore jumps to after a new process
d9eea1a5
MD		 889 * is created. The LWKT subsystem switches while holding a critical
890 * section and we maintain that abstraction here (e.g. because
891 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
892 * it before calling the initial function (typically fork_return()) and/or
893 * returning to user mode.
8a8d5d85 894 *
2b0bd8aa
MD		 895 * The MP lock is not held at any point but the critcount is bumped
896 * on entry to prevent interruption of the trampoline at a bad point.
cc9b6223
MD		 897 *
898 * This is effectively what td->td_switch() returns to. It 'returns' the
899 * old thread in %eax and since this is not returning to a td->td_switch()
900 * call from lwkt_switch() we must handle the cleanup for the old thread
901 * by calling lwkt_switch_return().
902 *
903 * fork_trampoline(%eax:otd, %esi:func, %ebx:arg)
26a0694b 904 */
984263bc 905ENTRY(fork_trampoline)
cc9b6223
MD		 906 pushl %eax
907 call lwkt_switch_return
908 addl $4,%esp
2954c92f 909 movl PCPU(curthread),%eax
f9235b6d 910 decl TD_CRITCOUNT(%eax)
8ad65e08 911
984263bc
MD		 912 /*
913 * cpu_set_fork_handler intercepts this function call to
914 * have this call a non-return function to stay in kernel mode.
96728c05
MD		 915 *
916 * initproc has its own fork handler, start_init(), which DOES
917 * return.
c7eb0589
SS		 918 *
919 * The function (set in pcb_esi) gets passed two arguments,
920 * the primary parameter set in pcb_ebx and a pointer to the
921 * trapframe.
922 * void (func)(int arg, struct trapframe *frame);
984263bc 923 */
c7eb0589 924 pushl %esp /* pass frame by reference */
984263bc
MD		 925 pushl %ebx /* arg1 */
926 call *%esi /* function */
c7eb0589 927 addl $8,%esp
984263bc
MD		 928 /* cut from syscall */
929
d9eea1a5 930 sti
96728c05
MD		 931 call splz
932
984263bc 933 /*
2954c92f 934 * Return via doreti to handle ASTs.
984263bc
MD		 935 */
936 pushl $0 /* cpl to restore */
984263bc 937 MEXITCOUNT
2954c92f 938 jmp doreti
984263bc
MD		 939
940
941/*
2954c92f 942 * Include vm86 call routines, which want to call doreti.
984263bc 943 */
f8334305 944#include "vm86bios.s"
984263bc 945
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