identcpu.c: Add MOVBE feature string.
[dragonfly.git] / sys / platform / pc32 / i386 / identcpu.c
CommitLineData
984263bc 1/*
984263bc 2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
bb832add 3 * Copyright (c) 1992 Terrence R. Lambert.
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4 * Copyright (c) 1997 KATO Takenori.
5 * Copyright (c) 2001 Tamotsu Hattori.
6 * Copyright (c) 2001 Mitsuru IWASAKI.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 *
40 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
9e3d0133 42 * $DragonFly: src/sys/platform/pc32/i386/identcpu.c,v 1.24 2008/11/24 13:14:21 swildner Exp $
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43 */
44
45#include "opt_cpu.h"
46
47#include <sys/param.h>
48#include <sys/systm.h>
49#include <sys/kernel.h>
50#include <sys/sysctl.h>
11e9db57 51#include <sys/lock.h>
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52
53#include <machine/asmacros.h>
54#include <machine/clock.h>
55#include <machine/cputypes.h>
56#include <machine/segments.h>
57#include <machine/specialreg.h>
58#include <machine/md_var.h>
59
a9295349 60#include <machine_base/isa/intr_machdep.h>
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61
62#define IDENTBLUE_CYRIX486 0
63#define IDENTBLUE_IBMCPU 1
64#define IDENTBLUE_CYRIXM2 2
65
66/* XXX - should be in header file: */
67void printcpuinfo(void);
68void finishidentcpu(void);
69#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
70void enable_K5_wt_alloc(void);
71void enable_K6_wt_alloc(void);
72void enable_K6_2_wt_alloc(void);
73#endif
74void panicifcpuunsupported(void);
75
76static void identifycyrix(void);
77#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
78static void print_AMD_features(void);
79#endif
80static void print_AMD_info(void);
81static void print_AMD_assoc(int i);
82static void print_transmeta_info(void);
83static void setup_tmx86_longrun(void);
84
85int cpu_class = CPUCLASS_386;
86u_int cpu_exthigh; /* Highest arg to extended CPUID */
87u_int cyrix_did; /* Device ID of Cyrix CPU */
a9295349 88char machine[] = MACHINE;
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89SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
90 machine, 0, "Machine class");
91
92static char cpu_model[128];
93SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
94 cpu_model, 0, "Machine model");
95
96static char cpu_brand[48];
97
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98#define MAX_ADDITIONAL_INFO 16
99
100static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101static u_int additional_cpu_info_count;
102
aca8cb34 103#define MAX_BRAND_INDEX 23
984263bc 104
aca8cb34
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105/*
106 * Brand ID's according to Intel document AP-485, number 241618-31, published
107 * September 2006, page 42.
108 */
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109static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
110 NULL, /* No brand */
111 "Intel Celeron",
112 "Intel Pentium III",
113 "Intel Pentium III Xeon",
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114 "Intel Pentium III",
115 NULL, /* Unspecified */
116 "Mobile Intel Pentium III-M",
117 "Mobile Intel Celeron",
118 "Intel Pentium 4",
119 "Intel Pentium 4",
120 "Intel Celeron",
121 "Intel Xeon",
122 "Intel Xeon MP",
123 NULL, /* Unspecified */
124 "Mobile Intel Pentium 4-M",
125 "Mobile Intel Celeron",
126 NULL, /* Unspecified */
127 "Mobile Genuine Intel",
128 "Intel Celeron M",
129 "Mobile Intel Celeron",
130 "Intel Celeron",
131 "Mobile Genuine Intel",
132 "Intel Pentium M",
133 "Mobile Intel Celeron"
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134};
135
136static struct cpu_nameclass i386_cpus[] = {
137 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
138 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
139 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
140 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
141 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
142 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
143 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
144 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
145 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
146 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
147 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
148 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
149 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
150 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
151 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
152 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
153 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
154};
155
156#if defined(I586_CPU) && !defined(NO_F00F_HACK)
157int has_f00f_bug = 0; /* Initialized so that it can be patched. */
158#endif
159
160void
161printcpuinfo(void)
162{
163#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
164 u_int regs[4], i;
165#endif
166 char *brand;
167
168 cpu_class = i386_cpus[cpu].cpu_class;
26be20a0 169 kprintf("CPU: ");
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170 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
171
172#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
173 /* Check for extended CPUID information and a processor name. */
174 if (cpu_high > 0 &&
175 (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
176 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
177 strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
178 strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
179 do_cpuid(0x80000000, regs);
180 if (regs[0] >= 0x80000000) {
181 cpu_exthigh = regs[0];
182 if (cpu_exthigh >= 0x80000004) {
183 brand = cpu_brand;
184 for (i = 0x80000002; i < 0x80000005; i++) {
185 do_cpuid(i, regs);
186 memcpy(brand, regs, sizeof(regs));
187 brand += sizeof(regs);
188 }
189 }
190 }
191 }
192
193 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
194 if ((cpu_id & 0xf00) > 0x300) {
195 u_int brand_index;
196
197 cpu_model[0] = '\0';
198
199 switch (cpu_id & 0x3000) {
200 case 0x1000:
201 strcpy(cpu_model, "Overdrive ");
202 break;
203 case 0x2000:
204 strcpy(cpu_model, "Dual ");
205 break;
206 }
207
208 switch (cpu_id & 0xf00) {
209 case 0x400:
210 strcat(cpu_model, "i486 ");
211 /* Check the particular flavor of 486 */
212 switch (cpu_id & 0xf0) {
213 case 0x00:
214 case 0x10:
215 strcat(cpu_model, "DX");
216 break;
217 case 0x20:
218 strcat(cpu_model, "SX");
219 break;
220 case 0x30:
221 strcat(cpu_model, "DX2");
222 break;
223 case 0x40:
224 strcat(cpu_model, "SL");
225 break;
226 case 0x50:
227 strcat(cpu_model, "SX2");
228 break;
229 case 0x70:
230 strcat(cpu_model,
231 "DX2 Write-Back Enhanced");
232 break;
233 case 0x80:
234 strcat(cpu_model, "DX4");
235 break;
236 }
237 break;
238 case 0x500:
239 /* Check the particular flavor of 586 */
240 strcat(cpu_model, "Pentium");
241 switch (cpu_id & 0xf0) {
242 case 0x00:
243 strcat(cpu_model, " A-step");
244 break;
245 case 0x10:
246 strcat(cpu_model, "/P5");
247 break;
248 case 0x20:
249 strcat(cpu_model, "/P54C");
250 break;
251 case 0x30:
252 strcat(cpu_model, "/P54T Overdrive");
253 break;
254 case 0x40:
255 strcat(cpu_model, "/P55C");
256 break;
257 case 0x70:
258 strcat(cpu_model, "/P54C");
259 break;
260 case 0x80:
261 strcat(cpu_model, "/P55C (quarter-micron)");
262 break;
263 default:
264 /* nothing */
265 break;
266 }
267#if defined(I586_CPU) && !defined(NO_F00F_HACK)
268 /*
269 * XXX - If/when Intel fixes the bug, this
270 * should also check the version of the
271 * CPU, not just that it's a Pentium.
272 */
273 has_f00f_bug = 1;
274#endif
275 break;
276 case 0x600:
277 /* Check the particular flavor of 686 */
278 switch (cpu_id & 0xf0) {
279 case 0x00:
280 strcat(cpu_model, "Pentium Pro A-step");
281 break;
282 case 0x10:
283 strcat(cpu_model, "Pentium Pro");
284 break;
285 case 0x30:
286 case 0x50:
287 case 0x60:
288 strcat(cpu_model,
289 "Pentium II/Pentium II Xeon/Celeron");
290 cpu = CPU_PII;
291 break;
292 case 0x70:
293 case 0x80:
294 case 0xa0:
295 case 0xb0:
296 strcat(cpu_model,
297 "Pentium III/Pentium III Xeon/Celeron");
298 cpu = CPU_PIII;
299 break;
300 default:
301 strcat(cpu_model, "Unknown 80686");
302 break;
303 }
304 break;
305 case 0xf00:
306 strcat(cpu_model, "Pentium 4");
307 cpu = CPU_P4;
308 break;
309 default:
310 strcat(cpu_model, "unknown");
311 break;
312 }
313
314 /*
315 * If we didn't get a brand name from the extended
316 * CPUID, try to look it up in the brand table.
317 */
318 if (cpu_high > 0 && *cpu_brand == '\0') {
319 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
320 if (brand_index <= MAX_BRAND_INDEX &&
321 cpu_brandtable[brand_index] != NULL)
322 strcpy(cpu_brand,
323 cpu_brandtable[brand_index]);
324 }
325 }
326 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
327 /*
328 * Values taken from AMD Processor Recognition
329 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
330 * (also describes ``Features'' encodings.
331 */
332 strcpy(cpu_model, "AMD ");
333 switch (cpu_id & 0xFF0) {
334 case 0x410:
335 strcat(cpu_model, "Standard Am486DX");
336 break;
337 case 0x430:
338 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
339 break;
340 case 0x470:
341 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
342 break;
343 case 0x480:
344 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
345 break;
346 case 0x490:
347 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
348 break;
349 case 0x4E0:
350 strcat(cpu_model, "Am5x86 Write-Through");
351 break;
352 case 0x4F0:
353 strcat(cpu_model, "Am5x86 Write-Back");
354 break;
355 case 0x500:
356 strcat(cpu_model, "K5 model 0");
357 tsc_is_broken = 1;
358 break;
359 case 0x510:
360 strcat(cpu_model, "K5 model 1");
361 break;
362 case 0x520:
363 strcat(cpu_model, "K5 PR166 (model 2)");
364 break;
365 case 0x530:
366 strcat(cpu_model, "K5 PR200 (model 3)");
367 break;
368 case 0x560:
369 strcat(cpu_model, "K6");
370 break;
371 case 0x570:
372 strcat(cpu_model, "K6 266 (model 1)");
373 break;
374 case 0x580:
375 strcat(cpu_model, "K6-2");
376 break;
377 case 0x590:
378 strcat(cpu_model, "K6-III");
379 break;
380 default:
381 strcat(cpu_model, "Unknown");
382 break;
383 }
384#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
385 if ((cpu_id & 0xf00) == 0x500) {
386 if (((cpu_id & 0x0f0) > 0)
387 && ((cpu_id & 0x0f0) < 0x60)
388 && ((cpu_id & 0x00f) > 3))
389 enable_K5_wt_alloc();
390 else if (((cpu_id & 0x0f0) > 0x80)
391 || (((cpu_id & 0x0f0) == 0x80)
392 && (cpu_id & 0x00f) > 0x07))
393 enable_K6_2_wt_alloc();
394 else if ((cpu_id & 0x0f0) > 0x50)
395 enable_K6_wt_alloc();
396 }
397#endif
398 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
399 strcpy(cpu_model, "Cyrix ");
400 switch (cpu_id & 0xff0) {
401 case 0x440:
402 strcat(cpu_model, "MediaGX");
403 break;
404 case 0x520:
405 strcat(cpu_model, "6x86");
406 break;
407 case 0x540:
408 cpu_class = CPUCLASS_586;
409 strcat(cpu_model, "GXm");
410 break;
411 case 0x600:
412 strcat(cpu_model, "6x86MX");
413 break;
414 default:
415 /*
416 * Even though CPU supports the cpuid
417 * instruction, it can be disabled.
418 * Therefore, this routine supports all Cyrix
419 * CPUs.
420 */
421 switch (cyrix_did & 0xf0) {
422 case 0x00:
423 switch (cyrix_did & 0x0f) {
424 case 0x00:
425 strcat(cpu_model, "486SLC");
426 break;
427 case 0x01:
428 strcat(cpu_model, "486DLC");
429 break;
430 case 0x02:
431 strcat(cpu_model, "486SLC2");
432 break;
433 case 0x03:
434 strcat(cpu_model, "486DLC2");
435 break;
436 case 0x04:
437 strcat(cpu_model, "486SRx");
438 break;
439 case 0x05:
440 strcat(cpu_model, "486DRx");
441 break;
442 case 0x06:
443 strcat(cpu_model, "486SRx2");
444 break;
445 case 0x07:
446 strcat(cpu_model, "486DRx2");
447 break;
448 case 0x08:
449 strcat(cpu_model, "486SRu");
450 break;
451 case 0x09:
452 strcat(cpu_model, "486DRu");
453 break;
454 case 0x0a:
455 strcat(cpu_model, "486SRu2");
456 break;
457 case 0x0b:
458 strcat(cpu_model, "486DRu2");
459 break;
460 default:
461 strcat(cpu_model, "Unknown");
462 break;
463 }
464 break;
465 case 0x10:
466 switch (cyrix_did & 0x0f) {
467 case 0x00:
468 strcat(cpu_model, "486S");
469 break;
470 case 0x01:
471 strcat(cpu_model, "486S2");
472 break;
473 case 0x02:
474 strcat(cpu_model, "486Se");
475 break;
476 case 0x03:
477 strcat(cpu_model, "486S2e");
478 break;
479 case 0x0a:
480 strcat(cpu_model, "486DX");
481 break;
482 case 0x0b:
483 strcat(cpu_model, "486DX2");
484 break;
485 case 0x0f:
486 strcat(cpu_model, "486DX4");
487 break;
488 default:
489 strcat(cpu_model, "Unknown");
490 break;
491 }
492 break;
493 case 0x20:
494 if ((cyrix_did & 0x0f) < 8)
495 strcat(cpu_model, "6x86"); /* Where did you get it? */
496 else
497 strcat(cpu_model, "5x86");
498 break;
499 case 0x30:
500 strcat(cpu_model, "6x86");
501 break;
502 case 0x40:
503 if ((cyrix_did & 0xf000) == 0x3000) {
504 cpu_class = CPUCLASS_586;
505 strcat(cpu_model, "GXm");
506 } else
507 strcat(cpu_model, "MediaGX");
508 break;
509 case 0x50:
510 strcat(cpu_model, "6x86MX");
511 break;
512 case 0xf0:
513 switch (cyrix_did & 0x0f) {
514 case 0x0d:
515 strcat(cpu_model, "Overdrive CPU");
12afb922 516 break;
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517 case 0x0e:
518 strcpy(cpu_model, "Texas Instruments 486SXL");
519 break;
520 case 0x0f:
521 strcat(cpu_model, "486SLC/DLC");
522 break;
523 default:
524 strcat(cpu_model, "Unknown");
525 break;
526 }
527 break;
528 default:
529 strcat(cpu_model, "Unknown");
530 break;
531 }
532 break;
533 }
534 } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
535 strcpy(cpu_model, "Rise ");
536 switch (cpu_id & 0xff0) {
537 case 0x500:
538 strcat(cpu_model, "mP6");
539 break;
540 default:
541 strcat(cpu_model, "Unknown");
542 }
543 } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
544 switch (cpu_id & 0xff0) {
545 case 0x540:
546 strcpy(cpu_model, "IDT WinChip C6");
547 tsc_is_broken = 1;
548 break;
549 case 0x580:
550 strcpy(cpu_model, "IDT WinChip 2");
551 break;
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552 case 0x660:
553 strcpy(cpu_model, "VIA C3 Samuel");
554 break;
984263bc 555 case 0x670:
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556 if (cpu_id & 0x8)
557 strcpy(cpu_model, "VIA C3 Ezra");
558 else
559 strcpy(cpu_model, "VIA C3 Samuel 2");
560 break;
561 case 0x680:
562 strcpy(cpu_model, "VIA C3 Ezra-T");
563 break;
564 case 0x690:
565 strcpy(cpu_model, "VIA C3 Nehemiah");
566 do_cpuid(0xc0000000, regs);
567 if (regs[0] == 0xc0000001) {
568 do_cpuid(0xc0000001, regs);
569 if ((cpu_id & 0xf) >= 3)
570 if ((regs[3] & 0x0c) == 0x0c)
571 strcat(cpu_model, "+RNG");
572 if ((cpu_id & 0xf) >= 8)
573 if ((regs[3] & 0xc0) == 0xc0)
574 strcat(cpu_model, "+ACE");
575 }
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576 break;
577 default:
578 strcpy(cpu_model, "VIA/IDT Unknown");
579 }
580 } else if (strcmp(cpu_vendor, "IBM") == 0) {
581 strcpy(cpu_model, "Blue Lightning CPU");
582 }
583
584 /*
585 * Replace cpu_model with cpu_brand minus leading spaces if
586 * we have one.
587 */
588 brand = cpu_brand;
589 while (*brand == ' ')
590 ++brand;
591 if (*brand != '\0')
592 strcpy(cpu_model, brand);
593
594#endif
595
26be20a0 596 kprintf("%s (", cpu_model);
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597 switch(cpu_class) {
598 case CPUCLASS_286:
26be20a0 599 kprintf("286");
984263bc 600 break;
984263bc 601 case CPUCLASS_386:
26be20a0 602 kprintf("386");
984263bc 603 break;
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604#if defined(I486_CPU)
605 case CPUCLASS_486:
26be20a0 606 kprintf("486");
6a6c02da 607 /* bzero = i486_bzero; */
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608 break;
609#endif
610#if defined(I586_CPU)
611 case CPUCLASS_586:
926a4e8a
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612 kprintf("%lld.%02lld-MHz ",
613 (tsc_frequency + 4999LL) / 1000000LL,
614 ((tsc_frequency + 4999LL) / 10000LL) % 100LL);
26be20a0 615 kprintf("586");
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616 break;
617#endif
618#if defined(I686_CPU)
619 case CPUCLASS_686:
926a4e8a
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620 kprintf("%lld.%02lld-MHz ",
621 (tsc_frequency + 4999LL) / 1000000LL,
622 ((tsc_frequency + 4999LL) / 10000LL) % 100LL);
26be20a0 623 kprintf("686");
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624 break;
625#endif
626 default:
26be20a0 627 kprintf("Unknown"); /* will panic below... */
984263bc 628 }
26be20a0 629 kprintf("-class CPU)\n");
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630#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
631 if(*cpu_vendor)
26be20a0 632 kprintf(" Origin = \"%s\"",cpu_vendor);
984263bc 633 if(cpu_id)
26be20a0 634 kprintf(" Id = 0x%x", cpu_id);
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635
636 if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
637 strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
638 strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
639 strcmp(cpu_vendor, "CentaurHauls") == 0 ||
640 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
641 ((cpu_id & 0xf00) > 0x500))) {
26be20a0 642 kprintf(" Stepping = %u", cpu_id & 0xf);
984263bc 643 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
26be20a0 644 kprintf(" DIR=0x%04x", cyrix_did);
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MD
645 if (cpu_high > 0) {
646 /*
647 * Here we should probably set up flags indicating
648 * whether or not various features are available.
649 * The interesting ones are probably VME, PSE, PAE,
650 * and PGE. The code already assumes without bothering
651 * to check that all CPUs >= Pentium have a TSC and
652 * MSRs.
653 */
26be20a0 654 kprintf("\n Features=0x%b", cpu_feature,
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655 "\020"
656 "\001FPU" /* Integral FPU */
657 "\002VME" /* Extended VM86 mode support */
658 "\003DE" /* Debugging Extensions (CR4.DE) */
659 "\004PSE" /* 4MByte page tables */
660 "\005TSC" /* Timestamp counter */
661 "\006MSR" /* Machine specific registers */
662 "\007PAE" /* Physical address extension */
663 "\010MCE" /* Machine Check support */
664 "\011CX8" /* CMPEXCH8 instruction */
665 "\012APIC" /* SMP local APIC */
666 "\013oldMTRR" /* Previous implementation of MTRR */
667 "\014SEP" /* Fast System Call */
668 "\015MTRR" /* Memory Type Range Registers */
669 "\016PGE" /* PG_G (global bit) support */
670 "\017MCA" /* Machine Check Architecture */
671 "\020CMOV" /* CMOV instruction */
672 "\021PAT" /* Page attributes table */
673 "\022PSE36" /* 36 bit address space support */
674 "\023PN" /* Processor Serial number */
675 "\024CLFLUSH" /* Has the CLFLUSH instruction */
676 "\025<b20>"
677 "\026DTS" /* Debug Trace Store */
678 "\027ACPI" /* ACPI support */
679 "\030MMX" /* MMX instructions */
680 "\031FXSR" /* FXSAVE/FXRSTOR */
681 "\032SSE" /* Streaming SIMD Extensions */
682 "\033SSE2" /* Streaming SIMD Extensions #2 */
683 "\034SS" /* Self snoop */
684 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
685 "\036TM" /* Thermal Monitor clock slowdown */
686 "\037IA64" /* CPU can execute IA64 instructions */
687 "\040PBE" /* Pending Break Enable */
688 );
689
97ee3efc 690 if (cpu_feature2 != 0) {
e6164301 691 kprintf("\n Features2=0x%b", cpu_feature2,
97ee3efc
TS
692 "\020"
693 "\001SSE3" /* SSE3 */
694 "\002<b1>"
9e3d0133 695 "\003DTES64" /* 64-bit Debug Trace */
97ee3efc
TS
696 "\004MON" /* MONITOR/MWAIT Instructions */
697 "\005DS_CPL" /* CPL Qualified Debug Store */
698 "\006VMX" /* Virtual Machine Extensions */
9e3d0133 699 "\007SMX" /* Safer Mode Extensions */
97ee3efc
TS
700 "\010EST" /* Enhanced SpeedStep */
701 "\011TM2" /* Thermal Monitor 2 */
9e3d0133
SW
702 "\012SSSE3" /* SSSE3 */
703 "\013CNXT-ID" /* L1 context ID available */
97ee3efc
TS
704 "\014<b11>"
705 "\015<b12>"
706 "\016CX16" /* CMPXCHG16B Instruction */
9e3d0133
SW
707 "\017xTPR" /* Send Task Priority Messages*/
708 "\020PDCM" /* Perf/Debug Capability MSR */
97ee3efc
TS
709 "\021<b16>"
710 "\022<b17>"
9e3d0133
SW
711 "\023DCA" /* Direct Cache Access */
712 "\024SSE4.1"
713 "\025SSE4.2"
714 "\026x2APIC" /* xAPIC Extensions */
33a33a56 715 "\027MOVBE" /* MOVBE instruction */
9e3d0133 716 "\030POPCNT"
97ee3efc
TS
717 "\031<b24>"
718 "\032<b25>"
9e3d0133
SW
719 "\033XSAVE"
720 "\034OSXSAVE"
97ee3efc
TS
721 "\035<b28>"
722 "\036<b29>"
723 "\037<b30>"
724 "\040<b31>"
725 );
726 }
727
984263bc
MD
728 /*
729 * If this CPU supports hyperthreading then mention
730 * the number of logical CPU's it contains.
731 */
732 if (cpu_feature & CPUID_HTT &&
733 (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
26be20a0 734 kprintf("\n Hyperthreading: %d logical CPUs",
984263bc
MD
735 (cpu_procinfo & CPUID_HTT_CORES) >> 16);
736 }
737 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
738 cpu_exthigh >= 0x80000001)
739 print_AMD_features();
740 } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
26be20a0
SW
741 kprintf(" DIR=0x%04x", cyrix_did);
742 kprintf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
743 kprintf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
984263bc
MD
744#ifndef CYRIX_CACHE_REALLY_WORKS
745 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
26be20a0 746 kprintf("\n CPU cache: write-through mode");
984263bc
MD
747#endif
748 }
749 /* Avoid ugly blank lines: only print newline when we have to. */
750 if (*cpu_vendor || cpu_id)
26be20a0 751 kprintf("\n");
984263bc
MD
752
753#endif
754 if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
755 strcmp(cpu_vendor, "TransmetaCPU") == 0) {
756 setup_tmx86_longrun();
757 }
758
20f0a2d3 759 for (i = 0; i < additional_cpu_info_count; ++i) {
26be20a0 760 kprintf(" %s\n", additional_cpu_info_ary[i]);
20f0a2d3
MD
761 }
762
984263bc
MD
763 if (!bootverbose)
764 return;
765
766 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
767 print_AMD_info();
768 else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
769 strcmp(cpu_vendor, "TransmetaCPU") == 0)
770 print_transmeta_info();
771
772#ifdef I686_CPU
773 /*
774 * XXX - Do PPro CPUID level=2 stuff here?
775 *
776 * No, but maybe in a print_Intel_info() function called from here.
777 */
778#endif
779}
780
781void
782panicifcpuunsupported(void)
783{
784
4db955e1 785#if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
984263bc
MD
786#error This kernel is not configured for one of the supported CPUs
787#endif
788 /*
789 * Now that we have told the user what they have,
790 * let them know if that machine type isn't configured.
791 */
792 switch (cpu_class) {
4db955e1
MD
793 /*
794 * A 286 and 386 should not make it this far, anyway.
795 */
796 case CPUCLASS_286:
984263bc 797 case CPUCLASS_386:
984263bc
MD
798#if !defined(I486_CPU)
799 case CPUCLASS_486:
800#endif
801#if !defined(I586_CPU)
802 case CPUCLASS_586:
803#endif
804#if !defined(I686_CPU)
805 case CPUCLASS_686:
806#endif
807 panic("CPU class not configured");
808 default:
809 break;
810 }
811}
812
813
814static volatile u_int trap_by_rdmsr;
815
816/*
817 * Special exception 6 handler.
818 * The rdmsr instruction generates invalid opcodes fault on 486-class
819 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
820 * function identblue() when this handler is called. Stacked eip should
821 * be advanced.
822 */
823inthand_t bluetrap6;
89b88cd2
MD
824
825__asm(
826 " .text \n"
827 " .p2align 2,0x90 \n"
828 " .type " __XSTRING(CNAME(bluetrap6)) ",@function \n"
829 __XSTRING(CNAME(bluetrap6)) ": \n"
830 " ss \n"
831 " movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
832 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
833 " iret \n"
834);
984263bc
MD
835
836/*
837 * Special exception 13 handler.
838 * Accessing non-existent MSR generates general protection fault.
839 */
840inthand_t bluetrap13;
89b88cd2
MD
841
842__asm(
843 " .text \n"
844 " .p2align 2,0x90 \n"
845 " .type " __XSTRING(CNAME(bluetrap13)) ",@function \n"
846 __XSTRING(CNAME(bluetrap13)) ": \n"
847 " ss \n"
848 " movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n"
849 " popl %eax # discard errorcode. \n"
850 " addl $2, (%esp) # I know rdmsr is a 2-bytes instruction. \n"
851 " iret \n"
852);
984263bc
MD
853
854/*
855 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
856 * support cpuid instruction. This function should be called after
857 * loading interrupt descriptor table register.
858 *
859 * I don't like this method that handles fault, but I couldn't get
860 * information for any other methods. Does blue giant know?
861 */
862static int
863identblue(void)
864{
865
866 trap_by_rdmsr = 0;
867
868 /*
869 * Cyrix 486-class CPU does not support rdmsr instruction.
870 * The rdmsr instruction generates invalid opcode fault, and exception
871 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
872 * bluetrap6() set the magic number to trap_by_rdmsr.
873 */
874 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
875
876 /*
877 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
878 * In this case, rdmsr generates general protection fault, and
879 * exception will be trapped by bluetrap13().
880 */
881 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
882
883 rdmsr(0x1002); /* Cyrix CPU generates fault. */
884
885 if (trap_by_rdmsr == 0xa8c1d)
886 return IDENTBLUE_CYRIX486;
887 else if (trap_by_rdmsr == 0xa89c4)
888 return IDENTBLUE_CYRIXM2;
889 return IDENTBLUE_IBMCPU;
890}
891
892
893/*
894 * identifycyrix() set lower 16 bits of cyrix_did as follows:
895 *
896 * F E D C B A 9 8 7 6 5 4 3 2 1 0
897 * +-------+-------+---------------+
898 * | SID | RID | Device ID |
899 * | (DIR 1) | (DIR 0) |
900 * +-------+-------+---------------+
901 */
902static void
903identifycyrix(void)
904{
984263bc
MD
905 int ccr2_test = 0, dir_test = 0;
906 u_char ccr2, ccr3;
907
8a8d5d85 908 mpintr_lock();
984263bc
MD
909
910 ccr2 = read_cyrix_reg(CCR2);
911 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
912 read_cyrix_reg(CCR2);
913 if (read_cyrix_reg(CCR2) != ccr2)
914 ccr2_test = 1;
915 write_cyrix_reg(CCR2, ccr2);
916
917 ccr3 = read_cyrix_reg(CCR3);
918 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
919 read_cyrix_reg(CCR3);
920 if (read_cyrix_reg(CCR3) != ccr3)
921 dir_test = 1; /* CPU supports DIRs. */
922 write_cyrix_reg(CCR3, ccr3);
923
924 if (dir_test) {
925 /* Device ID registers are available. */
926 cyrix_did = read_cyrix_reg(DIR1) << 8;
927 cyrix_did += read_cyrix_reg(DIR0);
928 } else if (ccr2_test)
929 cyrix_did = 0x0010; /* 486S A-step */
930 else
931 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
932
8a8d5d85 933 mpintr_unlock();
984263bc
MD
934}
935
936/*
937 * Final stage of CPU identification. -- Should I check TI?
938 */
939void
940finishidentcpu(void)
941{
942 int isblue = 0;
943 u_char ccr3;
944 u_int regs[4];
945
946 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
947 if (cpu == CPU_486) {
948 /*
949 * These conditions are equivalent to:
950 * - CPU does not support cpuid instruction.
951 * - Cyrix/IBM CPU is detected.
952 */
953 isblue = identblue();
954 if (isblue == IDENTBLUE_IBMCPU) {
955 strcpy(cpu_vendor, "IBM");
956 cpu = CPU_BLUE;
957 return;
958 }
959 }
960 switch (cpu_id & 0xf00) {
961 case 0x600:
962 /*
963 * Cyrix's datasheet does not describe DIRs.
964 * Therefor, I assume it does not have them
965 * and use the result of the cpuid instruction.
966 * XXX they seem to have it for now at least. -Peter
967 */
968 identifycyrix();
969 cpu = CPU_M2;
970 break;
971 default:
972 identifycyrix();
973 /*
974 * This routine contains a trick.
975 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
976 */
977 switch (cyrix_did & 0x00f0) {
978 case 0x00:
979 case 0xf0:
980 cpu = CPU_486DLC;
981 break;
982 case 0x10:
983 cpu = CPU_CY486DX;
984 break;
985 case 0x20:
986 if ((cyrix_did & 0x000f) < 8)
987 cpu = CPU_M1;
988 else
989 cpu = CPU_M1SC;
990 break;
991 case 0x30:
992 cpu = CPU_M1;
993 break;
994 case 0x40:
995 /* MediaGX CPU */
996 cpu = CPU_M1SC;
997 break;
998 default:
999 /* M2 and later CPUs are treated as M2. */
1000 cpu = CPU_M2;
1001
1002 /*
1003 * enable cpuid instruction.
1004 */
1005 ccr3 = read_cyrix_reg(CCR3);
1006 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1007 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1008 write_cyrix_reg(CCR3, ccr3);
1009
1010 do_cpuid(0, regs);
1011 cpu_high = regs[0]; /* eax */
1012 do_cpuid(1, regs);
1013 cpu_id = regs[0]; /* eax */
1014 cpu_feature = regs[3]; /* edx */
1015 break;
1016 }
1017 }
1018 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1019 /*
1020 * There are BlueLightning CPUs that do not change
1021 * undefined flags by dividing 5 by 2. In this case,
1022 * the CPU identification routine in locore.s leaves
1023 * cpu_vendor null string and puts CPU_486 into the
1024 * cpu.
1025 */
1026 isblue = identblue();
1027 if (isblue == IDENTBLUE_IBMCPU) {
1028 strcpy(cpu_vendor, "IBM");
1029 cpu = CPU_BLUE;
1030 return;
1031 }
1032 }
1033}
1034
1035static void
1036print_AMD_assoc(int i)
1037{
1038 if (i == 255)
26be20a0 1039 kprintf(", fully associative\n");
984263bc 1040 else
26be20a0 1041 kprintf(", %d-way associative\n", i);
984263bc
MD
1042}
1043
2ef741b7
SZ
1044/*
1045 * #31116 Rev 3.06 section 3.9
1046 * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1047 */
1048static void
1049print_AMD_L2L3_assoc(int i)
1050{
1051 static const char *assoc_str[] = {
1052 [0x0] = "disabled",
1053 [0x1] = "direct mapped",
1054 [0x2] = "2-way associative",
1055 [0x4] = "4-way associative",
1056 [0x6] = "8-way associative",
1057 [0x8] = "16-way associative",
1058 [0xa] = "32-way associative",
1059 [0xb] = "48-way associative",
1060 [0xc] = "64-way associative",
1061 [0xd] = "96-way associative",
1062 [0xe] = "128-way associative",
1063 [0xf] = "fully associative"
1064 };
1065
1066 i &= 0xf;
1067 if (assoc_str[i] == NULL)
1068 kprintf(", unknown associative\n");
1069 else
1070 kprintf(", %s\n", assoc_str[i]);
1071}
1072
984263bc
MD
1073static void
1074print_AMD_info(void)
1075{
1076 quad_t amd_whcr;
1077
1078 if (cpu_exthigh >= 0x80000005) {
1079 u_int regs[4];
1080
1081 do_cpuid(0x80000005, regs);
26be20a0 1082 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
984263bc 1083 print_AMD_assoc(regs[1] >> 24);
26be20a0 1084 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
984263bc 1085 print_AMD_assoc((regs[1] >> 8) & 0xff);
26be20a0
SW
1086 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1087 kprintf(", %d bytes/line", regs[2] & 0xff);
1088 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
984263bc 1089 print_AMD_assoc((regs[2] >> 16) & 0xff);
26be20a0
SW
1090 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1091 kprintf(", %d bytes/line", regs[3] & 0xff);
1092 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
984263bc 1093 print_AMD_assoc((regs[3] >> 16) & 0xff);
9b95ebe5 1094 if (cpu_exthigh >= 0x80000006) { /* K6-III, or later */
984263bc 1095 do_cpuid(0x80000006, regs);
9b95ebe5
HP
1096 /*
1097 * Report right L2 cache size on Duron rev. A0.
1098 */
1099 if ((cpu_id & 0xFF0) == 0x630)
26be20a0 1100 kprintf("L2 internal cache: 64 kbytes");
9b95ebe5 1101 else
26be20a0 1102 kprintf("L2 internal cache: %d kbytes",
9b95ebe5
HP
1103 regs[2] >> 16);
1104
26be20a0
SW
1105 kprintf(", %d bytes/line", regs[2] & 0xff);
1106 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
2ef741b7
SZ
1107 print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1108
1109 /*
1110 * #31116 Rev 3.06 section 2.16.2:
1111 * ... If EDX[31:16] is not zero then the processor
1112 * includes an L3. ...
1113 */
1114 if ((regs[3] & 0xffff0000) != 0) {
1115 kprintf("L3 shared cache: %d kbytes",
1116 (regs[3] >> 18) * 512);
1117 kprintf(", %d bytes/line", regs[3] & 0xff);
1118 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1119 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1120 }
984263bc
MD
1121 }
1122 }
1123 if (((cpu_id & 0xf00) == 0x500)
1124 && (((cpu_id & 0x0f0) > 0x80)
1125 || (((cpu_id & 0x0f0) == 0x80)
1126 && (cpu_id & 0x00f) > 0x07))) {
1127 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1128 amd_whcr = rdmsr(0xc0000082);
1129 if (!(amd_whcr & (0x3ff << 22))) {
26be20a0 1130 kprintf("Write Allocate Disable\n");
984263bc 1131 } else {
26be20a0 1132 kprintf("Write Allocate Enable Limit: %dM bytes\n",
984263bc 1133 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
26be20a0 1134 kprintf("Write Allocate 15-16M bytes: %s\n",
984263bc
MD
1135 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1136 }
1137 } else if (((cpu_id & 0xf00) == 0x500)
1138 && ((cpu_id & 0x0f0) > 0x50)) {
1139 /* K6, K6-2(old core) */
1140 amd_whcr = rdmsr(0xc0000082);
1141 if (!(amd_whcr & (0x7f << 1))) {
26be20a0 1142 kprintf("Write Allocate Disable\n");
984263bc 1143 } else {
26be20a0 1144 kprintf("Write Allocate Enable Limit: %dM bytes\n",
984263bc 1145 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
26be20a0 1146 kprintf("Write Allocate 15-16M bytes: %s\n",
984263bc 1147 (amd_whcr & 0x0001) ? "Enable" : "Disable");
26be20a0 1148 kprintf("Hardware Write Allocate Control: %s\n",
984263bc
MD
1149 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1150 }
1151 }
1152}
1153
1154#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1155static void
1156print_AMD_features(void)
1157{
1158 u_int regs[4];
1159
1160 /*
1161 * Values taken from AMD Processor Recognition
1162 * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1163 */
1164 do_cpuid(0x80000001, regs);
26be20a0 1165 kprintf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
984263bc
MD
1166 "\020" /* in hex */
1167 "\001FPU" /* Integral FPU */
1168 "\002VME" /* Extended VM86 mode support */
1169 "\003DE" /* Debug extensions */
1170 "\004PSE" /* 4MByte page tables */
1171 "\005TSC" /* Timestamp counter */
1172 "\006MSR" /* Machine specific registers */
1173 "\007PAE" /* Physical address extension */
1174 "\010MCE" /* Machine Check support */
1175 "\011CX8" /* CMPEXCH8 instruction */
1176 "\012APIC" /* SMP local APIC */
1177 "\013<b10>"
1178 "\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
1179 "\015MTRR" /* Memory Type Range Registers */
1180 "\016PGE" /* PG_G (global bit) support */
1181 "\017MCA" /* Machine Check Architecture */
1182 "\020ICMOV" /* CMOV instruction */
1183 "\021PAT" /* Page attributes table */
1184 "\022PGE36" /* 36 bit address space support */
1185 "\023RSVD" /* Reserved, unknown */
1186 "\024MP" /* Multiprocessor Capable */
d0cfd270 1187 "\025NX" /* No-execute page protection */
984263bc
MD
1188 "\026<b21>"
1189 "\027AMIE" /* AMD MMX Instruction Extensions */
1190 "\030MMX"
1191 "\031FXSAVE" /* FXSAVE/FXRSTOR */
1192 "\032<b25>"
1193 "\033<b26>"
d0cfd270 1194 "\034RDTSCP" /* RDTSCP instruction */
984263bc 1195 "\035<b28>"
d0cfd270 1196 "\036LM" /* Long mode */
984263bc
MD
1197 "\037DSP" /* AMD 3DNow! Instruction Extensions */
1198 "\0403DNow!"
1199 );
1200}
1201#endif
1202
1203/*
1204 * Transmeta Crusoe LongRun Support by Tamotsu Hattori.
1205 */
1206
1207#define MSR_TMx86_LONGRUN 0x80868010
1208#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
1209
1210#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
1211#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
1212#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1213
1214#define LONGRUN_MODE_MINFREQUENCY 0x00
1215#define LONGRUN_MODE_ECONOMY 0x01
1216#define LONGRUN_MODE_PERFORMANCE 0x02
1217#define LONGRUN_MODE_MAXFREQUENCY 0x03
1218#define LONGRUN_MODE_UNKNOWN 0x04
1219#define LONGRUN_MODE_MAX 0x04
1220
1221union msrinfo {
1222 u_int64_t msr;
1223 u_int32_t regs[2];
1224};
1225
1226u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1227 /* MSR low, MSR high, flags bit0 */
1228 { 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
1229 { 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
1230 { 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
1231 { 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
1232};
1233
1234static u_int
1235tmx86_get_longrun_mode(void)
1236{
984263bc
MD
1237 union msrinfo msrinfo;
1238 u_int low, high, flags, mode;
1239
8a8d5d85 1240 mpintr_lock();
984263bc
MD
1241
1242 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1243 low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1244 high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1245 flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1246
1247 for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1248 if (low == longrun_modes[mode][0] &&
1249 high == longrun_modes[mode][1] &&
1250 flags == longrun_modes[mode][2]) {
1251 goto out;
1252 }
1253 }
1254 mode = LONGRUN_MODE_UNKNOWN;
1255out:
8a8d5d85 1256 mpintr_unlock();
984263bc
MD
1257 return (mode);
1258}
1259
1260static u_int
1261tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1262{
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1263 u_int regs[4];
1264
8a8d5d85 1265 mpintr_lock();
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1266
1267 do_cpuid(0x80860007, regs);
1268 *frequency = regs[0];
1269 *voltage = regs[1];
1270 *percentage = regs[2];
1271
8a8d5d85 1272 mpintr_unlock();
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1273 return (1);
1274}
1275
1276static u_int
1277tmx86_set_longrun_mode(u_int mode)
1278{
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1279 union msrinfo msrinfo;
1280
1281 if (mode >= LONGRUN_MODE_UNKNOWN) {
1282 return (0);
1283 }
1284
8a8d5d85 1285 mpintr_lock();
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1286
1287 /* Write LongRun mode values to Model Specific Register. */
1288 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1289 msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1290 longrun_modes[mode][0]);
1291 msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1292 longrun_modes[mode][1]);
1293 wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1294
1295 /* Write LongRun mode flags to Model Specific Register. */
1296 msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1297 msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1298 wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1299
8a8d5d85 1300 mpintr_unlock();
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1301 return (1);
1302}
1303
1304static u_int crusoe_longrun;
1305static u_int crusoe_frequency;
1306static u_int crusoe_voltage;
1307static u_int crusoe_percentage;
1308static struct sysctl_ctx_list crusoe_sysctl_ctx;
1309static struct sysctl_oid *crusoe_sysctl_tree;
1310
1311static int
1312tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1313{
1314 u_int mode;
1315 int error;
1316
1317 crusoe_longrun = tmx86_get_longrun_mode();
1318 mode = crusoe_longrun;
1319 error = sysctl_handle_int(oidp, &mode, 0, req);
1320 if (error || !req->newptr) {
1321 return (error);
1322 }
1323 if (mode >= LONGRUN_MODE_UNKNOWN) {
1324 error = EINVAL;
1325 return (error);
1326 }
1327 if (crusoe_longrun != mode) {
1328 crusoe_longrun = mode;
1329 tmx86_set_longrun_mode(crusoe_longrun);
1330 }
1331
1332 return (error);
1333}
1334
1335static int
1336tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1337{
1338 u_int val;
1339 int error;
1340
1341 tmx86_get_longrun_status(&crusoe_frequency,
1342 &crusoe_voltage, &crusoe_percentage);
1343 val = *(u_int *)oidp->oid_arg1;
1344 error = sysctl_handle_int(oidp, &val, 0, req);
1345 return (error);
1346}
1347
1348static void
1349setup_tmx86_longrun(void)
1350{
1351 static int done = 0;
1352
1353 if (done)
1354 return;
1355 done++;
1356
1357 sysctl_ctx_init(&crusoe_sysctl_ctx);
1358 crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1359 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1360 "crusoe", CTLFLAG_RD, 0,
1361 "Transmeta Crusoe LongRun support");
1362 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1363 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1364 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1365 "LongRun mode [0-3]");
1366 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1367 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1368 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1369 "Current frequency (MHz)");
1370 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1371 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1372 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1373 "Current voltage (mV)");
1374 SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1375 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1376 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1377 "Processing performance (%)");
1378}
1379
1380static void
f123d5a1 1381print_transmeta_info(void)
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1382{
1383 u_int regs[4], nreg = 0;
1384
1385 do_cpuid(0x80860000, regs);
1386 nreg = regs[0];
1387 if (nreg >= 0x80860001) {
1388 do_cpuid(0x80860001, regs);
26be20a0 1389 kprintf(" Processor revision %u.%u.%u.%u\n",
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1390 (regs[1] >> 24) & 0xff,
1391 (regs[1] >> 16) & 0xff,
1392 (regs[1] >> 8) & 0xff,
1393 regs[1] & 0xff);
1394 }
1395 if (nreg >= 0x80860002) {
1396 do_cpuid(0x80860002, regs);
26be20a0 1397 kprintf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
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1398 (regs[1] >> 24) & 0xff,
1399 (regs[1] >> 16) & 0xff,
1400 (regs[1] >> 8) & 0xff,
1401 regs[1] & 0xff,
1402 regs[2]);
1403 }
1404 if (nreg >= 0x80860006) {
1405 char info[65];
1406 do_cpuid(0x80860003, (u_int*) &info[0]);
1407 do_cpuid(0x80860004, (u_int*) &info[16]);
1408 do_cpuid(0x80860005, (u_int*) &info[32]);
1409 do_cpuid(0x80860006, (u_int*) &info[48]);
1410 info[64] = 0;
26be20a0 1411 kprintf(" %s\n", info);
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1412 }
1413
1414 crusoe_longrun = tmx86_get_longrun_mode();
1415 tmx86_get_longrun_status(&crusoe_frequency,
1416 &crusoe_voltage, &crusoe_percentage);
26be20a0 1417 kprintf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
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1418 crusoe_frequency, crusoe_voltage, crusoe_percentage);
1419}
1420
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1421void
1422additional_cpu_info(const char *line)
1423{
1424 int i;
1425
1426 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1427 additional_cpu_info_ary[i] = line;
1428 ++additional_cpu_info_count;
1429 }
1430}
1431