ioapic/x86_64: Allow GSI > 191
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
CommitLineData
c8fe38ae
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1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 1996, by Steve Passe. All rights reserved.
4 * Copyright (c) 2005,2008 The DragonFly Project. All rights reserved.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The DragonFly Project
8 * by Matthew Dillon <dillon@backplane.com>
9 *
10 * This code is derived from software contributed to Berkeley by
11 * William Jolitz.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 * 3. Neither the name of The DragonFly Project nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific, prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
c8fe38ae
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39 */
40
41#include <sys/param.h>
42#include <sys/systm.h>
43#include <sys/kernel.h>
44#include <sys/machintr.h>
45#include <sys/interrupt.h>
46#include <sys/bus.h>
981239a7 47#include <sys/rman.h>
95874ffd 48#include <sys/thread2.h>
c8fe38ae
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49
50#include <machine/smp.h>
51#include <machine/segments.h>
52#include <machine/md_var.h>
57a9c56b 53#include <machine/intr_machdep.h>
c8fe38ae 54#include <machine/globaldata.h>
4234567c 55#include <machine/msi_var.h>
c8fe38ae 56
104463f2 57#include <machine_base/isa/isa_intr.h>
61452645 58#include <machine_base/icu/icu.h>
6b809ec7 59#include <machine_base/icu/icu_var.h>
61452645 60#include <machine_base/apic/ioapic.h>
929c940f 61#include <machine_base/apic/ioapic_abi.h>
77f86d14 62#include <machine_base/apic/ioapic_ipl.h>
9a4bd8f3 63#include <machine_base/apic/apicreg.h>
c8fe38ae 64
95874ffd
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65#include <dev/acpica5/acpi_sci_var.h>
66
451af8d9
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67#define IOAPIC_HWI_VECTORS IDT_HWI_VECTORS
68
c8fe38ae 69extern inthand_t
9e0e3f85
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70 IDTVEC(ioapic_intr0),
71 IDTVEC(ioapic_intr1),
72 IDTVEC(ioapic_intr2),
73 IDTVEC(ioapic_intr3),
74 IDTVEC(ioapic_intr4),
75 IDTVEC(ioapic_intr5),
76 IDTVEC(ioapic_intr6),
77 IDTVEC(ioapic_intr7),
78 IDTVEC(ioapic_intr8),
79 IDTVEC(ioapic_intr9),
80 IDTVEC(ioapic_intr10),
81 IDTVEC(ioapic_intr11),
82 IDTVEC(ioapic_intr12),
83 IDTVEC(ioapic_intr13),
84 IDTVEC(ioapic_intr14),
85 IDTVEC(ioapic_intr15),
86 IDTVEC(ioapic_intr16),
87 IDTVEC(ioapic_intr17),
88 IDTVEC(ioapic_intr18),
89 IDTVEC(ioapic_intr19),
90 IDTVEC(ioapic_intr20),
91 IDTVEC(ioapic_intr21),
92 IDTVEC(ioapic_intr22),
93 IDTVEC(ioapic_intr23),
94 IDTVEC(ioapic_intr24),
95 IDTVEC(ioapic_intr25),
96 IDTVEC(ioapic_intr26),
97 IDTVEC(ioapic_intr27),
98 IDTVEC(ioapic_intr28),
99 IDTVEC(ioapic_intr29),
100 IDTVEC(ioapic_intr30),
101 IDTVEC(ioapic_intr31),
102 IDTVEC(ioapic_intr32),
103 IDTVEC(ioapic_intr33),
104 IDTVEC(ioapic_intr34),
105 IDTVEC(ioapic_intr35),
106 IDTVEC(ioapic_intr36),
107 IDTVEC(ioapic_intr37),
108 IDTVEC(ioapic_intr38),
109 IDTVEC(ioapic_intr39),
110 IDTVEC(ioapic_intr40),
111 IDTVEC(ioapic_intr41),
112 IDTVEC(ioapic_intr42),
113 IDTVEC(ioapic_intr43),
114 IDTVEC(ioapic_intr44),
115 IDTVEC(ioapic_intr45),
116 IDTVEC(ioapic_intr46),
117 IDTVEC(ioapic_intr47),
118 IDTVEC(ioapic_intr48),
119 IDTVEC(ioapic_intr49),
120 IDTVEC(ioapic_intr50),
121 IDTVEC(ioapic_intr51),
122 IDTVEC(ioapic_intr52),
123 IDTVEC(ioapic_intr53),
124 IDTVEC(ioapic_intr54),
125 IDTVEC(ioapic_intr55),
126 IDTVEC(ioapic_intr56),
127 IDTVEC(ioapic_intr57),
128 IDTVEC(ioapic_intr58),
129 IDTVEC(ioapic_intr59),
130 IDTVEC(ioapic_intr60),
131 IDTVEC(ioapic_intr61),
132 IDTVEC(ioapic_intr62),
133 IDTVEC(ioapic_intr63),
134 IDTVEC(ioapic_intr64),
135 IDTVEC(ioapic_intr65),
136 IDTVEC(ioapic_intr66),
137 IDTVEC(ioapic_intr67),
138 IDTVEC(ioapic_intr68),
139 IDTVEC(ioapic_intr69),
140 IDTVEC(ioapic_intr70),
141 IDTVEC(ioapic_intr71),
142 IDTVEC(ioapic_intr72),
143 IDTVEC(ioapic_intr73),
144 IDTVEC(ioapic_intr74),
145 IDTVEC(ioapic_intr75),
146 IDTVEC(ioapic_intr76),
147 IDTVEC(ioapic_intr77),
148 IDTVEC(ioapic_intr78),
149 IDTVEC(ioapic_intr79),
150 IDTVEC(ioapic_intr80),
151 IDTVEC(ioapic_intr81),
152 IDTVEC(ioapic_intr82),
153 IDTVEC(ioapic_intr83),
154 IDTVEC(ioapic_intr84),
155 IDTVEC(ioapic_intr85),
156 IDTVEC(ioapic_intr86),
157 IDTVEC(ioapic_intr87),
158 IDTVEC(ioapic_intr88),
159 IDTVEC(ioapic_intr89),
160 IDTVEC(ioapic_intr90),
161 IDTVEC(ioapic_intr91),
162 IDTVEC(ioapic_intr92),
163 IDTVEC(ioapic_intr93),
164 IDTVEC(ioapic_intr94),
165 IDTVEC(ioapic_intr95),
166 IDTVEC(ioapic_intr96),
167 IDTVEC(ioapic_intr97),
168 IDTVEC(ioapic_intr98),
169 IDTVEC(ioapic_intr99),
170 IDTVEC(ioapic_intr100),
171 IDTVEC(ioapic_intr101),
172 IDTVEC(ioapic_intr102),
173 IDTVEC(ioapic_intr103),
174 IDTVEC(ioapic_intr104),
175 IDTVEC(ioapic_intr105),
176 IDTVEC(ioapic_intr106),
177 IDTVEC(ioapic_intr107),
178 IDTVEC(ioapic_intr108),
179 IDTVEC(ioapic_intr109),
180 IDTVEC(ioapic_intr110),
181 IDTVEC(ioapic_intr111),
182 IDTVEC(ioapic_intr112),
183 IDTVEC(ioapic_intr113),
184 IDTVEC(ioapic_intr114),
185 IDTVEC(ioapic_intr115),
186 IDTVEC(ioapic_intr116),
187 IDTVEC(ioapic_intr117),
188 IDTVEC(ioapic_intr118),
189 IDTVEC(ioapic_intr119),
190 IDTVEC(ioapic_intr120),
191 IDTVEC(ioapic_intr121),
192 IDTVEC(ioapic_intr122),
193 IDTVEC(ioapic_intr123),
194 IDTVEC(ioapic_intr124),
195 IDTVEC(ioapic_intr125),
196 IDTVEC(ioapic_intr126),
197 IDTVEC(ioapic_intr127),
198 IDTVEC(ioapic_intr128),
199 IDTVEC(ioapic_intr129),
200 IDTVEC(ioapic_intr130),
201 IDTVEC(ioapic_intr131),
202 IDTVEC(ioapic_intr132),
203 IDTVEC(ioapic_intr133),
204 IDTVEC(ioapic_intr134),
205 IDTVEC(ioapic_intr135),
206 IDTVEC(ioapic_intr136),
207 IDTVEC(ioapic_intr137),
208 IDTVEC(ioapic_intr138),
209 IDTVEC(ioapic_intr139),
210 IDTVEC(ioapic_intr140),
211 IDTVEC(ioapic_intr141),
212 IDTVEC(ioapic_intr142),
213 IDTVEC(ioapic_intr143),
214 IDTVEC(ioapic_intr144),
215 IDTVEC(ioapic_intr145),
216 IDTVEC(ioapic_intr146),
217 IDTVEC(ioapic_intr147),
218 IDTVEC(ioapic_intr148),
219 IDTVEC(ioapic_intr149),
220 IDTVEC(ioapic_intr150),
221 IDTVEC(ioapic_intr151),
222 IDTVEC(ioapic_intr152),
223 IDTVEC(ioapic_intr153),
224 IDTVEC(ioapic_intr154),
225 IDTVEC(ioapic_intr155),
226 IDTVEC(ioapic_intr156),
227 IDTVEC(ioapic_intr157),
228 IDTVEC(ioapic_intr158),
229 IDTVEC(ioapic_intr159),
230 IDTVEC(ioapic_intr160),
231 IDTVEC(ioapic_intr161),
232 IDTVEC(ioapic_intr162),
233 IDTVEC(ioapic_intr163),
234 IDTVEC(ioapic_intr164),
235 IDTVEC(ioapic_intr165),
236 IDTVEC(ioapic_intr166),
237 IDTVEC(ioapic_intr167),
238 IDTVEC(ioapic_intr168),
239 IDTVEC(ioapic_intr169),
240 IDTVEC(ioapic_intr170),
241 IDTVEC(ioapic_intr171),
242 IDTVEC(ioapic_intr172),
243 IDTVEC(ioapic_intr173),
244 IDTVEC(ioapic_intr174),
245 IDTVEC(ioapic_intr175),
246 IDTVEC(ioapic_intr176),
247 IDTVEC(ioapic_intr177),
248 IDTVEC(ioapic_intr178),
249 IDTVEC(ioapic_intr179),
250 IDTVEC(ioapic_intr180),
251 IDTVEC(ioapic_intr181),
252 IDTVEC(ioapic_intr182),
253 IDTVEC(ioapic_intr183),
254 IDTVEC(ioapic_intr184),
255 IDTVEC(ioapic_intr185),
256 IDTVEC(ioapic_intr186),
257 IDTVEC(ioapic_intr187),
258 IDTVEC(ioapic_intr188),
259 IDTVEC(ioapic_intr189),
260 IDTVEC(ioapic_intr190),
261 IDTVEC(ioapic_intr191);
262
263static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
264 &IDTVEC(ioapic_intr0),
265 &IDTVEC(ioapic_intr1),
266 &IDTVEC(ioapic_intr2),
267 &IDTVEC(ioapic_intr3),
268 &IDTVEC(ioapic_intr4),
269 &IDTVEC(ioapic_intr5),
270 &IDTVEC(ioapic_intr6),
271 &IDTVEC(ioapic_intr7),
272 &IDTVEC(ioapic_intr8),
273 &IDTVEC(ioapic_intr9),
274 &IDTVEC(ioapic_intr10),
275 &IDTVEC(ioapic_intr11),
276 &IDTVEC(ioapic_intr12),
277 &IDTVEC(ioapic_intr13),
278 &IDTVEC(ioapic_intr14),
279 &IDTVEC(ioapic_intr15),
280 &IDTVEC(ioapic_intr16),
281 &IDTVEC(ioapic_intr17),
282 &IDTVEC(ioapic_intr18),
283 &IDTVEC(ioapic_intr19),
284 &IDTVEC(ioapic_intr20),
285 &IDTVEC(ioapic_intr21),
286 &IDTVEC(ioapic_intr22),
287 &IDTVEC(ioapic_intr23),
288 &IDTVEC(ioapic_intr24),
289 &IDTVEC(ioapic_intr25),
290 &IDTVEC(ioapic_intr26),
291 &IDTVEC(ioapic_intr27),
292 &IDTVEC(ioapic_intr28),
293 &IDTVEC(ioapic_intr29),
294 &IDTVEC(ioapic_intr30),
295 &IDTVEC(ioapic_intr31),
296 &IDTVEC(ioapic_intr32),
297 &IDTVEC(ioapic_intr33),
298 &IDTVEC(ioapic_intr34),
299 &IDTVEC(ioapic_intr35),
300 &IDTVEC(ioapic_intr36),
301 &IDTVEC(ioapic_intr37),
302 &IDTVEC(ioapic_intr38),
303 &IDTVEC(ioapic_intr39),
304 &IDTVEC(ioapic_intr40),
305 &IDTVEC(ioapic_intr41),
306 &IDTVEC(ioapic_intr42),
307 &IDTVEC(ioapic_intr43),
308 &IDTVEC(ioapic_intr44),
309 &IDTVEC(ioapic_intr45),
310 &IDTVEC(ioapic_intr46),
311 &IDTVEC(ioapic_intr47),
312 &IDTVEC(ioapic_intr48),
313 &IDTVEC(ioapic_intr49),
314 &IDTVEC(ioapic_intr50),
315 &IDTVEC(ioapic_intr51),
316 &IDTVEC(ioapic_intr52),
317 &IDTVEC(ioapic_intr53),
318 &IDTVEC(ioapic_intr54),
319 &IDTVEC(ioapic_intr55),
320 &IDTVEC(ioapic_intr56),
321 &IDTVEC(ioapic_intr57),
322 &IDTVEC(ioapic_intr58),
323 &IDTVEC(ioapic_intr59),
324 &IDTVEC(ioapic_intr60),
325 &IDTVEC(ioapic_intr61),
326 &IDTVEC(ioapic_intr62),
327 &IDTVEC(ioapic_intr63),
328 &IDTVEC(ioapic_intr64),
329 &IDTVEC(ioapic_intr65),
330 &IDTVEC(ioapic_intr66),
331 &IDTVEC(ioapic_intr67),
332 &IDTVEC(ioapic_intr68),
333 &IDTVEC(ioapic_intr69),
334 &IDTVEC(ioapic_intr70),
335 &IDTVEC(ioapic_intr71),
336 &IDTVEC(ioapic_intr72),
337 &IDTVEC(ioapic_intr73),
338 &IDTVEC(ioapic_intr74),
339 &IDTVEC(ioapic_intr75),
340 &IDTVEC(ioapic_intr76),
341 &IDTVEC(ioapic_intr77),
342 &IDTVEC(ioapic_intr78),
343 &IDTVEC(ioapic_intr79),
344 &IDTVEC(ioapic_intr80),
345 &IDTVEC(ioapic_intr81),
346 &IDTVEC(ioapic_intr82),
347 &IDTVEC(ioapic_intr83),
348 &IDTVEC(ioapic_intr84),
349 &IDTVEC(ioapic_intr85),
350 &IDTVEC(ioapic_intr86),
351 &IDTVEC(ioapic_intr87),
352 &IDTVEC(ioapic_intr88),
353 &IDTVEC(ioapic_intr89),
354 &IDTVEC(ioapic_intr90),
355 &IDTVEC(ioapic_intr91),
356 &IDTVEC(ioapic_intr92),
357 &IDTVEC(ioapic_intr93),
358 &IDTVEC(ioapic_intr94),
359 &IDTVEC(ioapic_intr95),
360 &IDTVEC(ioapic_intr96),
361 &IDTVEC(ioapic_intr97),
362 &IDTVEC(ioapic_intr98),
363 &IDTVEC(ioapic_intr99),
364 &IDTVEC(ioapic_intr100),
365 &IDTVEC(ioapic_intr101),
366 &IDTVEC(ioapic_intr102),
367 &IDTVEC(ioapic_intr103),
368 &IDTVEC(ioapic_intr104),
369 &IDTVEC(ioapic_intr105),
370 &IDTVEC(ioapic_intr106),
371 &IDTVEC(ioapic_intr107),
372 &IDTVEC(ioapic_intr108),
373 &IDTVEC(ioapic_intr109),
374 &IDTVEC(ioapic_intr110),
375 &IDTVEC(ioapic_intr111),
376 &IDTVEC(ioapic_intr112),
377 &IDTVEC(ioapic_intr113),
378 &IDTVEC(ioapic_intr114),
379 &IDTVEC(ioapic_intr115),
380 &IDTVEC(ioapic_intr116),
381 &IDTVEC(ioapic_intr117),
382 &IDTVEC(ioapic_intr118),
383 &IDTVEC(ioapic_intr119),
384 &IDTVEC(ioapic_intr120),
385 &IDTVEC(ioapic_intr121),
386 &IDTVEC(ioapic_intr122),
387 &IDTVEC(ioapic_intr123),
388 &IDTVEC(ioapic_intr124),
389 &IDTVEC(ioapic_intr125),
390 &IDTVEC(ioapic_intr126),
391 &IDTVEC(ioapic_intr127),
392 &IDTVEC(ioapic_intr128),
393 &IDTVEC(ioapic_intr129),
394 &IDTVEC(ioapic_intr130),
395 &IDTVEC(ioapic_intr131),
396 &IDTVEC(ioapic_intr132),
397 &IDTVEC(ioapic_intr133),
398 &IDTVEC(ioapic_intr134),
399 &IDTVEC(ioapic_intr135),
400 &IDTVEC(ioapic_intr136),
401 &IDTVEC(ioapic_intr137),
402 &IDTVEC(ioapic_intr138),
403 &IDTVEC(ioapic_intr139),
404 &IDTVEC(ioapic_intr140),
405 &IDTVEC(ioapic_intr141),
406 &IDTVEC(ioapic_intr142),
407 &IDTVEC(ioapic_intr143),
408 &IDTVEC(ioapic_intr144),
409 &IDTVEC(ioapic_intr145),
410 &IDTVEC(ioapic_intr146),
411 &IDTVEC(ioapic_intr147),
412 &IDTVEC(ioapic_intr148),
413 &IDTVEC(ioapic_intr149),
414 &IDTVEC(ioapic_intr150),
415 &IDTVEC(ioapic_intr151),
416 &IDTVEC(ioapic_intr152),
417 &IDTVEC(ioapic_intr153),
418 &IDTVEC(ioapic_intr154),
419 &IDTVEC(ioapic_intr155),
420 &IDTVEC(ioapic_intr156),
421 &IDTVEC(ioapic_intr157),
422 &IDTVEC(ioapic_intr158),
423 &IDTVEC(ioapic_intr159),
424 &IDTVEC(ioapic_intr160),
425 &IDTVEC(ioapic_intr161),
426 &IDTVEC(ioapic_intr162),
427 &IDTVEC(ioapic_intr163),
428 &IDTVEC(ioapic_intr164),
429 &IDTVEC(ioapic_intr165),
430 &IDTVEC(ioapic_intr166),
431 &IDTVEC(ioapic_intr167),
432 &IDTVEC(ioapic_intr168),
433 &IDTVEC(ioapic_intr169),
434 &IDTVEC(ioapic_intr170),
435 &IDTVEC(ioapic_intr171),
436 &IDTVEC(ioapic_intr172),
437 &IDTVEC(ioapic_intr173),
438 &IDTVEC(ioapic_intr174),
439 &IDTVEC(ioapic_intr175),
440 &IDTVEC(ioapic_intr176),
441 &IDTVEC(ioapic_intr177),
442 &IDTVEC(ioapic_intr178),
443 &IDTVEC(ioapic_intr179),
444 &IDTVEC(ioapic_intr180),
445 &IDTVEC(ioapic_intr181),
446 &IDTVEC(ioapic_intr182),
447 &IDTVEC(ioapic_intr183),
448 &IDTVEC(ioapic_intr184),
449 &IDTVEC(ioapic_intr185),
450 &IDTVEC(ioapic_intr186),
451 &IDTVEC(ioapic_intr187),
452 &IDTVEC(ioapic_intr188),
453 &IDTVEC(ioapic_intr189),
454 &IDTVEC(ioapic_intr190),
455 &IDTVEC(ioapic_intr191)
c571da4a 456};
c8fe38ae 457
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458#define IOAPIC_HWI_SYSCALL (IDT_OFFSET_SYSCALL - IDT_OFFSET)
459
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460static struct ioapic_irqmap {
461 int im_type; /* IOAPIC_IMT_ */
462 enum intr_trigger im_trig;
f6915355 463 enum intr_polarity im_pola;
a3dd9120 464 int im_gsi;
4234567c 465 int im_msi_base;
d1ae7328 466 uint32_t im_flags; /* IOAPIC_IMF_ */
6f072945 467} ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
a3dd9120 468
4234567c
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469static struct lwkt_token ioapic_irqmap_tok =
470 LWKT_TOKEN_INITIALIZER(ioapic_irqmap_token);
471
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472#define IOAPIC_IMT_UNUSED 0
473#define IOAPIC_IMT_RESERVED 1
f9593a5d 474#define IOAPIC_IMT_LEGACY 2
474ba684 475#define IOAPIC_IMT_SYSCALL 3
4234567c 476#define IOAPIC_IMT_MSI 4
9dbe6e38 477#define IOAPIC_IMT_MSIX 5
a3dd9120 478
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479#define IOAPIC_IMT_ISHWI(map) ((map)->im_type != IOAPIC_IMT_RESERVED && \
480 (map)->im_type != IOAPIC_IMT_SYSCALL)
481
d1ae7328
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482#define IOAPIC_IMF_CONF 0x1
483
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484extern void IOAPIC_INTREN(int);
485extern void IOAPIC_INTRDIS(int);
486
85bcaa51
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487extern int imcr_present;
488
35b2edcb
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489static void ioapic_abi_intr_enable(int);
490static void ioapic_abi_intr_disable(int);
f416026e
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491static void ioapic_abi_intr_setup(int, int);
492static void ioapic_abi_intr_teardown(int);
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493
494static void ioapic_abi_legacy_intr_config(int,
aea76754 495 enum intr_trigger, enum intr_polarity);
bec969af 496static int ioapic_abi_legacy_intr_cpuid(int);
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497static int ioapic_abi_legacy_intr_find(int,
498 enum intr_trigger, enum intr_polarity);
499static int ioapic_abi_legacy_intr_find_bygsi(int,
500 enum intr_trigger, enum intr_polarity);
35b2edcb 501
4234567c
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502static int ioapic_abi_msi_alloc(int [], int, int);
503static void ioapic_abi_msi_release(const int [], int, int);
504static void ioapic_abi_msi_map(int, uint64_t *, uint32_t *, int);
9dbe6e38
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505static int ioapic_abi_msix_alloc(int *, int);
506static void ioapic_abi_msix_release(int, int);
507
508static int ioapic_abi_msi_alloc_intern(int, const char *,
509 int [], int, int);
510static void ioapic_abi_msi_release_intern(int, const char *,
511 const int [], int, int);
4234567c 512
aea76754
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513static void ioapic_abi_finalize(void);
514static void ioapic_abi_cleanup(void);
515static void ioapic_abi_setdefault(void);
516static void ioapic_abi_stabilize(void);
517static void ioapic_abi_initmap(void);
981239a7 518static void ioapic_abi_rman_setup(struct rman *);
9e0e3f85 519
95874ffd 520static int ioapic_abi_gsi_cpuid(int, int);
343b4f3a 521static int ioapic_find_unused_irqmap(int);
95874ffd 522
9e0e3f85
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523struct machintr_abi MachIntrABI_IOAPIC = {
524 MACHINTR_IOAPIC,
35b2edcb
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525 .intr_disable = ioapic_abi_intr_disable,
526 .intr_enable = ioapic_abi_intr_enable,
f416026e
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527 .intr_setup = ioapic_abi_intr_setup,
528 .intr_teardown = ioapic_abi_intr_teardown,
bec969af
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529
530 .legacy_intr_config = ioapic_abi_legacy_intr_config,
531 .legacy_intr_cpuid = ioapic_abi_legacy_intr_cpuid,
86d692fe
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532 .legacy_intr_find = ioapic_abi_legacy_intr_find,
533 .legacy_intr_find_bygsi = ioapic_abi_legacy_intr_find_bygsi,
35b2edcb 534
4234567c
SZ
535 .msi_alloc = ioapic_abi_msi_alloc,
536 .msi_release = ioapic_abi_msi_release,
537 .msi_map = ioapic_abi_msi_map,
9dbe6e38
SZ
538 .msix_alloc = ioapic_abi_msix_alloc,
539 .msix_release = ioapic_abi_msix_release,
4234567c 540
aea76754
SZ
541 .finalize = ioapic_abi_finalize,
542 .cleanup = ioapic_abi_cleanup,
543 .setdefault = ioapic_abi_setdefault,
544 .stabilize = ioapic_abi_stabilize,
981239a7
SZ
545 .initmap = ioapic_abi_initmap,
546 .rman_setup = ioapic_abi_rman_setup
c8fe38ae
MD
547};
548
6b809ec7 549static int ioapic_abi_extint_irq = -1;
f9593a5d 550static int ioapic_abi_legacy_irq_max;
2b195d6a 551static int ioapic_abi_gsi_balance;
7b87350b 552static int ioapic_abi_msi_start; /* NOTE: for testing only */
6b809ec7 553
5ac5ccd2 554struct ioapic_irqinfo ioapic_irqs[IOAPIC_HWI_VECTORS];
566d27d4
SZ
555
556static void
35b2edcb 557ioapic_abi_intr_enable(int irq)
566d27d4 558{
aef690c8
SZ
559 const struct ioapic_irqmap *map;
560
561 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
ed20d0e3 562 ("ioapic enable, invalid irq %d", irq));
aef690c8
SZ
563
564 map = &ioapic_irqmaps[mycpuid][irq];
565 KASSERT(IOAPIC_IMT_ISHWI(map),
ed20d0e3 566 ("ioapic enable, not hwi irq %d, type %d, cpu%d",
aef690c8 567 irq, map->im_type, mycpuid));
f9593a5d 568 if (map->im_type != IOAPIC_IMT_LEGACY)
566d27d4 569 return;
aef690c8 570
566d27d4
SZ
571 IOAPIC_INTREN(irq);
572}
573
574static void
35b2edcb 575ioapic_abi_intr_disable(int irq)
566d27d4 576{
aef690c8
SZ
577 const struct ioapic_irqmap *map;
578
579 KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
ed20d0e3 580 ("ioapic disable, invalid irq %d", irq));
aef690c8
SZ
581
582 map = &ioapic_irqmaps[mycpuid][irq];
583 KASSERT(IOAPIC_IMT_ISHWI(map),
ed20d0e3 584 ("ioapic disable, not hwi irq %d, type %d, cpu%d",
aef690c8 585 irq, map->im_type, mycpuid));
f9593a5d 586 if (map->im_type != IOAPIC_IMT_LEGACY)
566d27d4 587 return;
aef690c8 588
566d27d4
SZ
589 IOAPIC_INTRDIS(irq);
590}
591
c8fe38ae 592static void
aea76754 593ioapic_abi_finalize(void)
c8fe38ae 594{
e0918665 595 KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
f45bfca0 596 KKASSERT(ioapic_enable);
10db3cc6 597
339478ac
SZ
598 /*
599 * If an IMCR is present, program bit 0 to disconnect the 8259
e0918665 600 * from the BSP.
339478ac 601 */
9d758cc4 602 if (imcr_present) {
339478ac
SZ
603 outb(0x22, 0x70); /* select IMCR */
604 outb(0x23, 0x01); /* disconnect 8259 */
605 }
c8fe38ae
MD
606}
607
608/*
609 * This routine is called after physical interrupts are enabled but before
610 * the critical section is released. We need to clean out any interrupts
611 * that had already been posted to the cpu.
612 */
613static void
aea76754 614ioapic_abi_cleanup(void)
c8fe38ae 615{
9611ff20 616 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
c8fe38ae
MD
617}
618
7bf5fa56
SZ
619/* Must never be called */
620static void
aea76754 621ioapic_abi_stabilize(void)
7bf5fa56 622{
ed20d0e3 623 panic("ioapic_stabilize is called");
7bf5fa56
SZ
624}
625
f416026e
SZ
626static void
627ioapic_abi_intr_setup(int intr, int flags)
c8fe38ae 628{
88100cf6 629 const struct ioapic_irqmap *map;
f416026e 630 int vector, select;
339478ac 631 uint32_t value;
7bf5fa56 632 register_t ef;
c8fe38ae 633
88100cf6 634 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 635 ("ioapic setup, invalid irq %d", intr));
88100cf6
SZ
636
637 map = &ioapic_irqmaps[mycpuid][intr];
638 KASSERT(IOAPIC_IMT_ISHWI(map),
639 ("ioapic setup, not hwi irq %d, type %d, cpu%d",
640 intr, map->im_type, mycpuid));
f9593a5d 641 if (map->im_type != IOAPIC_IMT_LEGACY)
88100cf6 642 return;
88100cf6
SZ
643
644 KASSERT(ioapic_irqs[intr].io_addr != NULL,
ed20d0e3 645 ("ioapic setup, no GSI information, irq %d", intr));
f416026e
SZ
646
647 ef = read_rflags();
648 cpu_disable_intr();
649
650 vector = IDT_OFFSET + intr;
f416026e
SZ
651
652 /*
653 * Now reprogram the vector in the IO APIC. In order to avoid
654 * losing an EOI for a level interrupt, which is vector based,
655 * make sure that the IO APIC is programmed for edge-triggering
656 * first, then reprogrammed with the new vector. This should
657 * clear the IRR bit.
658 */
659 imen_lock();
660
661 select = ioapic_irqs[intr].io_idx;
662 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
663 value |= IOART_INTMSET;
664
665 ioapic_write(ioapic_irqs[intr].io_addr, select,
666 (value & ~APIC_TRIGMOD_MASK));
667 ioapic_write(ioapic_irqs[intr].io_addr, select,
668 (value & ~IOART_INTVEC) | vector);
669
670 imen_unlock();
671
26cf64b2 672 IOAPIC_INTREN(intr);
c8fe38ae 673
f416026e
SZ
674 write_rflags(ef);
675}
676
677static void
678ioapic_abi_intr_teardown(int intr)
679{
88100cf6 680 const struct ioapic_irqmap *map;
f416026e
SZ
681 int vector, select;
682 uint32_t value;
683 register_t ef;
684
88100cf6 685 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 686 ("ioapic teardown, invalid irq %d", intr));
88100cf6
SZ
687
688 map = &ioapic_irqmaps[mycpuid][intr];
689 KASSERT(IOAPIC_IMT_ISHWI(map),
690 ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
691 intr, map->im_type, mycpuid));
f9593a5d 692 if (map->im_type != IOAPIC_IMT_LEGACY)
88100cf6 693 return;
88100cf6
SZ
694
695 KASSERT(ioapic_irqs[intr].io_addr != NULL,
ed20d0e3 696 ("ioapic teardown, no GSI information, irq %d", intr));
5ac5ccd2 697
339478ac
SZ
698 ef = read_rflags();
699 cpu_disable_intr();
f416026e
SZ
700
701 /*
702 * Teardown an interrupt vector. The vector should already be
703 * installed in the cpu's IDT, but make sure.
704 */
26cf64b2 705 IOAPIC_INTRDIS(intr);
f416026e
SZ
706
707 vector = IDT_OFFSET + intr;
f416026e
SZ
708
709 /*
710 * In order to avoid losing an EOI for a level interrupt, which
711 * is vector based, make sure that the IO APIC is programmed for
712 * edge-triggering first, then reprogrammed with the new vector.
713 * This should clear the IRR bit.
714 */
715 imen_lock();
716
717 select = ioapic_irqs[intr].io_idx;
718 value = ioapic_read(ioapic_irqs[intr].io_addr, select);
719
720 ioapic_write(ioapic_irqs[intr].io_addr, select,
721 (value & ~APIC_TRIGMOD_MASK));
722 ioapic_write(ioapic_irqs[intr].io_addr, select,
723 (value & ~IOART_INTVEC) | vector);
724
725 imen_unlock();
c8fe38ae 726
339478ac 727 write_rflags(ef);
339478ac 728}
c8fe38ae 729
10db3cc6 730static void
aea76754 731ioapic_abi_setdefault(void)
10db3cc6
SZ
732{
733 int intr;
734
9e0e3f85 735 for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
474ba684 736 if (intr == IOAPIC_HWI_SYSCALL)
10db3cc6 737 continue;
8a06c6ee
SZ
738 setidt_global(IDT_OFFSET + intr, ioapic_intr[intr],
739 SDT_SYSIGT, SEL_KPL, 0);
10db3cc6
SZ
740 }
741}
742
a3dd9120 743static void
aea76754 744ioapic_abi_initmap(void)
a3dd9120 745{
6f072945 746 int cpu;
a3dd9120 747
2b195d6a
SZ
748 kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
749
7b87350b
SZ
750 kgetenv_int("hw.ioapic.msi_start", &ioapic_abi_msi_start);
751 ioapic_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */
752
6f072945
SZ
753 /*
754 * NOTE: ncpus is not ready yet
755 */
756 for (cpu = 0; cpu < MAXCPU; ++cpu) {
757 int i;
758
4234567c 759 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
6f072945 760 ioapic_irqmaps[cpu][i].im_gsi = -1;
4234567c
SZ
761 ioapic_irqmaps[cpu][i].im_msi_base = -1;
762 }
6f072945
SZ
763 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
764 IOAPIC_IMT_SYSCALL;
765 }
a3dd9120
SZ
766}
767
343b4f3a
SZ
768static int
769ioapic_find_unused_irqmap(int gsi)
770{
771 int cpuid, i;
772
773 cpuid = ioapic_abi_gsi_cpuid(-1, gsi);
774
775 for (i = ISA_IRQ_CNT; i < IOAPIC_HWI_VECTORS; ++i) {
776 if (i == acpi_sci_irqno())
777 continue;
778 if (ioapic_irqmaps[cpuid][i].im_type == IOAPIC_IMT_UNUSED)
779 return i;
780 }
781 return -1;
782}
783
929c940f 784void
027bbbfe 785ioapic_set_legacy_irqmap(int irq, int gsi, enum intr_trigger trig,
929c940f
SZ
786 enum intr_polarity pola)
787{
5ac5ccd2 788 struct ioapic_irqinfo *info;
929c940f
SZ
789 struct ioapic_irqmap *map;
790 void *ioaddr;
95874ffd 791 int pin, cpuid;
929c940f
SZ
792
793 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
794 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
929c940f 795
343b4f3a
SZ
796 KKASSERT(irq >= 0);
797 if (irq >= IOAPIC_HWI_VECTORS) {
798 /*
799 * Some BIOSes seem to assume that all 256 IDT vectors
800 * could be used, while we limit the available IDT
801 * vectors to 192; find an unused IRQ for this GSI.
802 */
803 irq = ioapic_find_unused_irqmap(gsi);
804 if (irq < 0) {
805 kprintf("failed to find unused irq for gsi %d\n", gsi);
806 return;
807 }
808 }
809 KKASSERT(irq < IOAPIC_HWI_VECTORS);
810
f9593a5d
SZ
811 if (irq > ioapic_abi_legacy_irq_max)
812 ioapic_abi_legacy_irq_max = irq;
bf2e6ffb 813
6f072945
SZ
814 cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
815
816 map = &ioapic_irqmaps[cpuid][irq];
929c940f
SZ
817
818 KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
f9593a5d 819 map->im_type = IOAPIC_IMT_LEGACY;
929c940f
SZ
820
821 map->im_gsi = gsi;
822 map->im_trig = trig;
823 map->im_pola = pola;
824
825 if (bootverbose) {
4ecd5d4d
SZ
826 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
827 irq, map->im_gsi,
828 intr_str_trigger(map->im_trig),
829 intr_str_polarity(map->im_pola));
929c940f
SZ
830 }
831
d1ae7328
SZ
832 pin = ioapic_gsi_pin(map->im_gsi);
833 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
929c940f 834
5ac5ccd2 835 info = &ioapic_irqs[irq];
929c940f 836
7bceaa10
SZ
837 imen_lock();
838
5ac5ccd2
SZ
839 info->io_addr = ioaddr;
840 info->io_idx = IOAPIC_REDTBL + (2 * pin);
841 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
d1ae7328 842 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 843 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328
SZ
844
845 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 846 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
847
848 imen_unlock();
d1ae7328
SZ
849}
850
4a913811 851void
027bbbfe 852ioapic_fixup_legacy_irqmaps(void)
4a913811 853{
6f072945
SZ
854 int cpu;
855
856 for (cpu = 0; cpu < ncpus; ++cpu) {
857 int i;
4a913811 858
6f072945
SZ
859 for (i = 0; i < ISA_IRQ_CNT; ++i) {
860 struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
4a913811 861
6f072945
SZ
862 if (map->im_type == IOAPIC_IMT_UNUSED) {
863 map->im_type = IOAPIC_IMT_RESERVED;
864 if (bootverbose) {
865 kprintf("IOAPIC: "
866 "cpu%d irq %d reserved\n", cpu, i);
867 }
868 }
4a913811
SZ
869 }
870 }
6f072945 871
f9593a5d
SZ
872 ioapic_abi_legacy_irq_max += 1;
873 if (bootverbose) {
874 kprintf("IOAPIC: legacy irq max %d\n",
875 ioapic_abi_legacy_irq_max);
876 }
4a913811
SZ
877}
878
86d692fe
SZ
879static int
880ioapic_abi_legacy_intr_find_bygsi(int gsi, enum intr_trigger trig,
027bbbfe 881 enum intr_polarity pola)
e90e7ac4 882{
6f072945 883 int cpu;
e90e7ac4 884
86d692fe
SZ
885#ifdef INVARIANTS
886 if (trig == INTR_TRIGGER_CONFORM) {
887 KKASSERT(pola == INTR_POLARITY_CONFORM);
888 } else {
889 KKASSERT(trig == INTR_TRIGGER_EDGE ||
890 trig == INTR_TRIGGER_LEVEL);
891 KKASSERT(pola == INTR_POLARITY_HIGH ||
892 pola == INTR_POLARITY_LOW);
893 }
894#endif
e90e7ac4 895
6f072945
SZ
896 for (cpu = 0; cpu < ncpus; ++cpu) {
897 int irq;
e90e7ac4 898
f9593a5d 899 for (irq = 0; irq < ioapic_abi_legacy_irq_max; ++irq) {
6f072945
SZ
900 const struct ioapic_irqmap *map =
901 &ioapic_irqmaps[cpu][irq];
e90e7ac4 902
6f072945 903 if (map->im_gsi == gsi) {
f9593a5d 904 KKASSERT(map->im_type == IOAPIC_IMT_LEGACY);
6f072945 905
86d692fe
SZ
906 if ((map->im_flags & IOAPIC_IMF_CONF) &&
907 trig != INTR_TRIGGER_CONFORM &&
908 pola != INTR_POLARITY_CONFORM) {
6f072945
SZ
909 if (map->im_trig != trig ||
910 map->im_pola != pola)
911 return -1;
912 }
913 return irq;
e90e7ac4 914 }
e90e7ac4
SZ
915 }
916 }
917 return -1;
918}
919
86d692fe
SZ
920static int
921ioapic_abi_legacy_intr_find(int irq, enum intr_trigger trig,
027bbbfe 922 enum intr_polarity pola)
e90e7ac4 923{
6f072945 924 int cpu;
e90e7ac4 925
86d692fe
SZ
926#ifdef INVARIANTS
927 if (trig == INTR_TRIGGER_CONFORM) {
928 KKASSERT(pola == INTR_POLARITY_CONFORM);
929 } else {
930 KKASSERT(trig == INTR_TRIGGER_EDGE ||
931 trig == INTR_TRIGGER_LEVEL);
932 KKASSERT(pola == INTR_POLARITY_HIGH ||
933 pola == INTR_POLARITY_LOW);
934 }
935#endif
e90e7ac4 936
f9593a5d 937 if (irq < 0 || irq >= ioapic_abi_legacy_irq_max)
e90e7ac4 938 return -1;
e90e7ac4 939
6f072945
SZ
940 for (cpu = 0; cpu < ncpus; ++cpu) {
941 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
e90e7ac4 942
f9593a5d 943 if (map->im_type == IOAPIC_IMT_LEGACY) {
86d692fe
SZ
944 if ((map->im_flags & IOAPIC_IMF_CONF) &&
945 trig != INTR_TRIGGER_CONFORM &&
946 pola != INTR_POLARITY_CONFORM) {
6f072945
SZ
947 if (map->im_trig != trig ||
948 map->im_pola != pola)
949 return -1;
950 }
951 return irq;
952 }
e90e7ac4 953 }
6f072945 954 return -1;
e90e7ac4
SZ
955}
956
d1ae7328 957static void
bec969af
SZ
958ioapic_abi_legacy_intr_config(int irq, enum intr_trigger trig,
959 enum intr_polarity pola)
d1ae7328 960{
5ac5ccd2 961 struct ioapic_irqinfo *info;
6f072945 962 struct ioapic_irqmap *map = NULL;
d1ae7328 963 void *ioaddr;
95874ffd 964 int pin, cpuid;
d1ae7328 965
d1ae7328
SZ
966 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
967 KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
d1ae7328 968
f9593a5d 969 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
6f072945
SZ
970 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
971 map = &ioapic_irqmaps[cpuid][irq];
f9593a5d 972 if (map->im_type == IOAPIC_IMT_LEGACY)
6f072945
SZ
973 break;
974 }
975 KKASSERT(cpuid < ncpus);
d1ae7328 976
7962296e 977#ifdef notyet
d1ae7328
SZ
978 if (map->im_flags & IOAPIC_IMF_CONF) {
979 if (trig != map->im_trig) {
ed20d0e3 980 panic("ioapic_intr_config: trig %s -> %s",
4ecd5d4d
SZ
981 intr_str_trigger(map->im_trig),
982 intr_str_trigger(trig));
d1ae7328
SZ
983 }
984 if (pola != map->im_pola) {
ed20d0e3 985 panic("ioapic_intr_config: pola %s -> %s",
4ecd5d4d
SZ
986 intr_str_polarity(map->im_pola),
987 intr_str_polarity(pola));
d1ae7328
SZ
988 }
989 return;
990 }
7962296e 991#endif
d1ae7328
SZ
992 map->im_flags |= IOAPIC_IMF_CONF;
993
994 if (trig == map->im_trig && pola == map->im_pola)
995 return;
996
997 if (bootverbose) {
4ecd5d4d
SZ
998 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
999 irq, map->im_gsi,
1000 intr_str_trigger(map->im_trig),
1001 intr_str_polarity(map->im_pola),
1002 intr_str_trigger(trig),
1003 intr_str_polarity(pola));
d1ae7328 1004 }
d1ae7328
SZ
1005 map->im_trig = trig;
1006 map->im_pola = pola;
1007
1008 pin = ioapic_gsi_pin(map->im_gsi);
1009 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1010
5ac5ccd2 1011 info = &ioapic_irqs[irq];
d1ae7328 1012
7bceaa10
SZ
1013 imen_lock();
1014
5ac5ccd2 1015 info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
d1ae7328 1016 if (map->im_trig == INTR_TRIGGER_LEVEL)
5ac5ccd2 1017 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
929c940f 1018
ecec8ddc 1019 ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
95874ffd 1020 map->im_trig, map->im_pola, cpuid);
7bceaa10
SZ
1021
1022 imen_unlock();
929c940f
SZ
1023}
1024
6b809ec7 1025int
027bbbfe 1026ioapic_conf_legacy_extint(int irq)
6b809ec7 1027{
5ac5ccd2 1028 struct ioapic_irqinfo *info;
6b809ec7
SZ
1029 struct ioapic_irqmap *map;
1030 void *ioaddr;
1031 int pin, error, vec;
1032
95874ffd
SZ
1033 /* XXX only irq0 is allowed */
1034 KKASSERT(irq == 0);
1035
6b809ec7
SZ
1036 vec = IDT_OFFSET + irq;
1037
1038 if (ioapic_abi_extint_irq == irq)
1039 return 0;
1040 else if (ioapic_abi_extint_irq >= 0)
1041 return EEXIST;
1042
1043 error = icu_ioapic_extint(irq, vec);
1044 if (error)
1045 return error;
1046
6f072945
SZ
1047 /* ExtINT is always targeted to cpu0 */
1048 map = &ioapic_irqmaps[0][irq];
6b809ec7
SZ
1049
1050 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
f9593a5d
SZ
1051 map->im_type == IOAPIC_IMT_LEGACY);
1052 if (map->im_type == IOAPIC_IMT_LEGACY) {
6b809ec7
SZ
1053 if (map->im_flags & IOAPIC_IMF_CONF)
1054 return EEXIST;
1055 }
1056 ioapic_abi_extint_irq = irq;
1057
f9593a5d 1058 map->im_type = IOAPIC_IMT_LEGACY;
6b809ec7
SZ
1059 map->im_trig = INTR_TRIGGER_EDGE;
1060 map->im_pola = INTR_POLARITY_HIGH;
1061 map->im_flags = IOAPIC_IMF_CONF;
1062
1063 map->im_gsi = ioapic_extpin_gsi();
1064 KKASSERT(map->im_gsi >= 0);
1065
1066 if (bootverbose) {
4ecd5d4d
SZ
1067 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
1068 irq, map->im_gsi,
1069 intr_str_trigger(map->im_trig),
1070 intr_str_polarity(map->im_pola));
6b809ec7
SZ
1071 }
1072
1073 pin = ioapic_gsi_pin(map->im_gsi);
1074 ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
1075
5ac5ccd2 1076 info = &ioapic_irqs[irq];
6b809ec7
SZ
1077
1078 imen_lock();
1079
5ac5ccd2
SZ
1080 info->io_addr = ioaddr;
1081 info->io_idx = IOAPIC_REDTBL + (2 * pin);
1082 info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
6b809ec7
SZ
1083
1084 ioapic_extpin_setup(ioaddr, pin, vec);
1085
1086 imen_unlock();
1087
1088 return 0;
1089}
a05c798c
SZ
1090
1091static int
bec969af 1092ioapic_abi_legacy_intr_cpuid(int irq)
a05c798c 1093{
6f072945
SZ
1094 const struct ioapic_irqmap *map = NULL;
1095 int cpuid;
95874ffd 1096
f9593a5d 1097 KKASSERT(irq >= 0 && irq < ioapic_abi_legacy_irq_max);
95874ffd 1098
6f072945
SZ
1099 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1100 map = &ioapic_irqmaps[cpuid][irq];
f9593a5d 1101 if (map->im_type == IOAPIC_IMT_LEGACY)
6f072945 1102 return cpuid;
95874ffd
SZ
1103 }
1104
6f072945
SZ
1105 /* XXX some drivers tries to peek at reserved IRQs */
1106 for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1107 map = &ioapic_irqmaps[cpuid][irq];
1108 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1109 }
1110 return 0;
95874ffd
SZ
1111}
1112
1113static int
1114ioapic_abi_gsi_cpuid(int irq, int gsi)
1115{
1116 char envpath[32];
1117 int cpuid = -1;
1118
1119 KKASSERT(gsi >= 0);
1120
1121 if (irq == 0 || gsi == 0) {
343b4f3a 1122 KKASSERT(irq >= 0);
621d2ccf
SZ
1123 if (bootverbose) {
1124 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1125 irq, gsi);
1126 }
95874ffd
SZ
1127 return 0;
1128 }
1129
343b4f3a 1130 if (irq >= 0 && irq == acpi_sci_irqno()) {
621d2ccf
SZ
1131 if (bootverbose) {
1132 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1133 irq, gsi);
1134 }
95874ffd
SZ
1135 return 0;
1136 }
1137
1138 ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1139 kgetenv_int(envpath, &cpuid);
1140
1141 if (cpuid < 0) {
b8dfb6b1 1142 if (!ioapic_abi_gsi_balance) {
343b4f3a 1143 if (irq >= 0 && bootverbose) {
b8dfb6b1
SZ
1144 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1145 "(fixed)\n", irq, gsi);
1146 }
1147 return 0;
1148 }
1149
95874ffd 1150 cpuid = gsi % ncpus;
343b4f3a 1151 if (irq >= 0 && bootverbose) {
621d2ccf
SZ
1152 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1153 irq, gsi, cpuid);
1154 }
95874ffd
SZ
1155 } else if (cpuid >= ncpus) {
1156 cpuid = ncpus - 1;
343b4f3a 1157 if (irq >= 0 && bootverbose) {
621d2ccf
SZ
1158 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1159 irq, gsi, cpuid);
1160 }
95874ffd 1161 } else {
343b4f3a 1162 if (irq >= 0 && bootverbose) {
621d2ccf
SZ
1163 kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1164 irq, gsi, cpuid);
1165 }
95874ffd
SZ
1166 }
1167 return cpuid;
a05c798c 1168}
981239a7
SZ
1169
1170static void
1171ioapic_abi_rman_setup(struct rman *rm)
1172{
1173 int start, end, i;
1174
1175 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1176 ("invalid rman cpuid %d", rm->rm_cpuid));
1177
1178 start = end = -1;
1179 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1180 const struct ioapic_irqmap *map =
1181 &ioapic_irqmaps[rm->rm_cpuid][i];
1182
1183 if (start < 0) {
1184 if (IOAPIC_IMT_ISHWI(map))
1185 start = end = i;
1186 } else {
1187 if (IOAPIC_IMT_ISHWI(map)) {
1188 end = i;
1189 } else {
1190 KKASSERT(end >= 0);
1191 if (bootverbose) {
1192 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1193 rm->rm_cpuid, start, end);
1194 }
1195 if (rman_manage_region(rm, start, end)) {
1196 panic("rman_manage_region"
1197 "(cpu%d %d - %d)", rm->rm_cpuid,
1198 start, end);
1199 }
1200 start = end = -1;
1201 }
1202 }
1203 }
1204 if (start >= 0) {
1205 KKASSERT(end >= 0);
1206 if (bootverbose) {
1207 kprintf("IOAPIC: rman cpu%d %d - %d\n",
1208 rm->rm_cpuid, start, end);
1209 }
1210 if (rman_manage_region(rm, start, end)) {
1211 panic("rman_manage_region(cpu%d %d - %d)",
1212 rm->rm_cpuid, start, end);
1213 }
1214 }
1215}
4234567c
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1216
1217static int
9dbe6e38
SZ
1218ioapic_abi_msi_alloc_intern(int type, const char *desc,
1219 int intrs[], int count, int cpuid)
4234567c
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1220{
1221 int i, error;
1222
1223 KASSERT(cpuid >= 0 && cpuid < ncpus,
1224 ("invalid cpuid %d", cpuid));
1225
ed20d0e3 1226 KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
4234567c 1227 KASSERT((count & (count - 1)) == 0,
ed20d0e3 1228 ("count %d is not power of 2", count));
4234567c
SZ
1229
1230 lwkt_gettoken(&ioapic_irqmap_tok);
1231
1232 /*
1233 * NOTE:
1234 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
1235 * we do not need to find out the first properly aligned
1236 * interrupt vector.
1237 */
1238
2c3d7ac8 1239 error = EMSGSIZE;
7b87350b 1240 for (i = ioapic_abi_msi_start; i < IOAPIC_HWI_VECTORS; i += count) {
4234567c
SZ
1241 int j;
1242
1243 if (ioapic_irqmaps[cpuid][i].im_type != IOAPIC_IMT_UNUSED)
1244 continue;
1245
1246 for (j = 1; j < count; ++j) {
1247 if (ioapic_irqmaps[cpuid][i + j].im_type !=
1248 IOAPIC_IMT_UNUSED)
1249 break;
1250 }
1251 if (j != count)
1252 continue;
1253
1254 for (j = 0; j < count; ++j) {
1255 struct ioapic_irqmap *map;
1256 int intr = i + j;
1257
1258 map = &ioapic_irqmaps[cpuid][intr];
1259 KASSERT(map->im_msi_base < 0,
ed20d0e3 1260 ("intr %d, stale %s-base %d",
9dbe6e38 1261 intr, desc, map->im_msi_base));
4234567c 1262
9dbe6e38 1263 map->im_type = type;
4234567c
SZ
1264 map->im_msi_base = i;
1265
1266 intrs[j] = intr;
1267 msi_setup(intr, cpuid);
1268
1269 if (bootverbose) {
9dbe6e38
SZ
1270 kprintf("alloc %s intr %d on cpu%d\n",
1271 desc, intr, cpuid);
4234567c 1272 }
4234567c
SZ
1273 }
1274 error = 0;
1275 break;
1276 }
1277
1278 lwkt_reltoken(&ioapic_irqmap_tok);
1279
1280 return error;
1281}
1282
1283static void
9dbe6e38
SZ
1284ioapic_abi_msi_release_intern(int type, const char *desc,
1285 const int intrs[], int count, int cpuid)
4234567c
SZ
1286{
1287 int i, msi_base = -1, intr_next = -1, mask;
1288
1289 KASSERT(cpuid >= 0 && cpuid < ncpus,
1290 ("invalid cpuid %d", cpuid));
1291
ed20d0e3 1292 KASSERT(count > 0 && count <= 32, ("invalid count %d", count));
4234567c
SZ
1293
1294 mask = count - 1;
ed20d0e3 1295 KASSERT((count & mask) == 0, ("count %d is not power of 2", count));
4234567c
SZ
1296
1297 lwkt_gettoken(&ioapic_irqmap_tok);
1298
1299 for (i = 0; i < count; ++i) {
1300 struct ioapic_irqmap *map;
1301 int intr = intrs[i];
1302
1303 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 1304 ("invalid intr %d", intr));
4234567c
SZ
1305
1306 map = &ioapic_irqmaps[cpuid][intr];
9dbe6e38 1307 KASSERT(map->im_type == type,
ed20d0e3 1308 ("trying to release non-%s intr %d, type %d", desc,
4234567c
SZ
1309 intr, map->im_type));
1310 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
ed20d0e3 1311 ("intr %d, invalid %s-base %d", intr, desc,
9dbe6e38 1312 map->im_msi_base));
4234567c 1313 KASSERT((map->im_msi_base & mask) == 0,
ed20d0e3 1314 ("intr %d, %s-base %d is not properly aligned %d",
9dbe6e38 1315 intr, desc, map->im_msi_base, count));
4234567c
SZ
1316
1317 if (msi_base < 0) {
1318 msi_base = map->im_msi_base;
1319 } else {
1320 KASSERT(map->im_msi_base == msi_base,
9dbe6e38 1321 ("intr %d, inconsistent %s-base, "
ed20d0e3 1322 "was %d, now %d",
9dbe6e38 1323 intr, desc, msi_base, map->im_msi_base));
4234567c
SZ
1324 }
1325
1326 if (intr_next < intr)
1327 intr_next = intr;
1328
1329 map->im_type = IOAPIC_IMT_UNUSED;
1330 map->im_msi_base = -1;
1331
9dbe6e38
SZ
1332 if (bootverbose) {
1333 kprintf("release %s intr %d on cpu%d\n",
1334 desc, intr, cpuid);
1335 }
4234567c
SZ
1336 }
1337
1338 KKASSERT(intr_next > 0);
1339 KKASSERT(msi_base >= 0);
1340
1341 ++intr_next;
1342 if (intr_next < IOAPIC_HWI_VECTORS) {
1343 const struct ioapic_irqmap *map =
1344 &ioapic_irqmaps[cpuid][intr_next];
1345
9dbe6e38 1346 if (map->im_type == type) {
4234567c 1347 KASSERT(map->im_msi_base != msi_base,
ed20d0e3 1348 ("more than %d %s was allocated", count, desc));
4234567c
SZ
1349 }
1350 }
1351
1352 lwkt_reltoken(&ioapic_irqmap_tok);
1353}
1354
9dbe6e38
SZ
1355static int
1356ioapic_abi_msi_alloc(int intrs[], int count, int cpuid)
1357{
1358 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSI, "MSI",
1359 intrs, count, cpuid);
1360}
1361
1362static void
1363ioapic_abi_msi_release(const int intrs[], int count, int cpuid)
1364{
1365 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSI, "MSI",
1366 intrs, count, cpuid);
1367}
1368
1369static int
1370ioapic_abi_msix_alloc(int *intr, int cpuid)
1371{
1372 return ioapic_abi_msi_alloc_intern(IOAPIC_IMT_MSIX, "MSI-X",
1373 intr, 1, cpuid);
1374}
1375
1376static void
1377ioapic_abi_msix_release(int intr, int cpuid)
1378{
1379 ioapic_abi_msi_release_intern(IOAPIC_IMT_MSIX, "MSI-X",
1380 &intr, 1, cpuid);
1381}
1382
4234567c
SZ
1383static void
1384ioapic_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
1385{
1386 const struct ioapic_irqmap *map;
1387
1388 KASSERT(cpuid >= 0 && cpuid < ncpus,
1389 ("invalid cpuid %d", cpuid));
1390
1391 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
ed20d0e3 1392 ("invalid intr %d", intr));
4234567c
SZ
1393
1394 lwkt_gettoken(&ioapic_irqmap_tok);
1395
1396 map = &ioapic_irqmaps[cpuid][intr];
9dbe6e38
SZ
1397 KASSERT(map->im_type == IOAPIC_IMT_MSI ||
1398 map->im_type == IOAPIC_IMT_MSIX,
ed20d0e3 1399 ("trying to map non-MSI/MSI-X intr %d, type %d", intr, map->im_type));
4234567c 1400 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
ed20d0e3 1401 ("intr %d, invalid %s-base %d", intr,
9dbe6e38
SZ
1402 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1403 map->im_msi_base));
4234567c
SZ
1404
1405 msi_map(map->im_msi_base, addr, data, cpuid);
1406
9dbe6e38
SZ
1407 if (bootverbose) {
1408 kprintf("map %s intr %d on cpu%d\n",
1409 map->im_type == IOAPIC_IMT_MSI ? "MSI" : "MSI-X",
1410 intr, cpuid);
1411 }
4234567c
SZ
1412
1413 lwkt_reltoken(&ioapic_irqmap_tok);
1414}