mpt(4): Pass INTR_MPSAFE when setting up the interrupt.
[dragonfly.git] / sys / dev / disk / mpt / mpt_pci.c
CommitLineData
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1/*-
2 * PCI specific probe and attach routines for LSI Fusion Adapters
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3 * FreeBSD Version.
4 *
d751f32e 5 * Copyright (c) 2000, 2001 by Greg Ansley
984263bc 6 * Partially derived from Matt Jacob's ISP driver.
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7 * Copyright (c) 1997, 1998, 1999, 2000, 2001, 2002 by Matthew Jacob
8 * Feral Software
9 * All rights reserved.
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10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice immediately at the beginning of the file, without modification,
16 * this list of conditions, and the following disclaimer.
17 * 2. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
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32/*-
33 * Copyright (c) 2002, 2006 by Matthew Jacob
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are
38 * met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
42 * substantially similar to the "NO WARRANTY" disclaimer below
43 * ("Disclaimer") and any redistribution must be conditioned upon including
44 * a substantially similar Disclaimer requirement for further binary
45 * redistribution.
46 * 3. Neither the names of the above listed copyright holders nor the names
47 * of any contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
60 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 * Support from Chris Ellsworth in order to make SAS adapters work
63 * is gratefully acknowledged.
64 *
65 * Support from LSI-Logic has also gone a great deal toward making this a
66 * workable subsystem and is gratefully acknowledged.
67 */
984263bc 68/*
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69 * Copyright (c) 2004, Avid Technology, Inc. and its contributors.
70 * Copyright (c) 2005, WHEEL Sp. z o.o.
71 * Copyright (c) 2004, 2005 Justin T. Gibbs
72 * All rights reserved.
73 *
74 * Redistribution and use in source and binary forms, with or without
75 * modification, are permitted provided that the following conditions are
76 * met:
77 * 1. Redistributions of source code must retain the above copyright
78 * notice, this list of conditions and the following disclaimer.
79 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
80 * substantially similar to the "NO WARRANTY" disclaimer below
81 * ("Disclaimer") and any redistribution must be conditioned upon including
82 * a substantially similar Disclaimer requirement for further binary
83 * redistribution.
84 * 3. Neither the names of the above listed copyright holders nor the names
85 * of any contributors may be used to endorse or promote products derived
86 * from this software without specific prior written permission.
87 *
88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
91 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
92 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
93 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
94 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
95 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
96 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
97 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
98 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af04f7 99 *
6d259fc1 100 * $FreeBSD: src/sys/dev/mpt/mpt_pci.c,v 1.61 2011/04/22 09:59:16 marius Exp $
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101 */
102
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103#include <dev/disk/mpt/mpt.h>
104#include <dev/disk/mpt/mpt_cam.h>
105#include <dev/disk/mpt/mpt_raid.h>
984263bc 106
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107#ifndef PCI_VENDOR_LSI
108#define PCI_VENDOR_LSI 0x1000
109#endif
984263bc 110
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111#ifndef PCI_PRODUCT_LSI_FC909
112#define PCI_PRODUCT_LSI_FC909 0x0620
113#endif
114
115#ifndef PCI_PRODUCT_LSI_FC909A
116#define PCI_PRODUCT_LSI_FC909A 0x0621
117#endif
118
119#ifndef PCI_PRODUCT_LSI_FC919
120#define PCI_PRODUCT_LSI_FC919 0x0624
121#endif
122
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123#ifndef PCI_PRODUCT_LSI_FC919_LAN
124#define PCI_PRODUCT_LSI_FC919_LAN 0x0625
125#endif
126
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127#ifndef PCI_PRODUCT_LSI_FC929
128#define PCI_PRODUCT_LSI_FC929 0x0622
129#endif
130
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131#ifndef PCI_PRODUCT_LSI_FC929_LAN
132#define PCI_PRODUCT_LSI_FC929_LAN 0x0623
133#endif
134
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135#ifndef PCI_PRODUCT_LSI_FC929X
136#define PCI_PRODUCT_LSI_FC929X 0x0626
137#endif
138
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139#ifndef PCI_PRODUCT_LSI_FC929X_LAN
140#define PCI_PRODUCT_LSI_FC929X_LAN 0x0627
141#endif
142
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143#ifndef PCI_PRODUCT_LSI_FC919X
144#define PCI_PRODUCT_LSI_FC919X 0x0628
145#endif
146
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147#ifndef PCI_PRODUCT_LSI_FC919X_LAN
148#define PCI_PRODUCT_LSI_FC919X_LAN 0x0629
149#endif
150
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151#ifndef PCI_PRODUCT_LSI_FC7X04X
152#define PCI_PRODUCT_LSI_FC7X04X 0x0640
153#endif
154
155#ifndef PCI_PRODUCT_LSI_FC646
156#define PCI_PRODUCT_LSI_FC646 0x0646
157#endif
158
159#ifndef PCI_PRODUCT_LSI_1030
160#define PCI_PRODUCT_LSI_1030 0x0030
161#endif
162
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163#ifndef PCI_PRODUCT_LSI_1030ZC
164#define PCI_PRODUCT_LSI_1030ZC 0x0031
165#endif
166
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167#ifndef PCI_PRODUCT_LSI_SAS1064
168#define PCI_PRODUCT_LSI_SAS1064 0x0050
169#endif
170
171#ifndef PCI_PRODUCT_LSI_SAS1064A
172#define PCI_PRODUCT_LSI_SAS1064A 0x005C
173#endif
174
175#ifndef PCI_PRODUCT_LSI_SAS1064E
176#define PCI_PRODUCT_LSI_SAS1064E 0x0056
177#endif
178
179#ifndef PCI_PRODUCT_LSI_SAS1066
180#define PCI_PRODUCT_LSI_SAS1066 0x005E
181#endif
182
183#ifndef PCI_PRODUCT_LSI_SAS1066E
184#define PCI_PRODUCT_LSI_SAS1066E 0x005A
185#endif
186
187#ifndef PCI_PRODUCT_LSI_SAS1068
188#define PCI_PRODUCT_LSI_SAS1068 0x0054
189#endif
190
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191#ifndef PCI_PRODUCT_LSI_SAS1068A
192#define PCI_PRODUCT_LSI_SAS1068A 0x0055
193#endif
194
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195#ifndef PCI_PRODUCT_LSI_SAS1068E
196#define PCI_PRODUCT_LSI_SAS1068E 0x0058
197#endif
198
199#ifndef PCI_PRODUCT_LSI_SAS1078
200#define PCI_PRODUCT_LSI_SAS1078 0x0062
201#endif
202
203#ifndef PCI_PRODUCT_LSI_SAS1078DE
204#define PCI_PRODUCT_LSI_SAS1078DE 0x007C
205#endif
984263bc 206
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207#ifndef PCIM_CMD_SERRESPEN
208#define PCIM_CMD_SERRESPEN 0x0100
209#endif
210
211
212
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213static int mpt_pci_probe(device_t);
214static int mpt_pci_attach(device_t);
215static void mpt_free_bus_resources(struct mpt_softc *mpt);
216static int mpt_pci_detach(device_t);
217static int mpt_pci_shutdown(device_t);
218static int mpt_dma_mem_alloc(struct mpt_softc *mpt);
219static void mpt_dma_mem_free(struct mpt_softc *mpt);
220static void mpt_read_config_regs(struct mpt_softc *mpt);
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221static void mpt_pci_intr(void *);
222
223static device_method_t mpt_methods[] = {
224 /* Device interface */
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225 DEVMETHOD(device_probe, mpt_pci_probe),
226 DEVMETHOD(device_attach, mpt_pci_attach),
227 DEVMETHOD(device_detach, mpt_pci_detach),
228 DEVMETHOD(device_shutdown, mpt_pci_shutdown),
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229 { 0, 0 }
230};
231
232static driver_t mpt_driver = {
d751f32e 233 "mpt", mpt_methods, sizeof(struct mpt_softc)
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234};
235static devclass_t mpt_devclass;
aa2b9d05 236DRIVER_MODULE(mpt, pci, mpt_driver, mpt_devclass, NULL, NULL);
d751f32e 237MODULE_DEPEND(mpt, pci, 1, 1, 1);
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238MODULE_VERSION(mpt, 1);
239
984263bc 240static int
d751f32e 241mpt_pci_probe(device_t dev)
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242{
243 char *desc;
244
d751f32e 245 if (pci_get_vendor(dev) != PCI_VENDOR_LSI) {
984263bc 246 return (ENXIO);
d751f32e 247 }
984263bc 248
a261e0e0 249 switch (pci_get_device(dev)) {
d751f32e 250 case PCI_PRODUCT_LSI_FC909:
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251 desc = "LSILogic FC909 FC Adapter";
252 break;
d751f32e 253 case PCI_PRODUCT_LSI_FC909A:
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254 desc = "LSILogic FC909A FC Adapter";
255 break;
d751f32e 256 case PCI_PRODUCT_LSI_FC919:
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257 desc = "LSILogic FC919 FC Adapter";
258 break;
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259 case PCI_PRODUCT_LSI_FC919_LAN:
260 desc = "LSILogic FC919 LAN Adapter";
261 break;
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262 case PCI_PRODUCT_LSI_FC929:
263 desc = "Dual LSILogic FC929 FC Adapter";
984263bc 264 break;
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265 case PCI_PRODUCT_LSI_FC929_LAN:
266 desc = "Dual LSILogic FC929 LAN Adapter";
267 break;
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268 case PCI_PRODUCT_LSI_FC919X:
269 desc = "LSILogic FC919 FC PCI-X Adapter";
d30c73c7 270 break;
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271 case PCI_PRODUCT_LSI_FC919X_LAN:
272 desc = "LSILogic FC919 LAN PCI-X Adapter";
273 break;
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274 case PCI_PRODUCT_LSI_FC929X:
275 desc = "Dual LSILogic FC929X 2Gb/s FC PCI-X Adapter";
276 break;
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277 case PCI_PRODUCT_LSI_FC929X_LAN:
278 desc = "Dual LSILogic FC929X LAN PCI-X Adapter";
279 break;
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280 case PCI_PRODUCT_LSI_FC646:
281 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-Express Adapter";
282 break;
283 case PCI_PRODUCT_LSI_FC7X04X:
284 desc = "Dual LSILogic FC7X04X 4Gb/s FC PCI-X Adapter";
285 break;
286 case PCI_PRODUCT_LSI_1030:
a261e0e0 287 case PCI_PRODUCT_LSI_1030ZC:
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288 desc = "LSILogic 1030 Ultra4 Adapter";
289 break;
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290 case PCI_PRODUCT_LSI_SAS1064:
291 case PCI_PRODUCT_LSI_SAS1064A:
292 case PCI_PRODUCT_LSI_SAS1064E:
293 case PCI_PRODUCT_LSI_SAS1066:
294 case PCI_PRODUCT_LSI_SAS1066E:
295 case PCI_PRODUCT_LSI_SAS1068:
a261e0e0 296 case PCI_PRODUCT_LSI_SAS1068A:
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297 case PCI_PRODUCT_LSI_SAS1068E:
298 case PCI_PRODUCT_LSI_SAS1078:
299 case PCI_PRODUCT_LSI_SAS1078DE:
300 desc = "LSILogic SAS/SATA Adapter";
301 break;
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302 default:
303 return (ENXIO);
304 }
305
306 device_set_desc(dev, desc);
307 return (0);
308}
309
984263bc 310static void
d751f32e 311mpt_set_options(struct mpt_softc *mpt)
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312{
313 int bitmap;
314
315 bitmap = 0;
2545bca0 316 if (kgetenv_int("mpt_disable", &bitmap)) {
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317 if (bitmap & (1 << mpt->unit)) {
318 mpt->disabled = 1;
319 }
320 }
d751f32e 321 bitmap = 0;
2545bca0 322 if (kgetenv_int("mpt_debug", &bitmap)) {
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323 if (bitmap & (1 << mpt->unit)) {
324 mpt->verbose = MPT_PRT_DEBUG;
325 }
326 }
327 bitmap = 0;
2545bca0 328 if (kgetenv_int("mpt_debug1", &bitmap)) {
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329 if (bitmap & (1 << mpt->unit)) {
330 mpt->verbose = MPT_PRT_DEBUG1;
331 }
332 }
333 bitmap = 0;
2545bca0 334 if (kgetenv_int("mpt_debug2", &bitmap)) {
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335 if (bitmap & (1 << mpt->unit)) {
336 mpt->verbose = MPT_PRT_DEBUG2;
337 }
338 }
339 bitmap = 0;
2545bca0 340 if (kgetenv_int("mpt_debug3", &bitmap)) {
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341 if (bitmap & (1 << mpt->unit)) {
342 mpt->verbose = MPT_PRT_DEBUG3;
343 }
344 }
984263bc 345
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346 mpt->cfg_role = MPT_ROLE_DEFAULT;
347 bitmap = 0;
2545bca0 348 if (kgetenv_int("mpt_nil_role", &bitmap)) {
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349 if (bitmap & (1 << mpt->unit)) {
350 mpt->cfg_role = 0;
351 }
352 mpt->do_cfg_role = 1;
353 }
354 bitmap = 0;
2545bca0 355 if (kgetenv_int("mpt_tgt_role", &bitmap)) {
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356 if (bitmap & (1 << mpt->unit)) {
357 mpt->cfg_role |= MPT_ROLE_TARGET;
358 }
359 mpt->do_cfg_role = 1;
360 }
984263bc 361 bitmap = 0;
2545bca0 362 if (kgetenv_int("mpt_ini_role", &bitmap)) {
984263bc 363 if (bitmap & (1 << mpt->unit)) {
d751f32e 364 mpt->cfg_role |= MPT_ROLE_INITIATOR;
984263bc 365 }
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366 mpt->do_cfg_role = 1;
367 }
368 mpt->msi_enable = 0;
369}
d751f32e 370
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371
372static void
d751f32e 373mpt_link_peer(struct mpt_softc *mpt)
984263bc 374{
d751f32e 375 struct mpt_softc *mpt2;
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376
377 if (mpt->unit == 0) {
378 return;
379 }
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380 /*
381 * XXX: depends on probe order
382 */
d751f32e 383 mpt2 = (struct mpt_softc *)devclass_get_softc(mpt_devclass,mpt->unit-1);
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384
385 if (mpt2 == NULL) {
386 return;
387 }
388 if (pci_get_vendor(mpt2->dev) != pci_get_vendor(mpt->dev)) {
389 return;
390 }
391 if (pci_get_device(mpt2->dev) != pci_get_device(mpt->dev)) {
392 return;
393 }
394 mpt->mpt2 = mpt2;
395 mpt2->mpt2 = mpt;
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396 if (mpt->verbose >= MPT_PRT_DEBUG) {
397 mpt_prt(mpt, "linking with peer (mpt%d)\n",
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398 device_get_unit(mpt2->dev));
399 }
400}
401
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402static void
403mpt_unlink_peer(struct mpt_softc *mpt)
404{
405 if (mpt->mpt2) {
406 mpt->mpt2->mpt2 = NULL;
407 }
408}
409
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410
411static int
d751f32e 412mpt_pci_attach(device_t dev)
984263bc 413{
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414 struct mpt_softc *mpt;
415 int iqd;
416 uint32_t data, cmd;
6d259fc1 417 int mpt_io_bar, mpt_mem_bar;
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418
419 /* Allocate the softc structure */
d751f32e 420 mpt = (struct mpt_softc*)device_get_softc(dev);
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421 if (mpt == NULL) {
422 device_printf(dev, "cannot allocate softc\n");
423 return (ENOMEM);
424 }
d751f32e 425 memset(mpt, 0, sizeof(struct mpt_softc));
a261e0e0 426 switch (pci_get_device(dev)) {
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427 case PCI_PRODUCT_LSI_FC909:
428 case PCI_PRODUCT_LSI_FC909A:
429 case PCI_PRODUCT_LSI_FC919:
a261e0e0 430 case PCI_PRODUCT_LSI_FC919_LAN:
d751f32e 431 case PCI_PRODUCT_LSI_FC929:
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432 case PCI_PRODUCT_LSI_FC929_LAN:
433 case PCI_PRODUCT_LSI_FC929X:
434 case PCI_PRODUCT_LSI_FC929X_LAN:
d751f32e 435 case PCI_PRODUCT_LSI_FC919X:
a261e0e0 436 case PCI_PRODUCT_LSI_FC919X_LAN:
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437 case PCI_PRODUCT_LSI_FC646:
438 case PCI_PRODUCT_LSI_FC7X04X:
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439 mpt->is_fc = 1;
440 break;
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441 case PCI_PRODUCT_LSI_SAS1064:
442 case PCI_PRODUCT_LSI_SAS1064A:
443 case PCI_PRODUCT_LSI_SAS1064E:
444 case PCI_PRODUCT_LSI_SAS1066:
445 case PCI_PRODUCT_LSI_SAS1066E:
446 case PCI_PRODUCT_LSI_SAS1068:
a261e0e0 447 case PCI_PRODUCT_LSI_SAS1068A:
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448 case PCI_PRODUCT_LSI_SAS1068E:
449 case PCI_PRODUCT_LSI_SAS1078:
450 case PCI_PRODUCT_LSI_SAS1078DE:
451 mpt->is_sas = 1;
452 break;
984263bc 453 default:
d751f32e 454 mpt->is_spi = 1;
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MD
455 break;
456 }
457 mpt->dev = dev;
458 mpt->unit = device_get_unit(dev);
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459 mpt->raid_resync_rate = MPT_RAID_RESYNC_RATE_DEFAULT;
460 mpt->raid_mwce_setting = MPT_RAID_MWCE_DEFAULT;
461 mpt->raid_queue_depth = MPT_RAID_QUEUE_DEPTH_DEFAULT;
462 mpt->verbose = MPT_PRT_NONE;
463 mpt->role = MPT_ROLE_NONE;
6d259fc1 464 mpt->mpt_ini_id = MPT_INI_ID_NONE;
984263bc 465 mpt_set_options(mpt);
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466 if (mpt->verbose == MPT_PRT_NONE) {
467 mpt->verbose = MPT_PRT_WARN;
468 /* Print INFO level (if any) if bootverbose is set */
469 mpt->verbose += (bootverbose != 0)? 1 : 0;
470 }
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MD
471 /* Make sure memory access decoders are enabled */
472 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
473 if ((cmd & PCIM_CMD_MEMEN) == 0) {
474 device_printf(dev, "Memory accesses disabled");
d751f32e 475 return (ENXIO);
984263bc
MD
476 }
477
478 /*
479 * Make sure that SERR, PERR, WRITE INVALIDATE and BUSMASTER are set.
480 */
481 cmd |=
482 PCIM_CMD_SERRESPEN | PCIM_CMD_PERRESPEN |
483 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MWRICEN;
484 pci_write_config(dev, PCIR_COMMAND, cmd, 2);
485
486 /*
487 * Make sure we've disabled the ROM.
488 */
489 data = pci_read_config(dev, PCIR_BIOS, 4);
6d259fc1 490 data &= ~PCIM_BIOS_ENABLE;
984263bc
MD
491 pci_write_config(dev, PCIR_BIOS, data, 4);
492
984263bc
MD
493 /*
494 * Is this part a dual?
495 * If so, link with our partner (around yet)
496 */
a261e0e0
SW
497 switch (pci_get_device(dev)) {
498 case PCI_PRODUCT_LSI_FC929:
499 case PCI_PRODUCT_LSI_FC929_LAN:
500 case PCI_PRODUCT_LSI_FC646:
501 case PCI_PRODUCT_LSI_FC7X04X:
502 case PCI_PRODUCT_LSI_1030:
503 case PCI_PRODUCT_LSI_1030ZC:
984263bc 504 mpt_link_peer(mpt);
a261e0e0
SW
505 break;
506 default:
507 break;
984263bc
MD
508 }
509
6d259fc1
SW
510 /*
511 * Figure out which are the I/O and MEM Bars
512 */
513 data = pci_read_config(dev, PCIR_BAR(0), 4);
514 if (PCI_BAR_IO(data)) {
515 /* BAR0 is IO, BAR1 is memory */
516 mpt_io_bar = 0;
517 mpt_mem_bar = 1;
518 } else {
519 /* BAR0 is memory, BAR1 is IO */
520 mpt_mem_bar = 0;
521 mpt_io_bar = 1;
522 }
523
d751f32e
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524 /*
525 * Set up register access. PIO mode is required for
526 * certain reset operations (but must be disabled for
527 * some cards otherwise).
528 */
6d259fc1
SW
529 mpt->pci_pio_rid = PCIR_BAR(mpt_io_bar);
530 mpt->pci_pio_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
531 &mpt->pci_pio_rid, RF_ACTIVE);
d751f32e
MD
532 if (mpt->pci_pio_reg == NULL) {
533 device_printf(dev, "unable to map registers in PIO mode\n");
534 goto bad;
535 }
536 mpt->pci_pio_st = rman_get_bustag(mpt->pci_pio_reg);
537 mpt->pci_pio_sh = rman_get_bushandle(mpt->pci_pio_reg);
538
984263bc 539 /* Allocate kernel virtual memory for the 9x9's Mem0 region */
6d259fc1
SW
540 mpt->pci_mem_rid = PCIR_BAR(mpt_mem_bar);
541 mpt->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
542 &mpt->pci_mem_rid, RF_ACTIVE);
984263bc 543 if (mpt->pci_reg == NULL) {
d751f32e
MD
544 device_printf(dev, "Unable to memory map registers.\n");
545 if (mpt->is_sas) {
546 device_printf(dev, "Giving Up.\n");
547 goto bad;
548 }
549 device_printf(dev, "Falling back to PIO mode.\n");
550 mpt->pci_st = mpt->pci_pio_st;
551 mpt->pci_sh = mpt->pci_pio_sh;
552 } else {
553 mpt->pci_st = rman_get_bustag(mpt->pci_reg);
554 mpt->pci_sh = rman_get_bushandle(mpt->pci_reg);
984263bc 555 }
984263bc
MD
556
557 /* Get a handle to the interrupt */
558 iqd = 0;
9dc47ee5 559#ifdef OLD_MSI
d751f32e
MD
560 if (mpt->msi_enable) {
561 /*
562 * First try to alloc an MSI-X message. If that
563 * fails, then try to alloc an MSI message instead.
564 */
565 if (pci_msix_count(dev) == 1) {
566 mpt->pci_msi_count = 1;
567 if (pci_alloc_msix(dev, &mpt->pci_msi_count) == 0) {
568 iqd = 1;
569 } else {
570 mpt->pci_msi_count = 0;
571 }
572 }
573 if (iqd == 0 && pci_msi_count(dev) == 1) {
574 mpt->pci_msi_count = 1;
575 if (pci_alloc_msi(dev, &mpt->pci_msi_count) == 0) {
576 iqd = 1;
577 } else {
578 mpt->pci_msi_count = 0;
579 }
580 }
581 }
9dc47ee5 582#endif
d751f32e
MD
583 mpt->pci_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &iqd,
584 RF_ACTIVE | RF_SHAREABLE);
984263bc
MD
585 if (mpt->pci_irq == NULL) {
586 device_printf(dev, "could not allocate interrupt\n");
587 goto bad;
588 }
589
984263bc
MD
590 MPT_LOCK_SETUP(mpt);
591
592 /* Disable interrupts at the part */
593 mpt_disable_ints(mpt);
594
d751f32e 595 /* Register the interrupt handler */
3592c6a6 596 if (mpt_setup_intr(dev, mpt->pci_irq, MPT_IFLAGS, NULL, mpt_pci_intr,
d751f32e
MD
597 mpt, &mpt->ih)) {
598 device_printf(dev, "could not setup interrupt\n");
599 goto bad;
600 }
601
984263bc 602 /* Allocate dma memory */
6d259fc1 603/* XXX JGibbs -Should really be done based on IOCFacts. */
984263bc 604 if (mpt_dma_mem_alloc(mpt)) {
d751f32e 605 mpt_prt(mpt, "Could not allocate DMA memory\n");
984263bc
MD
606 goto bad;
607 }
608
609 /*
610 * Save the PCI config register values
611 *
612 * Hard resets are known to screw up the BAR for diagnostic
613 * memory accesses (Mem1).
614 *
6d259fc1 615 * Using Mem1 is known to make the chip stop responding to
984263bc
MD
616 * configuration space transfers, so we need to save it now
617 */
618
619 mpt_read_config_regs(mpt);
620
d751f32e
MD
621 /*
622 * Disable PIO until we need it
623 */
624 if (mpt->is_sas) {
625 pci_disable_io(dev, SYS_RES_IOPORT);
626 }
627
984263bc
MD
628 /* Initialize the hardware */
629 if (mpt->disabled == 0) {
d751f32e 630 if (mpt_attach(mpt) != 0) {
984263bc
MD
631 goto bad;
632 }
d751f32e
MD
633 } else {
634 mpt_prt(mpt, "device disabled at user request\n");
635 goto bad;
984263bc
MD
636 }
637
d751f32e
MD
638 mpt->eh = EVENTHANDLER_REGISTER(shutdown_post_sync, mpt_pci_shutdown,
639 dev, SHUTDOWN_PRI_DEFAULT);
640
641 if (mpt->eh == NULL) {
642 mpt_prt(mpt, "shutdown event registration failed\n");
643 (void) mpt_detach(mpt);
644 goto bad;
645 }
984263bc
MD
646 return (0);
647
648bad:
649 mpt_dma_mem_free(mpt);
650 mpt_free_bus_resources(mpt);
d751f32e
MD
651 mpt_unlink_peer(mpt);
652
653 MPT_LOCK_DESTROY(mpt);
984263bc
MD
654
655 /*
656 * but return zero to preserve unit numbering
657 */
658 return (0);
659}
660
661/*
662 * Free bus resources
663 */
664static void
d751f32e 665mpt_free_bus_resources(struct mpt_softc *mpt)
984263bc
MD
666{
667 if (mpt->ih) {
668 bus_teardown_intr(mpt->dev, mpt->pci_irq, mpt->ih);
669 mpt->ih = 0;
670 }
671
672 if (mpt->pci_irq) {
d751f32e
MD
673 bus_release_resource(mpt->dev, SYS_RES_IRQ,
674 mpt->pci_msi_count ? 1 : 0, mpt->pci_irq);
984263bc
MD
675 mpt->pci_irq = 0;
676 }
677
d751f32e
MD
678 if (mpt->pci_msi_count) {
679 pci_release_msi(mpt->dev);
680 mpt->pci_msi_count = 0;
681 }
682
683 if (mpt->pci_pio_reg) {
684 bus_release_resource(mpt->dev, SYS_RES_IOPORT, mpt->pci_pio_rid,
685 mpt->pci_pio_reg);
686 mpt->pci_pio_reg = 0;
687 }
984263bc 688 if (mpt->pci_reg) {
d751f32e 689 bus_release_resource(mpt->dev, SYS_RES_MEMORY, mpt->pci_mem_rid,
984263bc
MD
690 mpt->pci_reg);
691 mpt->pci_reg = 0;
692 }
693 MPT_LOCK_DESTROY(mpt);
694}
695
696
697/*
698 * Disconnect ourselves from the system.
699 */
700static int
d751f32e 701mpt_pci_detach(device_t dev)
984263bc 702{
d751f32e 703 struct mpt_softc *mpt;
984263bc 704
d751f32e 705 mpt = (struct mpt_softc*)device_get_softc(dev);
984263bc
MD
706
707 if (mpt) {
708 mpt_disable_ints(mpt);
d751f32e
MD
709 mpt_detach(mpt);
710 mpt_reset(mpt, /*reinit*/FALSE);
984263bc
MD
711 mpt_dma_mem_free(mpt);
712 mpt_free_bus_resources(mpt);
d751f32e
MD
713 mpt_raid_free_mem(mpt);
714 if (mpt->eh != NULL) {
715 EVENTHANDLER_DEREGISTER(shutdown_post_sync, mpt->eh);
716 }
984263bc
MD
717 }
718 return(0);
719}
720
721
722/*
723 * Disable the hardware
724 */
725static int
d751f32e 726mpt_pci_shutdown(device_t dev)
984263bc 727{
d751f32e 728 struct mpt_softc *mpt;
984263bc 729
d751f32e 730 mpt = (struct mpt_softc *)device_get_softc(dev);
984263bc 731 if (mpt) {
d751f32e
MD
732 int r;
733 r = mpt_shutdown(mpt);
734 return (r);
984263bc
MD
735 }
736 return(0);
737}
738
984263bc 739static int
d751f32e 740mpt_dma_mem_alloc(struct mpt_softc *mpt)
984263bc 741{
984263bc 742 size_t len;
d751f32e 743 struct mpt_map_info mi;
984263bc
MD
744
745 /* Check if we alreay have allocated the reply memory */
3641b7ca 746 if (mpt->reply_phys != 0) {
984263bc
MD
747 return 0;
748 }
749
d751f32e 750 len = sizeof (request_t) * MPT_MAX_REQUESTS(mpt);
2545bca0 751 mpt->request_pool = (request_t *)kmalloc(len, M_DEVBUF, M_WAITOK|M_ZERO);
d751f32e
MD
752 if (mpt->request_pool == NULL) {
753 mpt_prt(mpt, "cannot allocate request pool\n");
754 return (1);
755 }
984263bc
MD
756
757 /*
d751f32e 758 * Create a parent dma tag for this device.
984263bc 759 *
d751f32e
MD
760 * Align at byte boundaries,
761 * Limit to 32-bit addressing for request/reply queues.
984263bc 762 */
6d259fc1 763 if (mpt_dma_tag_create(mpt, /*parent*/NULL,
d751f32e
MD
764 /*alignment*/1, /*boundary*/0, /*lowaddr*/BUS_SPACE_MAXADDR,
765 /*highaddr*/BUS_SPACE_MAXADDR, /*filter*/NULL, /*filterarg*/NULL,
766 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
6d259fc1
SW
767 /*nsegments*/BUS_SPACE_UNRESTRICTED,
768 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
984263bc 769 &mpt->parent_dmat) != 0) {
d751f32e 770 mpt_prt(mpt, "cannot create parent dma tag\n");
984263bc
MD
771 return (1);
772 }
773
774 /* Create a child tag for reply buffers */
d751f32e
MD
775 if (mpt_dma_tag_create(mpt, mpt->parent_dmat, PAGE_SIZE, 0,
776 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
777 NULL, NULL, 2 * PAGE_SIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0,
984263bc 778 &mpt->reply_dmat) != 0) {
d751f32e 779 mpt_prt(mpt, "cannot create a dma tag for replies\n");
984263bc
MD
780 return (1);
781 }
782
6d259fc1 783 /* Allocate some DMA accessible memory for replies */
984263bc
MD
784 if (bus_dmamem_alloc(mpt->reply_dmat, (void **)&mpt->reply,
785 BUS_DMA_NOWAIT, &mpt->reply_dmap) != 0) {
d751f32e
MD
786 mpt_prt(mpt, "cannot allocate %lu bytes of reply memory\n",
787 (u_long) (2 * PAGE_SIZE));
984263bc
MD
788 return (1);
789 }
790
d751f32e
MD
791 mi.mpt = mpt;
792 mi.error = 0;
984263bc
MD
793
794 /* Load and lock it into "bus space" */
795 bus_dmamap_load(mpt->reply_dmat, mpt->reply_dmap, mpt->reply,
d751f32e 796 2 * PAGE_SIZE, mpt_map_rquest, &mi, 0);
984263bc 797
d751f32e
MD
798 if (mi.error) {
799 mpt_prt(mpt, "error %d loading dma map for DMA reply queue\n",
800 mi.error);
984263bc
MD
801 return (1);
802 }
d751f32e 803 mpt->reply_phys = mi.phys;
984263bc 804
984263bc
MD
805 return (0);
806}
807
808
809
6d259fc1 810/* Deallocate memory that was allocated by mpt_dma_mem_alloc
984263bc
MD
811 */
812static void
d751f32e 813mpt_dma_mem_free(struct mpt_softc *mpt)
984263bc 814{
984263bc
MD
815
816 /* Make sure we aren't double destroying */
817 if (mpt->reply_dmat == 0) {
d751f32e 818 mpt_lprt(mpt, MPT_PRT_DEBUG, "already released dma memory\n");
984263bc
MD
819 return;
820 }
6d259fc1 821
984263bc
MD
822 bus_dmamap_unload(mpt->reply_dmat, mpt->reply_dmap);
823 bus_dmamem_free(mpt->reply_dmat, mpt->reply, mpt->reply_dmap);
824 bus_dma_tag_destroy(mpt->reply_dmat);
825 bus_dma_tag_destroy(mpt->parent_dmat);
826 mpt->reply_dmat = 0;
2545bca0 827 kfree(mpt->request_pool, M_DEVBUF);
984263bc
MD
828 mpt->request_pool = 0;
829
830}
831
832
833
834/* Reads modifiable (via PCI transactions) config registers */
835static void
d751f32e 836mpt_read_config_regs(struct mpt_softc *mpt)
984263bc
MD
837{
838 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
839 mpt->pci_cfg.LatencyTimer_LineSize =
840 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
d751f32e
MD
841 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
842 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
843 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
844 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
845 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(4), 4);
984263bc
MD
846 mpt->pci_cfg.ROM_BAR = pci_read_config(mpt->dev, PCIR_BIOS, 4);
847 mpt->pci_cfg.IntLine = pci_read_config(mpt->dev, PCIR_INTLINE, 1);
848 mpt->pci_cfg.PMCSR = pci_read_config(mpt->dev, 0x44, 4);
849}
850
851/* Sets modifiable config registers */
852void
d751f32e 853mpt_set_config_regs(struct mpt_softc *mpt)
984263bc 854{
d751f32e 855 uint32_t val;
984263bc
MD
856
857#define MPT_CHECK(reg, offset, size) \
858 val = pci_read_config(mpt->dev, offset, size); \
859 if (mpt->pci_cfg.reg != val) { \
d751f32e 860 mpt_prt(mpt, \
984263bc
MD
861 "Restoring " #reg " to 0x%X from 0x%X\n", \
862 mpt->pci_cfg.reg, val); \
863 }
864
d751f32e 865 if (mpt->verbose >= MPT_PRT_DEBUG) {
984263bc
MD
866 MPT_CHECK(Command, PCIR_COMMAND, 2);
867 MPT_CHECK(LatencyTimer_LineSize, PCIR_CACHELNSZ, 2);
d751f32e
MD
868 MPT_CHECK(IO_BAR, PCIR_BAR(0), 4);
869 MPT_CHECK(Mem0_BAR[0], PCIR_BAR(1), 4);
870 MPT_CHECK(Mem0_BAR[1], PCIR_BAR(2), 4);
871 MPT_CHECK(Mem1_BAR[0], PCIR_BAR(3), 4);
872 MPT_CHECK(Mem1_BAR[1], PCIR_BAR(4), 4);
984263bc
MD
873 MPT_CHECK(ROM_BAR, PCIR_BIOS, 4);
874 MPT_CHECK(IntLine, PCIR_INTLINE, 1);
875 MPT_CHECK(PMCSR, 0x44, 4);
876 }
877#undef MPT_CHECK
878
879 pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
880 pci_write_config(mpt->dev, PCIR_CACHELNSZ,
881 mpt->pci_cfg.LatencyTimer_LineSize, 2);
d751f32e
MD
882 pci_write_config(mpt->dev, PCIR_BAR(0), mpt->pci_cfg.IO_BAR, 4);
883 pci_write_config(mpt->dev, PCIR_BAR(1), mpt->pci_cfg.Mem0_BAR[0], 4);
884 pci_write_config(mpt->dev, PCIR_BAR(2), mpt->pci_cfg.Mem0_BAR[1], 4);
885 pci_write_config(mpt->dev, PCIR_BAR(3), mpt->pci_cfg.Mem1_BAR[0], 4);
886 pci_write_config(mpt->dev, PCIR_BAR(4), mpt->pci_cfg.Mem1_BAR[1], 4);
984263bc
MD
887 pci_write_config(mpt->dev, PCIR_BIOS, mpt->pci_cfg.ROM_BAR, 4);
888 pci_write_config(mpt->dev, PCIR_INTLINE, mpt->pci_cfg.IntLine, 1);
889 pci_write_config(mpt->dev, 0x44, mpt->pci_cfg.PMCSR, 4);
890}
891
892static void
893mpt_pci_intr(void *arg)
894{
d751f32e
MD
895 struct mpt_softc *mpt;
896
897 mpt = (struct mpt_softc *)arg;
984263bc 898 MPT_LOCK(mpt);
d751f32e 899 mpt_intr(mpt);
984263bc
MD
900 MPT_UNLOCK(mpt);
901}