Remove all remaining SPL code. Replace the mtd_cpl field in the machine
[dragonfly.git] / sys / dev / disk / sym / sym_hipd.c
CommitLineData
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1/*
2 * Device driver optimized for the Symbios/LSI 53C896/53C895A/53C1010
3 * PCI-SCSI controllers.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver also supports the following Symbios/LSI PCI-SCSI chips:
8 * 53C810A, 53C825A, 53C860, 53C875, 53C876, 53C885, 53C895,
9 * 53C810, 53C815, 53C825 and the 53C1510D is 53C8XX mode.
10 *
11 *
12 * This driver for FreeBSD-CAM is derived from the Linux sym53c8xx driver.
13 * Copyright (C) 1998-1999 Gerard Roudier
14 *
15 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
16 * a port of the FreeBSD ncr driver to Linux-1.2.13.
17 *
18 * The original ncr driver has been written for 386bsd and FreeBSD by
19 * Wolfgang Stanglmeier <wolf@cologne.de>
20 * Stefan Esser <se@mi.Uni-Koeln.de>
21 * Copyright (C) 1994 Wolfgang Stanglmeier
22 *
23 * The initialisation code, and part of the code that addresses
24 * FreeBSD-CAM services is based on the aic7xxx driver for FreeBSD-CAM
25 * written by Justin T. Gibbs.
26 *
27 * Other major contributions:
28 *
29 * NVRAM detection and reading.
30 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
31 *
32 *-----------------------------------------------------------------------------
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. The name of the author may not be used to endorse or promote products
43 * derived from this software without specific prior written permission.
44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 * SUCH DAMAGE.
56 */
57
58/* $FreeBSD: src/sys/dev/sym/sym_hipd.c,v 1.6.2.12 2001/12/02 19:01:10 groudier Exp $ */
38787eef 59/* $DragonFly: src/sys/dev/disk/sym/sym_hipd.c,v 1.15 2005/06/16 21:12:30 dillon Exp $ */
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60
61#define SYM_DRIVER_NAME "sym-1.6.5-20000902"
62
63/* #define SYM_DEBUG_GENERIC_SUPPORT */
64/* #define CAM_NEW_TRAN_CODE */
65
1f2de5d4 66#include "use_pci.h"
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67#include <sys/param.h>
68
69/*
70 * Only use the BUS stuff for PCI under FreeBSD 4 and later versions.
71 * Note that the old BUS stuff also works for FreeBSD 4 and spares
72 * about 1 KB for the driver object file.
73 */
84754cd0 74#if defined(__DragonFly__) || __FreeBSD_version >= 400000
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75#define FreeBSD_Bus_Dma_Abstraction
76#define FreeBSD_Bus_Io_Abstraction
77#define FreeBSD_Bus_Space_Abstraction
78#endif
79
80/*
81 * Driver configuration options.
82 */
83#include "opt_sym.h"
1f2de5d4 84#include "sym_conf.h"
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85
86#ifndef FreeBSD_Bus_Io_Abstraction
1f2de5d4 87#include "use_ncr.h" /* To know if the ncr has been configured */
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88#endif
89
90#include <sys/systm.h>
91#include <sys/malloc.h>
92#include <sys/kernel.h>
93#ifdef FreeBSD_Bus_Io_Abstraction
94#include <sys/module.h>
95#include <sys/bus.h>
96#endif
2c9868e4 97#include <sys/thread2.h>
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98
99#include <sys/proc.h>
100
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101#include <bus/pci/pcireg.h>
102#include <bus/pci/pcivar.h>
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103
104#ifdef FreeBSD_Bus_Space_Abstraction
105#include <machine/bus_memio.h>
106/*
107 * Only include bus_pio if needed.
108 * This avoids bus space primitives to be uselessly bloated
109 * by out-of-age PIO operations.
110 */
111#ifdef SYM_CONF_IOMAPPED
112#include <machine/bus_pio.h>
113#endif
114#endif
115#include <machine/bus.h>
116
117#ifdef FreeBSD_Bus_Io_Abstraction
118#include <machine/resource.h>
119#include <sys/rman.h>
120#endif
121#include <machine/clock.h>
122
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123#include <bus/cam/cam.h>
124#include <bus/cam/cam_ccb.h>
125#include <bus/cam/cam_sim.h>
126#include <bus/cam/cam_xpt_sim.h>
127#include <bus/cam/cam_debug.h>
984263bc 128
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129#include <bus/cam/scsi/scsi_all.h>
130#include <bus/cam/scsi/scsi_message.h>
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131
132#include <vm/vm.h>
133#include <vm/vm_param.h>
134#include <vm/pmap.h>
135
136/* Short and quite clear integer types */
137typedef int8_t s8;
138typedef int16_t s16;
139typedef int32_t s32;
140typedef u_int8_t u8;
141typedef u_int16_t u16;
142typedef u_int32_t u32;
143
144/*
145 * From 'cam.error_recovery_diffs.20010313.context' patch.
146 */
147#ifdef CAM_NEW_TRAN_CODE
148#define FreeBSD_New_Tran_Settings
149#endif /* CAM_NEW_TRAN_CODE */
150
151/*
152 * Driver definitions.
153 */
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154#include "sym_defs.h"
155#include "sym_fw.h"
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156
157/*
158 * IA32 architecture does not reorder STORES and prevents
159 * LOADS from passing STORES. It is called `program order'
160 * by Intel and allows device drivers to deal with memory
161 * ordering by only ensuring that the code is not reordered
162 * by the compiler when ordering is required.
163 * Other architectures implement a weaker ordering that
164 * requires memory barriers (and also IO barriers when they
165 * make sense) to be used.
166 */
167
168#if defined __i386__
169#define MEMORY_BARRIER() do { ; } while(0)
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170#elif defined __powerpc__
171#define MEMORY_BARRIER() __asm__ volatile("eieio; sync" : : : "memory")
172#elif defined __ia64__
173#define MEMORY_BARRIER() __asm__ volatile("mf.a; mf" : : : "memory")
174#elif defined __sparc64__
175#define MEMORY_BARRIER() __asm__ volatile("membar #Sync" : : : "memory")
176#else
177#error "Not supported platform"
178#endif
179
180/*
181 * Portable but silly implemented byte order primitives.
182 * We define the primitives we need, since FreeBSD doesn't
183 * seem to have them yet.
184 */
185#if BYTE_ORDER == BIG_ENDIAN
186
187#define __revb16(x) ( (((u16)(x) & (u16)0x00ffU) << 8) | \
188 (((u16)(x) & (u16)0xff00U) >> 8) )
189#define __revb32(x) ( (((u32)(x) & 0x000000ffU) << 24) | \
190 (((u32)(x) & 0x0000ff00U) << 8) | \
191 (((u32)(x) & 0x00ff0000U) >> 8) | \
192 (((u32)(x) & 0xff000000U) >> 24) )
193
194#define __htole16(v) __revb16(v)
195#define __htole32(v) __revb32(v)
196#define __le16toh(v) __htole16(v)
197#define __le32toh(v) __htole32(v)
198
199static __inline u16 _htole16(u16 v) { return __htole16(v); }
200static __inline u32 _htole32(u32 v) { return __htole32(v); }
201#define _le16toh _htole16
202#define _le32toh _htole32
203
204#else /* LITTLE ENDIAN */
205
206#define __htole16(v) (v)
207#define __htole32(v) (v)
208#define __le16toh(v) (v)
209#define __le32toh(v) (v)
210
211#define _htole16(v) (v)
212#define _htole32(v) (v)
213#define _le16toh(v) (v)
214#define _le32toh(v) (v)
215
216#endif /* BYTE_ORDER */
217
218/*
219 * A la VMS/CAM-3 queue management.
220 */
221
222typedef struct sym_quehead {
223 struct sym_quehead *flink; /* Forward pointer */
224 struct sym_quehead *blink; /* Backward pointer */
225} SYM_QUEHEAD;
226
227#define sym_que_init(ptr) do { \
228 (ptr)->flink = (ptr); (ptr)->blink = (ptr); \
229} while (0)
230
231static __inline struct sym_quehead *sym_que_first(struct sym_quehead *head)
232{
233 return (head->flink == head) ? 0 : head->flink;
234}
235
236static __inline struct sym_quehead *sym_que_last(struct sym_quehead *head)
237{
238 return (head->blink == head) ? 0 : head->blink;
239}
240
241static __inline void __sym_que_add(struct sym_quehead * new,
242 struct sym_quehead * blink,
243 struct sym_quehead * flink)
244{
245 flink->blink = new;
246 new->flink = flink;
247 new->blink = blink;
248 blink->flink = new;
249}
250
251static __inline void __sym_que_del(struct sym_quehead * blink,
252 struct sym_quehead * flink)
253{
254 flink->blink = blink;
255 blink->flink = flink;
256}
257
258static __inline int sym_que_empty(struct sym_quehead *head)
259{
260 return head->flink == head;
261}
262
263static __inline void sym_que_splice(struct sym_quehead *list,
264 struct sym_quehead *head)
265{
266 struct sym_quehead *first = list->flink;
267
268 if (first != list) {
269 struct sym_quehead *last = list->blink;
270 struct sym_quehead *at = head->flink;
271
272 first->blink = head;
273 head->flink = first;
274
275 last->flink = at;
276 at->blink = last;
277 }
278}
279
280#define sym_que_entry(ptr, type, member) \
281 ((type *)((char *)(ptr)-(unsigned int)(&((type *)0)->member)))
282
283
284#define sym_insque(new, pos) __sym_que_add(new, pos, (pos)->flink)
285
286#define sym_remque(el) __sym_que_del((el)->blink, (el)->flink)
287
288#define sym_insque_head(new, head) __sym_que_add(new, head, (head)->flink)
289
290static __inline struct sym_quehead *sym_remque_head(struct sym_quehead *head)
291{
292 struct sym_quehead *elem = head->flink;
293
294 if (elem != head)
295 __sym_que_del(head, elem->flink);
296 else
297 elem = 0;
298 return elem;
299}
300
301#define sym_insque_tail(new, head) __sym_que_add(new, (head)->blink, head)
302
303static __inline struct sym_quehead *sym_remque_tail(struct sym_quehead *head)
304{
305 struct sym_quehead *elem = head->blink;
306
307 if (elem != head)
308 __sym_que_del(elem->blink, head);
309 else
310 elem = 0;
311 return elem;
312}
313
314/*
315 * This one may be useful.
316 */
317#define FOR_EACH_QUEUED_ELEMENT(head, qp) \
318 for (qp = (head)->flink; qp != (head); qp = qp->flink)
319/*
320 * FreeBSD does not offer our kind of queue in the CAM CCB.
321 * So, we have to cast.
322 */
323#define sym_qptr(p) ((struct sym_quehead *) (p))
324
325/*
326 * Simple bitmap operations.
327 */
328#define sym_set_bit(p, n) (((u32 *)(p))[(n)>>5] |= (1<<((n)&0x1f)))
329#define sym_clr_bit(p, n) (((u32 *)(p))[(n)>>5] &= ~(1<<((n)&0x1f)))
330#define sym_is_bit(p, n) (((u32 *)(p))[(n)>>5] & (1<<((n)&0x1f)))
331
332/*
333 * Number of tasks per device we want to handle.
334 */
335#if SYM_CONF_MAX_TAG_ORDER > 8
336#error "more than 256 tags per logical unit not allowed."
337#endif
338#define SYM_CONF_MAX_TASK (1<<SYM_CONF_MAX_TAG_ORDER)
339
340/*
341 * Donnot use more tasks that we can handle.
342 */
343#ifndef SYM_CONF_MAX_TAG
344#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
345#endif
346#if SYM_CONF_MAX_TAG > SYM_CONF_MAX_TASK
347#undef SYM_CONF_MAX_TAG
348#define SYM_CONF_MAX_TAG SYM_CONF_MAX_TASK
349#endif
350
351/*
352 * This one means 'NO TAG for this job'
353 */
354#define NO_TAG (256)
355
356/*
357 * Number of SCSI targets.
358 */
359#if SYM_CONF_MAX_TARGET > 16
360#error "more than 16 targets not allowed."
361#endif
362
363/*
364 * Number of logical units per target.
365 */
366#if SYM_CONF_MAX_LUN > 64
367#error "more than 64 logical units per target not allowed."
368#endif
369
370/*
371 * Asynchronous pre-scaler (ns). Shall be 40 for
372 * the SCSI timings to be compliant.
373 */
374#define SYM_CONF_MIN_ASYNC (40)
375
376/*
377 * Number of entries in the START and DONE queues.
378 *
379 * We limit to 1 PAGE in order to succeed allocation of
380 * these queues. Each entry is 8 bytes long (2 DWORDS).
381 */
382#ifdef SYM_CONF_MAX_START
383#define SYM_CONF_MAX_QUEUE (SYM_CONF_MAX_START+2)
384#else
385#define SYM_CONF_MAX_QUEUE (7*SYM_CONF_MAX_TASK+2)
386#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
387#endif
388
389#if SYM_CONF_MAX_QUEUE > PAGE_SIZE/8
390#undef SYM_CONF_MAX_QUEUE
391#define SYM_CONF_MAX_QUEUE PAGE_SIZE/8
392#undef SYM_CONF_MAX_START
393#define SYM_CONF_MAX_START (SYM_CONF_MAX_QUEUE-2)
394#endif
395
396/*
397 * For this one, we want a short name :-)
398 */
399#define MAX_QUEUE SYM_CONF_MAX_QUEUE
400
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401/*
402 * Active debugging tags and verbosity.
403 */
404#define DEBUG_ALLOC (0x0001)
405#define DEBUG_PHASE (0x0002)
406#define DEBUG_POLL (0x0004)
407#define DEBUG_QUEUE (0x0008)
408#define DEBUG_RESULT (0x0010)
409#define DEBUG_SCATTER (0x0020)
410#define DEBUG_SCRIPT (0x0040)
411#define DEBUG_TINY (0x0080)
412#define DEBUG_TIMING (0x0100)
413#define DEBUG_NEGO (0x0200)
414#define DEBUG_TAGS (0x0400)
415#define DEBUG_POINTER (0x0800)
416
417#if 0
418static int sym_debug = 0;
419 #define DEBUG_FLAGS sym_debug
420#else
421/* #define DEBUG_FLAGS (0x0631) */
422 #define DEBUG_FLAGS (0x0000)
423
424#endif
425#define sym_verbose (np->verbose)
426
427/*
428 * Insert a delay in micro-seconds and milli-seconds.
429 */
430static void UDELAY(int us) { DELAY(us); }
431static void MDELAY(int ms) { while (ms--) UDELAY(1000); }
432
433/*
434 * Simple power of two buddy-like allocator.
435 *
436 * This simple code is not intended to be fast, but to
437 * provide power of 2 aligned memory allocations.
438 * Since the SCRIPTS processor only supplies 8 bit arithmetic,
439 * this allocator allows simple and fast address calculations
440 * from the SCRIPTS code. In addition, cache line alignment
441 * is guaranteed for power of 2 cache line size.
442 *
443 * This allocator has been developped for the Linux sym53c8xx
444 * driver, since this O/S does not provide naturally aligned
445 * allocations.
446 * It has the advantage of allowing the driver to use private
447 * pages of memory that will be useful if we ever need to deal
448 * with IO MMUs for PCI.
449 */
450
451#define MEMO_SHIFT 4 /* 16 bytes minimum memory chunk */
452#define MEMO_PAGE_ORDER 0 /* 1 PAGE maximum */
453#if 0
454#define MEMO_FREE_UNUSED /* Free unused pages immediately */
455#endif
456#define MEMO_WARN 1
457#define MEMO_CLUSTER_SHIFT (PAGE_SHIFT+MEMO_PAGE_ORDER)
458#define MEMO_CLUSTER_SIZE (1UL << MEMO_CLUSTER_SHIFT)
459#define MEMO_CLUSTER_MASK (MEMO_CLUSTER_SIZE-1)
460
5f7c464a 461#define get_pages() malloc(MEMO_CLUSTER_SIZE, M_DEVBUF, M_INTWAIT)
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462#define free_pages(p) free((p), M_DEVBUF)
463
464typedef u_long m_addr_t; /* Enough bits to bit-hack addresses */
465
466typedef struct m_link { /* Link between free memory chunks */
467 struct m_link *next;
468} m_link_s;
469
470#ifdef FreeBSD_Bus_Dma_Abstraction
471typedef struct m_vtob { /* Virtual to Bus address translation */
472 struct m_vtob *next;
473 bus_dmamap_t dmamap; /* Map for this chunk */
474 m_addr_t vaddr; /* Virtual address */
475 m_addr_t baddr; /* Bus physical address */
476} m_vtob_s;
477/* Hash this stuff a bit to speed up translations */
478#define VTOB_HASH_SHIFT 5
479#define VTOB_HASH_SIZE (1UL << VTOB_HASH_SHIFT)
480#define VTOB_HASH_MASK (VTOB_HASH_SIZE-1)
481#define VTOB_HASH_CODE(m) \
482 ((((m_addr_t) (m)) >> MEMO_CLUSTER_SHIFT) & VTOB_HASH_MASK)
483#endif
484
485typedef struct m_pool { /* Memory pool of a given kind */
486#ifdef FreeBSD_Bus_Dma_Abstraction
487 bus_dma_tag_t dev_dmat; /* Identifies the pool */
488 bus_dma_tag_t dmat; /* Tag for our fixed allocations */
489 m_addr_t (*getp)(struct m_pool *);
490#ifdef MEMO_FREE_UNUSED
491 void (*freep)(struct m_pool *, m_addr_t);
492#endif
493#define M_GETP() mp->getp(mp)
494#define M_FREEP(p) mp->freep(mp, p)
495 int nump;
496 m_vtob_s *(vtob[VTOB_HASH_SIZE]);
497 struct m_pool *next;
498#else
499#define M_GETP() get_pages()
500#define M_FREEP(p) free_pages(p)
501#endif /* FreeBSD_Bus_Dma_Abstraction */
502 struct m_link h[MEMO_CLUSTER_SHIFT - MEMO_SHIFT + 1];
503} m_pool_s;
504
505static void *___sym_malloc(m_pool_s *mp, int size)
506{
507 int i = 0;
508 int s = (1 << MEMO_SHIFT);
509 int j;
510 m_addr_t a;
511 m_link_s *h = mp->h;
512
513 if (size > MEMO_CLUSTER_SIZE)
514 return 0;
515
516 while (size > s) {
517 s <<= 1;
518 ++i;
519 }
520
521 j = i;
522 while (!h[j].next) {
523 if (s == MEMO_CLUSTER_SIZE) {
524 h[j].next = (m_link_s *) M_GETP();
525 if (h[j].next)
526 h[j].next->next = 0;
527 break;
528 }
529 ++j;
530 s <<= 1;
531 }
532 a = (m_addr_t) h[j].next;
533 if (a) {
534 h[j].next = h[j].next->next;
535 while (j > i) {
536 j -= 1;
537 s >>= 1;
538 h[j].next = (m_link_s *) (a+s);
539 h[j].next->next = 0;
540 }
541 }
542#ifdef DEBUG
543 printf("___sym_malloc(%d) = %p\n", size, (void *) a);
544#endif
545 return (void *) a;
546}
547
548static void ___sym_mfree(m_pool_s *mp, void *ptr, int size)
549{
550 int i = 0;
551 int s = (1 << MEMO_SHIFT);
552 m_link_s *q;
553 m_addr_t a, b;
554 m_link_s *h = mp->h;
555
556#ifdef DEBUG
557 printf("___sym_mfree(%p, %d)\n", ptr, size);
558#endif
559
560 if (size > MEMO_CLUSTER_SIZE)
561 return;
562
563 while (size > s) {
564 s <<= 1;
565 ++i;
566 }
567
568 a = (m_addr_t) ptr;
569
570 while (1) {
571#ifdef MEMO_FREE_UNUSED
572 if (s == MEMO_CLUSTER_SIZE) {
573 M_FREEP(a);
574 break;
575 }
576#endif
577 b = a ^ s;
578 q = &h[i];
579 while (q->next && q->next != (m_link_s *) b) {
580 q = q->next;
581 }
582 if (!q->next) {
583 ((m_link_s *) a)->next = h[i].next;
584 h[i].next = (m_link_s *) a;
585 break;
586 }
587 q->next = q->next->next;
588 a = a & b;
589 s <<= 1;
590 ++i;
591 }
592}
593
594static void *__sym_calloc2(m_pool_s *mp, int size, char *name, int uflags)
595{
596 void *p;
597
598 p = ___sym_malloc(mp, size);
599
600 if (DEBUG_FLAGS & DEBUG_ALLOC)
601 printf ("new %-10s[%4d] @%p.\n", name, size, p);
602
603 if (p)
604 bzero(p, size);
605 else if (uflags & MEMO_WARN)
606 printf ("__sym_calloc2: failed to allocate %s[%d]\n", name, size);
607
608 return p;
609}
610
611#define __sym_calloc(mp, s, n) __sym_calloc2(mp, s, n, MEMO_WARN)
612
613static void __sym_mfree(m_pool_s *mp, void *ptr, int size, char *name)
614{
615 if (DEBUG_FLAGS & DEBUG_ALLOC)
616 printf ("freeing %-10s[%4d] @%p.\n", name, size, ptr);
617
618 ___sym_mfree(mp, ptr, size);
619
620}
621
622/*
623 * Default memory pool we donnot need to involve in DMA.
624 */
625#ifndef FreeBSD_Bus_Dma_Abstraction
626/*
627 * Without the `bus dma abstraction', all the memory is assumed
628 * DMAable and a single pool is all what we need.
629 */
630static m_pool_s mp0;
631
632#else
633/*
634 * With the `bus dma abstraction', we use a separate pool for
635 * memory we donnot need to involve in DMA.
636 */
637static m_addr_t ___mp0_getp(m_pool_s *mp)
638{
639 m_addr_t m = (m_addr_t) get_pages();
640 if (m)
641 ++mp->nump;
642 return m;
643}
644
645#ifdef MEMO_FREE_UNUSED
646static void ___mp0_freep(m_pool_s *mp, m_addr_t m)
647{
648 free_pages(m);
649 --mp->nump;
650}
651#endif
652
653#ifdef MEMO_FREE_UNUSED
654static m_pool_s mp0 = {0, 0, ___mp0_getp, ___mp0_freep};
655#else
656static m_pool_s mp0 = {0, 0, ___mp0_getp};
657#endif
658
659#endif /* FreeBSD_Bus_Dma_Abstraction */
660
661/*
662 * Actual memory allocation routine for non-DMAed memory.
663 */
664static void *sym_calloc(int size, char *name)
665{
666 void *m;
667 /* Lock */
668 m = __sym_calloc(&mp0, size, name);
669 /* Unlock */
670 return m;
671}
672
673/*
674 * Actual memory allocation routine for non-DMAed memory.
675 */
676static void sym_mfree(void *ptr, int size, char *name)
677{
678 /* Lock */
679 __sym_mfree(&mp0, ptr, size, name);
680 /* Unlock */
681}
682
683/*
684 * DMAable pools.
685 */
686#ifndef FreeBSD_Bus_Dma_Abstraction
687/*
688 * Without `bus dma abstraction', all the memory is DMAable, and
689 * only a single pool is needed (vtophys() is our friend).
690 */
691#define __sym_calloc_dma(b, s, n) sym_calloc(s, n)
692#define __sym_mfree_dma(b, p, s, n) sym_mfree(p, s, n)
984263bc 693#define __vtobus(b, p) vtophys(p)
984263bc
MD
694
695#else
696/*
697 * With `bus dma abstraction', we use a separate pool per parent
698 * BUS handle. A reverse table (hashed) is maintained for virtual
699 * to BUS address translation.
700 */
701static void getbaddrcb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
702{
703 bus_addr_t *baddr;
704 baddr = (bus_addr_t *)arg;
705 *baddr = segs->ds_addr;
706}
707
708static m_addr_t ___dma_getp(m_pool_s *mp)
709{
710 m_vtob_s *vbp;
711 void *vaddr = 0;
712 bus_addr_t baddr = 0;
713
714 vbp = __sym_calloc(&mp0, sizeof(*vbp), "VTOB");
715 if (!vbp)
716 goto out_err;
717
718 if (bus_dmamem_alloc(mp->dmat, &vaddr,
719 BUS_DMA_NOWAIT, &vbp->dmamap))
720 goto out_err;
721 bus_dmamap_load(mp->dmat, vbp->dmamap, vaddr,
722 MEMO_CLUSTER_SIZE, getbaddrcb, &baddr, 0);
723 if (baddr) {
724 int hc = VTOB_HASH_CODE(vaddr);
725 vbp->vaddr = (m_addr_t) vaddr;
726 vbp->baddr = (m_addr_t) baddr;
727 vbp->next = mp->vtob[hc];
728 mp->vtob[hc] = vbp;
729 ++mp->nump;
730 return (m_addr_t) vaddr;
731 }
732out_err:
733 if (baddr)
734 bus_dmamap_unload(mp->dmat, vbp->dmamap);
735 if (vaddr)
736 bus_dmamem_free(mp->dmat, vaddr, vbp->dmamap);
737 if (vbp->dmamap)
738 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
739 if (vbp)
740 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
741 return 0;
742}
743
744#ifdef MEMO_FREE_UNUSED
745static void ___dma_freep(m_pool_s *mp, m_addr_t m)
746{
747 m_vtob_s **vbpp, *vbp;
748 int hc = VTOB_HASH_CODE(m);
749
750 vbpp = &mp->vtob[hc];
751 while (*vbpp && (*vbpp)->vaddr != m)
752 vbpp = &(*vbpp)->next;
753 if (*vbpp) {
754 vbp = *vbpp;
755 *vbpp = (*vbpp)->next;
756 bus_dmamap_unload(mp->dmat, vbp->dmamap);
757 bus_dmamem_free(mp->dmat, (void *) vbp->vaddr, vbp->dmamap);
758 bus_dmamap_destroy(mp->dmat, vbp->dmamap);
759 __sym_mfree(&mp0, vbp, sizeof(*vbp), "VTOB");
760 --mp->nump;
761 }
762}
763#endif
764
765static __inline m_pool_s *___get_dma_pool(bus_dma_tag_t dev_dmat)
766{
767 m_pool_s *mp;
768 for (mp = mp0.next; mp && mp->dev_dmat != dev_dmat; mp = mp->next);
769 return mp;
770}
771
772static m_pool_s *___cre_dma_pool(bus_dma_tag_t dev_dmat)
773{
774 m_pool_s *mp = 0;
775
776 mp = __sym_calloc(&mp0, sizeof(*mp), "MPOOL");
777 if (mp) {
778 mp->dev_dmat = dev_dmat;
779 if (!bus_dma_tag_create(dev_dmat, 1, MEMO_CLUSTER_SIZE,
780 BUS_SPACE_MAXADDR_32BIT,
781 BUS_SPACE_MAXADDR_32BIT,
782 NULL, NULL, MEMO_CLUSTER_SIZE, 1,
783 MEMO_CLUSTER_SIZE, 0, &mp->dmat)) {
784 mp->getp = ___dma_getp;
785#ifdef MEMO_FREE_UNUSED
786 mp->freep = ___dma_freep;
787#endif
788 mp->next = mp0.next;
789 mp0.next = mp;
790 return mp;
791 }
792 }
793 if (mp)
794 __sym_mfree(&mp0, mp, sizeof(*mp), "MPOOL");
795 return 0;
796}
797
798#ifdef MEMO_FREE_UNUSED
799static void ___del_dma_pool(m_pool_s *p)
800{
801 struct m_pool **pp = &mp0.next;
802
803 while (*pp && *pp != p)
804 pp = &(*pp)->next;
805 if (*pp) {
806 *pp = (*pp)->next;
807 bus_dma_tag_destroy(p->dmat);
808 __sym_mfree(&mp0, p, sizeof(*p), "MPOOL");
809 }
810}
811#endif
812
813static void *__sym_calloc_dma(bus_dma_tag_t dev_dmat, int size, char *name)
814{
815 struct m_pool *mp;
816 void *m = 0;
817
818 /* Lock */
819 mp = ___get_dma_pool(dev_dmat);
820 if (!mp)
821 mp = ___cre_dma_pool(dev_dmat);
822 if (mp)
823 m = __sym_calloc(mp, size, name);
824#ifdef MEMO_FREE_UNUSED
825 if (mp && !mp->nump)
826 ___del_dma_pool(mp);
827#endif
828 /* Unlock */
829
830 return m;
831}
832
833static void
834__sym_mfree_dma(bus_dma_tag_t dev_dmat, void *m, int size, char *name)
835{
836 struct m_pool *mp;
837
838 /* Lock */
839 mp = ___get_dma_pool(dev_dmat);
840 if (mp)
841 __sym_mfree(mp, m, size, name);
842#ifdef MEMO_FREE_UNUSED
843 if (mp && !mp->nump)
844 ___del_dma_pool(mp);
845#endif
846 /* Unlock */
847}
848
849static m_addr_t __vtobus(bus_dma_tag_t dev_dmat, void *m)
850{
851 m_pool_s *mp;
852 int hc = VTOB_HASH_CODE(m);
853 m_vtob_s *vp = 0;
854 m_addr_t a = ((m_addr_t) m) & ~MEMO_CLUSTER_MASK;
855
856 /* Lock */
857 mp = ___get_dma_pool(dev_dmat);
858 if (mp) {
859 vp = mp->vtob[hc];
860 while (vp && (m_addr_t) vp->vaddr != a)
861 vp = vp->next;
862 }
863 /* Unlock */
864 if (!vp)
865 panic("sym: VTOBUS FAILED!\n");
866 return vp ? vp->baddr + (((m_addr_t) m) - a) : 0;
867}
868
869#endif /* FreeBSD_Bus_Dma_Abstraction */
870
871/*
872 * Verbs for DMAable memory handling.
873 * The _uvptv_ macro avoids a nasty warning about pointer to volatile
874 * being discarded.
875 */
876#define _uvptv_(p) ((void *)((vm_offset_t)(p)))
877#define _sym_calloc_dma(np, s, n) __sym_calloc_dma(np->bus_dmat, s, n)
878#define _sym_mfree_dma(np, p, s, n) \
879 __sym_mfree_dma(np->bus_dmat, _uvptv_(p), s, n)
880#define sym_calloc_dma(s, n) _sym_calloc_dma(np, s, n)
881#define sym_mfree_dma(p, s, n) _sym_mfree_dma(np, p, s, n)
882#define _vtobus(np, p) __vtobus(np->bus_dmat, _uvptv_(p))
883#define vtobus(p) _vtobus(np, p)
884
885
886/*
887 * Print a buffer in hexadecimal format.
888 */
889static void sym_printb_hex (u_char *p, int n)
890{
891 while (n-- > 0)
892 printf (" %x", *p++);
893}
894
895/*
896 * Same with a label at beginning and .\n at end.
897 */
898static void sym_printl_hex (char *label, u_char *p, int n)
899{
900 printf ("%s", label);
901 sym_printb_hex (p, n);
902 printf (".\n");
903}
904
905/*
906 * Return a string for SCSI BUS mode.
907 */
908static char *sym_scsi_bus_mode(int mode)
909{
910 switch(mode) {
911 case SMODE_HVD: return "HVD";
912 case SMODE_SE: return "SE";
913 case SMODE_LVD: return "LVD";
914 }
915 return "??";
916}
917
918/*
919 * Some poor and bogus sync table that refers to Tekram NVRAM layout.
920 */
921#ifdef SYM_CONF_NVRAM_SUPPORT
922static u_char Tekram_sync[16] =
923 {25,31,37,43, 50,62,75,125, 12,15,18,21, 6,7,9,10};
924#endif
925
926/*
927 * Union of supported NVRAM formats.
928 */
929struct sym_nvram {
930 int type;
931#define SYM_SYMBIOS_NVRAM (1)
932#define SYM_TEKRAM_NVRAM (2)
933#ifdef SYM_CONF_NVRAM_SUPPORT
934 union {
935 Symbios_nvram Symbios;
936 Tekram_nvram Tekram;
937 } data;
938#endif
939};
940
941/*
942 * This one is hopefully useless, but actually useful. :-)
943 */
944#ifndef assert
945#define assert(expression) { \
946 if (!(expression)) { \
947 (void)panic( \
948 "assertion \"%s\" failed: file \"%s\", line %d\n", \
949 #expression, \
950 __FILE__, __LINE__); \
951 } \
952}
953#endif
954
955/*
956 * Some provision for a possible big endian mode supported by
957 * Symbios chips (never seen, by the way).
958 * For now, this stuff does not deserve any comments. :)
959 */
960
961#define sym_offb(o) (o)
962#define sym_offw(o) (o)
963
964/*
965 * Some provision for support for BIG ENDIAN CPU.
966 * Btw, FreeBSD does not seem to be ready yet for big endian.
967 */
968
969#if BYTE_ORDER == BIG_ENDIAN
970#define cpu_to_scr(dw) _htole32(dw)
971#define scr_to_cpu(dw) _le32toh(dw)
972#else
973#define cpu_to_scr(dw) (dw)
974#define scr_to_cpu(dw) (dw)
975#endif
976
977/*
978 * Access to the chip IO registers and on-chip RAM.
979 * We use the `bus space' interface under FreeBSD-4 and
980 * later kernel versions.
981 */
982
983#ifdef FreeBSD_Bus_Space_Abstraction
984
985#if defined(SYM_CONF_IOMAPPED)
986
987#define INB_OFF(o) bus_space_read_1(np->io_tag, np->io_bsh, o)
988#define INW_OFF(o) bus_space_read_2(np->io_tag, np->io_bsh, o)
989#define INL_OFF(o) bus_space_read_4(np->io_tag, np->io_bsh, o)
990
991#define OUTB_OFF(o, v) bus_space_write_1(np->io_tag, np->io_bsh, o, (v))
992#define OUTW_OFF(o, v) bus_space_write_2(np->io_tag, np->io_bsh, o, (v))
993#define OUTL_OFF(o, v) bus_space_write_4(np->io_tag, np->io_bsh, o, (v))
994
995#else /* Memory mapped IO */
996
997#define INB_OFF(o) bus_space_read_1(np->mmio_tag, np->mmio_bsh, o)
998#define INW_OFF(o) bus_space_read_2(np->mmio_tag, np->mmio_bsh, o)
999#define INL_OFF(o) bus_space_read_4(np->mmio_tag, np->mmio_bsh, o)
1000
1001#define OUTB_OFF(o, v) bus_space_write_1(np->mmio_tag, np->mmio_bsh, o, (v))
1002#define OUTW_OFF(o, v) bus_space_write_2(np->mmio_tag, np->mmio_bsh, o, (v))
1003#define OUTL_OFF(o, v) bus_space_write_4(np->mmio_tag, np->mmio_bsh, o, (v))
1004
1005#endif /* SYM_CONF_IOMAPPED */
1006
1007#define OUTRAM_OFF(o, a, l) \
1008 bus_space_write_region_1(np->ram_tag, np->ram_bsh, o, (a), (l))
1009
1010#else /* not defined FreeBSD_Bus_Space_Abstraction */
1011
1012#if BYTE_ORDER == BIG_ENDIAN
1013#error "BIG ENDIAN support requires bus space kernel interface"
1014#endif
1015
1016/*
1017 * Access to the chip IO registers and on-chip RAM.
1018 * We use legacy MMIO and IO interface for FreeBSD 3.X versions.
1019 */
1020
1021/*
1022 * Define some understable verbs for IO and MMIO.
1023 */
1024#define io_read8(p) scr_to_cpu(inb((p)))
1025#define io_read16(p) scr_to_cpu(inw((p)))
1026#define io_read32(p) scr_to_cpu(inl((p)))
1027#define io_write8(p, v) outb((p), cpu_to_scr(v))
1028#define io_write16(p, v) outw((p), cpu_to_scr(v))
1029#define io_write32(p, v) outl((p), cpu_to_scr(v))
1030
984263bc
MD
1031#define mmio_read8(a) scr_to_cpu((*(volatile unsigned char *) (a)))
1032#define mmio_read16(a) scr_to_cpu((*(volatile unsigned short *) (a)))
1033#define mmio_read32(a) scr_to_cpu((*(volatile unsigned int *) (a)))
1034#define mmio_write8(a, b) (*(volatile unsigned char *) (a)) = cpu_to_scr(b)
1035#define mmio_write16(a, b) (*(volatile unsigned short *) (a)) = cpu_to_scr(b)
1036#define mmio_write32(a, b) (*(volatile unsigned int *) (a)) = cpu_to_scr(b)
1037#define memcpy_to_pci(d, s, n) bcopy((s), (void *)(d), (n))
1038
984263bc
MD
1039/*
1040 * Normal IO
1041 */
1042#if defined(SYM_CONF_IOMAPPED)
1043
1044#define INB_OFF(o) io_read8(np->io_port + sym_offb(o))
1045#define OUTB_OFF(o, v) io_write8(np->io_port + sym_offb(o), (v))
1046
1047#define INW_OFF(o) io_read16(np->io_port + sym_offw(o))
1048#define OUTW_OFF(o, v) io_write16(np->io_port + sym_offw(o), (v))
1049
1050#define INL_OFF(o) io_read32(np->io_port + (o))
1051#define OUTL_OFF(o, v) io_write32(np->io_port + (o), (v))
1052
1053#else /* Memory mapped IO */
1054
1055#define INB_OFF(o) mmio_read8(np->mmio_va + sym_offb(o))
1056#define OUTB_OFF(o, v) mmio_write8(np->mmio_va + sym_offb(o), (v))
1057
1058#define INW_OFF(o) mmio_read16(np->mmio_va + sym_offw(o))
1059#define OUTW_OFF(o, v) mmio_write16(np->mmio_va + sym_offw(o), (v))
1060
1061#define INL_OFF(o) mmio_read32(np->mmio_va + (o))
1062#define OUTL_OFF(o, v) mmio_write32(np->mmio_va + (o), (v))
1063
1064#endif
1065
1066#define OUTRAM_OFF(o, a, l) memcpy_to_pci(np->ram_va + (o), (a), (l))
1067
1068#endif /* FreeBSD_Bus_Space_Abstraction */
1069
1070/*
1071 * Common definitions for both bus space and legacy IO methods.
1072 */
1073#define INB(r) INB_OFF(offsetof(struct sym_reg,r))
1074#define INW(r) INW_OFF(offsetof(struct sym_reg,r))
1075#define INL(r) INL_OFF(offsetof(struct sym_reg,r))
1076
1077#define OUTB(r, v) OUTB_OFF(offsetof(struct sym_reg,r), (v))
1078#define OUTW(r, v) OUTW_OFF(offsetof(struct sym_reg,r), (v))
1079#define OUTL(r, v) OUTL_OFF(offsetof(struct sym_reg,r), (v))
1080
1081#define OUTONB(r, m) OUTB(r, INB(r) | (m))
1082#define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
1083#define OUTONW(r, m) OUTW(r, INW(r) | (m))
1084#define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
1085#define OUTONL(r, m) OUTL(r, INL(r) | (m))
1086#define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
1087
1088/*
1089 * We normally want the chip to have a consistent view
1090 * of driver internal data structures when we restart it.
1091 * Thus these macros.
1092 */
1093#define OUTL_DSP(v) \
1094 do { \
1095 MEMORY_BARRIER(); \
1096 OUTL (nc_dsp, (v)); \
1097 } while (0)
1098
1099#define OUTONB_STD() \
1100 do { \
1101 MEMORY_BARRIER(); \
1102 OUTONB (nc_dcntl, (STD|NOCOM)); \
1103 } while (0)
1104
1105/*
1106 * Command control block states.
1107 */
1108#define HS_IDLE (0)
1109#define HS_BUSY (1)
1110#define HS_NEGOTIATE (2) /* sync/wide data transfer*/
1111#define HS_DISCONNECT (3) /* Disconnected by target */
1112#define HS_WAIT (4) /* waiting for resource */
1113
1114#define HS_DONEMASK (0x80)
1115#define HS_COMPLETE (4|HS_DONEMASK)
1116#define HS_SEL_TIMEOUT (5|HS_DONEMASK) /* Selection timeout */
1117#define HS_UNEXPECTED (6|HS_DONEMASK) /* Unexpected disconnect */
1118#define HS_COMP_ERR (7|HS_DONEMASK) /* Completed with error */
1119
1120/*
1121 * Software Interrupt Codes
1122 */
1123#define SIR_BAD_SCSI_STATUS (1)
1124#define SIR_SEL_ATN_NO_MSG_OUT (2)
1125#define SIR_MSG_RECEIVED (3)
1126#define SIR_MSG_WEIRD (4)
1127#define SIR_NEGO_FAILED (5)
1128#define SIR_NEGO_PROTO (6)
1129#define SIR_SCRIPT_STOPPED (7)
1130#define SIR_REJECT_TO_SEND (8)
1131#define SIR_SWIDE_OVERRUN (9)
1132#define SIR_SODL_UNDERRUN (10)
1133#define SIR_RESEL_NO_MSG_IN (11)
1134#define SIR_RESEL_NO_IDENTIFY (12)
1135#define SIR_RESEL_BAD_LUN (13)
1136#define SIR_TARGET_SELECTED (14)
1137#define SIR_RESEL_BAD_I_T_L (15)
1138#define SIR_RESEL_BAD_I_T_L_Q (16)
1139#define SIR_ABORT_SENT (17)
1140#define SIR_RESEL_ABORTED (18)
1141#define SIR_MSG_OUT_DONE (19)
1142#define SIR_COMPLETE_ERROR (20)
1143#define SIR_DATA_OVERRUN (21)
1144#define SIR_BAD_PHASE (22)
1145#define SIR_MAX (22)
1146
1147/*
1148 * Extended error bit codes.
1149 * xerr_status field of struct sym_ccb.
1150 */
1151#define XE_EXTRA_DATA (1) /* unexpected data phase */
1152#define XE_BAD_PHASE (1<<1) /* illegal phase (4/5) */
1153#define XE_PARITY_ERR (1<<2) /* unrecovered SCSI parity error */
1154#define XE_SODL_UNRUN (1<<3) /* ODD transfer in DATA OUT phase */
1155#define XE_SWIDE_OVRUN (1<<4) /* ODD transfer in DATA IN phase */
1156
1157/*
1158 * Negotiation status.
1159 * nego_status field of struct sym_ccb.
1160 */
1161#define NS_SYNC (1)
1162#define NS_WIDE (2)
1163#define NS_PPR (3)
1164
1165/*
1166 * A CCB hashed table is used to retrieve CCB address
1167 * from DSA value.
1168 */
1169#define CCB_HASH_SHIFT 8
1170#define CCB_HASH_SIZE (1UL << CCB_HASH_SHIFT)
1171#define CCB_HASH_MASK (CCB_HASH_SIZE-1)
1172#define CCB_HASH_CODE(dsa) (((dsa) >> 9) & CCB_HASH_MASK)
1173
1174/*
1175 * Device flags.
1176 */
1177#define SYM_DISC_ENABLED (1)
1178#define SYM_TAGS_ENABLED (1<<1)
1179#define SYM_SCAN_BOOT_DISABLED (1<<2)
1180#define SYM_SCAN_LUNS_DISABLED (1<<3)
1181
1182/*
1183 * Host adapter miscellaneous flags.
1184 */
1185#define SYM_AVOID_BUS_RESET (1)
1186#define SYM_SCAN_TARGETS_HILO (1<<1)
1187
1188/*
1189 * Device quirks.
1190 * Some devices, for example the CHEETAH 2 LVD, disconnects without
1191 * saving the DATA POINTER then reselects and terminates the IO.
1192 * On reselection, the automatic RESTORE DATA POINTER makes the
1193 * CURRENT DATA POINTER not point at the end of the IO.
1194 * This behaviour just breaks our calculation of the residual.
1195 * For now, we just force an AUTO SAVE on disconnection and will
1196 * fix that in a further driver version.
1197 */
1198#define SYM_QUIRK_AUTOSAVE 1
1199
1200/*
1201 * Misc.
1202 */
1203#define SYM_SNOOP_TIMEOUT (10000000)
1204#define SYM_PCI_IO PCIR_MAPS
1205#define SYM_PCI_MMIO (PCIR_MAPS + 4)
1206#define SYM_PCI_RAM (PCIR_MAPS + 8)
1207#define SYM_PCI_RAM64 (PCIR_MAPS + 12)
1208
1209/*
1210 * Back-pointer from the CAM CCB to our data structures.
1211 */
1212#define sym_hcb_ptr spriv_ptr0
1213/* #define sym_ccb_ptr spriv_ptr1 */
1214
1215/*
1216 * We mostly have to deal with pointers.
1217 * Thus these typedef's.
1218 */
1219typedef struct sym_tcb *tcb_p;
1220typedef struct sym_lcb *lcb_p;
1221typedef struct sym_ccb *ccb_p;
1222typedef struct sym_hcb *hcb_p;
1223
1224/*
1225 * Gather negotiable parameters value
1226 */
1227struct sym_trans {
1228#ifdef FreeBSD_New_Tran_Settings
1229 u8 scsi_version;
1230 u8 spi_version;
1231#endif
1232 u8 period;
1233 u8 offset;
1234 u8 width;
1235 u8 options; /* PPR options */
1236};
1237
1238struct sym_tinfo {
1239 struct sym_trans current;
1240 struct sym_trans goal;
1241 struct sym_trans user;
1242};
1243
1244#define BUS_8_BIT MSG_EXT_WDTR_BUS_8_BIT
1245#define BUS_16_BIT MSG_EXT_WDTR_BUS_16_BIT
1246
1247/*
1248 * Global TCB HEADER.
1249 *
1250 * Due to lack of indirect addressing on earlier NCR chips,
1251 * this substructure is copied from the TCB to a global
1252 * address after selection.
1253 * For SYMBIOS chips that support LOAD/STORE this copy is
1254 * not needed and thus not performed.
1255 */
1256struct sym_tcbh {
1257 /*
1258 * Scripts bus addresses of LUN table accessed from scripts.
1259 * LUN #0 is a special case, since multi-lun devices are rare,
1260 * and we we want to speed-up the general case and not waste
1261 * resources.
1262 */
1263 u32 luntbl_sa; /* bus address of this table */
1264 u32 lun0_sa; /* bus address of LCB #0 */
1265 /*
1266 * Actual SYNC/WIDE IO registers value for this target.
1267 * 'sval', 'wval' and 'uval' are read from SCRIPTS and
1268 * so have alignment constraints.
1269 */
1270/*0*/ u_char uval; /* -> SCNTL4 register */
1271/*1*/ u_char sval; /* -> SXFER io register */
1272/*2*/ u_char filler1;
1273/*3*/ u_char wval; /* -> SCNTL3 io register */
1274};
1275
1276/*
1277 * Target Control Block
1278 */
1279struct sym_tcb {
1280 /*
1281 * TCB header.
1282 * Assumed at offset 0.
1283 */
1284/*0*/ struct sym_tcbh head;
1285
1286 /*
1287 * LUN table used by the SCRIPTS processor.
1288 * An array of bus addresses is used on reselection.
1289 */
1290 u32 *luntbl; /* LCBs bus address table */
1291
1292 /*
1293 * LUN table used by the C code.
1294 */
1295 lcb_p lun0p; /* LCB of LUN #0 (usual case) */
1296#if SYM_CONF_MAX_LUN > 1
1297 lcb_p *lunmp; /* Other LCBs [1..MAX_LUN] */
1298#endif
1299
1300 /*
1301 * Bitmap that tells about LUNs that succeeded at least
1302 * 1 IO and therefore assumed to be a real device.
1303 * Avoid useless allocation of the LCB structure.
1304 */
1305 u32 lun_map[(SYM_CONF_MAX_LUN+31)/32];
1306
1307 /*
1308 * Bitmap that tells about LUNs that haven't yet an LCB
1309 * allocated (not discovered or LCB allocation failed).
1310 */
1311 u32 busy0_map[(SYM_CONF_MAX_LUN+31)/32];
1312
1313 /*
1314 * Transfer capabilities (SIP)
1315 */
1316 struct sym_tinfo tinfo;
1317
1318 /*
1319 * Keep track of the CCB used for the negotiation in order
1320 * to ensure that only 1 negotiation is queued at a time.
1321 */
1322 ccb_p nego_cp; /* CCB used for the nego */
1323
1324 /*
1325 * Set when we want to reset the device.
1326 */
1327 u_char to_reset;
1328
1329 /*
1330 * Other user settable limits and options.
1331 * These limits are read from the NVRAM if present.
1332 */
1333 u_char usrflags;
1334 u_short usrtags;
1335};
1336
1337/*
1338 * Global LCB HEADER.
1339 *
1340 * Due to lack of indirect addressing on earlier NCR chips,
1341 * this substructure is copied from the LCB to a global
1342 * address after selection.
1343 * For SYMBIOS chips that support LOAD/STORE this copy is
1344 * not needed and thus not performed.
1345 */
1346struct sym_lcbh {
1347 /*
1348 * SCRIPTS address jumped by SCRIPTS on reselection.
1349 * For not probed logical units, this address points to
1350 * SCRIPTS that deal with bad LU handling (must be at
1351 * offset zero of the LCB for that reason).
1352 */
1353/*0*/ u32 resel_sa;
1354
1355 /*
1356 * Task (bus address of a CCB) read from SCRIPTS that points
1357 * to the unique ITL nexus allowed to be disconnected.
1358 */
1359 u32 itl_task_sa;
1360
1361 /*
1362 * Task table bus address (read from SCRIPTS).
1363 */
1364 u32 itlq_tbl_sa;
1365};
1366
1367/*
1368 * Logical Unit Control Block
1369 */
1370struct sym_lcb {
1371 /*
1372 * TCB header.
1373 * Assumed at offset 0.
1374 */
1375/*0*/ struct sym_lcbh head;
1376
1377 /*
1378 * Task table read from SCRIPTS that contains pointers to
1379 * ITLQ nexuses. The bus address read from SCRIPTS is
1380 * inside the header.
1381 */
1382 u32 *itlq_tbl; /* Kernel virtual address */
1383
1384 /*
1385 * Busy CCBs management.
1386 */
1387 u_short busy_itlq; /* Number of busy tagged CCBs */
1388 u_short busy_itl; /* Number of busy untagged CCBs */
1389
1390 /*
1391 * Circular tag allocation buffer.
1392 */
1393 u_short ia_tag; /* Tag allocation index */
1394 u_short if_tag; /* Tag release index */
1395 u_char *cb_tags; /* Circular tags buffer */
1396
1397 /*
1398 * Set when we want to clear all tasks.
1399 */
1400 u_char to_clear;
1401
1402 /*
1403 * Capabilities.
1404 */
1405 u_char user_flags;
1406 u_char current_flags;
1407};
1408
1409/*
1410 * Action from SCRIPTS on a task.
1411 * Is part of the CCB, but is also used separately to plug
1412 * error handling action to perform from SCRIPTS.
1413 */
1414struct sym_actscr {
1415 u32 start; /* Jumped by SCRIPTS after selection */
1416 u32 restart; /* Jumped by SCRIPTS on relection */
1417};
1418
1419/*
1420 * Phase mismatch context.
1421 *
1422 * It is part of the CCB and is used as parameters for the
1423 * DATA pointer. We need two contexts to handle correctly the
1424 * SAVED DATA POINTER.
1425 */
1426struct sym_pmc {
1427 struct sym_tblmove sg; /* Updated interrupted SG block */
1428 u32 ret; /* SCRIPT return address */
1429};
1430
1431/*
1432 * LUN control block lookup.
1433 * We use a direct pointer for LUN #0, and a table of
1434 * pointers which is only allocated for devices that support
1435 * LUN(s) > 0.
1436 */
1437#if SYM_CONF_MAX_LUN <= 1
1438#define sym_lp(np, tp, lun) (!lun) ? (tp)->lun0p : 0
1439#else
1440#define sym_lp(np, tp, lun) \
1441 (!lun) ? (tp)->lun0p : (tp)->lunmp ? (tp)->lunmp[(lun)] : 0
1442#endif
1443
1444/*
1445 * Status are used by the host and the script processor.
1446 *
1447 * The last four bytes (status[4]) are copied to the
1448 * scratchb register (declared as scr0..scr3) just after the
1449 * select/reselect, and copied back just after disconnecting.
1450 * Inside the script the XX_REG are used.
1451 */
1452
1453/*
1454 * Last four bytes (script)
1455 */
1456#define QU_REG scr0
1457#define HS_REG scr1
1458#define HS_PRT nc_scr1
1459#define SS_REG scr2
1460#define SS_PRT nc_scr2
1461#define HF_REG scr3
1462#define HF_PRT nc_scr3
1463
1464/*
1465 * Last four bytes (host)
1466 */
1467#define actualquirks phys.head.status[0]
1468#define host_status phys.head.status[1]
1469#define ssss_status phys.head.status[2]
1470#define host_flags phys.head.status[3]
1471
1472/*
1473 * Host flags
1474 */
1475#define HF_IN_PM0 1u
1476#define HF_IN_PM1 (1u<<1)
1477#define HF_ACT_PM (1u<<2)
1478#define HF_DP_SAVED (1u<<3)
1479#define HF_SENSE (1u<<4)
1480#define HF_EXT_ERR (1u<<5)
1481#define HF_DATA_IN (1u<<6)
1482#ifdef SYM_CONF_IARB_SUPPORT
1483#define HF_HINT_IARB (1u<<7)
1484#endif
1485
1486/*
1487 * Global CCB HEADER.
1488 *
1489 * Due to lack of indirect addressing on earlier NCR chips,
1490 * this substructure is copied from the ccb to a global
1491 * address after selection (or reselection) and copied back
1492 * before disconnect.
1493 * For SYMBIOS chips that support LOAD/STORE this copy is
1494 * not needed and thus not performed.
1495 */
1496
1497struct sym_ccbh {
1498 /*
1499 * Start and restart SCRIPTS addresses (must be at 0).
1500 */
1501/*0*/ struct sym_actscr go;
1502
1503 /*
1504 * SCRIPTS jump address that deal with data pointers.
1505 * 'savep' points to the position in the script responsible
1506 * for the actual transfer of data.
1507 * It's written on reception of a SAVE_DATA_POINTER message.
1508 */
1509 u32 savep; /* Jump address to saved data pointer */
1510 u32 lastp; /* SCRIPTS address at end of data */
1511 u32 goalp; /* Not accessed for now from SCRIPTS */
1512
1513 /*
1514 * Status fields.
1515 */
1516 u8 status[4];
1517};
1518
1519/*
1520 * Data Structure Block
1521 *
1522 * During execution of a ccb by the script processor, the
1523 * DSA (data structure address) register points to this
1524 * substructure of the ccb.
1525 */
1526struct sym_dsb {
1527 /*
1528 * CCB header.
1529 * Also assumed at offset 0 of the sym_ccb structure.
1530 */
1531/*0*/ struct sym_ccbh head;
1532
1533 /*
1534 * Phase mismatch contexts.
1535 * We need two to handle correctly the SAVED DATA POINTER.
1536 * MUST BOTH BE AT OFFSET < 256, due to using 8 bit arithmetic
1537 * for address calculation from SCRIPTS.
1538 */
1539 struct sym_pmc pm0;
1540 struct sym_pmc pm1;
1541
1542 /*
1543 * Table data for Script
1544 */
1545 struct sym_tblsel select;
1546 struct sym_tblmove smsg;
1547 struct sym_tblmove smsg_ext;
1548 struct sym_tblmove cmd;
1549 struct sym_tblmove sense;
1550 struct sym_tblmove wresid;
1551 struct sym_tblmove data [SYM_CONF_MAX_SG];
1552};
1553
1554/*
1555 * Our Command Control Block
1556 */
1557struct sym_ccb {
1558 /*
1559 * This is the data structure which is pointed by the DSA
1560 * register when it is executed by the script processor.
1561 * It must be the first entry.
1562 */
1563 struct sym_dsb phys;
1564
1565 /*
1566 * Pointer to CAM ccb and related stuff.
1567 */
1568 union ccb *cam_ccb; /* CAM scsiio ccb */
1569 u8 cdb_buf[16]; /* Copy of CDB */
1570 u8 *sns_bbuf; /* Bounce buffer for sense data */
1571#define SYM_SNS_BBUF_LEN sizeof(struct scsi_sense_data)
1572 int data_len; /* Total data length */
1573 int segments; /* Number of SG segments */
1574
1575 /*
1576 * Miscellaneous status'.
1577 */
1578 u_char nego_status; /* Negotiation status */
1579 u_char xerr_status; /* Extended error flags */
1580 u32 extra_bytes; /* Extraneous bytes transferred */
1581
1582 /*
1583 * Message areas.
1584 * We prepare a message to be sent after selection.
1585 * We may use a second one if the command is rescheduled
1586 * due to CHECK_CONDITION or COMMAND TERMINATED.
1587 * Contents are IDENTIFY and SIMPLE_TAG.
1588 * While negotiating sync or wide transfer,
1589 * a SDTR or WDTR message is appended.
1590 */
1591 u_char scsi_smsg [12];
1592 u_char scsi_smsg2[12];
1593
1594 /*
1595 * Auto request sense related fields.
1596 */
1597 u_char sensecmd[6]; /* Request Sense command */
1598 u_char sv_scsi_status; /* Saved SCSI status */
1599 u_char sv_xerr_status; /* Saved extended status */
1600 int sv_resid; /* Saved residual */
1601
1602 /*
1603 * Map for the DMA of user data.
1604 */
1605#ifdef FreeBSD_Bus_Dma_Abstraction
1606 void *arg; /* Argument for some callback */
1607 bus_dmamap_t dmamap; /* DMA map for user data */
1608 u_char dmamapped;
1609#define SYM_DMA_NONE 0
1610#define SYM_DMA_READ 1
1611#define SYM_DMA_WRITE 2
1612#endif
1613 /*
1614 * Other fields.
1615 */
1616 u32 ccb_ba; /* BUS address of this CCB */
1617 u_short tag; /* Tag for this transfer */
1618 /* NO_TAG means no tag */
1619 u_char target;
1620 u_char lun;
1621 ccb_p link_ccbh; /* Host adapter CCB hash chain */
1622 SYM_QUEHEAD
1623 link_ccbq; /* Link to free/busy CCB queue */
1624 u32 startp; /* Initial data pointer */
1625 int ext_sg; /* Extreme data pointer, used */
1626 int ext_ofs; /* to calculate the residual. */
1627 u_char to_abort; /* Want this IO to be aborted */
1628};
1629
1630#define CCB_BA(cp,lbl) (cp->ccb_ba + offsetof(struct sym_ccb, lbl))
1631
1632/*
1633 * Host Control Block
1634 */
1635struct sym_hcb {
1636 /*
1637 * Global headers.
1638 * Due to poorness of addressing capabilities, earlier
1639 * chips (810, 815, 825) copy part of the data structures
1640 * (CCB, TCB and LCB) in fixed areas.
1641 */
1642#ifdef SYM_CONF_GENERIC_SUPPORT
1643 struct sym_ccbh ccb_head;
1644 struct sym_tcbh tcb_head;
1645 struct sym_lcbh lcb_head;
1646#endif
1647 /*
1648 * Idle task and invalid task actions and
1649 * their bus addresses.
1650 */
1651 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1652 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1653
1654 /*
1655 * Dummy lun table to protect us against target
1656 * returning bad lun number on reselection.
1657 */
1658 u32 *badluntbl; /* Table physical address */
1659 u32 badlun_sa; /* SCRIPT handler BUS address */
1660
1661 /*
1662 * Bus address of this host control block.
1663 */
1664 u32 hcb_ba;
1665
1666 /*
1667 * Bit 32-63 of the on-chip RAM bus address in LE format.
1668 * The START_RAM64 script loads the MMRS and MMWS from this
1669 * field.
1670 */
1671 u32 scr_ram_seg;
1672
1673 /*
1674 * Chip and controller indentification.
1675 */
1676#ifdef FreeBSD_Bus_Io_Abstraction
1677 device_t device;
1678#else
1679 pcici_t pci_tag;
1680#endif
1681 int unit;
1682 char inst_name[8];
1683
1684 /*
1685 * Initial value of some IO register bits.
1686 * These values are assumed to have been set by BIOS, and may
1687 * be used to probe adapter implementation differences.
1688 */
1689 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1690 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1691 sv_stest1;
1692
1693 /*
1694 * Actual initial value of IO register bits used by the
1695 * driver. They are loaded at initialisation according to
1696 * features that are to be enabled/disabled.
1697 */
1698 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1699 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1700
1701 /*
1702 * Target data.
1703 */
1704 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1705
1706 /*
1707 * Target control block bus address array used by the SCRIPT
1708 * on reselection.
1709 */
1710 u32 *targtbl;
1711 u32 targtbl_ba;
1712
1713 /*
1714 * CAM SIM information for this instance.
1715 */
1716 struct cam_sim *sim;
1717 struct cam_path *path;
1718
1719 /*
1720 * Allocated hardware resources.
1721 */
1722#ifdef FreeBSD_Bus_Io_Abstraction
1723 struct resource *irq_res;
1724 struct resource *io_res;
1725 struct resource *mmio_res;
1726 struct resource *ram_res;
1727 int ram_id;
1728 void *intr;
1729#endif
1730
1731 /*
1732 * Bus stuff.
1733 *
1734 * My understanding of PCI is that all agents must share the
1735 * same addressing range and model.
1736 * But some hardware architecture guys provide complex and
1737 * brain-deaded stuff that makes shit.
1738 * This driver only support PCI compliant implementations and
1739 * deals with part of the BUS stuff complexity only to fit O/S
1740 * requirements.
1741 */
1742#ifdef FreeBSD_Bus_Io_Abstraction
1743 bus_space_handle_t io_bsh;
1744 bus_space_tag_t io_tag;
1745 bus_space_handle_t mmio_bsh;
1746 bus_space_tag_t mmio_tag;
1747 bus_space_handle_t ram_bsh;
1748 bus_space_tag_t ram_tag;
1749#endif
1750
1751 /*
1752 * DMA stuff.
1753 */
1754#ifdef FreeBSD_Bus_Dma_Abstraction
1755 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1756 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1757#endif
1758 /*
1759 * Virtual and physical bus addresses of the chip.
1760 */
1761 vm_offset_t mmio_va; /* MMIO kernel virtual address */
1762 vm_offset_t mmio_pa; /* MMIO CPU physical address */
1763 vm_offset_t mmio_ba; /* MMIO BUS address */
1764 int mmio_ws; /* MMIO Window size */
1765
1766 vm_offset_t ram_va; /* RAM kernel virtual address */
1767 vm_offset_t ram_pa; /* RAM CPU physical address */
1768 vm_offset_t ram_ba; /* RAM BUS address */
1769 int ram_ws; /* RAM window size */
1770 u32 io_port; /* IO port address */
1771
1772 /*
1773 * SCRIPTS virtual and physical bus addresses.
1774 * 'script' is loaded in the on-chip RAM if present.
1775 * 'scripth' stays in main memory for all chips except the
1776 * 53C895A, 53C896 and 53C1010 that provide 8K on-chip RAM.
1777 */
1778 u_char *scripta0; /* Copies of script and scripth */
1779 u_char *scriptb0; /* Copies of script and scripth */
1780 vm_offset_t scripta_ba; /* Actual script and scripth */
1781 vm_offset_t scriptb_ba; /* bus addresses. */
1782 vm_offset_t scriptb0_ba;
1783 u_short scripta_sz; /* Actual size of script A */
1784 u_short scriptb_sz; /* Actual size of script B */
1785
1786 /*
1787 * Bus addresses, setup and patch methods for
1788 * the selected firmware.
1789 */
1790 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1791 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1792 void (*fw_setup)(hcb_p np, struct sym_fw *fw);
1793 void (*fw_patch)(hcb_p np);
1794 char *fw_name;
1795
1796 /*
1797 * General controller parameters and configuration.
1798 */
1799 u_short device_id; /* PCI device id */
1800 u_char revision_id; /* PCI device revision id */
1801 u_int features; /* Chip features map */
1802 u_char myaddr; /* SCSI id of the adapter */
1803 u_char maxburst; /* log base 2 of dwords burst */
1804 u_char maxwide; /* Maximum transfer width */
1805 u_char minsync; /* Min sync period factor (ST) */
1806 u_char maxsync; /* Max sync period factor (ST) */
1807 u_char maxoffs; /* Max scsi offset (ST) */
1808 u_char minsync_dt; /* Min sync period factor (DT) */
1809 u_char maxsync_dt; /* Max sync period factor (DT) */
1810 u_char maxoffs_dt; /* Max scsi offset (DT) */
1811 u_char multiplier; /* Clock multiplier (1,2,4) */
1812 u_char clock_divn; /* Number of clock divisors */
1813 u32 clock_khz; /* SCSI clock frequency in KHz */
1814 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1815 /*
1816 * Start queue management.
1817 * It is filled up by the host processor and accessed by the
1818 * SCRIPTS processor in order to start SCSI commands.
1819 */
1820 volatile /* Prevent code optimizations */
1821 u32 *squeue; /* Start queue virtual address */
1822 u32 squeue_ba; /* Start queue BUS address */
1823 u_short squeueput; /* Next free slot of the queue */
1824 u_short actccbs; /* Number of allocated CCBs */
1825
1826 /*
1827 * Command completion queue.
1828 * It is the same size as the start queue to avoid overflow.
1829 */
1830 u_short dqueueget; /* Next position to scan */
1831 volatile /* Prevent code optimizations */
1832 u32 *dqueue; /* Completion (done) queue */
1833 u32 dqueue_ba; /* Done queue BUS address */
1834
1835 /*
1836 * Miscellaneous buffers accessed by the scripts-processor.
1837 * They shall be DWORD aligned, because they may be read or
1838 * written with a script command.
1839 */
1840 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1841 u_char msgin [8]; /* Buffer for MESSAGE IN */
1842 u32 lastmsg; /* Last SCSI message sent */
1843 u_char scratch; /* Scratch for SCSI receive */
1844
1845 /*
1846 * Miscellaneous configuration and status parameters.
1847 */
1848 u_char usrflags; /* Miscellaneous user flags */
1849 u_char scsi_mode; /* Current SCSI BUS mode */
1850 u_char verbose; /* Verbosity for this controller*/
1851 u32 cache; /* Used for cache test at init. */
1852
1853 /*
1854 * CCB lists and queue.
1855 */
1856 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1857 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1858 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1859
1860 /*
1861 * During error handling and/or recovery,
1862 * active CCBs that are to be completed with
1863 * error or requeued are moved from the busy_ccbq
1864 * to the comp_ccbq prior to completion.
1865 */
1866 SYM_QUEHEAD comp_ccbq;
1867
1868 /*
1869 * CAM CCB pending queue.
1870 */
1871 SYM_QUEHEAD cam_ccbq;
1872
1873 /*
1874 * IMMEDIATE ARBITRATION (IARB) control.
1875 *
1876 * We keep track in 'last_cp' of the last CCB that has been
1877 * queued to the SCRIPTS processor and clear 'last_cp' when
1878 * this CCB completes. If last_cp is not zero at the moment
1879 * we queue a new CCB, we set a flag in 'last_cp' that is
1880 * used by the SCRIPTS as a hint for setting IARB.
1881 * We donnot set more than 'iarb_max' consecutive hints for
1882 * IARB in order to leave devices a chance to reselect.
1883 * By the way, any non zero value of 'iarb_max' is unfair. :)
1884 */
1885#ifdef SYM_CONF_IARB_SUPPORT
1886 u_short iarb_max; /* Max. # consecutive IARB hints*/
1887 u_short iarb_count; /* Actual # of these hints */
1888 ccb_p last_cp;
1889#endif
1890
1891 /*
1892 * Command abort handling.
1893 * We need to synchronize tightly with the SCRIPTS
1894 * processor in order to handle things correctly.
1895 */
1896 u_char abrt_msg[4]; /* Message to send buffer */
1897 struct sym_tblmove abrt_tbl; /* Table for the MOV of it */
1898 struct sym_tblsel abrt_sel; /* Sync params for selection */
1899 u_char istat_sem; /* Tells the chip to stop (SEM) */
1900};
1901
1902#define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl))
1903
1904/*
1905 * Return the name of the controller.
1906 */
1907static __inline char *sym_name(hcb_p np)
1908{
1909 return np->inst_name;
1910}
1911
1912/*--------------------------------------------------------------------------*/
1913/*------------------------------ FIRMWARES ---------------------------------*/
1914/*--------------------------------------------------------------------------*/
1915
1916/*
1917 * This stuff will be moved to a separate source file when
1918 * the driver will be broken into several source modules.
1919 */
1920
1921/*
1922 * Macros used for all firmwares.
1923 */
1924#define SYM_GEN_A(s, label) ((short) offsetof(s, label)),
1925#define SYM_GEN_B(s, label) ((short) offsetof(s, label)),
1926#define PADDR_A(label) SYM_GEN_PADDR_A(struct SYM_FWA_SCR, label)
1927#define PADDR_B(label) SYM_GEN_PADDR_B(struct SYM_FWB_SCR, label)
1928
1929
1930#ifdef SYM_CONF_GENERIC_SUPPORT
1931/*
1932 * Allocate firmware #1 script area.
1933 */
1934#define SYM_FWA_SCR sym_fw1a_scr
1935#define SYM_FWB_SCR sym_fw1b_scr
1f2de5d4 1936#include "sym_fw1.h"
984263bc
MD
1937struct sym_fwa_ofs sym_fw1a_ofs = {
1938 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1939};
1940struct sym_fwb_ofs sym_fw1b_ofs = {
1941 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1942};
1943#undef SYM_FWA_SCR
1944#undef SYM_FWB_SCR
1945#endif /* SYM_CONF_GENERIC_SUPPORT */
1946
1947/*
1948 * Allocate firmware #2 script area.
1949 */
1950#define SYM_FWA_SCR sym_fw2a_scr
1951#define SYM_FWB_SCR sym_fw2b_scr
1f2de5d4 1952#include "sym_fw2.h"
984263bc
MD
1953struct sym_fwa_ofs sym_fw2a_ofs = {
1954 SYM_GEN_FW_A(struct SYM_FWA_SCR)
1955};
1956struct sym_fwb_ofs sym_fw2b_ofs = {
1957 SYM_GEN_FW_B(struct SYM_FWB_SCR)
1958 SYM_GEN_B(struct SYM_FWB_SCR, start64)
1959 SYM_GEN_B(struct SYM_FWB_SCR, pm_handle)
1960};
1961#undef SYM_FWA_SCR
1962#undef SYM_FWB_SCR
1963
1964#undef SYM_GEN_A
1965#undef SYM_GEN_B
1966#undef PADDR_A
1967#undef PADDR_B
1968
1969#ifdef SYM_CONF_GENERIC_SUPPORT
1970/*
1971 * Patch routine for firmware #1.
1972 */
1973static void
1974sym_fw1_patch(hcb_p np)
1975{
1976 struct sym_fw1a_scr *scripta0;
1977 struct sym_fw1b_scr *scriptb0;
1978
1979 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
1980 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
1981
1982 /*
1983 * Remove LED support if not needed.
1984 */
1985 if (!(np->features & FE_LED0)) {
1986 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
1987 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
1988 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
1989 }
1990
1991#ifdef SYM_CONF_IARB_SUPPORT
1992 /*
1993 * If user does not want to use IMMEDIATE ARBITRATION
1994 * when we are reselected while attempting to arbitrate,
1995 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
1996 */
1997 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
1998 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
1999#endif
2000 /*
2001 * Patch some data in SCRIPTS.
2002 * - start and done queue initial bus address.
2003 * - target bus address table bus address.
2004 */
2005 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
2006 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
2007 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
2008}
2009#endif /* SYM_CONF_GENERIC_SUPPORT */
2010
2011/*
2012 * Patch routine for firmware #2.
2013 */
2014static void
2015sym_fw2_patch(hcb_p np)
2016{
2017 struct sym_fw2a_scr *scripta0;
2018 struct sym_fw2b_scr *scriptb0;
2019
2020 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
2021 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
2022
2023 /*
2024 * Remove LED support if not needed.
2025 */
2026 if (!(np->features & FE_LED0)) {
2027 scripta0->idle[0] = cpu_to_scr(SCR_NO_OP);
2028 scripta0->reselected[0] = cpu_to_scr(SCR_NO_OP);
2029 scripta0->start[0] = cpu_to_scr(SCR_NO_OP);
2030 }
2031
2032#ifdef SYM_CONF_IARB_SUPPORT
2033 /*
2034 * If user does not want to use IMMEDIATE ARBITRATION
2035 * when we are reselected while attempting to arbitrate,
2036 * patch the SCRIPTS accordingly with a SCRIPT NO_OP.
2037 */
2038 if (!SYM_CONF_SET_IARB_ON_ARB_LOST)
2039 scripta0->ungetjob[0] = cpu_to_scr(SCR_NO_OP);
2040#endif
2041 /*
2042 * Patch some variable in SCRIPTS.
2043 * - start and done queue initial bus address.
2044 * - target bus address table bus address.
2045 */
2046 scriptb0->startpos[0] = cpu_to_scr(np->squeue_ba);
2047 scriptb0->done_pos[0] = cpu_to_scr(np->dqueue_ba);
2048 scriptb0->targtbl[0] = cpu_to_scr(np->targtbl_ba);
2049
2050 /*
2051 * Remove the load of SCNTL4 on reselection if not a C10.
2052 */
2053 if (!(np->features & FE_C10)) {
2054 scripta0->resel_scntl4[0] = cpu_to_scr(SCR_NO_OP);
2055 scripta0->resel_scntl4[1] = cpu_to_scr(0);
2056 }
2057
2058 /*
2059 * Remove a couple of work-arounds specific to C1010 if
2060 * they are not desirable. See `sym_fw2.h' for more details.
2061 */
2062 if (!(np->device_id == PCI_ID_LSI53C1010_2 &&
2063 np->revision_id < 0x1 &&
2064 np->pciclk_khz < 60000)) {
2065 scripta0->datao_phase[0] = cpu_to_scr(SCR_NO_OP);
2066 scripta0->datao_phase[1] = cpu_to_scr(0);
2067 }
2068 if (!(np->device_id == PCI_ID_LSI53C1010 &&
2069 /* np->revision_id < 0xff */ 1)) {
2070 scripta0->sel_done[0] = cpu_to_scr(SCR_NO_OP);
2071 scripta0->sel_done[1] = cpu_to_scr(0);
2072 }
2073
2074 /*
2075 * Patch some other variables in SCRIPTS.
2076 * These ones are loaded by the SCRIPTS processor.
2077 */
2078 scriptb0->pm0_data_addr[0] =
2079 cpu_to_scr(np->scripta_ba +
2080 offsetof(struct sym_fw2a_scr, pm0_data));
2081 scriptb0->pm1_data_addr[0] =
2082 cpu_to_scr(np->scripta_ba +
2083 offsetof(struct sym_fw2a_scr, pm1_data));
2084}
2085
2086/*
2087 * Fill the data area in scripts.
2088 * To be done for all firmwares.
2089 */
2090static void
2091sym_fw_fill_data (u32 *in, u32 *out)
2092{
2093 int i;
2094
2095 for (i = 0; i < SYM_CONF_MAX_SG; i++) {
2096 *in++ = SCR_CHMOV_TBL ^ SCR_DATA_IN;
2097 *in++ = offsetof (struct sym_dsb, data[i]);
2098 *out++ = SCR_CHMOV_TBL ^ SCR_DATA_OUT;
2099 *out++ = offsetof (struct sym_dsb, data[i]);
2100 }
2101}
2102
2103/*
2104 * Setup useful script bus addresses.
2105 * To be done for all firmwares.
2106 */
2107static void
2108sym_fw_setup_bus_addresses(hcb_p np, struct sym_fw *fw)
2109{
2110 u32 *pa;
2111 u_short *po;
2112 int i;
2113
2114 /*
2115 * Build the bus address table for script A
2116 * from the script A offset table.
2117 */
2118 po = (u_short *) fw->a_ofs;
2119 pa = (u32 *) &np->fwa_bas;
2120 for (i = 0 ; i < sizeof(np->fwa_bas)/sizeof(u32) ; i++)
2121 pa[i] = np->scripta_ba + po[i];
2122
2123 /*
2124 * Same for script B.
2125 */
2126 po = (u_short *) fw->b_ofs;
2127 pa = (u32 *) &np->fwb_bas;
2128 for (i = 0 ; i < sizeof(np->fwb_bas)/sizeof(u32) ; i++)
2129 pa[i] = np->scriptb_ba + po[i];
2130}
2131
2132#ifdef SYM_CONF_GENERIC_SUPPORT
2133/*
2134 * Setup routine for firmware #1.
2135 */
2136static void
2137sym_fw1_setup(hcb_p np, struct sym_fw *fw)
2138{
2139 struct sym_fw1a_scr *scripta0;
2140 struct sym_fw1b_scr *scriptb0;
2141
2142 scripta0 = (struct sym_fw1a_scr *) np->scripta0;
2143 scriptb0 = (struct sym_fw1b_scr *) np->scriptb0;
2144
2145 /*
2146 * Fill variable parts in scripts.
2147 */
2148 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2149
2150 /*
2151 * Setup bus addresses used from the C code..
2152 */
2153 sym_fw_setup_bus_addresses(np, fw);
2154}
2155#endif /* SYM_CONF_GENERIC_SUPPORT */
2156
2157/*
2158 * Setup routine for firmware #2.
2159 */
2160static void
2161sym_fw2_setup(hcb_p np, struct sym_fw *fw)
2162{
2163 struct sym_fw2a_scr *scripta0;
2164 struct sym_fw2b_scr *scriptb0;
2165
2166 scripta0 = (struct sym_fw2a_scr *) np->scripta0;
2167 scriptb0 = (struct sym_fw2b_scr *) np->scriptb0;
2168
2169 /*
2170 * Fill variable parts in scripts.
2171 */
2172 sym_fw_fill_data(scripta0->data_in, scripta0->data_out);
2173
2174 /*
2175 * Setup bus addresses used from the C code..
2176 */
2177 sym_fw_setup_bus_addresses(np, fw);
2178}
2179
2180/*
2181 * Allocate firmware descriptors.
2182 */
2183#ifdef SYM_CONF_GENERIC_SUPPORT
2184static struct sym_fw sym_fw1 = SYM_FW_ENTRY(sym_fw1, "NCR-generic");
2185#endif /* SYM_CONF_GENERIC_SUPPORT */
2186static struct sym_fw sym_fw2 = SYM_FW_ENTRY(sym_fw2, "LOAD/STORE-based");
2187
2188/*
2189 * Find the most appropriate firmware for a chip.
2190 */
2191static struct sym_fw *
2192sym_find_firmware(struct sym_pci_chip *chip)
2193{
2194 if (chip->features & FE_LDSTR)
2195 return &sym_fw2;
2196#ifdef SYM_CONF_GENERIC_SUPPORT
2197 else if (!(chip->features & (FE_PFEN|FE_NOPM|FE_DAC)))
2198 return &sym_fw1;
2199#endif
2200 else
2201 return 0;
2202}
2203
2204/*
2205 * Bind a script to physical addresses.
2206 */
2207static void sym_fw_bind_script (hcb_p np, u32 *start, int len)
2208{
2209 u32 opcode, new, old, tmp1, tmp2;
2210 u32 *end, *cur;
2211 int relocs;
2212
2213 cur = start;
2214 end = start + len/4;
2215
2216 while (cur < end) {
2217
2218 opcode = *cur;
2219
2220 /*
2221 * If we forget to change the length
2222 * in scripts, a field will be
2223 * padded with 0. This is an illegal
2224 * command.
2225 */
2226 if (opcode == 0) {
2227 printf ("%s: ERROR0 IN SCRIPT at %d.\n",
2228 sym_name(np), (int) (cur-start));
2229 MDELAY (10000);
2230 ++cur;
2231 continue;
2232 };
2233
2234 /*
2235 * We use the bogus value 0xf00ff00f ;-)
2236 * to reserve data area in SCRIPTS.
2237 */
2238 if (opcode == SCR_DATA_ZERO) {
2239 *cur++ = 0;
2240 continue;
2241 }
2242
2243 if (DEBUG_FLAGS & DEBUG_SCRIPT)
2244 printf ("%d: <%x>\n", (int) (cur-start),
2245 (unsigned)opcode);
2246
2247 /*
2248 * We don't have to decode ALL commands
2249 */
2250 switch (opcode >> 28) {
2251 case 0xf:
2252 /*
2253 * LOAD / STORE DSA relative, don't relocate.
2254 */
2255 relocs = 0;
2256 break;
2257 case 0xe:
2258 /*
2259 * LOAD / STORE absolute.
2260 */
2261 relocs = 1;
2262 break;
2263 case 0xc:
2264 /*
2265 * COPY has TWO arguments.
2266 */
2267 relocs = 2;
2268 tmp1 = cur[1];
2269 tmp2 = cur[2];
2270 if ((tmp1 ^ tmp2) & 3) {
2271 printf ("%s: ERROR1 IN SCRIPT at %d.\n",
2272 sym_name(np), (int) (cur-start));
2273 MDELAY (10000);
2274 }
2275 /*
2276 * If PREFETCH feature not enabled, remove
2277 * the NO FLUSH bit if present.
2278 */
2279 if ((opcode & SCR_NO_FLUSH) &&
2280 !(np->features & FE_PFEN)) {
2281 opcode = (opcode & ~SCR_NO_FLUSH);
2282 }
2283 break;
2284 case 0x0:
2285 /*
2286 * MOVE/CHMOV (absolute address)
2287 */
2288 if (!(np->features & FE_WIDE))
2289 opcode = (opcode | OPC_MOVE);
2290 relocs = 1;
2291 break;
2292 case 0x1:
2293 /*
2294 * MOVE/CHMOV (table indirect)
2295 */
2296 if (!(np->features & FE_WIDE))
2297 opcode = (opcode | OPC_MOVE);
2298 relocs = 0;
2299 break;
2300 case 0x8:
2301 /*
2302 * JUMP / CALL
2303 * dont't relocate if relative :-)
2304 */
2305 if (opcode & 0x00800000)
2306 relocs = 0;
2307 else if ((opcode & 0xf8400000) == 0x80400000)/*JUMP64*/
2308 relocs = 2;
2309 else
2310 relocs = 1;
2311 break;
2312 case 0x4:
2313 case 0x5:
2314 case 0x6:
2315 case 0x7:
2316 relocs = 1;
2317 break;
2318 default:
2319 relocs = 0;
2320 break;
2321 };
2322
2323 /*
2324 * Scriptify:) the opcode.
2325 */
2326 *cur++ = cpu_to_scr(opcode);
2327
2328 /*
2329 * If no relocation, assume 1 argument
2330 * and just scriptize:) it.
2331 */
2332 if (!relocs) {
2333 *cur = cpu_to_scr(*cur);
2334 ++cur;
2335 continue;
2336 }
2337
2338 /*
2339 * Otherwise performs all needed relocations.
2340 */
2341 while (relocs--) {
2342 old = *cur;
2343
2344 switch (old & RELOC_MASK) {
2345 case RELOC_REGISTER:
2346 new = (old & ~RELOC_MASK) + np->mmio_ba;
2347 break;
2348 case RELOC_LABEL_A:
2349 new = (old & ~RELOC_MASK) + np->scripta_ba;
2350 break;
2351 case RELOC_LABEL_B:
2352 new = (old & ~RELOC_MASK) + np->scriptb_ba;
2353 break;
2354 case RELOC_SOFTC:
2355 new = (old & ~RELOC_MASK) + np->hcb_ba;
2356 break;
2357 case 0:
2358 /*
2359 * Don't relocate a 0 address.
2360 * They are mostly used for patched or
2361 * script self-modified areas.
2362 */
2363 if (old == 0) {
2364 new = old;
2365 break;
2366 }
2367 /* fall through */
2368 default:
2369 new = 0;
2370 panic("sym_fw_bind_script: "
2371 "weird relocation %x\n", old);
2372 break;
2373 }
2374
2375 *cur++ = cpu_to_scr(new);
2376 }
2377 };
2378}
2379
2380/*--------------------------------------------------------------------------*/
2381/*--------------------------- END OF FIRMARES -----------------------------*/
2382/*--------------------------------------------------------------------------*/
2383
2384/*
2385 * Function prototypes.
2386 */
2387static void sym_save_initial_setting (hcb_p np);
2388static int sym_prepare_setting (hcb_p np, struct sym_nvram *nvram);
2389static int sym_prepare_nego (hcb_p np, ccb_p cp, int nego, u_char *msgptr);
2390static void sym_put_start_queue (hcb_p np, ccb_p cp);
2391static void sym_chip_reset (hcb_p np);
2392static void sym_soft_reset (hcb_p np);
2393static void sym_start_reset (hcb_p np);
2394static int sym_reset_scsi_bus (hcb_p np, int enab_int);
2395static int sym_wakeup_done (hcb_p np);
2396static void sym_flush_busy_queue (hcb_p np, int cam_status);
2397static void sym_flush_comp_queue (hcb_p np, int cam_status);
2398static void sym_init (hcb_p np, int reason);
2399static int sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp,
2400 u_char *fakp);
2401static void sym_setsync (hcb_p np, ccb_p cp, u_char ofs, u_char per,
2402 u_char div, u_char fak);
2403static void sym_setwide (hcb_p np, ccb_p cp, u_char wide);
2404static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2405 u_char per, u_char wide, u_char div, u_char fak);
2406static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
2407 u_char per, u_char wide, u_char div, u_char fak);
2408static void sym_log_hard_error (hcb_p np, u_short sist, u_char dstat);
2409static void sym_intr (void *arg);
2410static void sym_poll (struct cam_sim *sim);
2411static void sym_recover_scsi_int (hcb_p np, u_char hsts);
2412static void sym_int_sto (hcb_p np);
2413static void sym_int_udc (hcb_p np);
2414static void sym_int_sbmc (hcb_p np);
2415static void sym_int_par (hcb_p np, u_short sist);
2416static void sym_int_ma (hcb_p np);
2417static int sym_dequeue_from_squeue(hcb_p np, int i, int target, int lun,
2418 int task);
2419static void sym_sir_bad_scsi_status (hcb_p np, int num, ccb_p cp);
2420static int sym_clear_tasks (hcb_p np, int status, int targ, int lun, int task);
2421static void sym_sir_task_recovery (hcb_p np, int num);
2422static int sym_evaluate_dp (hcb_p np, ccb_p cp, u32 scr, int *ofs);
2423static void sym_modify_dp (hcb_p np, tcb_p tp, ccb_p cp, int ofs);
2424static int sym_compute_residual (hcb_p np, ccb_p cp);
2425static int sym_show_msg (u_char * msg);
2426static void sym_print_msg (ccb_p cp, char *label, u_char *msg);
2427static void sym_sync_nego (hcb_p np, tcb_p tp, ccb_p cp);
2428static void sym_ppr_nego (hcb_p np, tcb_p tp, ccb_p cp);
2429static void sym_wide_nego (hcb_p np, tcb_p tp, ccb_p cp);
2430static void sym_nego_default (hcb_p np, tcb_p tp, ccb_p cp);
2431static void sym_nego_rejected (hcb_p np, tcb_p tp, ccb_p cp);
2432static void sym_int_sir (hcb_p np);
2433static void sym_free_ccb (hcb_p np, ccb_p cp);
2434static ccb_p sym_get_ccb (hcb_p np, u_char tn, u_char ln, u_char tag_order);
2435static ccb_p sym_alloc_ccb (hcb_p np);
2436static ccb_p sym_ccb_from_dsa (hcb_p np, u32 dsa);
2437static lcb_p sym_alloc_lcb (hcb_p np, u_char tn, u_char ln);
2438static void sym_alloc_lcb_tags (hcb_p np, u_char tn, u_char ln);
2439static int sym_snooptest (hcb_p np);
2440static void sym_selectclock(hcb_p np, u_char scntl3);
2441static void sym_getclock (hcb_p np, int mult);
2442static int sym_getpciclock (hcb_p np);
2443static void sym_complete_ok (hcb_p np, ccb_p cp);
2444static void sym_complete_error (hcb_p np, ccb_p cp);
2445static void sym_timeout (void *arg);
2446static int sym_abort_scsiio (hcb_p np, union ccb *ccb, int timed_out);
2447static void sym_reset_dev (hcb_p np, union ccb *ccb);
2448static void sym_action (struct cam_sim *sim, union ccb *ccb);
2449static void sym_action1 (struct cam_sim *sim, union ccb *ccb);
2450static int sym_setup_cdb (hcb_p np, struct ccb_scsiio *csio, ccb_p cp);
2451static void sym_setup_data_and_start (hcb_p np, struct ccb_scsiio *csio,
2452 ccb_p cp);
2453#ifdef FreeBSD_Bus_Dma_Abstraction
2454static int sym_fast_scatter_sg_physical(hcb_p np, ccb_p cp,
2455 bus_dma_segment_t *psegs, int nsegs);
2456#else
2457static int sym_scatter_virtual (hcb_p np, ccb_p cp, vm_offset_t vaddr,
2458 vm_size_t len);
2459static int sym_scatter_sg_virtual (hcb_p np, ccb_p cp,
2460 bus_dma_segment_t *psegs, int nsegs);
2461static int sym_scatter_physical (hcb_p np, ccb_p cp, vm_offset_t paddr,
2462 vm_size_t len);
2463#endif
2464static int sym_scatter_sg_physical (hcb_p np, ccb_p cp,
2465 bus_dma_segment_t *psegs, int nsegs);
2466static void sym_action2 (struct cam_sim *sim, union ccb *ccb);
2467static void sym_update_trans (hcb_p np, tcb_p tp, struct sym_trans *tip,
2468 struct ccb_trans_settings *cts);
2469static void sym_update_dflags(hcb_p np, u_char *flags,
2470 struct ccb_trans_settings *cts);
2471
2472#ifdef FreeBSD_Bus_Io_Abstraction
2473static struct sym_pci_chip *sym_find_pci_chip (device_t dev);
2474static int sym_pci_probe (device_t dev);
2475static int sym_pci_attach (device_t dev);
2476#else
2477static struct sym_pci_chip *sym_find_pci_chip (pcici_t tag);
2478static const char *sym_pci_probe (pcici_t tag, pcidi_t type);
2479static void sym_pci_attach (pcici_t tag, int unit);
2480static int sym_pci_attach2 (pcici_t tag, int unit);
2481#endif
2482
2483static void sym_pci_free (hcb_p np);
2484static int sym_cam_attach (hcb_p np);
2485static void sym_cam_free (hcb_p np);
2486
2487static void sym_nvram_setup_host (hcb_p np, struct sym_nvram *nvram);
2488static void sym_nvram_setup_target (hcb_p np, int targ, struct sym_nvram *nvp);
2489static int sym_read_nvram (hcb_p np, struct sym_nvram *nvp);
2490
2491/*
2492 * Print something which allows to retrieve the controler type,
2493 * unit, target, lun concerned by a kernel message.
2494 */
2495static void PRINT_TARGET (hcb_p np, int target)
2496{
2497 printf ("%s:%d:", sym_name(np), target);
2498}
2499
2500static void PRINT_LUN(hcb_p np, int target, int lun)
2501{
2502 printf ("%s:%d:%d:", sym_name(np), target, lun);
2503}
2504
2505static void PRINT_ADDR (ccb_p cp)
2506{
2507 if (cp && cp->cam_ccb)
2508 xpt_print_path(cp->cam_ccb->ccb_h.path);
2509}
2510
2511/*
2512 * Take into account this ccb in the freeze count.
2513 */
2514static void sym_freeze_cam_ccb(union ccb *ccb)
2515{
2516 if (!(ccb->ccb_h.flags & CAM_DEV_QFRZDIS)) {
2517 if (!(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2518 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2519 xpt_freeze_devq(ccb->ccb_h.path, 1);
2520 }
2521 }
2522}
2523
2524/*
2525 * Set the status field of a CAM CCB.
2526 */
2527static __inline void sym_set_cam_status(union ccb *ccb, cam_status status)
2528{
2529 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2530 ccb->ccb_h.status |= status;
2531}
2532
2533/*
2534 * Get the status field of a CAM CCB.
2535 */
2536static __inline int sym_get_cam_status(union ccb *ccb)
2537{
2538 return ccb->ccb_h.status & CAM_STATUS_MASK;
2539}
2540
2541/*
2542 * Enqueue a CAM CCB.
2543 */
2544static void sym_enqueue_cam_ccb(hcb_p np, union ccb *ccb)
2545{
2546 assert(!(ccb->ccb_h.status & CAM_SIM_QUEUED));
2547 ccb->ccb_h.status = CAM_REQ_INPROG;
2548
ddcafce9
JS
2549 callout_reset(&ccb->ccb_h.timeout_ch, ccb->ccb_h.timeout*hz/1000,
2550 sym_timeout, ccb);
984263bc
MD
2551 ccb->ccb_h.status |= CAM_SIM_QUEUED;
2552 ccb->ccb_h.sym_hcb_ptr = np;
2553
2554 sym_insque_tail(sym_qptr(&ccb->ccb_h.sim_links), &np->cam_ccbq);
2555}
2556
2557/*
2558 * Complete a pending CAM CCB.
2559 */
2560static void sym_xpt_done(hcb_p np, union ccb *ccb)
2561{
2562 if (ccb->ccb_h.status & CAM_SIM_QUEUED) {
ddcafce9 2563 callout_stop(&ccb->ccb_h.timeout_ch);
984263bc
MD
2564 sym_remque(sym_qptr(&ccb->ccb_h.sim_links));
2565 ccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2566 ccb->ccb_h.sym_hcb_ptr = 0;
2567 }
2568 if (ccb->ccb_h.flags & CAM_DEV_QFREEZE)
2569 sym_freeze_cam_ccb(ccb);
2570 xpt_done(ccb);
2571}
2572
2573static void sym_xpt_done2(hcb_p np, union ccb *ccb, int cam_status)
2574{
2575 sym_set_cam_status(ccb, cam_status);
2576 sym_xpt_done(np, ccb);
2577}
2578
2579/*
2580 * SYMBIOS chip clock divisor table.
2581 *
2582 * Divisors are multiplied by 10,000,000 in order to make
2583 * calculations more simple.
2584 */
2585#define _5M 5000000
2586static u32 div_10M[] = {2*_5M, 3*_5M, 4*_5M, 6*_5M, 8*_5M, 12*_5M, 16*_5M};
2587
2588/*
2589 * SYMBIOS chips allow burst lengths of 2, 4, 8, 16, 32, 64,
2590 * 128 transfers. All chips support at least 16 transfers
2591 * bursts. The 825A, 875 and 895 chips support bursts of up
2592 * to 128 transfers and the 895A and 896 support bursts of up
2593 * to 64 transfers. All other chips support up to 16
2594 * transfers bursts.
2595 *
2596 * For PCI 32 bit data transfers each transfer is a DWORD.
2597 * It is a QUADWORD (8 bytes) for PCI 64 bit data transfers.
2598 *
2599 * We use log base 2 (burst length) as internal code, with
2600 * value 0 meaning "burst disabled".
2601 */
2602
2603/*
2604 * Burst length from burst code.
2605 */
2606#define burst_length(bc) (!(bc))? 0 : 1 << (bc)
2607
2608/*
2609 * Burst code from io register bits.
2610 */
2611#define burst_code(dmode, ctest4, ctest5) \
2612 (ctest4) & 0x80? 0 : (((dmode) & 0xc0) >> 6) + ((ctest5) & 0x04) + 1
2613
2614/*
2615 * Set initial io register bits from burst code.
2616 */
2617static __inline void sym_init_burst(hcb_p np, u_char bc)
2618{
2619 np->rv_ctest4 &= ~0x80;
2620 np->rv_dmode &= ~(0x3 << 6);
2621 np->rv_ctest5 &= ~0x4;
2622
2623 if (!bc) {
2624 np->rv_ctest4 |= 0x80;
2625 }
2626 else {
2627 --bc;
2628 np->rv_dmode |= ((bc & 0x3) << 6);
2629 np->rv_ctest5 |= (bc & 0x4);
2630 }
2631}
2632
2633
2634/*
2635 * Print out the list of targets that have some flag disabled by user.
2636 */
2637static void sym_print_targets_flag(hcb_p np, int mask, char *msg)
2638{
2639 int cnt;
2640 int i;
2641
2642 for (cnt = 0, i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2643 if (i == np->myaddr)
2644 continue;
2645 if (np->target[i].usrflags & mask) {
2646 if (!cnt++)
2647 printf("%s: %s disabled for targets",
2648 sym_name(np), msg);
2649 printf(" %d", i);
2650 }
2651 }
2652 if (cnt)
2653 printf(".\n");
2654}
2655
2656/*
2657 * Save initial settings of some IO registers.
2658 * Assumed to have been set by BIOS.
2659 * We cannot reset the chip prior to reading the
2660 * IO registers, since informations will be lost.
2661 * Since the SCRIPTS processor may be running, this
2662 * is not safe on paper, but it seems to work quite
2663 * well. :)
2664 */
2665static void sym_save_initial_setting (hcb_p np)
2666{
2667 np->sv_scntl0 = INB(nc_scntl0) & 0x0a;
2668 np->sv_scntl3 = INB(nc_scntl3) & 0x07;
2669 np->sv_dmode = INB(nc_dmode) & 0xce;
2670 np->sv_dcntl = INB(nc_dcntl) & 0xa8;
2671 np->sv_ctest3 = INB(nc_ctest3) & 0x01;
2672 np->sv_ctest4 = INB(nc_ctest4) & 0x80;
2673 np->sv_gpcntl = INB(nc_gpcntl);
2674 np->sv_stest1 = INB(nc_stest1);
2675 np->sv_stest2 = INB(nc_stest2) & 0x20;
2676 np->sv_stest4 = INB(nc_stest4);
2677 if (np->features & FE_C10) { /* Always large DMA fifo + ultra3 */
2678 np->sv_scntl4 = INB(nc_scntl4);
2679 np->sv_ctest5 = INB(nc_ctest5) & 0x04;
2680 }
2681 else
2682 np->sv_ctest5 = INB(nc_ctest5) & 0x24;
2683}
2684
2685/*
2686 * Prepare io register values used by sym_init() according
2687 * to selected and supported features.
2688 */
2689static int sym_prepare_setting(hcb_p np, struct sym_nvram *nvram)
2690{
2691 u_char burst_max;
2692 u32 period;
2693 int i;
2694
2695 /*
2696 * Wide ?
2697 */
2698 np->maxwide = (np->features & FE_WIDE)? 1 : 0;
2699
2700 /*
2701 * Get the frequency of the chip's clock.
2702 */
2703 if (np->features & FE_QUAD)
2704 np->multiplier = 4;
2705 else if (np->features & FE_DBLR)
2706 np->multiplier = 2;
2707 else
2708 np->multiplier = 1;
2709
2710 np->clock_khz = (np->features & FE_CLK80)? 80000 : 40000;
2711 np->clock_khz *= np->multiplier;
2712
2713 if (np->clock_khz != 40000)
2714 sym_getclock(np, np->multiplier);
2715
2716 /*
2717 * Divisor to be used for async (timer pre-scaler).
2718 */
2719 i = np->clock_divn - 1;
2720 while (--i >= 0) {
2721 if (10ul * SYM_CONF_MIN_ASYNC * np->clock_khz > div_10M[i]) {
2722 ++i;
2723 break;
2724 }
2725 }
2726 np->rv_scntl3 = i+1;
2727
2728 /*
2729 * The C1010 uses hardwired divisors for async.
2730 * So, we just throw away, the async. divisor.:-)
2731 */
2732 if (np->features & FE_C10)
2733 np->rv_scntl3 = 0;
2734
2735 /*
2736 * Minimum synchronous period factor supported by the chip.
2737 * Btw, 'period' is in tenths of nanoseconds.
2738 */
2739 period = (4 * div_10M[0] + np->clock_khz - 1) / np->clock_khz;
2740 if (period <= 250) np->minsync = 10;
2741 else if (period <= 303) np->minsync = 11;
2742 else if (period <= 500) np->minsync = 12;
2743 else np->minsync = (period + 40 - 1) / 40;
2744
2745 /*
2746 * Check against chip SCSI standard support (SCSI-2,ULTRA,ULTRA2).
2747 */
2748 if (np->minsync < 25 &&
2749 !(np->features & (FE_ULTRA|FE_ULTRA2|FE_ULTRA3)))
2750 np->minsync = 25;
2751 else if (np->minsync < 12 &&
2752 !(np->features & (FE_ULTRA2|FE_ULTRA3)))
2753 np->minsync = 12;
2754
2755 /*
2756 * Maximum synchronous period factor supported by the chip.
2757 */
2758 period = (11 * div_10M[np->clock_divn - 1]) / (4 * np->clock_khz);
2759 np->maxsync = period > 2540 ? 254 : period / 10;
2760
2761 /*
2762 * If chip is a C1010, guess the sync limits in DT mode.
2763 */
2764 if ((np->features & (FE_C10|FE_ULTRA3)) == (FE_C10|FE_ULTRA3)) {
2765 if (np->clock_khz == 160000) {
2766 np->minsync_dt = 9;
2767 np->maxsync_dt = 50;
2768 np->maxoffs_dt = 62;
2769 }
2770 }
2771
2772 /*
2773 * 64 bit addressing (895A/896/1010) ?
2774 */
2775 if (np->features & FE_DAC)
2776#if BITS_PER_LONG > 32
2777 np->rv_ccntl1 |= (XTIMOD | EXTIBMV);
2778#else
2779 np->rv_ccntl1 |= (DDAC);
2780#endif
2781
2782 /*
2783 * Phase mismatch handled by SCRIPTS (895A/896/1010) ?
2784 */
2785 if (np->features & FE_NOPM)
2786 np->rv_ccntl0 |= (ENPMJ);
2787
2788 /*
2789 * C1010 Errata.
2790 * In dual channel mode, contention occurs if internal cycles
2791 * are used. Disable internal cycles.
2792 */
2793 if (np->device_id == PCI_ID_LSI53C1010 &&
2794 np->revision_id < 0x2)
2795 np->rv_ccntl0 |= DILS;
2796
2797 /*
2798 * Select burst length (dwords)
2799 */
2800 burst_max = SYM_SETUP_BURST_ORDER;
2801 if (burst_max == 255)
2802 burst_max = burst_code(np->sv_dmode, np->sv_ctest4,
2803 np->sv_ctest5);
2804 if (burst_max > 7)
2805 burst_max = 7;
2806 if (burst_max > np->maxburst)
2807 burst_max = np->maxburst;
2808
2809 /*
2810 * DEL 352 - 53C810 Rev x11 - Part Number 609-0392140 - ITEM 2.
2811 * This chip and the 860 Rev 1 may wrongly use PCI cache line
2812 * based transactions on LOAD/STORE instructions. So we have
2813 * to prevent these chips from using such PCI transactions in
2814 * this driver. The generic ncr driver that does not use
2815 * LOAD/STORE instructions does not need this work-around.
2816 */
2817 if ((np->device_id == PCI_ID_SYM53C810 &&
2818 np->revision_id >= 0x10 && np->revision_id <= 0x11) ||
2819 (np->device_id == PCI_ID_SYM53C860 &&
2820 np->revision_id <= 0x1))
2821 np->features &= ~(FE_WRIE|FE_ERL|FE_ERMP);
2822
2823 /*
2824 * Select all supported special features.
2825 * If we are using on-board RAM for scripts, prefetch (PFEN)
2826 * does not help, but burst op fetch (BOF) does.
2827 * Disabling PFEN makes sure BOF will be used.
2828 */
2829 if (np->features & FE_ERL)
2830 np->rv_dmode |= ERL; /* Enable Read Line */
2831 if (np->features & FE_BOF)
2832 np->rv_dmode |= BOF; /* Burst Opcode Fetch */
2833 if (np->features & FE_ERMP)
2834 np->rv_dmode |= ERMP; /* Enable Read Multiple */
2835#if 1
2836 if ((np->features & FE_PFEN) && !np->ram_ba)
2837#else
2838 if (np->features & FE_PFEN)
2839#endif
2840 np->rv_dcntl |= PFEN; /* Prefetch Enable */
2841 if (np->features & FE_CLSE)
2842 np->rv_dcntl |= CLSE; /* Cache Line Size Enable */
2843 if (np->features & FE_WRIE)
2844 np->rv_ctest3 |= WRIE; /* Write and Invalidate */
2845 if (np->features & FE_DFS)
2846 np->rv_ctest5 |= DFS; /* Dma Fifo Size */
2847
2848 /*
2849 * Select some other
2850 */
2851 if (SYM_SETUP_PCI_PARITY)
2852 np->rv_ctest4 |= MPEE; /* Master parity checking */
2853 if (SYM_SETUP_SCSI_PARITY)
2854 np->rv_scntl0 |= 0x0a; /* full arb., ena parity, par->ATN */
2855
2856 /*
2857 * Get parity checking, host ID and verbose mode from NVRAM
2858 */
2859 np->myaddr = 255;
2860 sym_nvram_setup_host (np, nvram);
2861
2862 /*
2863 * Get SCSI addr of host adapter (set by bios?).
2864 */
2865 if (np->myaddr == 255) {
2866 np->myaddr = INB(nc_scid) & 0x07;
2867 if (!np->myaddr)
2868 np->myaddr = SYM_SETUP_HOST_ID;
2869 }
2870
2871 /*
2872 * Prepare initial io register bits for burst length
2873 */
2874 sym_init_burst(np, burst_max);
2875
2876 /*
2877 * Set SCSI BUS mode.
2878 * - LVD capable chips (895/895A/896/1010) report the
2879 * current BUS mode through the STEST4 IO register.
2880 * - For previous generation chips (825/825A/875),
2881 * user has to tell us how to check against HVD,
2882 * since a 100% safe algorithm is not possible.
2883 */
2884 np->scsi_mode = SMODE_SE;
2885 if (np->features & (FE_ULTRA2|FE_ULTRA3))
2886 np->scsi_mode = (np->sv_stest4 & SMODE);
2887 else if (np->features & FE_DIFF) {
2888 if (SYM_SETUP_SCSI_DIFF == 1) {
2889 if (np->sv_scntl3) {
2890 if (np->sv_stest2 & 0x20)
2891 np->scsi_mode = SMODE_HVD;
2892 }
2893 else if (nvram->type == SYM_SYMBIOS_NVRAM) {
2894 if (!(INB(nc_gpreg) & 0x08))
2895 np->scsi_mode = SMODE_HVD;
2896 }
2897 }
2898 else if (SYM_SETUP_SCSI_DIFF == 2)
2899 np->scsi_mode = SMODE_HVD;
2900 }
2901 if (np->scsi_mode == SMODE_HVD)
2902 np->rv_stest2 |= 0x20;
2903
2904 /*
2905 * Set LED support from SCRIPTS.
2906 * Ignore this feature for boards known to use a
2907 * specific GPIO wiring and for the 895A, 896
2908 * and 1010 that drive the LED directly.
2909 */
2910 if ((SYM_SETUP_SCSI_LED ||
2911 (nvram->type == SYM_SYMBIOS_NVRAM ||
2912 (nvram->type == SYM_TEKRAM_NVRAM &&
2913 np->device_id == PCI_ID_SYM53C895))) &&
2914 !(np->features & FE_LEDC) && !(np->sv_gpcntl & 0x01))
2915 np->features |= FE_LED0;
2916
2917 /*
2918 * Set irq mode.
2919 */
2920 switch(SYM_SETUP_IRQ_MODE & 3) {
2921 case 2:
2922 np->rv_dcntl |= IRQM;
2923 break;
2924 case 1:
2925 np->rv_dcntl |= (np->sv_dcntl & IRQM);
2926 break;
2927 default:
2928 break;
2929 }
2930
2931 /*
2932 * Configure targets according to driver setup.
2933 * If NVRAM present get targets setup from NVRAM.
2934 */
2935 for (i = 0 ; i < SYM_CONF_MAX_TARGET ; i++) {
2936 tcb_p tp = &np->target[i];
2937
2938#ifdef FreeBSD_New_Tran_Settings
2939 tp->tinfo.user.scsi_version = tp->tinfo.current.scsi_version= 2;
2940 tp->tinfo.user.spi_version = tp->tinfo.current.spi_version = 2;
2941#endif
2942 tp->tinfo.user.period = np->minsync;
2943 tp->tinfo.user.offset = np->maxoffs;
2944 tp->tinfo.user.width = np->maxwide ? BUS_16_BIT : BUS_8_BIT;
2945 tp->usrflags |= (SYM_DISC_ENABLED | SYM_TAGS_ENABLED);
2946 tp->usrtags = SYM_SETUP_MAX_TAG;
2947
2948 sym_nvram_setup_target (np, i, nvram);
2949
2950 /*
2951 * For now, guess PPR/DT support from the period
2952 * and BUS width.
2953 */
2954 if (np->features & FE_ULTRA3) {
2955 if (tp->tinfo.user.period <= 9 &&
2956 tp->tinfo.user.width == BUS_16_BIT) {
2957 tp->tinfo.user.options |= PPR_OPT_DT;
2958 tp->tinfo.user.offset = np->maxoffs_dt;
2959#ifdef FreeBSD_New_Tran_Settings
2960 tp->tinfo.user.spi_version = 3;
2961#endif
2962 }
2963 }
2964
2965 if (!tp->usrtags)
2966 tp->usrflags &= ~SYM_TAGS_ENABLED;
2967 }
2968
2969 /*
2970 * Let user know about the settings.
2971 */
2972 i = nvram->type;
2973 printf("%s: %s NVRAM, ID %d, Fast-%d, %s, %s\n", sym_name(np),
2974 i == SYM_SYMBIOS_NVRAM ? "Symbios" :
2975 (i == SYM_TEKRAM_NVRAM ? "Tekram" : "No"),
2976 np->myaddr,
2977 (np->features & FE_ULTRA3) ? 80 :
2978 (np->features & FE_ULTRA2) ? 40 :
2979 (np->features & FE_ULTRA) ? 20 : 10,
2980 sym_scsi_bus_mode(np->scsi_mode),
2981 (np->rv_scntl0 & 0xa) ? "parity checking" : "NO parity");
2982 /*
2983 * Tell him more on demand.
2984 */
2985 if (sym_verbose) {
2986 printf("%s: %s IRQ line driver%s\n",
2987 sym_name(np),
2988 np->rv_dcntl & IRQM ? "totem pole" : "open drain",
2989 np->ram_ba ? ", using on-chip SRAM" : "");
2990 printf("%s: using %s firmware.\n", sym_name(np), np->fw_name);
2991 if (np->features & FE_NOPM)
2992 printf("%s: handling phase mismatch from SCRIPTS.\n",
2993 sym_name(np));
2994 }
2995 /*
2996 * And still more.
2997 */
2998 if (sym_verbose > 1) {
2999 printf ("%s: initial SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
3000 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
3001 sym_name(np), np->sv_scntl3, np->sv_dmode, np->sv_dcntl,
3002 np->sv_ctest3, np->sv_ctest4, np->sv_ctest5);
3003
3004 printf ("%s: final SCNTL3/DMODE/DCNTL/CTEST3/4/5 = "
3005 "(hex) %02x/%02x/%02x/%02x/%02x/%02x\n",
3006 sym_name(np), np->rv_scntl3, np->rv_dmode, np->rv_dcntl,
3007 np->rv_ctest3, np->rv_ctest4, np->rv_ctest5);
3008 }
3009 /*
3010 * Let user be aware of targets that have some disable flags set.
3011 */
3012 sym_print_targets_flag(np, SYM_SCAN_BOOT_DISABLED, "SCAN AT BOOT");
3013 if (sym_verbose)
3014 sym_print_targets_flag(np, SYM_SCAN_LUNS_DISABLED,
3015 "SCAN FOR LUNS");
3016
3017 return 0;
3018}
3019
3020/*
3021 * Prepare the next negotiation message if needed.
3022 *
3023 * Fill in the part of message buffer that contains the
3024 * negotiation and the nego_status field of the CCB.
3025 * Returns the size of the message in bytes.
3026 */
3027
3028static int sym_prepare_nego(hcb_p np, ccb_p cp, int nego, u_char *msgptr)
3029{
3030 tcb_p tp = &np->target[cp->target];
3031 int msglen = 0;
3032
3033 /*
3034 * Early C1010 chips need a work-around for DT
3035 * data transfer to work.
3036 */
3037 if (!(np->features & FE_U3EN))
3038 tp->tinfo.goal.options = 0;
3039 /*
3040 * negotiate using PPR ?
3041 */
3042 if (tp->tinfo.goal.options & PPR_OPT_MASK)
3043 nego = NS_PPR;
3044 /*
3045 * negotiate wide transfers ?
3046 */
3047 else if (tp->tinfo.current.width != tp->tinfo.goal.width)
3048 nego = NS_WIDE;
3049 /*
3050 * negotiate synchronous transfers?
3051 */
3052 else if (tp->tinfo.current.period != tp->tinfo.goal.period ||
3053 tp->tinfo.current.offset != tp->tinfo.goal.offset)
3054 nego = NS_SYNC;
3055
3056 switch (nego) {
3057 case NS_SYNC:
3058 msgptr[msglen++] = M_EXTENDED;
3059 msgptr[msglen++] = 3;
3060 msgptr[msglen++] = M_X_SYNC_REQ;
3061 msgptr[msglen++] = tp->tinfo.goal.period;
3062 msgptr[msglen++] = tp->tinfo.goal.offset;
3063 break;
3064 case NS_WIDE:
3065 msgptr[msglen++] = M_EXTENDED;
3066 msgptr[msglen++] = 2;
3067 msgptr[msglen++] = M_X_WIDE_REQ;
3068 msgptr[msglen++] = tp->tinfo.goal.width;
3069 break;
3070 case NS_PPR:
3071 msgptr[msglen++] = M_EXTENDED;
3072 msgptr[msglen++] = 6;
3073 msgptr[msglen++] = M_X_PPR_REQ;
3074 msgptr[msglen++] = tp->tinfo.goal.period;
3075 msgptr[msglen++] = 0;
3076 msgptr[msglen++] = tp->tinfo.goal.offset;
3077 msgptr[msglen++] = tp->tinfo.goal.width;
3078 msgptr[msglen++] = tp->tinfo.goal.options & PPR_OPT_DT;
3079 break;
3080 };
3081
3082 cp->nego_status = nego;
3083
3084 if (nego) {
3085 tp->nego_cp = cp; /* Keep track a nego will be performed */
3086 if (DEBUG_FLAGS & DEBUG_NEGO) {
3087 sym_print_msg(cp, nego == NS_SYNC ? "sync msgout" :
3088 nego == NS_WIDE ? "wide msgout" :
3089 "ppr msgout", msgptr);
3090 };
3091 };
3092
3093 return msglen;
3094}
3095
3096/*
3097 * Insert a job into the start queue.
3098 */
3099static void sym_put_start_queue(hcb_p np, ccb_p cp)
3100{
3101 u_short qidx;
3102
3103#ifdef SYM_CONF_IARB_SUPPORT
3104 /*
3105 * If the previously queued CCB is not yet done,
3106 * set the IARB hint. The SCRIPTS will go with IARB
3107 * for this job when starting the previous one.
3108 * We leave devices a chance to win arbitration by
3109 * not using more than 'iarb_max' consecutive
3110 * immediate arbitrations.
3111 */
3112 if (np->last_cp && np->iarb_count < np->iarb_max) {
3113 np->last_cp->host_flags |= HF_HINT_IARB;
3114 ++np->iarb_count;
3115 }
3116 else
3117 np->iarb_count = 0;
3118 np->last_cp = cp;
3119#endif
3120
3121 /*
3122 * Insert first the idle task and then our job.
3123 * The MB should ensure proper ordering.
3124 */
3125 qidx = np->squeueput + 2;
3126 if (qidx >= MAX_QUEUE*2) qidx = 0;
3127
3128 np->squeue [qidx] = cpu_to_scr(np->idletask_ba);
3129 MEMORY_BARRIER();
3130 np->squeue [np->squeueput] = cpu_to_scr(cp->ccb_ba);
3131
3132 np->squeueput = qidx;
3133
3134 if (DEBUG_FLAGS & DEBUG_QUEUE)
3135 printf ("%s: queuepos=%d.\n", sym_name (np), np->squeueput);
3136
3137 /*
3138 * Script processor may be waiting for reselect.
3139 * Wake it up.
3140 */
3141 MEMORY_BARRIER();
3142 OUTB (nc_istat, SIGP|np->istat_sem);
3143}
3144
3145
3146/*
3147 * Soft reset the chip.
3148 *
3149 * Raising SRST when the chip is running may cause
3150 * problems on dual function chips (see below).
3151 * On the other hand, LVD devices need some delay
3152 * to settle and report actual BUS mode in STEST4.
3153 */
3154static void sym_chip_reset (hcb_p np)
3155{
3156 OUTB (nc_istat, SRST);
3157 UDELAY (10);
3158 OUTB (nc_istat, 0);
3159 UDELAY(2000); /* For BUS MODE to settle */
3160}
3161
3162/*
3163 * Soft reset the chip.
3164 *
3165 * Some 896 and 876 chip revisions may hang-up if we set
3166 * the SRST (soft reset) bit at the wrong time when SCRIPTS
3167 * are running.
3168 * So, we need to abort the current operation prior to
3169 * soft resetting the chip.
3170 */
3171static void sym_soft_reset (hcb_p np)
3172{
3173 u_char istat;
3174 int i;
3175
3176 OUTB (nc_istat, CABRT);
3177 for (i = 1000000 ; i ; --i) {
3178 istat = INB (nc_istat);
3179 if (istat & SIP) {
3180 INW (nc_sist);
3181 continue;
3182 }
3183 if (istat & DIP) {
3184 OUTB (nc_istat, 0);
3185 INB (nc_dstat);
3186 break;
3187 }
3188 }
3189 if (!i)
3190 printf("%s: unable to abort current chip operation.\n",
3191 sym_name(np));
3192 sym_chip_reset (np);
3193}
3194
3195/*
3196 * Start reset process.
3197 *
3198 * The interrupt handler will reinitialize the chip.
3199 */
3200static void sym_start_reset(hcb_p np)
3201{
3202 (void) sym_reset_scsi_bus(np, 1);
3203}
3204
3205static int sym_reset_scsi_bus(hcb_p np, int enab_int)
3206{
3207 u32 term;
3208 int retv = 0;
3209
3210 sym_soft_reset(np); /* Soft reset the chip */
3211 if (enab_int)
3212 OUTW (nc_sien, RST);
3213 /*
3214 * Enable Tolerant, reset IRQD if present and
3215 * properly set IRQ mode, prior to resetting the bus.
3216 */
3217 OUTB (nc_stest3, TE);
3218 OUTB (nc_dcntl, (np->rv_dcntl & IRQM));
3219 OUTB (nc_scntl1, CRST);
3220 UDELAY (200);
3221
3222 if (!SYM_SETUP_SCSI_BUS_CHECK)
3223 goto out;
3224 /*
3225 * Check for no terminators or SCSI bus shorts to ground.
3226 * Read SCSI data bus, data parity bits and control signals.
3227 * We are expecting RESET to be TRUE and other signals to be
3228 * FALSE.
3229 */
3230 term = INB(nc_sstat0);
3231 term = ((term & 2) << 7) + ((term & 1) << 17); /* rst sdp0 */
3232 term |= ((INB(nc_sstat2) & 0x01) << 26) | /* sdp1 */
3233 ((INW(nc_sbdl) & 0xff) << 9) | /* d7-0 */
3234 ((INW(nc_sbdl) & 0xff00) << 10) | /* d15-8 */
3235 INB(nc_sbcl); /* req ack bsy sel atn msg cd io */
3236
3237 if (!(np->features & FE_WIDE))
3238 term &= 0x3ffff;
3239
3240 if (term != (2<<7)) {
3241 printf("%s: suspicious SCSI data while resetting the BUS.\n",
3242 sym_name(np));
3243 printf("%s: %sdp0,d7-0,rst,req,ack,bsy,sel,atn,msg,c/d,i/o = "
3244 "0x%lx, expecting 0x%lx\n",
3245 sym_name(np),
3246 (np->features & FE_WIDE) ? "dp1,d15-8," : "",
3247 (u_long)term, (u_long)(2<<7));
3248 if (SYM_SETUP_SCSI_BUS_CHECK == 1)
3249 retv = 1;
3250 }
3251out:
3252 OUTB (nc_scntl1, 0);
3253 /* MDELAY(100); */
3254 return retv;
3255}
3256
3257/*
3258 * The chip may have completed jobs. Look at the DONE QUEUE.
3259 *
3260 * On architectures that may reorder LOAD/STORE operations,
3261 * a memory barrier may be needed after the reading of the
3262 * so-called `flag' and prior to dealing with the data.
3263 */
3264static int sym_wakeup_done (hcb_p np)
3265{
3266 ccb_p cp;
3267 int i, n;
3268 u32 dsa;
3269
3270 n = 0;
3271 i = np->dqueueget;
3272 while (1) {
3273 dsa = scr_to_cpu(np->dqueue[i]);
3274 if (!dsa)
3275 break;
3276 np->dqueue[i] = 0;
3277 if ((i = i+2) >= MAX_QUEUE*2)
3278 i = 0;
3279
3280 cp = sym_ccb_from_dsa(np, dsa);
3281 if (cp) {
3282 MEMORY_BARRIER();
3283 sym_complete_ok (np, cp);
3284 ++n;
3285 }
3286 else
3287 printf ("%s: bad DSA (%x) in done queue.\n",
3288 sym_name(np), (u_int) dsa);
3289 }
3290 np->dqueueget = i;
3291
3292 return n;
3293}
3294
3295/*
3296 * Complete all active CCBs with error.
3297 * Used on CHIP/SCSI RESET.
3298 */
3299static void sym_flush_busy_queue (hcb_p np, int cam_status)
3300{
3301 /*
3302 * Move all active CCBs to the COMP queue
3303 * and flush this queue.
3304 */
3305 sym_que_splice(&np->busy_ccbq, &np->comp_ccbq);
3306 sym_que_init(&np->busy_ccbq);
3307 sym_flush_comp_queue(np, cam_status);
3308}
3309
3310/*
3311 * Start chip.
3312 *
3313 * 'reason' means:
3314 * 0: initialisation.
3315 * 1: SCSI BUS RESET delivered or received.
3316 * 2: SCSI BUS MODE changed.
3317 */
3318static void sym_init (hcb_p np, int reason)
3319{
3320 int i;
3321 u32 phys;
3322
3323 /*
3324 * Reset chip if asked, otherwise just clear fifos.
3325 */
3326 if (reason == 1)
3327 sym_soft_reset(np);
3328 else {
3329 OUTB (nc_stest3, TE|CSF);
3330 OUTONB (nc_ctest3, CLF);
3331 }
3332
3333 /*
3334 * Clear Start Queue
3335 */
3336 phys = np->squeue_ba;
3337 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3338 np->squeue[i] = cpu_to_scr(np->idletask_ba);
3339 np->squeue[i+1] = cpu_to_scr(phys + (i+2)*4);
3340 }
3341 np->squeue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3342
3343 /*
3344 * Start at first entry.
3345 */
3346 np->squeueput = 0;
3347
3348 /*
3349 * Clear Done Queue
3350 */
3351 phys = np->dqueue_ba;
3352 for (i = 0; i < MAX_QUEUE*2; i += 2) {
3353 np->dqueue[i] = 0;
3354 np->dqueue[i+1] = cpu_to_scr(phys + (i+2)*4);
3355 }
3356 np->dqueue[MAX_QUEUE*2-1] = cpu_to_scr(phys);
3357
3358 /*
3359 * Start at first entry.
3360 */
3361 np->dqueueget = 0;
3362
3363 /*
3364 * Install patches in scripts.
3365 * This also let point to first position the start
3366 * and done queue pointers used from SCRIPTS.
3367 */
3368 np->fw_patch(np);
3369
3370 /*
3371 * Wakeup all pending jobs.
3372 */
3373 sym_flush_busy_queue(np, CAM_SCSI_BUS_RESET);
3374
3375 /*
3376 * Init chip.
3377 */
3378 OUTB (nc_istat, 0x00 ); /* Remove Reset, abort */
3379 UDELAY (2000); /* The 895 needs time for the bus mode to settle */
3380
3381 OUTB (nc_scntl0, np->rv_scntl0 | 0xc0);
3382 /* full arb., ena parity, par->ATN */
3383 OUTB (nc_scntl1, 0x00); /* odd parity, and remove CRST!! */
3384
3385 sym_selectclock(np, np->rv_scntl3); /* Select SCSI clock */
3386
3387 OUTB (nc_scid , RRE|np->myaddr); /* Adapter SCSI address */
3388 OUTW (nc_respid, 1ul<<np->myaddr); /* Id to respond to */
3389 OUTB (nc_istat , SIGP ); /* Signal Process */
3390 OUTB (nc_dmode , np->rv_dmode); /* Burst length, dma mode */
3391 OUTB (nc_ctest5, np->rv_ctest5); /* Large fifo + large burst */
3392
3393 OUTB (nc_dcntl , NOCOM|np->rv_dcntl); /* Protect SFBR */
3394 OUTB (nc_ctest3, np->rv_ctest3); /* Write and invalidate */
3395 OUTB (nc_ctest4, np->rv_ctest4); /* Master parity checking */
3396
3397 /* Extended Sreq/Sack filtering not supported on the C10 */
3398 if (np->features & FE_C10)
3399 OUTB (nc_stest2, np->rv_stest2);
3400 else
3401 OUTB (nc_stest2, EXT|np->rv_stest2);
3402
3403 OUTB (nc_stest3, TE); /* TolerANT enable */
3404 OUTB (nc_stime0, 0x0c); /* HTH disabled STO 0.25 sec */
3405
3406 /*
3407 * For now, disable AIP generation on C1010-66.
3408 */
3409 if (np->device_id == PCI_ID_LSI53C1010_2)
3410 OUTB (nc_aipcntl1, DISAIP);
3411
3412 /*
3413 * C10101 Errata.
3414 * Errant SGE's when in narrow. Write bits 4 & 5 of
3415 * STEST1 register to disable SGE. We probably should do
3416 * that from SCRIPTS for each selection/reselection, but
3417 * I just don't want. :)
3418 */
3419 if (np->device_id == PCI_ID_LSI53C1010 &&
3420 /* np->revision_id < 0xff */ 1)
3421 OUTB (nc_stest1, INB(nc_stest1) | 0x30);
3422
3423 /*
3424 * DEL 441 - 53C876 Rev 5 - Part Number 609-0392787/2788 - ITEM 2.
3425 * Disable overlapped arbitration for some dual function devices,
3426 * regardless revision id (kind of post-chip-design feature. ;-))
3427 */
3428 if (np->device_id == PCI_ID_SYM53C875)
3429 OUTB (nc_ctest0, (1<<5));
3430 else if (np->device_id == PCI_ID_SYM53C896)
3431 np->rv_ccntl0 |= DPR;
3432
3433 /*
3434 * Write CCNTL0/CCNTL1 for chips capable of 64 bit addressing
3435 * and/or hardware phase mismatch, since only such chips
3436 * seem to support those IO registers.
3437 */
3438 if (np->features & (FE_DAC|FE_NOPM)) {
3439 OUTB (nc_ccntl0, np->rv_ccntl0);
3440 OUTB (nc_ccntl1, np->rv_ccntl1);
3441 }
3442
3443 /*
3444 * If phase mismatch handled by scripts (895A/896/1010),
3445 * set PM jump addresses.
3446 */
3447 if (np->features & FE_NOPM) {
3448 OUTL (nc_pmjad1, SCRIPTB_BA (np, pm_handle));
3449 OUTL (nc_pmjad2, SCRIPTB_BA (np, pm_handle));
3450 }
3451
3452 /*
3453 * Enable GPIO0 pin for writing if LED support from SCRIPTS.
3454 * Also set GPIO5 and clear GPIO6 if hardware LED control.
3455 */
3456 if (np->features & FE_LED0)
3457 OUTB(nc_gpcntl, INB(nc_gpcntl) & ~0x01);
3458 else if (np->features & FE_LEDC)
3459 OUTB(nc_gpcntl, (INB(nc_gpcntl) & ~0x41) | 0x20);
3460
3461 /*
3462 * enable ints
3463 */
3464 OUTW (nc_sien , STO|HTH|MA|SGE|UDC|RST|PAR);
3465 OUTB (nc_dien , MDPE|BF|SSI|SIR|IID);
3466
3467 /*
3468 * For 895/6 enable SBMC interrupt and save current SCSI bus mode.
3469 * Try to eat the spurious SBMC interrupt that may occur when
3470 * we reset the chip but not the SCSI BUS (at initialization).
3471 */
3472 if (np->features & (FE_ULTRA2|FE_ULTRA3)) {
3473 OUTONW (nc_sien, SBMC);
3474 if (reason == 0) {
3475 MDELAY(100);
3476 INW (nc_sist);
3477 }
3478 np->scsi_mode = INB (nc_stest4) & SMODE;
3479 }
3480
3481 /*
3482 * Fill in target structure.
3483 * Reinitialize usrsync.
3484 * Reinitialize usrwide.
3485 * Prepare sync negotiation according to actual SCSI bus mode.
3486 */
3487 for (i=0;i<SYM_CONF_MAX_TARGET;i++) {
3488 tcb_p tp = &np->target[i];
3489
3490 tp->to_reset = 0;
3491 tp->head.sval = 0;
3492 tp->head.wval = np->rv_scntl3;
3493 tp->head.uval = 0;
3494
3495 tp->tinfo.current.period = 0;
3496 tp->tinfo.current.offset = 0;
3497 tp->tinfo.current.width = BUS_8_BIT;
3498 tp->tinfo.current.options = 0;
3499 }
3500
3501 /*
3502 * Download SCSI SCRIPTS to on-chip RAM if present,
3503 * and start script processor.
3504 */
3505 if (np->ram_ba) {
3506 if (sym_verbose > 1)
3507 printf ("%s: Downloading SCSI SCRIPTS.\n",
3508 sym_name(np));
3509 if (np->ram_ws == 8192) {
3510 OUTRAM_OFF(4096, np->scriptb0, np->scriptb_sz);
3511 OUTL (nc_mmws, np->scr_ram_seg);
3512 OUTL (nc_mmrs, np->scr_ram_seg);
3513 OUTL (nc_sfs, np->scr_ram_seg);
3514 phys = SCRIPTB_BA (np, start64);
3515 }
3516 else
3517 phys = SCRIPTA_BA (np, init);
3518 OUTRAM_OFF(0, np->scripta0, np->scripta_sz);
3519 }
3520 else
3521 phys = SCRIPTA_BA (np, init);
3522
3523 np->istat_sem = 0;
3524
3525 OUTL (nc_dsa, np->hcb_ba);
3526 OUTL_DSP (phys);
3527
3528 /*
3529 * Notify the XPT about the RESET condition.
3530 */
3531 if (reason != 0)
3532 xpt_async(AC_BUS_RESET, np->path, NULL);
3533}
3534
3535/*
3536 * Get clock factor and sync divisor for a given
3537 * synchronous factor period.
3538 */
3539static int
3540sym_getsync(hcb_p np, u_char dt, u_char sfac, u_char *divp, u_char *fakp)
3541{
3542 u32 clk = np->clock_khz; /* SCSI clock frequency in kHz */
3543 int div = np->clock_divn; /* Number of divisors supported */
3544 u32 fak; /* Sync factor in sxfer */
3545 u32 per; /* Period in tenths of ns */
3546 u32 kpc; /* (per * clk) */
3547 int ret;
3548
3549 /*
3550 * Compute the synchronous period in tenths of nano-seconds
3551 */
3552 if (dt && sfac <= 9) per = 125;
3553 else if (sfac <= 10) per = 250;
3554 else if (sfac == 11) per = 303;
3555 else if (sfac == 12) per = 500;
3556 else per = 40 * sfac;
3557 ret = per;
3558
3559 kpc = per * clk;
3560 if (dt)
3561 kpc <<= 1;
3562
3563 /*
3564 * For earliest C10 revision 0, we cannot use extra
3565 * clocks for the setting of the SCSI clocking.
3566 * Note that this limits the lowest sync data transfer
3567 * to 5 Mega-transfers per second and may result in
3568 * using higher clock divisors.
3569 */
3570#if 1
3571 if ((np->features & (FE_C10|FE_U3EN)) == FE_C10) {
3572 /*
3573 * Look for the lowest clock divisor that allows an
3574 * output speed not faster than the period.
3575 */
3576 while (div > 0) {
3577 --div;
3578 if (kpc > (div_10M[div] << 2)) {
3579 ++div;
3580 break;
3581 }
3582 }
3583 fak = 0; /* No extra clocks */
3584 if (div == np->clock_divn) { /* Are we too fast ? */
3585 ret = -1;
3586 }
3587 *divp = div;
3588 *fakp = fak;
3589 return ret;
3590 }
3591#endif
3592
3593 /*
3594 * Look for the greatest clock divisor that allows an
3595 * input speed faster than the period.
3596 */
3597 while (div-- > 0)
3598 if (kpc >= (div_10M[div] << 2)) break;
3599
3600 /*
3601 * Calculate the lowest clock factor that allows an output
3602 * speed not faster than the period, and the max output speed.
3603 * If fak >= 1 we will set both XCLKH_ST and XCLKH_DT.
3604 * If fak >= 2 we will also set XCLKS_ST and XCLKS_DT.
3605 */
3606 if (dt) {
3607 fak = (kpc - 1) / (div_10M[div] << 1) + 1 - 2;
3608 /* ret = ((2+fak)*div_10M[div])/np->clock_khz; */
3609 }
3610 else {
3611 fak = (kpc - 1) / div_10M[div] + 1 - 4;
3612 /* ret = ((4+fak)*div_10M[div])/np->clock_khz; */
3613 }
3614
3615 /*
3616 * Check against our hardware limits, or bugs :).
3617 */
3618 if (fak < 0) {fak = 0; ret = -1;}
3619 if (fak > 2) {fak = 2; ret = -1;}
3620
3621 /*
3622 * Compute and return sync parameters.
3623 */
3624 *divp = div;
3625 *fakp = fak;
3626
3627 return ret;
3628}
3629
3630/*
3631 * Tell the SCSI layer about the new transfer parameters.
3632 */
3633static void
3634sym_xpt_async_transfer_neg(hcb_p np, int target, u_int spi_valid)
3635{
3636 struct ccb_trans_settings cts;
3637 struct cam_path *path;
3638 int sts;
3639 tcb_p tp = &np->target[target];
3640
3641 sts = xpt_create_path(&path, NULL, cam_sim_path(np->sim), target,
3642 CAM_LUN_WILDCARD);
3643 if (sts != CAM_REQ_CMP)
3644 return;
3645
3646 bzero(&cts, sizeof(cts));
3647
3648#ifdef FreeBSD_New_Tran_Settings
3649#define cts__scsi (cts.proto_specific.scsi)
3650#define cts__spi (cts.xport_specific.spi)
3651
3652 cts.type = CTS_TYPE_CURRENT_SETTINGS;
3653 cts.protocol = PROTO_SCSI;
3654 cts.transport = XPORT_SPI;
3655 cts.protocol_version = tp->tinfo.current.scsi_version;
3656 cts.transport_version = tp->tinfo.current.spi_version;
3657
3658 cts__spi.valid = spi_valid;
3659 if (spi_valid & CTS_SPI_VALID_SYNC_RATE)
3660 cts__spi.sync_period = tp->tinfo.current.period;
3661 if (spi_valid & CTS_SPI_VALID_SYNC_OFFSET)
3662 cts__spi.sync_offset = tp->tinfo.current.offset;
3663 if (spi_valid & CTS_SPI_VALID_BUS_WIDTH)
3664 cts__spi.bus_width = tp->tinfo.current.width;
3665 if (spi_valid & CTS_SPI_VALID_PPR_OPTIONS)
3666 cts__spi.ppr_options = tp->tinfo.current.options;
3667#undef cts__spi
3668#undef cts__scsi
3669#else
3670 cts.valid = spi_valid;
3671 if (spi_valid & CCB_TRANS_SYNC_RATE_VALID)
3672 cts.sync_period = tp->tinfo.current.period;
3673 if (spi_valid & CCB_TRANS_SYNC_OFFSET_VALID)
3674 cts.sync_offset = tp->tinfo.current.offset;
3675 if (spi_valid & CCB_TRANS_BUS_WIDTH_VALID)
3676 cts.bus_width = tp->tinfo.current.width;
3677#endif
3678 xpt_setup_ccb(&cts.ccb_h, path, /*priority*/1);
3679 xpt_async(AC_TRANSFER_NEG, path, &cts);
3680 xpt_free_path(path);
3681}
3682
3683#ifdef FreeBSD_New_Tran_Settings
3684#define SYM_SPI_VALID_WDTR \
3685 CTS_SPI_VALID_BUS_WIDTH | \
3686 CTS_SPI_VALID_SYNC_RATE | \
3687 CTS_SPI_VALID_SYNC_OFFSET
3688#define SYM_SPI_VALID_SDTR \
3689 CTS_SPI_VALID_SYNC_RATE | \
3690 CTS_SPI_VALID_SYNC_OFFSET
3691#define SYM_SPI_VALID_PPR \
3692 CTS_SPI_VALID_PPR_OPTIONS | \
3693 CTS_SPI_VALID_BUS_WIDTH | \
3694 CTS_SPI_VALID_SYNC_RATE | \
3695 CTS_SPI_VALID_SYNC_OFFSET
3696#else
3697#define SYM_SPI_VALID_WDTR \
3698 CCB_TRANS_BUS_WIDTH_VALID | \
3699 CCB_TRANS_SYNC_RATE_VALID | \
3700 CCB_TRANS_SYNC_OFFSET_VALID
3701#define SYM_SPI_VALID_SDTR \
3702 CCB_TRANS_SYNC_RATE_VALID | \
3703 CCB_TRANS_SYNC_OFFSET_VALID
3704#define SYM_SPI_VALID_PPR \
3705 CCB_TRANS_BUS_WIDTH_VALID | \
3706 CCB_TRANS_SYNC_RATE_VALID | \
3707 CCB_TRANS_SYNC_OFFSET_VALID
3708#endif
3709
3710/*
3711 * We received a WDTR.
3712 * Let everything be aware of the changes.
3713 */
3714static void sym_setwide(hcb_p np, ccb_p cp, u_char wide)
3715{
3716 tcb_p tp = &np->target[cp->target];
3717
3718 sym_settrans(np, cp, 0, 0, 0, wide, 0, 0);
3719
3720 /*
3721 * Tell the SCSI layer about the new transfer parameters.
3722 */
3723 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3724 tp->tinfo.current.offset = 0;
3725 tp->tinfo.current.period = 0;
3726 tp->tinfo.current.options = 0;
3727
3728 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_WDTR);
3729}
3730
3731/*
3732 * We received a SDTR.
3733 * Let everything be aware of the changes.
3734 */
3735static void
3736sym_setsync(hcb_p np, ccb_p cp, u_char ofs, u_char per, u_char div, u_char fak)
3737{
3738 tcb_p tp = &np->target[cp->target];
3739 u_char wide = (cp->phys.select.sel_scntl3 & EWS) ? 1 : 0;
3740
3741 sym_settrans(np, cp, 0, ofs, per, wide, div, fak);
3742
3743 /*
3744 * Tell the SCSI layer about the new transfer parameters.
3745 */
3746 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3747 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3748 tp->tinfo.goal.options = tp->tinfo.current.options = 0;
3749
3750 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_SDTR);
3751}
3752
3753/*
3754 * We received a PPR.
3755 * Let everything be aware of the changes.
3756 */
3757static void sym_setpprot(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3758 u_char per, u_char wide, u_char div, u_char fak)
3759{
3760 tcb_p tp = &np->target[cp->target];
3761
3762 sym_settrans(np, cp, dt, ofs, per, wide, div, fak);
3763
3764 /*
3765 * Tell the SCSI layer about the new transfer parameters.
3766 */
3767 tp->tinfo.goal.width = tp->tinfo.current.width = wide;
3768 tp->tinfo.goal.period = tp->tinfo.current.period = per;
3769 tp->tinfo.goal.offset = tp->tinfo.current.offset = ofs;
3770 tp->tinfo.goal.options = tp->tinfo.current.options = dt;
3771
3772 sym_xpt_async_transfer_neg(np, cp->target, SYM_SPI_VALID_PPR);
3773}
3774
3775/*
3776 * Switch trans mode for current job and it's target.
3777 */
3778static void sym_settrans(hcb_p np, ccb_p cp, u_char dt, u_char ofs,
3779 u_char per, u_char wide, u_char div, u_char fak)
3780{
3781 SYM_QUEHEAD *qp;
3782 union ccb *ccb;
3783 tcb_p tp;
3784 u_char target = INB (nc_sdid) & 0x0f;
3785 u_char sval, wval, uval;
3786
3787 assert (cp);
3788 if (!cp) return;
3789 ccb = cp->cam_ccb;
3790 assert (ccb);
3791 if (!ccb) return;
3792 assert (target == (cp->target & 0xf));
3793 tp = &np->target[target];
3794
3795 sval = tp->head.sval;
3796 wval = tp->head.wval;
3797 uval = tp->head.uval;
3798
3799#if 0
3800 printf("XXXX sval=%x wval=%x uval=%x (%x)\n",
3801 sval, wval, uval, np->rv_scntl3);
3802#endif
3803 /*
3804 * Set the offset.
3805 */
3806 if (!(np->features & FE_C10))
3807 sval = (sval & ~0x1f) | ofs;
3808 else
3809 sval = (sval & ~0x3f) | ofs;
3810
3811 /*
3812 * Set the sync divisor and extra clock factor.
3813 */
3814 if (ofs != 0) {
3815 wval = (wval & ~0x70) | ((div+1) << 4);
3816 if (!(np->features & FE_C10))
3817 sval = (sval & ~0xe0) | (fak << 5);
3818 else {
3819 uval = uval & ~(XCLKH_ST|XCLKH_DT|XCLKS_ST|XCLKS_DT);
3820 if (fak >= 1) uval |= (XCLKH_ST|XCLKH_DT);
3821 if (fak >= 2) uval |= (XCLKS_ST|XCLKS_DT);
3822 }
3823 }
3824
3825 /*
3826 * Set the bus width.
3827 */
3828 wval = wval & ~EWS;
3829 if (wide != 0)
3830 wval |= EWS;
3831
3832 /*
3833 * Set misc. ultra enable bits.
3834 */
3835 if (np->features & FE_C10) {
3836 uval = uval & ~(U3EN|AIPCKEN);
3837 if (dt) {
3838 assert(np->features & FE_U3EN);
3839 uval |= U3EN;
3840 }
3841 }
3842 else {
3843 wval = wval & ~ULTRA;
3844 if (per <= 12) wval |= ULTRA;
3845 }
3846
3847 /*
3848 * Stop there if sync parameters are unchanged.
3849 */
3850 if (tp->head.sval == sval &&
3851 tp->head.wval == wval &&
3852 tp->head.uval == uval)
3853 return;
3854 tp->head.sval = sval;
3855 tp->head.wval = wval;
3856 tp->head.uval = uval;
3857
3858 /*
3859 * Disable extended Sreq/Sack filtering if per < 50.
3860 * Not supported on the C1010.
3861 */
3862 if (per < 50 && !(np->features & FE_C10))
3863 OUTOFFB (nc_stest2, EXT);
3864
3865 /*
3866 * set actual value and sync_status
3867 */
3868 OUTB (nc_sxfer, tp->head.sval);
3869 OUTB (nc_scntl3, tp->head.wval);
3870
3871 if (np->features & FE_C10) {
3872 OUTB (nc_scntl4, tp->head.uval);
3873 }
3874
3875 /*
3876 * patch ALL busy ccbs of this target.
3877 */
3878 FOR_EACH_QUEUED_ELEMENT(&np->busy_ccbq, qp) {
3879 cp = sym_que_entry(qp, struct sym_ccb, link_ccbq);
3880 if (cp->target != target)
3881 continue;
3882 cp->phys.select.sel_scntl3 = tp->head.wval;
3883 cp->phys.select.sel_sxfer = tp->head.sval;
3884 if (np->features & FE_C10) {
3885 cp->phys.select.sel_scntl4 = tp->head.uval;
3886 }
3887 }
3888}
3889
3890/*
3891 * log message for real hard errors
3892 *
3893 * sym0 targ 0?: ERROR (ds:si) (so-si-sd) (sxfer/scntl3) @ name (dsp:dbc).
3894 * reg: r0 r1 r2 r3 r4 r5 r6 ..... rf.
3895 *
3896 * exception register:
3897 * ds: dstat
3898 * si: sist
3899 *
3900 * SCSI bus lines:
3901 * so: control lines as driven by chip.
3902 * si: control lines as seen by chip.
3903 * sd: scsi data lines as seen by chip.
3904 *
3905 * wide/fastmode:
3906 * sxfer: (see the manual)
3907 * scntl3: (see the manual)
3908 *
3909 * current script command:
3910 * dsp: script adress (relative to start of script).
3911 * dbc: first word of script command.
3912 *
3913 * First 24 register of the chip:
3914 * r0..rf
3915 */
3916static void sym_log_hard_error(hcb_p np, u_short sist, u_char dstat)
3917{
3918 u32 dsp;
3919 int script_ofs;
3920 int script_size;
3921 char *script_name;
3922 u_char *script_base;
3923 int i;
3924
3925 dsp = INL (nc_dsp);
3926
3927 if (dsp > np->scripta_ba &&
3928 dsp <= np->scripta_ba + np->scripta_sz) {
3929 script_ofs = dsp - np->scripta_ba;
3930 script_size = np->scripta_sz;
3931 script_base = (u_char *) np->scripta0;
3932 script_name = "scripta";
3933 }
3934 else if (np->scriptb_ba < dsp &&
3935 dsp <= np->scriptb_ba + np->scriptb_sz) {
3936 script_ofs = dsp - np->scriptb_ba;
3937 script_size = np->scriptb_sz;
3938 script_base = (u_char *) np->scriptb0;
3939 script_name = "scriptb";
3940 } else {
3941 script_ofs = dsp;
3942 script_size = 0;
3943 script_base = 0;
3944 script_name = "mem";
3945 }
3946
3947 printf ("%s:%d: ERROR (%x:%x) (%x-%x-%x) (%x/%x) @ (%s %x:%08x).\n",
3948 sym_name (np), (unsigned)INB (nc_sdid)&0x0f, dstat, sist,
3949 (unsigned)INB (nc_socl), (unsigned)INB (nc_sbcl),
3950 (unsigned)INB (nc_sbdl), (unsigned)INB (nc_sxfer),
3951 (unsigned)INB (nc_scntl3), script_name, script_ofs,
3952 (unsigned)INL (nc_dbc));
3953
3954 if (((script_ofs & 3) == 0) &&
3955 (unsigned)script_ofs < script_size) {
3956 printf ("%s: script cmd = %08x\n", sym_name(np),
3957 scr_to_cpu((int) *(u32 *)(script_base + script_ofs)));
3958 }
3959
3960 printf ("%s: regdump:", sym_name(np));
3961 for (i=0; i<24;i++)
3962 printf (" %02x", (unsigned)INB_OFF(i));
3963 printf (".\n");
3964
3965 /*
3966 * PCI BUS error, read the PCI ststus register.
3967 */
3968 if (dstat & (MDPE|BF)) {
3969 u_short pci_sts;
3970#ifdef FreeBSD_Bus_Io_Abstraction
3971 pci_sts = pci_read_config(np->device, PCIR_STATUS, 2);
3972#else
3973 pci_sts = pci_cfgread(np->pci_tag, PCIR_STATUS, 2);
3974#endif
3975 if (pci_sts & 0xf900) {
3976#ifdef FreeBSD_Bus_Io_Abstraction
3977 pci_write_config(np->device, PCIR_STATUS, pci_sts, 2);
3978#else
3979 pci_cfgwrite(np->pci_tag, PCIR_STATUS, pci_sts, 2);
3980#endif
3981 printf("%s: PCI STATUS = 0x%04x\n",
3982 sym_name(np), pci_sts & 0xf900);
3983 }
3984 }
3985}
3986
3987/*
3988 * chip interrupt handler
3989 *
3990 * In normal situations, interrupt conditions occur one at
3991 * a time. But when something bad happens on the SCSI BUS,
3992 * the chip may raise several interrupt flags before
3993 * stopping and interrupting the CPU. The additionnal
3994 * interrupt flags are stacked in some extra registers
3995 * after the SIP and/or DIP flag has been raised in the
3996 * ISTAT. After the CPU has read the interrupt condition
3997 * flag from SIST or DSTAT, the chip unstacks the other
3998 * interrupt flags and sets the corresponding bits in
3999 * SIST or DSTAT. Since the chip starts stacking once the
4000 * SIP or DIP flag is set, there is a small window of time
4001 * where the stacking does not occur.
4002 *
4003 * Typically, multiple interrupt conditions may happen in
4004 * the following situations:
4005 *
4006 * - SCSI parity error + Phase mismatch (PAR|MA)
4007 * When an parity error is detected in input phase
4008 * and the device switches to msg-in phase inside a
4009 * block MOV.
4010 * - SCSI parity error + Unexpected disconnect (PAR|UDC)
4011 * When a stupid device does not want to handle the
4012 * recovery of an SCSI parity error.
4013 * - Some combinations of STO, PAR, UDC, ...
4014 * When using non compliant SCSI stuff, when user is
4015 * doing non compliant hot tampering on the BUS, when
4016 * something really bad happens to a device, etc ...
4017 *
4018 * The heuristic suggested by SYMBIOS to handle
4019 * multiple interrupts is to try unstacking all
4020 * interrupts conditions and to handle them on some
4021 * priority based on error severity.
4022 * This will work when the unstacking has been
4023 * successful, but we cannot be 100 % sure of that,
4024 * since the CPU may have been faster to unstack than
4025 * the chip is able to stack. Hmmm ... But it seems that