Remove all remaining SPL code. Replace the mtd_cpl field in the machine
[dragonfly.git] / sys / platform / pc32 / i386 / exception.s
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/i386/i386/exception.s,v 1.65.2.3 2001/08/15 01:23:49 peter Exp $
38787eef 34 * $DragonFly: src/sys/platform/pc32/i386/exception.s,v 1.24 2005/06/16 21:12:44 dillon Exp $
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35 */
36
1f2de5d4 37#include "use_npx.h"
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38
39#include <machine/asmacros.h>
40#include <machine/ipl.h>
41#include <machine/lock.h>
42#include <machine/psl.h>
43#include <machine/trap.h>
984263bc 44#include <machine/smptests.h> /** various SMP options */
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45
46#include "assym.s"
47
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48#define SEL_RPL_MASK 0x0003
49
50 .text
51
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52#ifdef DEBUG_INTERRUPTS
53 .globl Xrsvdary
54
55Xrsvdary:
56 .long Xrsvd0
57 .long Xrsvd1 , Xrsvd2 , Xrsvd3 , Xrsvd4 , Xrsvd5 , Xrsvd6 , Xrsvd7 , Xrsvd8
58 .long Xrsvd9 , Xrsvd10 , Xrsvd11 , Xrsvd12 , Xrsvd13 , Xrsvd14 , Xrsvd15 , Xrsvd16
59 .long Xrsvd17 , Xrsvd18 , Xrsvd19 , Xrsvd20 , Xrsvd21 , Xrsvd22 , Xrsvd23 , Xrsvd24
60 .long Xrsvd25 , Xrsvd26 , Xrsvd27 , Xrsvd28 , Xrsvd29 , Xrsvd30 , Xrsvd31 , Xrsvd32
61 .long Xrsvd33 , Xrsvd34 , Xrsvd35 , Xrsvd36 , Xrsvd37 , Xrsvd38 , Xrsvd39 , Xrsvd40
62 .long Xrsvd41 , Xrsvd42 , Xrsvd43 , Xrsvd44 , Xrsvd45 , Xrsvd46 , Xrsvd47 , Xrsvd48
63 .long Xrsvd49 , Xrsvd50 , Xrsvd51 , Xrsvd52 , Xrsvd53 , Xrsvd54 , Xrsvd55 , Xrsvd56
64 .long Xrsvd57 , Xrsvd58 , Xrsvd59 , Xrsvd60 , Xrsvd61 , Xrsvd62 , Xrsvd63 , Xrsvd64
65 .long Xrsvd65 , Xrsvd66 , Xrsvd67 , Xrsvd68 , Xrsvd69 , Xrsvd70 , Xrsvd71 , Xrsvd72
66 .long Xrsvd73 , Xrsvd74 , Xrsvd75 , Xrsvd76 , Xrsvd77 , Xrsvd78 , Xrsvd79 , Xrsvd80
67 .long Xrsvd81 , Xrsvd82 , Xrsvd83 , Xrsvd84 , Xrsvd85 , Xrsvd86 , Xrsvd87 , Xrsvd88
68 .long Xrsvd89 , Xrsvd90 , Xrsvd91 , Xrsvd92 , Xrsvd93 , Xrsvd94 , Xrsvd95 , Xrsvd96
69 .long Xrsvd97 , Xrsvd98 , Xrsvd99 , Xrsvd100, Xrsvd101, Xrsvd102, Xrsvd103, Xrsvd104
70 .long Xrsvd105, Xrsvd106, Xrsvd107, Xrsvd108, Xrsvd109, Xrsvd110, Xrsvd111, Xrsvd112
71 .long Xrsvd113, Xrsvd114, Xrsvd115, Xrsvd116, Xrsvd117, Xrsvd118, Xrsvd119, Xrsvd120
72 .long Xrsvd121, Xrsvd122, Xrsvd123, Xrsvd124, Xrsvd125, Xrsvd126, Xrsvd127, Xrsvd128
73 .long Xrsvd129, Xrsvd130, Xrsvd131, Xrsvd132, Xrsvd133, Xrsvd134, Xrsvd135, Xrsvd136
74 .long Xrsvd137, Xrsvd138, Xrsvd139, Xrsvd140, Xrsvd141, Xrsvd142, Xrsvd143, Xrsvd144
75 .long Xrsvd145, Xrsvd146, Xrsvd147, Xrsvd148, Xrsvd149, Xrsvd150, Xrsvd151, Xrsvd152
76 .long Xrsvd153, Xrsvd154, Xrsvd155, Xrsvd156, Xrsvd157, Xrsvd158, Xrsvd159, Xrsvd160
77 .long Xrsvd161, Xrsvd162, Xrsvd163, Xrsvd164, Xrsvd165, Xrsvd166, Xrsvd167, Xrsvd168
78 .long Xrsvd169, Xrsvd170, Xrsvd171, Xrsvd172, Xrsvd173, Xrsvd174, Xrsvd175, Xrsvd176
79 .long Xrsvd177, Xrsvd178, Xrsvd179, Xrsvd180, Xrsvd181, Xrsvd182, Xrsvd183, Xrsvd184
80 .long Xrsvd185, Xrsvd186, Xrsvd187, Xrsvd188, Xrsvd189, Xrsvd190, Xrsvd191, Xrsvd192
81 .long Xrsvd193, Xrsvd194, Xrsvd195, Xrsvd196, Xrsvd197, Xrsvd198, Xrsvd199, Xrsvd200
82 .long Xrsvd201, Xrsvd202, Xrsvd203, Xrsvd204, Xrsvd205, Xrsvd206, Xrsvd207, Xrsvd208
83 .long Xrsvd209, Xrsvd210, Xrsvd211, Xrsvd212, Xrsvd213, Xrsvd214, Xrsvd215, Xrsvd216
84 .long Xrsvd217, Xrsvd218, Xrsvd219, Xrsvd220, Xrsvd221, Xrsvd222, Xrsvd223, Xrsvd224
85 .long Xrsvd225, Xrsvd226, Xrsvd227, Xrsvd228, Xrsvd229, Xrsvd230, Xrsvd231, Xrsvd232
86 .long Xrsvd233, Xrsvd234, Xrsvd235, Xrsvd236, Xrsvd237, Xrsvd238, Xrsvd239, Xrsvd240
87 .long Xrsvd241, Xrsvd242, Xrsvd243, Xrsvd244, Xrsvd245, Xrsvd246, Xrsvd247, Xrsvd248
88 .long Xrsvd249, Xrsvd250, Xrsvd251, Xrsvd252, Xrsvd253, Xrsvd254, Xrsvd255
89
90#endif
91
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92/*****************************************************************************/
93/* Trap handling */
94/*****************************************************************************/
95/*
96 * Trap and fault vector routines.
97 *
98 * Most traps are 'trap gates', SDT_SYS386TGT. A trap gate pushes state on
99 * the stack that mostly looks like an interrupt, but does not disable
100 * interrupts. A few of the traps we are use are interrupt gates,
101 * SDT_SYS386IGT, which are nearly the same thing except interrupts are
102 * disabled on entry.
103 *
104 * The cpu will push a certain amount of state onto the kernel stack for
105 * the current process. The amount of state depends on the type of trap
106 * and whether the trap crossed rings or not. See i386/include/frame.h.
107 * At the very least the current EFLAGS (status register, which includes
108 * the interrupt disable state prior to the trap), the code segment register,
109 * and the return instruction pointer are pushed by the cpu. The cpu
110 * will also push an 'error' code for certain traps. We push a dummy
111 * error code for those traps where the cpu doesn't in order to maintain
112 * a consistent frame. We also push a contrived 'trap number'.
113 *
114 * The cpu does not push the general registers, we must do that, and we
115 * must restore them prior to calling 'iret'. The cpu adjusts the %cs and
116 * %ss segment registers, but does not mess with %ds, %es, or %fs. Thus we
117 * must load them with appropriate values for supervisor mode operation.
118 *
119 * On entry to a trap or interrupt WE DO NOT OWN THE MP LOCK. This means
120 * that we must be careful in regards to accessing global variables. We
121 * save (push) the current cpl (our software interrupt disable mask), call
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122 * the trap function, then jump to doreti to restore the cpl and deal with
123 * ASTs (software interrupts). doreti will determine if the restoration
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124 * of the cpl unmasked any pending interrupts and will issue those interrupts
125 * synchronously prior to doing the iret.
984263bc 126 */
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127#define IDTVEC(name) ALIGN_TEXT; .globl __CONCAT(X,name); \
128 .type __CONCAT(X,name),@function; __CONCAT(X,name):
129#define TRAP(a) pushl $(a) ; jmp alltraps
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130
131#ifdef BDE_DEBUGGER
132#define BDBTRAP(name) \
133 ss ; \
2954c92f 134 cmpb $0,bdb_exists ; \
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135 je 1f ; \
136 testb $SEL_RPL_MASK,4(%esp) ; \
137 jne 1f ; \
138 ss ; \
139 .globl __CONCAT(__CONCAT(bdb_,name),_ljmp); \
140__CONCAT(__CONCAT(bdb_,name),_ljmp): \
141 ljmp $0,$0 ; \
1421:
143#else
144#define BDBTRAP(name)
145#endif
146
147#define BPTTRAP(a) testl $PSL_I,4+8(%esp) ; je 1f ; sti ; 1: ; TRAP(a)
148
149MCOUNT_LABEL(user)
150MCOUNT_LABEL(btrap)
151
152IDTVEC(div)
153 pushl $0; TRAP(T_DIVIDE)
154IDTVEC(dbg)
155 BDBTRAP(dbg)
156 pushl $0; BPTTRAP(T_TRCTRAP)
157IDTVEC(nmi)
158 pushl $0; TRAP(T_NMI)
159IDTVEC(bpt)
160 BDBTRAP(bpt)
161 pushl $0; BPTTRAP(T_BPTFLT)
162IDTVEC(ofl)
163 pushl $0; TRAP(T_OFLOW)
164IDTVEC(bnd)
165 pushl $0; TRAP(T_BOUND)
166IDTVEC(ill)
167 pushl $0; TRAP(T_PRIVINFLT)
168IDTVEC(dna)
169 pushl $0; TRAP(T_DNA)
170IDTVEC(fpusegm)
171 pushl $0; TRAP(T_FPOPFLT)
172IDTVEC(tss)
173 TRAP(T_TSSFLT)
174IDTVEC(missing)
175 TRAP(T_SEGNPFLT)
176IDTVEC(stk)
177 TRAP(T_STKFLT)
178IDTVEC(prot)
179 TRAP(T_PROTFLT)
180IDTVEC(page)
181 TRAP(T_PAGEFLT)
182IDTVEC(mchk)
183 pushl $0; TRAP(T_MCHK)
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184
185IDTVEC(rsvd0)
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186 pushl $0; TRAP(T_RESERVED)
187
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188#ifdef DEBUG_INTERRUPTS
189
190IDTVEC(rsvd1)
191 pushl $1; TRAP(T_RESERVED)
192IDTVEC(rsvd2)
193 pushl $2; TRAP(T_RESERVED)
194IDTVEC(rsvd3)
195 pushl $3; TRAP(T_RESERVED)
196IDTVEC(rsvd4)
197 pushl $4; TRAP(T_RESERVED)
198IDTVEC(rsvd5)
199 pushl $5; TRAP(T_RESERVED)
200IDTVEC(rsvd6)
201 pushl $6; TRAP(T_RESERVED)
202IDTVEC(rsvd7)
203 pushl $7; TRAP(T_RESERVED)
204IDTVEC(rsvd8)
205 pushl $8; TRAP(T_RESERVED)
206IDTVEC(rsvd9)
207 pushl $9; TRAP(T_RESERVED)
208IDTVEC(rsvd10)
209 pushl $10; TRAP(T_RESERVED)
210IDTVEC(rsvd11)
211 pushl $11; TRAP(T_RESERVED)
212IDTVEC(rsvd12)
213 pushl $12; TRAP(T_RESERVED)
214IDTVEC(rsvd13)
215 pushl $13; TRAP(T_RESERVED)
216IDTVEC(rsvd14)
217 pushl $14; TRAP(T_RESERVED)
218IDTVEC(rsvd15)
219 pushl $15; TRAP(T_RESERVED)
220IDTVEC(rsvd16)
221 pushl $16; TRAP(T_RESERVED)
222IDTVEC(rsvd17)
223 pushl $17; TRAP(T_RESERVED)
224IDTVEC(rsvd18)
225 pushl $18; TRAP(T_RESERVED)
226IDTVEC(rsvd19)
227 pushl $19; TRAP(T_RESERVED)
228IDTVEC(rsvd20)
229 pushl $20; TRAP(T_RESERVED)
230IDTVEC(rsvd21)
231 pushl $21; TRAP(T_RESERVED)
232IDTVEC(rsvd22)
233 pushl $22; TRAP(T_RESERVED)
234IDTVEC(rsvd23)
235 pushl $23; TRAP(T_RESERVED)
236IDTVEC(rsvd24)
237 pushl $24; TRAP(T_RESERVED)
238IDTVEC(rsvd25)
239 pushl $25; TRAP(T_RESERVED)
240IDTVEC(rsvd26)
241 pushl $26; TRAP(T_RESERVED)
242IDTVEC(rsvd27)
243 pushl $27; TRAP(T_RESERVED)
244IDTVEC(rsvd28)
245 pushl $28; TRAP(T_RESERVED)
246IDTVEC(rsvd29)
247 pushl $29; TRAP(T_RESERVED)
248IDTVEC(rsvd30)
249 pushl $30; TRAP(T_RESERVED)
250IDTVEC(rsvd31)
251 pushl $31; TRAP(T_RESERVED)
252IDTVEC(rsvd32)
253 pushl $32; TRAP(T_RESERVED)
254IDTVEC(rsvd33)
255 pushl $33; TRAP(T_RESERVED)
256IDTVEC(rsvd34)
257 pushl $34; TRAP(T_RESERVED)
258IDTVEC(rsvd35)
259 pushl $35; TRAP(T_RESERVED)
260IDTVEC(rsvd36)
261 pushl $36; TRAP(T_RESERVED)
262IDTVEC(rsvd37)
263 pushl $37; TRAP(T_RESERVED)
264IDTVEC(rsvd38)
265 pushl $38; TRAP(T_RESERVED)
266IDTVEC(rsvd39)
267 pushl $39; TRAP(T_RESERVED)
268IDTVEC(rsvd40)
269 pushl $40; TRAP(T_RESERVED)
270IDTVEC(rsvd41)
271 pushl $41; TRAP(T_RESERVED)
272IDTVEC(rsvd42)
273 pushl $42; TRAP(T_RESERVED)
274IDTVEC(rsvd43)
275 pushl $43; TRAP(T_RESERVED)
276IDTVEC(rsvd44)
277 pushl $44; TRAP(T_RESERVED)
278IDTVEC(rsvd45)
279 pushl $45; TRAP(T_RESERVED)
280IDTVEC(rsvd46)
281 pushl $46; TRAP(T_RESERVED)
282IDTVEC(rsvd47)
283 pushl $47; TRAP(T_RESERVED)
284IDTVEC(rsvd48)
285 pushl $48; TRAP(T_RESERVED)
286IDTVEC(rsvd49)
287 pushl $49; TRAP(T_RESERVED)
288IDTVEC(rsvd50)
289 pushl $50; TRAP(T_RESERVED)
290IDTVEC(rsvd51)
291 pushl $51; TRAP(T_RESERVED)
292IDTVEC(rsvd52)
293 pushl $52; TRAP(T_RESERVED)
294IDTVEC(rsvd53)
295 pushl $53; TRAP(T_RESERVED)
296IDTVEC(rsvd54)
297 pushl $54; TRAP(T_RESERVED)
298IDTVEC(rsvd55)
299 pushl $55; TRAP(T_RESERVED)
300IDTVEC(rsvd56)
301 pushl $56; TRAP(T_RESERVED)
302IDTVEC(rsvd57)
303 pushl $57; TRAP(T_RESERVED)
304IDTVEC(rsvd58)
305 pushl $58; TRAP(T_RESERVED)
306IDTVEC(rsvd59)
307 pushl $59; TRAP(T_RESERVED)
308IDTVEC(rsvd60)
309 pushl $60; TRAP(T_RESERVED)
310IDTVEC(rsvd61)
311 pushl $61; TRAP(T_RESERVED)
312IDTVEC(rsvd62)
313 pushl $62; TRAP(T_RESERVED)
314IDTVEC(rsvd63)
315 pushl $63; TRAP(T_RESERVED)
316IDTVEC(rsvd64)
317 pushl $64; TRAP(T_RESERVED)
318IDTVEC(rsvd65)
319 pushl $65; TRAP(T_RESERVED)
320IDTVEC(rsvd66)
321 pushl $66; TRAP(T_RESERVED)
322IDTVEC(rsvd67)
323 pushl $67; TRAP(T_RESERVED)
324IDTVEC(rsvd68)
325 pushl $68; TRAP(T_RESERVED)
326IDTVEC(rsvd69)
327 pushl $69; TRAP(T_RESERVED)
328IDTVEC(rsvd70)
329 pushl $70; TRAP(T_RESERVED)
330IDTVEC(rsvd71)
331 pushl $71; TRAP(T_RESERVED)
332IDTVEC(rsvd72)
333 pushl $72; TRAP(T_RESERVED)
334IDTVEC(rsvd73)
335 pushl $73; TRAP(T_RESERVED)
336IDTVEC(rsvd74)
337 pushl $74; TRAP(T_RESERVED)
338IDTVEC(rsvd75)
339 pushl $75; TRAP(T_RESERVED)
340IDTVEC(rsvd76)
341 pushl $76; TRAP(T_RESERVED)
342IDTVEC(rsvd77)
343 pushl $77; TRAP(T_RESERVED)
344IDTVEC(rsvd78)
345 pushl $78; TRAP(T_RESERVED)
346IDTVEC(rsvd79)
347 pushl $79; TRAP(T_RESERVED)
348IDTVEC(rsvd80)
349 pushl $80; TRAP(T_RESERVED)
350IDTVEC(rsvd81)
351 pushl $81; TRAP(T_RESERVED)
352IDTVEC(rsvd82)
353 pushl $82; TRAP(T_RESERVED)
354IDTVEC(rsvd83)
355 pushl $83; TRAP(T_RESERVED)
356IDTVEC(rsvd84)
357 pushl $84; TRAP(T_RESERVED)
358IDTVEC(rsvd85)
359 pushl $85; TRAP(T_RESERVED)
360IDTVEC(rsvd86)
361 pushl $86; TRAP(T_RESERVED)
362IDTVEC(rsvd87)
363 pushl $87; TRAP(T_RESERVED)
364IDTVEC(rsvd88)
365 pushl $88; TRAP(T_RESERVED)
366IDTVEC(rsvd89)
367 pushl $89; TRAP(T_RESERVED)
368IDTVEC(rsvd90)
369 pushl $90; TRAP(T_RESERVED)
370IDTVEC(rsvd91)
371 pushl $91; TRAP(T_RESERVED)
372IDTVEC(rsvd92)
373 pushl $92; TRAP(T_RESERVED)
374IDTVEC(rsvd93)
375 pushl $93; TRAP(T_RESERVED)
376IDTVEC(rsvd94)
377 pushl $94; TRAP(T_RESERVED)
378IDTVEC(rsvd95)
379 pushl $95; TRAP(T_RESERVED)
380IDTVEC(rsvd96)
381 pushl $96; TRAP(T_RESERVED)
382IDTVEC(rsvd97)
383 pushl $97; TRAP(T_RESERVED)
384IDTVEC(rsvd98)
385 pushl $98; TRAP(T_RESERVED)
386IDTVEC(rsvd99)
387 pushl $99; TRAP(T_RESERVED)
388IDTVEC(rsvd100)
389 pushl $100; TRAP(T_RESERVED)
390IDTVEC(rsvd101)
391 pushl $101; TRAP(T_RESERVED)
392IDTVEC(rsvd102)
393 pushl $102; TRAP(T_RESERVED)
394IDTVEC(rsvd103)
395 pushl $103; TRAP(T_RESERVED)
396IDTVEC(rsvd104)
397 pushl $104; TRAP(T_RESERVED)
398IDTVEC(rsvd105)
399 pushl $105; TRAP(T_RESERVED)
400IDTVEC(rsvd106)
401 pushl $106; TRAP(T_RESERVED)
402IDTVEC(rsvd107)
403 pushl $107; TRAP(T_RESERVED)
404IDTVEC(rsvd108)
405 pushl $108; TRAP(T_RESERVED)
406IDTVEC(rsvd109)
407 pushl $109; TRAP(T_RESERVED)
408IDTVEC(rsvd110)
409 pushl $110; TRAP(T_RESERVED)
410IDTVEC(rsvd111)
411 pushl $111; TRAP(T_RESERVED)
412IDTVEC(rsvd112)
413 pushl $112; TRAP(T_RESERVED)
414IDTVEC(rsvd113)
415 pushl $113; TRAP(T_RESERVED)
416IDTVEC(rsvd114)
417 pushl $114; TRAP(T_RESERVED)
418IDTVEC(rsvd115)
419 pushl $115; TRAP(T_RESERVED)
420IDTVEC(rsvd116)
421 pushl $116; TRAP(T_RESERVED)
422IDTVEC(rsvd117)
423 pushl $117; TRAP(T_RESERVED)
424IDTVEC(rsvd118)
425 pushl $118; TRAP(T_RESERVED)
426IDTVEC(rsvd119)
427 pushl $119; TRAP(T_RESERVED)
428IDTVEC(rsvd120)
429 pushl $120; TRAP(T_RESERVED)
430IDTVEC(rsvd121)
431 pushl $121; TRAP(T_RESERVED)
432IDTVEC(rsvd122)
433 pushl $122; TRAP(T_RESERVED)
434IDTVEC(rsvd123)
435 pushl $123; TRAP(T_RESERVED)
436IDTVEC(rsvd124)
437 pushl $124; TRAP(T_RESERVED)
438IDTVEC(rsvd125)
439 pushl $125; TRAP(T_RESERVED)
440IDTVEC(rsvd126)
441 pushl $126; TRAP(T_RESERVED)
442IDTVEC(rsvd127)
443 pushl $127; TRAP(T_RESERVED)
444IDTVEC(rsvd128)
445 pushl $128; TRAP(T_RESERVED)
446IDTVEC(rsvd129)
447 pushl $129; TRAP(T_RESERVED)
448IDTVEC(rsvd130)
449 pushl $130; TRAP(T_RESERVED)
450IDTVEC(rsvd131)
451 pushl $131; TRAP(T_RESERVED)
452IDTVEC(rsvd132)
453 pushl $132; TRAP(T_RESERVED)
454IDTVEC(rsvd133)
455 pushl $133; TRAP(T_RESERVED)
456IDTVEC(rsvd134)
457 pushl $134; TRAP(T_RESERVED)
458IDTVEC(rsvd135)
459 pushl $135; TRAP(T_RESERVED)
460IDTVEC(rsvd136)
461 pushl $136; TRAP(T_RESERVED)
462IDTVEC(rsvd137)
463 pushl $137; TRAP(T_RESERVED)
464IDTVEC(rsvd138)
465 pushl $138; TRAP(T_RESERVED)
466IDTVEC(rsvd139)
467 pushl $139; TRAP(T_RESERVED)
468IDTVEC(rsvd140)
469 pushl $140; TRAP(T_RESERVED)
470IDTVEC(rsvd141)
471 pushl $141; TRAP(T_RESERVED)
472IDTVEC(rsvd142)
473 pushl $142; TRAP(T_RESERVED)
474IDTVEC(rsvd143)
475 pushl $143; TRAP(T_RESERVED)
476IDTVEC(rsvd144)
477 pushl $144; TRAP(T_RESERVED)
478IDTVEC(rsvd145)
479 pushl $145; TRAP(T_RESERVED)
480IDTVEC(rsvd146)
481 pushl $146; TRAP(T_RESERVED)
482IDTVEC(rsvd147)
483 pushl $147; TRAP(T_RESERVED)
484IDTVEC(rsvd148)
485 pushl $148; TRAP(T_RESERVED)
486IDTVEC(rsvd149)
487 pushl $149; TRAP(T_RESERVED)
488IDTVEC(rsvd150)
489 pushl $150; TRAP(T_RESERVED)
490IDTVEC(rsvd151)
491 pushl $151; TRAP(T_RESERVED)
492IDTVEC(rsvd152)
493 pushl $152; TRAP(T_RESERVED)
494IDTVEC(rsvd153)
495 pushl $153; TRAP(T_RESERVED)
496IDTVEC(rsvd154)
497 pushl $154; TRAP(T_RESERVED)
498IDTVEC(rsvd155)
499 pushl $155; TRAP(T_RESERVED)
500IDTVEC(rsvd156)
501 pushl $156; TRAP(T_RESERVED)
502IDTVEC(rsvd157)
503 pushl $157; TRAP(T_RESERVED)
504IDTVEC(rsvd158)
505 pushl $158; TRAP(T_RESERVED)
506IDTVEC(rsvd159)
507 pushl $159; TRAP(T_RESERVED)
508IDTVEC(rsvd160)
509 pushl $160; TRAP(T_RESERVED)
510IDTVEC(rsvd161)
511 pushl $161; TRAP(T_RESERVED)
512IDTVEC(rsvd162)
513 pushl $162; TRAP(T_RESERVED)
514IDTVEC(rsvd163)
515 pushl $163; TRAP(T_RESERVED)
516IDTVEC(rsvd164)
517 pushl $164; TRAP(T_RESERVED)
518IDTVEC(rsvd165)
519 pushl $165; TRAP(T_RESERVED)
520IDTVEC(rsvd166)
521 pushl $166; TRAP(T_RESERVED)
522IDTVEC(rsvd167)
523 pushl $167; TRAP(T_RESERVED)
524IDTVEC(rsvd168)
525 pushl $168; TRAP(T_RESERVED)
526IDTVEC(rsvd169)
527 pushl $169; TRAP(T_RESERVED)
528IDTVEC(rsvd170)
529 pushl $170; TRAP(T_RESERVED)
530IDTVEC(rsvd171)
531 pushl $171; TRAP(T_RESERVED)
532IDTVEC(rsvd172)
533 pushl $172; TRAP(T_RESERVED)
534IDTVEC(rsvd173)
535 pushl $173; TRAP(T_RESERVED)
536IDTVEC(rsvd174)
537 pushl $174; TRAP(T_RESERVED)
538IDTVEC(rsvd175)
539 pushl $175; TRAP(T_RESERVED)
540IDTVEC(rsvd176)
541 pushl $176; TRAP(T_RESERVED)
542IDTVEC(rsvd177)
543 pushl $177; TRAP(T_RESERVED)
544IDTVEC(rsvd178)
545 pushl $178; TRAP(T_RESERVED)
546IDTVEC(rsvd179)
547 pushl $179; TRAP(T_RESERVED)
548IDTVEC(rsvd180)
549 pushl $180; TRAP(T_RESERVED)
550IDTVEC(rsvd181)
551 pushl $181; TRAP(T_RESERVED)
552IDTVEC(rsvd182)
553 pushl $182; TRAP(T_RESERVED)
554IDTVEC(rsvd183)
555 pushl $183; TRAP(T_RESERVED)
556IDTVEC(rsvd184)
557 pushl $184; TRAP(T_RESERVED)
558IDTVEC(rsvd185)
559 pushl $185; TRAP(T_RESERVED)
560IDTVEC(rsvd186)
561 pushl $186; TRAP(T_RESERVED)
562IDTVEC(rsvd187)
563 pushl $187; TRAP(T_RESERVED)
564IDTVEC(rsvd188)
565 pushl $188; TRAP(T_RESERVED)
566IDTVEC(rsvd189)
567 pushl $189; TRAP(T_RESERVED)
568IDTVEC(rsvd190)
569 pushl $190; TRAP(T_RESERVED)
570IDTVEC(rsvd191)
571 pushl $191; TRAP(T_RESERVED)
572IDTVEC(rsvd192)
573 pushl $192; TRAP(T_RESERVED)
574IDTVEC(rsvd193)
575 pushl $193; TRAP(T_RESERVED)
576IDTVEC(rsvd194)
577 pushl $194; TRAP(T_RESERVED)
578IDTVEC(rsvd195)
579 pushl $195; TRAP(T_RESERVED)
580IDTVEC(rsvd196)
581 pushl $196; TRAP(T_RESERVED)
582IDTVEC(rsvd197)
583 pushl $197; TRAP(T_RESERVED)
584IDTVEC(rsvd198)
585 pushl $198; TRAP(T_RESERVED)
586IDTVEC(rsvd199)
587 pushl $199; TRAP(T_RESERVED)
588IDTVEC(rsvd200)
589 pushl $200; TRAP(T_RESERVED)
590IDTVEC(rsvd201)
591 pushl $201; TRAP(T_RESERVED)
592IDTVEC(rsvd202)
593 pushl $202; TRAP(T_RESERVED)
594IDTVEC(rsvd203)
595 pushl $203; TRAP(T_RESERVED)
596IDTVEC(rsvd204)
597 pushl $204; TRAP(T_RESERVED)
598IDTVEC(rsvd205)
599 pushl $205; TRAP(T_RESERVED)
600IDTVEC(rsvd206)
601 pushl $206; TRAP(T_RESERVED)
602IDTVEC(rsvd207)
603 pushl $207; TRAP(T_RESERVED)
604IDTVEC(rsvd208)
605 pushl $208; TRAP(T_RESERVED)
606IDTVEC(rsvd209)
607 pushl $209; TRAP(T_RESERVED)
608IDTVEC(rsvd210)
609 pushl $210; TRAP(T_RESERVED)
610IDTVEC(rsvd211)
611 pushl $211; TRAP(T_RESERVED)
612IDTVEC(rsvd212)
613 pushl $212; TRAP(T_RESERVED)
614IDTVEC(rsvd213)
615 pushl $213; TRAP(T_RESERVED)
616IDTVEC(rsvd214)
617 pushl $214; TRAP(T_RESERVED)
618IDTVEC(rsvd215)
619 pushl $215; TRAP(T_RESERVED)
620IDTVEC(rsvd216)
621 pushl $216; TRAP(T_RESERVED)
622IDTVEC(rsvd217)
623 pushl $217; TRAP(T_RESERVED)
624IDTVEC(rsvd218)
625 pushl $218; TRAP(T_RESERVED)
626IDTVEC(rsvd219)
627 pushl $219; TRAP(T_RESERVED)
628IDTVEC(rsvd220)
629 pushl $220; TRAP(T_RESERVED)
630IDTVEC(rsvd221)
631 pushl $221; TRAP(T_RESERVED)
632IDTVEC(rsvd222)
633 pushl $222; TRAP(T_RESERVED)
634IDTVEC(rsvd223)
635 pushl $223; TRAP(T_RESERVED)
636IDTVEC(rsvd224)
637 pushl $224; TRAP(T_RESERVED)
638IDTVEC(rsvd225)
639 pushl $225; TRAP(T_RESERVED)
640IDTVEC(rsvd226)
641 pushl $226; TRAP(T_RESERVED)
642IDTVEC(rsvd227)
643 pushl $227; TRAP(T_RESERVED)
644IDTVEC(rsvd228)
645 pushl $228; TRAP(T_RESERVED)
646IDTVEC(rsvd229)
647 pushl $229; TRAP(T_RESERVED)
648IDTVEC(rsvd230)
649 pushl $230; TRAP(T_RESERVED)
650IDTVEC(rsvd231)
651 pushl $231; TRAP(T_RESERVED)
652IDTVEC(rsvd232)
653 pushl $232; TRAP(T_RESERVED)
654IDTVEC(rsvd233)
655 pushl $233; TRAP(T_RESERVED)
656IDTVEC(rsvd234)
657 pushl $234; TRAP(T_RESERVED)
658IDTVEC(rsvd235)
659 pushl $235; TRAP(T_RESERVED)
660IDTVEC(rsvd236)
661 pushl $236; TRAP(T_RESERVED)
662IDTVEC(rsvd237)
663 pushl $237; TRAP(T_RESERVED)
664IDTVEC(rsvd238)
665 pushl $238; TRAP(T_RESERVED)
666IDTVEC(rsvd239)
667 pushl $239; TRAP(T_RESERVED)
668IDTVEC(rsvd240)
669 pushl $240; TRAP(T_RESERVED)
670IDTVEC(rsvd241)
671 pushl $241; TRAP(T_RESERVED)
672IDTVEC(rsvd242)
673 pushl $242; TRAP(T_RESERVED)
674IDTVEC(rsvd243)
675 pushl $243; TRAP(T_RESERVED)
676IDTVEC(rsvd244)
677 pushl $244; TRAP(T_RESERVED)
678IDTVEC(rsvd245)
679 pushl $245; TRAP(T_RESERVED)
680IDTVEC(rsvd246)
681 pushl $246; TRAP(T_RESERVED)
682IDTVEC(rsvd247)
683 pushl $247; TRAP(T_RESERVED)
684IDTVEC(rsvd248)
685 pushl $248; TRAP(T_RESERVED)
686IDTVEC(rsvd249)
687 pushl $249; TRAP(T_RESERVED)
688IDTVEC(rsvd250)
689 pushl $250; TRAP(T_RESERVED)
690IDTVEC(rsvd251)
691 pushl $251; TRAP(T_RESERVED)
692IDTVEC(rsvd252)
693 pushl $252; TRAP(T_RESERVED)
694IDTVEC(rsvd253)
695 pushl $253; TRAP(T_RESERVED)
696IDTVEC(rsvd254)
697 pushl $254; TRAP(T_RESERVED)
698IDTVEC(rsvd255)
699 pushl $255; TRAP(T_RESERVED)
700
701#endif
702
984263bc
MD
703IDTVEC(fpu)
704#if NNPX > 0
705 /*
706 * Handle like an interrupt (except for accounting) so that we can
707 * call npx_intr to clear the error. It would be better to handle
708 * npx interrupts as traps. Nested interrupts would probably have
709 * to be converted to ASTs.
710 */
711 pushl $0 /* dummy error code */
712 pushl $0 /* dummy trap type */
713 pushal
714 pushl %ds
715 pushl %es /* now stack frame is a trap frame */
716 pushl %fs
717 mov $KDSEL,%ax
718 mov %ax,%ds
719 mov %ax,%es
12e4aaff 720 mov $KPSEL,%ax
984263bc
MD
721 mov %ax,%fs
722 FAKE_MCOUNT(13*4(%esp))
723
12e4aaff 724 incl PCPU(cnt)+V_TRAP
984263bc 725
bc588e93
MD
726 /* additional dummy pushes to fake an interrupt frame */
727 pushl $0 /* ppl */
728 pushl $0 /* vector */
729
730 /* warning, trap frame dummy arg, no extra reg pushes */
2954c92f 731 call npx_intr /* note: call might mess w/ argument */
984263bc 732
bc588e93
MD
733 /* convert back to a trapframe for doreti */
734 addl $4,%esp
38787eef 735 movl $0,(%esp) /* DUMMY CPL FOR DORETI */
984263bc 736 MEXITCOUNT
2954c92f 737 jmp doreti
984263bc
MD
738#else /* NNPX > 0 */
739 pushl $0; TRAP(T_ARITHTRAP)
740#endif /* NNPX > 0 */
741
742IDTVEC(align)
743 TRAP(T_ALIGNFLT)
744
745IDTVEC(xmm)
746 pushl $0; TRAP(T_XMMFLT)
747
748 /*
749 * _alltraps entry point. Interrupts are enabled if this was a trap
750 * gate (TGT), else disabled if this was an interrupt gate (IGT).
751 * Note that int0x80_syscall is a trap gate. Only page faults
752 * use an interrupt gate.
753 *
8a8d5d85 754 * Note that we are MP through to the call to trap().
984263bc
MD
755 */
756
757 SUPERALIGN_TEXT
2954c92f
MD
758 .globl alltraps
759 .type alltraps,@function
760alltraps:
984263bc
MD
761 pushal
762 pushl %ds
763 pushl %es
764 pushl %fs
765alltraps_with_regs_pushed:
766 mov $KDSEL,%ax
767 mov %ax,%ds
768 mov %ax,%es
12e4aaff 769 mov $KPSEL,%ax
984263bc
MD
770 mov %ax,%fs
771 FAKE_MCOUNT(13*4(%esp))
772calltrap:
2954c92f 773 FAKE_MCOUNT(btrap) /* init "from" _btrap -> calltrap */
96728c05 774 incl PCPU(cnt)+V_TRAP
bc588e93 775 /* warning, trap frame dummy arg, no extra reg pushes */
2954c92f 776 call trap
984263bc
MD
777
778 /*
2954c92f 779 * Return via doreti to handle ASTs. Have to change trap frame
984263bc
MD
780 * to interrupt frame.
781 */
38787eef 782 pushl $0 /* DUMMY CPL FOR DORETI */
984263bc 783 MEXITCOUNT
2954c92f 784 jmp doreti
984263bc
MD
785
786/*
787 * SYSCALL CALL GATE (old entry point for a.out binaries)
788 *
789 * The intersegment call has been set up to specify one dummy parameter.
790 *
791 * This leaves a place to put eflags so that the call frame can be
792 * converted to a trap frame. Note that the eflags is (semi-)bogusly
793 * pushed into (what will be) tf_err and then copied later into the
794 * final spot. It has to be done this way because esp can't be just
795 * temporarily altered for the pushfl - an interrupt might come in
796 * and clobber the saved cs/eip.
797 *
798 * We do not obtain the MP lock, but the call to syscall2 might. If it
799 * does it will release the lock prior to returning.
800 */
801 SUPERALIGN_TEXT
802IDTVEC(syscall)
803 pushfl /* save eflags in tf_err for now */
804 subl $4,%esp /* skip over tf_trapno */
805 pushal
806 pushl %ds
807 pushl %es
808 pushl %fs
809 mov $KDSEL,%ax /* switch to kernel segments */
810 mov %ax,%ds
811 mov %ax,%es
12e4aaff 812 mov $KPSEL,%ax
984263bc
MD
813 mov %ax,%fs
814 movl TF_ERR(%esp),%eax /* copy saved eflags to final spot */
815 movl %eax,TF_EFLAGS(%esp)
816 movl $7,TF_ERR(%esp) /* sizeof "lcall 7,0" */
817 FAKE_MCOUNT(13*4(%esp))
12e4aaff 818 incl PCPU(cnt)+V_SYSCALL /* YYY per-cpu */
bc588e93 819 /* warning, trap frame dummy arg, no extra reg pushes */
2954c92f 820 call syscall2
984263bc 821 MEXITCOUNT
235957ed
MD
822 cli /* atomic reqflags interlock w/iret */
823 cmpl $0,PCPU(reqflags)
984263bc 824 je doreti_syscall_ret
984263bc 825 pushl $0 /* cpl to restore */
2954c92f 826 jmp doreti
984263bc
MD
827
828/*
a64ba182 829 * Trap gate entry for FreeBSD ELF and Linux/NetBSD syscall (int 0x80)
984263bc
MD
830 *
831 * Even though the name says 'int0x80', this is actually a TGT (trap gate)
832 * rather then an IGT (interrupt gate). Thus interrupts are enabled on
833 * entry just as they are for a normal syscall.
834 *
835 * We do not obtain the MP lock, but the call to syscall2 might. If it
836 * does it will release the lock prior to returning.
837 */
838 SUPERALIGN_TEXT
839IDTVEC(int0x80_syscall)
840 subl $8,%esp /* skip over tf_trapno and tf_err */
841 pushal
842 pushl %ds
843 pushl %es
844 pushl %fs
845 mov $KDSEL,%ax /* switch to kernel segments */
846 mov %ax,%ds
847 mov %ax,%es
12e4aaff 848 mov $KPSEL,%ax
984263bc
MD
849 mov %ax,%fs
850 movl $2,TF_ERR(%esp) /* sizeof "int 0x80" */
851 FAKE_MCOUNT(13*4(%esp))
a64ba182 852 incl PCPU(cnt)+V_SYSCALL
bc588e93 853 /* warning, trap frame dummy arg, no extra reg pushes */
2954c92f 854 call syscall2
984263bc 855 MEXITCOUNT
235957ed
MD
856 cli /* atomic reqflags interlock w/irq */
857 cmpl $0,PCPU(reqflags)
984263bc 858 je doreti_syscall_ret
984263bc 859 pushl $0 /* cpl to restore */
2954c92f 860 jmp doreti
984263bc 861
a64ba182 862/*
7062f5b4 863 * Trap gate entry for syscall messaging interface (int 0x81).
a64ba182
MD
864 * Arguments are passed in registers, the return value is placed in %eax.
865 *
866 * eax:error = int0x81(eax:port, ecx:msg, edx:msgsize)
867 *
7062f5b4 868 * Performs message sending and flushing
a64ba182
MD
869 * functinos.
870 */
871 SUPERALIGN_TEXT
872IDTVEC(int0x81_syscall)
873 subl $8,%esp /* skip over tf_trapno and tf_err */
874 pushal
875 pushl %ds
876 pushl %es
877 pushl %fs
878 mov $KDSEL,%ax /* switch to kernel segments */
879 mov %ax,%ds
880 mov %ax,%es
881 mov $KPSEL,%ax
882 mov %ax,%fs
883 /* note: tf_err is not used */
884 FAKE_MCOUNT(13*4(%esp))
885 incl PCPU(cnt)+V_SENDSYS
bc588e93 886 /* warning, trap frame dummy arg, no extra reg pushes */
a64ba182
MD
887 call sendsys2
888 MEXITCOUNT
889 cli /* atomic reqflags interlock w/irq */
7062f5b4
EN
890 cmpl $0,PCPU(reqflags)
891 je doreti_syscall_ret
892 pushl $0 /* cpl to restore */
893 jmp doreti
894
895/*
896 * Trap gate entry for syscall messaging interface (int 0x82).
897 * Arguments are passed in registers, the return value is placed in %eax.
898 *
899 * eax:error = int0x82(eax:port, ecx:msg, edx:msgsize)
900 *
901 * Performs message and port waiting functions.
902 */
903 SUPERALIGN_TEXT
904IDTVEC(int0x82_syscall)
905 subl $8,%esp /* skip over tf_trapno and tf_err */
906 pushal
907 pushl %ds
908 pushl %es
909 pushl %fs
910 mov $KDSEL,%ax /* switch to kernel segments */
911 mov %ax,%ds
912 mov %ax,%es
913 mov $KPSEL,%ax
914 mov %ax,%fs
915 /* note: tf_err is not used */
916 FAKE_MCOUNT(13*4(%esp))
917 incl PCPU(cnt)+V_WAITSYS
918 /* warning, trap frame dummy arg, no extra reg pushes */
919 call waitsys2
920 MEXITCOUNT
921 cli /* atomic reqflags interlock w/irq */
a64ba182
MD
922 cmpl $0,PCPU(reqflags)
923 je doreti_syscall_ret
924 pushl $0 /* cpl to restore */
a64ba182
MD
925 jmp doreti
926
26a0694b
MD
927/*
928 * This function is what cpu_heavy_restore jumps to after a new process
d9eea1a5
MD
929 * is created. The LWKT subsystem switches while holding a critical
930 * section and we maintain that abstraction here (e.g. because
931 * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
932 * it before calling the initial function (typically fork_return()) and/or
933 * returning to user mode.
8a8d5d85 934 *
d9eea1a5 935 * The MP lock is held on entry, but for processes fork_return(esi)
8a8d5d85 936 * releases it. 'doreti' always runs without the MP lock.
26a0694b 937 */
984263bc 938ENTRY(fork_trampoline)
2954c92f 939 movl PCPU(curthread),%eax
26a0694b 940 subl $TDPRI_CRIT,TD_PRI(%eax)
8ad65e08 941
984263bc
MD
942 /*
943 * cpu_set_fork_handler intercepts this function call to
944 * have this call a non-return function to stay in kernel mode.
96728c05
MD
945 *
946 * initproc has its own fork handler, start_init(), which DOES
947 * return.
984263bc
MD
948 */
949 pushl %ebx /* arg1 */
950 call *%esi /* function */
951 addl $4,%esp
952 /* cut from syscall */
953
d9eea1a5 954 sti
96728c05
MD
955 call splz
956
957#if defined(INVARIANTS) && defined(SMP)
958 movl PCPU(curthread),%eax
959 cmpl $0,TD_MPCOUNT(%eax)
960 je 1f
961 pushl %esi
962 pushl TD_MPCOUNT(%eax)
963 pushl $pmsg4
964 call panic
965pmsg4: .asciz "fork_trampoline mpcount %d after calling %p"
d9eea1a5 966 .p2align 2
96728c05
MD
9671:
968#endif
984263bc 969 /*
2954c92f 970 * Return via doreti to handle ASTs.
984263bc
MD
971 */
972 pushl $0 /* cpl to restore */
984263bc 973 MEXITCOUNT
2954c92f 974 jmp doreti
984263bc
MD
975
976
977/*
2954c92f 978 * Include vm86 call routines, which want to call doreti.
984263bc
MD
979 */
980#include "i386/i386/vm86bios.s"
981
982/*
983 * Include what was once config+isa-dependent code.
984 * XXX it should be in a stand-alone file. It's still icu-dependent and
985 * belongs in i386/isa.
986 */
987#include "i386/isa/vector.s"
988
989/*
990 * Include what was once icu-dependent code.
991 * XXX it should be merged into this file (also move the definition of
992 * imen to vector.s or isa.c).
993 * Before including it, set up a normal asm environment so that vector.s
994 * doesn't have to know that stuff is included after it.
995 */
996 .data
997 ALIGN_DATA
998 .text
999 SUPERALIGN_TEXT
1000#include "i386/isa/ipl.s"