Remove all remaining SPL code. Replace the mtd_cpl field in the machine
[dragonfly.git] / sys / platform / pc32 / isa / npx.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
38787eef 36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.24 2005/06/16 21:12:47 dillon Exp $
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37 */
38
39#include "opt_cpu.h"
40#include "opt_debug_npx.h"
41#include "opt_math_emulate.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/bus.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/module.h>
49#include <sys/sysctl.h>
50#include <sys/proc.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#ifdef NPX_DEBUG
54#include <sys/syslog.h>
55#endif
56#include <sys/signalvar.h>
bd331ffe 57#include <sys/thread2.h>
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58
59#ifndef SMP
60#include <machine/asmacros.h>
61#endif
62#include <machine/cputypes.h>
63#include <machine/frame.h>
64#include <machine/ipl.h>
65#include <machine/md_var.h>
66#include <machine/pcb.h>
67#include <machine/psl.h>
68#ifndef SMP
69#include <machine/clock.h>
70#endif
71#include <machine/resource.h>
72#include <machine/specialreg.h>
73#include <machine/segments.h>
85100692 74#include <machine/globaldata.h>
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75
76#ifndef SMP
77#include <i386/isa/icu.h>
78#include <i386/isa/intr_machdep.h>
1f2de5d4 79#include <bus/isa/i386/isa.h>
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80#endif
81
82/*
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
84 */
85
86/* Configuration flags. */
87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90#define NPX_PREFER_EMULATOR (1 << 3)
91
92#ifdef __GNUC__
93
94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95#define fnclex() __asm("fnclex")
96#define fninit() __asm("fninit")
97#define fnop() __asm("fnop")
98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
642a6e88 103#ifndef CPU_DISABLE_SSE
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104#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
106#endif
107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109#define stop_emulating() __asm("clts")
110
111#else /* not __GNUC__ */
112
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113void fldcw (caddr_t addr);
114void fnclex (void);
115void fninit (void);
116void fnop (void);
117void fnsave (caddr_t addr);
118void fnstcw (caddr_t addr);
119void fnstsw (caddr_t addr);
120void fp_divide_by_0 (void);
121void frstor (caddr_t addr);
642a6e88 122#ifndef CPU_DISABLE_SSE
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123void fxsave (caddr_t addr);
124void fxrstor (caddr_t addr);
984263bc 125#endif
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126void start_emulating (void);
127void stop_emulating (void);
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128
129#endif /* __GNUC__ */
130
642a6e88 131#ifndef CPU_DISABLE_SSE
65d6ce10 132#define GET_FPU_EXSW_PTR(td) \
984263bc 133 (cpu_fxsr ? \
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134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 136#else /* CPU_DISABLE_SSE */
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137#define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 139#endif /* CPU_DISABLE_SSE */
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140
141typedef u_char bool_t;
142
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143static int npx_attach (device_t dev);
144 void npx_intr (void *);
145static void npx_identify (driver_t *driver, device_t parent);
146static int npx_probe (device_t dev);
147static int npx_probe1 (device_t dev);
148static void fpusave (union savefpu *);
149static void fpurstor (union savefpu *);
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150
151int hw_float; /* XXX currently just alias for npx_exists */
152
153SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
154 CTLFLAG_RD, &hw_float, 0,
155 "Floatingpoint instructions executed in hardware");
629f74cc 156#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
29ad119f 157int mmxopt = 1;
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158SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
159 "MMX/XMM optimized bcopy/copyin/copyout support");
160#endif
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161
162#ifndef SMP
38787eef 163static u_int npx0_imask;
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164static struct gate_descriptor npx_idt_probeintr;
165static int npx_intrno;
166static volatile u_int npx_intrs_while_probing;
167static volatile u_int npx_traps_while_probing;
168#endif
169
170static bool_t npx_ex16;
171static bool_t npx_exists;
172static bool_t npx_irq13;
173static int npx_irq; /* irq number */
174
175#ifndef SMP
176/*
177 * Special interrupt handlers. Someday intr0-intr15 will be used to count
178 * interrupts. We'll still need a special exception 16 handler. The busy
179 * latch stuff in probeintr() can be moved to npxprobe().
180 */
181inthand_t probeintr;
182__asm(" \n\
183 .text \n\
184 .p2align 2,0x90 \n\
185 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
186" __XSTRING(CNAME(probeintr)) ": \n\
187 ss \n\
188 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
189 pushl %eax \n\
190 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
191 outb %al,$0xa0 # IO_ICU2 \n\
192 outb %al,$0x20 # IO_ICU1 \n\
193 movb $0,%al \n\
194 outb %al,$0xf0 # clear BUSY# latch \n\
195 popl %eax \n\
196 iret \n\
197");
198
199inthand_t probetrap;
200__asm(" \n\
201 .text \n\
202 .p2align 2,0x90 \n\
203 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
204" __XSTRING(CNAME(probetrap)) ": \n\
205 ss \n\
206 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
207 fnclex \n\
208 iret \n\
209");
210#endif /* SMP */
211
212/*
213 * Identify routine. Create a connection point on our parent for probing.
214 */
215static void
a02705a9 216npx_identify(driver_t *driver, device_t parent)
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217{
218 device_t child;
219
220 child = BUS_ADD_CHILD(parent, 0, "npx", 0);
221 if (child == NULL)
222 panic("npx_identify");
223}
224
225/*
226 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
227 * whether the device exists or not (XXX should be elsewhere). Set flags
228 * to tell npxattach() what to do. Modify device struct if npx doesn't
229 * need to use interrupts. Return 1 if device exists.
230 */
231static int
a02705a9 232npx_probe(device_t dev)
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233{
234#ifdef SMP
235
236 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
237 npx_irq = 13;
238 return npx_probe1(dev);
239
240#else /* SMP */
241
242 int result;
243 u_long save_eflags;
244 u_char save_icu1_mask;
245 u_char save_icu2_mask;
246 struct gate_descriptor save_idt_npxintr;
247 struct gate_descriptor save_idt_npxtrap;
248 /*
249 * This routine is now just a wrapper for npxprobe1(), to install
250 * special npx interrupt and trap handlers, to enable npx interrupts
251 * and to disable other interrupts. Someday isa_configure() will
252 * install suitable handlers and run with interrupts enabled so we
253 * won't need to do so much here.
254 */
255 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
256 npx_irq = 13;
257 npx_intrno = NRSVIDT + npx_irq;
258 save_eflags = read_eflags();
8a8d5d85 259 cpu_disable_intr();
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260 save_icu1_mask = inb(IO_ICU1 + 1);
261 save_icu2_mask = inb(IO_ICU2 + 1);
262 save_idt_npxintr = idt[npx_intrno];
263 save_idt_npxtrap = idt[16];
264 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
265 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
266 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
267 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
268 npx_idt_probeintr = idt[npx_intrno];
8a8d5d85 269 cpu_enable_intr();
984263bc 270 result = npx_probe1(dev);
8a8d5d85 271 cpu_disable_intr();
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272 outb(IO_ICU1 + 1, save_icu1_mask);
273 outb(IO_ICU2 + 1, save_icu2_mask);
274 idt[npx_intrno] = save_idt_npxintr;
275 idt[16] = save_idt_npxtrap;
276 write_eflags(save_eflags);
277 return (result);
278
279#endif /* SMP */
280}
281
282static int
a02705a9 283npx_probe1(device_t dev)
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284{
285#ifndef SMP
286 u_short control;
287 u_short status;
288#endif
289
290 /*
291 * Partially reset the coprocessor, if any. Some BIOS's don't reset
292 * it after a warm boot.
293 */
294 outb(0xf1, 0); /* full reset on some systems, NOP on others */
295 outb(0xf0, 0); /* clear BUSY# latch */
296 /*
297 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
298 * instructions. We must set the CR0_MP bit and use the CR0_TS
299 * bit to control the trap, because setting the CR0_EM bit does
300 * not cause WAIT instructions to trap. It's important to trap
301 * WAIT instructions - otherwise the "wait" variants of no-wait
302 * control instructions would degenerate to the "no-wait" variants
303 * after FP context switches but work correctly otherwise. It's
304 * particularly important to trap WAITs when there is no NPX -
305 * otherwise the "wait" variants would always degenerate.
306 *
307 * Try setting CR0_NE to get correct error reporting on 486DX's.
308 * Setting it should fail or do nothing on lesser processors.
309 */
310 load_cr0(rcr0() | CR0_MP | CR0_NE);
311 /*
312 * But don't trap while we're probing.
313 */
314 stop_emulating();
315 /*
316 * Finish resetting the coprocessor, if any. If there is an error
317 * pending, then we may get a bogus IRQ13, but probeintr() will handle
318 * it OK. Bogus halts have never been observed, but we enabled
319 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
320 */
321 fninit();
322
323#ifdef SMP
324 /*
325 * Exception 16 MUST work for SMP.
326 */
327 npx_irq13 = 0;
328 npx_ex16 = hw_float = npx_exists = 1;
329 device_set_desc(dev, "math processor");
330 return (0);
331
332#else /* !SMP */
333 device_set_desc(dev, "math processor");
334
335 /*
336 * Don't use fwait here because it might hang.
337 * Don't use fnop here because it usually hangs if there is no FPU.
338 */
339 DELAY(1000); /* wait for any IRQ13 */
340#ifdef DIAGNOSTIC
341 if (npx_intrs_while_probing != 0)
342 printf("fninit caused %u bogus npx interrupt(s)\n",
343 npx_intrs_while_probing);
344 if (npx_traps_while_probing != 0)
345 printf("fninit caused %u bogus npx trap(s)\n",
346 npx_traps_while_probing);
347#endif
348 /*
349 * Check for a status of mostly zero.
350 */
351 status = 0x5a5a;
352 fnstsw(&status);
353 if ((status & 0xb8ff) == 0) {
354 /*
355 * Good, now check for a proper control word.
356 */
357 control = 0x5a5a;
358 fnstcw(&control);
359 if ((control & 0x1f3f) == 0x033f) {
360 hw_float = npx_exists = 1;
361 /*
362 * We have an npx, now divide by 0 to see if exception
363 * 16 works.
364 */
365 control &= ~(1 << 2); /* enable divide by 0 trap */
366 fldcw(&control);
367 npx_traps_while_probing = npx_intrs_while_probing = 0;
368 fp_divide_by_0();
369 if (npx_traps_while_probing != 0) {
370 /*
371 * Good, exception 16 works.
372 */
373 npx_ex16 = 1;
374 return (0);
375 }
376 if (npx_intrs_while_probing != 0) {
377 int rid;
378 struct resource *r;
379 void *intr;
380 /*
381 * Bad, we are stuck with IRQ13.
382 */
383 npx_irq13 = 1;
384 /*
385 * npxattach would be too late to set npx0_imask
386 */
387 npx0_imask |= (1 << npx_irq);
388
389 /*
390 * We allocate these resources permanently,
391 * so there is no need to keep track of them.
392 */
393 rid = 0;
394 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
395 &rid, IO_NPX, IO_NPX,
396 IO_NPXSIZE, RF_ACTIVE);
397 if (r == 0)
398 panic("npx: can't get ports");
399 rid = 0;
400 r = bus_alloc_resource(dev, SYS_RES_IRQ,
401 &rid, npx_irq, npx_irq,
402 1, RF_ACTIVE);
403 if (r == 0)
404 panic("npx: can't get IRQ");
405 BUS_SETUP_INTR(device_get_parent(dev),
406 dev, r, INTR_TYPE_MISC,
e9cb6d99 407 npx_intr, 0, &intr, NULL);
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408 if (intr == 0)
409 panic("npx: can't create intr");
410
411 return (0);
412 }
413 /*
414 * Worse, even IRQ13 is broken. Use emulator.
415 */
416 }
417 }
418 /*
419 * Probe failed, but we want to get to npxattach to initialize the
420 * emulator and say that it has been installed. XXX handle devices
421 * that aren't really devices better.
422 */
423 return (0);
424#endif /* SMP */
425}
426
427/*
428 * Attach routine - announce which it is, and wire into system
429 */
430int
a02705a9 431npx_attach(device_t dev)
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432{
433 int flags;
434
435 if (resource_int_value("npx", 0, "flags", &flags) != 0)
436 flags = 0;
437
438 if (flags)
439 device_printf(dev, "flags 0x%x ", flags);
440 if (npx_irq13) {
441 device_printf(dev, "using IRQ 13 interface\n");
442 } else {
6f535fd5 443#if defined(MATH_EMULATE)
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444 if (npx_ex16) {
445 if (!(flags & NPX_PREFER_EMULATOR))
446 device_printf(dev, "INT 16 interface\n");
447 else {
448 device_printf(dev, "FPU exists, but flags request "
449 "emulator\n");
450 hw_float = npx_exists = 0;
451 }
452 } else if (npx_exists) {
453 device_printf(dev, "error reporting broken; using 387 emulator\n");
454 hw_float = npx_exists = 0;
455 } else
456 device_printf(dev, "387 emulator\n");
457#else
458 if (npx_ex16) {
459 device_printf(dev, "INT 16 interface\n");
460 if (flags & NPX_PREFER_EMULATOR) {
461 device_printf(dev, "emulator requested, but none compiled "
462 "into kernel, using FPU\n");
463 }
464 } else
465 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
466#endif
467 }
468 npxinit(__INITIAL_NPXCW__);
469
bd331ffe 470#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
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471 /*
472 * The asm_mmx_*() routines actually use XMM as well, so only
473 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
474 */
475 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
476 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
477 (cpu_feature & CPUID_SSE2) &&
478 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
479 ) {
480 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
481 bcopy_vector = (void **)asm_xmm_bcopy;
482 ovbcopy_vector = (void **)asm_xmm_bcopy;
483 memcpy_vector = (void **)asm_xmm_memcpy;
484 printf("Using XMM optimized bcopy/copyin/copyout\n");
485 }
486 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
487 /* XXX */
488 }
489 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
490 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
491 ) {
492 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
493 bcopy_vector = (void **)asm_mmx_bcopy;
494 ovbcopy_vector = (void **)asm_mmx_bcopy;
495 memcpy_vector = (void **)asm_mmx_memcpy;
496 printf("Using MMX optimized bcopy/copyin/copyout\n");
497 }
498 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
499 /* XXX */
500 }
501 }
502#endif
503#if 0
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504 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
505 timezero("i586_bzero()", i586_bzero) <
506 timezero("bzero()", bzero) * 4 / 5) {
507 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
508 bcopy_vector = i586_bcopy;
509 ovbcopy_vector = i586_bcopy;
510 }
511 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
512 bzero = i586_bzero;
513 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
514 copyin_vector = i586_copyin;
515 copyout_vector = i586_copyout;
516 }
517 }
518#endif
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519 return (0); /* XXX unused */
520}
521
522/*
a02705a9 523 * Initialize the floating point unit.
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524 */
525void
a02705a9 526npxinit(u_short control)
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527{
528 static union savefpu dummy;
529
530 if (!npx_exists)
531 return;
532 /*
533 * fninit has the same h/w bugs as fnsave. Use the detoxified
534 * fnsave to throw away any junk in the fpu. npxsave() initializes
af0bff84 535 * the fpu and sets npxthread = NULL as important side effects.
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536 */
537 npxsave(&dummy);
a02705a9 538 crit_enter();
984263bc 539 stop_emulating();
984263bc 540 fldcw(&control);
65d6ce10 541 fpusave(curthread->td_savefpu);
a02705a9 542 mdcpu->gd_npxthread = NULL;
984263bc 543 start_emulating();
a02705a9 544 crit_exit();
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545}
546
547/*
548 * Free coprocessor (if we have it).
549 */
550void
85100692 551npxexit(struct proc *p)
984263bc 552{
a2a5ad0d 553 if (p->p_thread == mdcpu->gd_npxthread)
65d6ce10 554 npxsave(curthread->td_savefpu);
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555#ifdef NPX_DEBUG
556 if (npx_exists) {
557 u_int masked_exceptions;
558
b7c628e4 559 masked_exceptions =
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560 curthread->td_savefpu->sv_87.sv_env.en_cw
561 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
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562 /*
563 * Log exceptions that would have trapped with the old
564 * control word (overflow, divide by 0, and invalid operand).
565 */
566 if (masked_exceptions & 0x0d)
567 log(LOG_ERR,
568 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
569 p->p_pid, p->p_comm, masked_exceptions);
570 }
571#endif
572}
573
574/*
575 * The following mechanism is used to ensure that the FPE_... value
576 * that is passed as a trapcode to the signal handler of the user
577 * process does not have more than one bit set.
578 *
579 * Multiple bits may be set if the user process modifies the control
580 * word while a status word bit is already set. While this is a sign
581 * of bad coding, we have no choise than to narrow them down to one
582 * bit, since we must not send a trapcode that is not exactly one of
583 * the FPE_ macros.
584 *
585 * The mechanism has a static table with 127 entries. Each combination
586 * of the 7 FPU status word exception bits directly translates to a
587 * position in this table, where a single FPE_... value is stored.
588 * This FPE_... value stored there is considered the "most important"
589 * of the exception bits and will be sent as the signal code. The
590 * precedence of the bits is based upon Intel Document "Numerical
591 * Applications", Chapter "Special Computational Situations".
592 *
593 * The macro to choose one of these values does these steps: 1) Throw
594 * away status word bits that cannot be masked. 2) Throw away the bits
595 * currently masked in the control word, assuming the user isn't
596 * interested in them anymore. 3) Reinsert status word bit 7 (stack
597 * fault) if it is set, which cannot be masked but must be presered.
598 * 4) Use the remaining bits to point into the trapcode table.
599 *
600 * The 6 maskable bits in order of their preference, as stated in the
601 * above referenced Intel manual:
602 * 1 Invalid operation (FP_X_INV)
603 * 1a Stack underflow
604 * 1b Stack overflow
605 * 1c Operand of unsupported format
606 * 1d SNaN operand.
607 * 2 QNaN operand (not an exception, irrelavant here)
608 * 3 Any other invalid-operation not mentioned above or zero divide
609 * (FP_X_INV, FP_X_DZ)
610 * 4 Denormal operand (FP_X_DNML)
611 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
612 * 6 Inexact result (FP_X_IMP)
613 */
614static char fpetable[128] = {
615 0,
616 FPE_FLTINV, /* 1 - INV */
617 FPE_FLTUND, /* 2 - DNML */
618 FPE_FLTINV, /* 3 - INV | DNML */
619 FPE_FLTDIV, /* 4 - DZ */
620 FPE_FLTINV, /* 5 - INV | DZ */
621 FPE_FLTDIV, /* 6 - DNML | DZ */
622 FPE_FLTINV, /* 7 - INV | DNML | DZ */
623 FPE_FLTOVF, /* 8 - OFL */
624 FPE_FLTINV, /* 9 - INV | OFL */
625 FPE_FLTUND, /* A - DNML | OFL */
626 FPE_FLTINV, /* B - INV | DNML | OFL */
627 FPE_FLTDIV, /* C - DZ | OFL */
628 FPE_FLTINV, /* D - INV | DZ | OFL */
629 FPE_FLTDIV, /* E - DNML | DZ | OFL */
630 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
631 FPE_FLTUND, /* 10 - UFL */
632 FPE_FLTINV, /* 11 - INV | UFL */
633 FPE_FLTUND, /* 12 - DNML | UFL */
634 FPE_FLTINV, /* 13 - INV | DNML | UFL */
635 FPE_FLTDIV, /* 14 - DZ | UFL */
636 FPE_FLTINV, /* 15 - INV | DZ | UFL */
637 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
638 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
639 FPE_FLTOVF, /* 18 - OFL | UFL */
640 FPE_FLTINV, /* 19 - INV | OFL | UFL */
641 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
642 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
643 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
644 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
645 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
646 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
647 FPE_FLTRES, /* 20 - IMP */
648 FPE_FLTINV, /* 21 - INV | IMP */
649 FPE_FLTUND, /* 22 - DNML | IMP */
650 FPE_FLTINV, /* 23 - INV | DNML | IMP */
651 FPE_FLTDIV, /* 24 - DZ | IMP */
652 FPE_FLTINV, /* 25 - INV | DZ | IMP */
653 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
654 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
655 FPE_FLTOVF, /* 28 - OFL | IMP */
656 FPE_FLTINV, /* 29 - INV | OFL | IMP */
657 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
658 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
659 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
660 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
661 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
662 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
663 FPE_FLTUND, /* 30 - UFL | IMP */
664 FPE_FLTINV, /* 31 - INV | UFL | IMP */
665 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
666 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
667 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
668 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
669 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
670 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
671 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
672 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
673 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
674 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
675 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
676 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
677 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
678 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
679 FPE_FLTSUB, /* 40 - STK */
680 FPE_FLTSUB, /* 41 - INV | STK */
681 FPE_FLTUND, /* 42 - DNML | STK */
682 FPE_FLTSUB, /* 43 - INV | DNML | STK */
683 FPE_FLTDIV, /* 44 - DZ | STK */
684 FPE_FLTSUB, /* 45 - INV | DZ | STK */
685 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
686 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
687 FPE_FLTOVF, /* 48 - OFL | STK */
688 FPE_FLTSUB, /* 49 - INV | OFL | STK */
689 FPE_FLTUND, /* 4A - DNML | OFL | STK */
690 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
691 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
692 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
693 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
694 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
695 FPE_FLTUND, /* 50 - UFL | STK */
696 FPE_FLTSUB, /* 51 - INV | UFL | STK */
697 FPE_FLTUND, /* 52 - DNML | UFL | STK */
698 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
699 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
700 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
701 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
702 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
703 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
704 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
705 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
706 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
707 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
708 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
709 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
710 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
711 FPE_FLTRES, /* 60 - IMP | STK */
712 FPE_FLTSUB, /* 61 - INV | IMP | STK */
713 FPE_FLTUND, /* 62 - DNML | IMP | STK */
714 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
715 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
716 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
717 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
718 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
719 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
720 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
721 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
722 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
723 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
724 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
725 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
726 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
727 FPE_FLTUND, /* 70 - UFL | IMP | STK */
728 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
729 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
730 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
731 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
732 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
733 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
734 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
735 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
736 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
737 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
738 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
739 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
740 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
741 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
742 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
743};
744
745/*
746 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
747 *
748 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
749 * depend on longjmp() restoring a usable state. Restoring the state
750 * or examining it might fail if we didn't clear exceptions.
751 *
752 * The error code chosen will be one of the FPE_... macros. It will be
753 * sent as the second argument to old BSD-style signal handlers and as
754 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
755 *
756 * XXX the FP state is not preserved across signal handlers. So signal
757 * handlers cannot afford to do FP unless they preserve the state or
758 * longjmp() out. Both preserving the state and longjmp()ing may be
759 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
760 * solution for signals other than SIGFPE.
8a8d5d85
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761 *
762 * The MP lock is not held on entry (see i386/i386/exception.s) and
763 * should not be held on exit.
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764 */
765void
a02705a9 766npx_intr(void *dummy)
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767{
768 int code;
769 u_short control;
770 struct intrframe *frame;
771 u_long *exstat;
772
a2a5ad0d 773 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
8a8d5d85 774 get_mplock();
af0bff84 775 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 776 mdcpu->gd_npxthread, curthread, npx_exists);
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777 panic("npxintr from nowhere");
778 }
a2a5ad0d 779 if (mdcpu->gd_npxthread != curthread) {
8a8d5d85 780 get_mplock();
af0bff84 781 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 782 mdcpu->gd_npxthread, curthread, npx_exists);
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783 panic("npxintr from non-current process");
784 }
785
65d6ce10 786 exstat = GET_FPU_EXSW_PTR(curthread);
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787 outb(0xf0, 0);
788 fnstsw(exstat);
789 fnstcw(&control);
790 fnclex();
791
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792 get_mplock();
793
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794 /*
795 * Pass exception to process.
796 */
797 frame = (struct intrframe *)&dummy; /* XXX */
798 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
799 /*
800 * Interrupt is essentially a trap, so we can afford to call
801 * the SIGFPE handler (if any) as soon as the interrupt
802 * returns.
803 *
804 * XXX little or nothing is gained from this, and plenty is
805 * lost - the interrupt frame has to contain the trap frame
806 * (this is otherwise only necessary for the rescheduling trap
807 * in doreti, and the frame for that could easily be set up
808 * just before it is used).
809 */
810 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
811 /*
812 * Encode the appropriate code for detailed information on
813 * this exception.
814 */
815 code =
816 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
817 trapsignal(curproc, SIGFPE, code);
818 } else {
819 /*
820 * Nested interrupt. These losers occur when:
821 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
822 * o immediately after an fnsave or frstor of an
823 * error state.
824 * o a couple of 386 instructions after
825 * "fstpl _memvar" causes a stack overflow.
826 * These are especially nasty when combined with a
827 * trace trap.
828 * o an IRQ13 occurs at the same time as another higher-
829 * priority interrupt.
830 *
831 * Treat them like a true async interrupt.
832 */
833 psignal(curproc, SIGFPE);
834 }
8a8d5d85 835 rel_mplock();
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836}
837
838/*
a02705a9
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839 * Implement the device not available (DNA) exception. gd_npxthread had
840 * better be NULL. Restore the current thread's FP state and set gd_npxthread
841 * to curthread.
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842 */
843int
a02705a9 844npxdna(void)
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845{
846 u_long *exstat;
847
848 if (!npx_exists)
849 return (0);
a2a5ad0d 850 if (mdcpu->gd_npxthread != NULL) {
af0bff84 851 printf("npxdna: npxthread = %p, curthread = %p\n",
a2a5ad0d 852 mdcpu->gd_npxthread, curthread);
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853 panic("npxdna");
854 }
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855 /*
856 * The setting of gd_npxthread and the call to fpurstor() must not
857 * be preempted by an interrupt thread or we will take an npxdna
858 * trap and potentially save our current fpstate (which is garbage)
859 * and then restore the garbage rather then the originally saved
860 * fpstate.
861 */
bd331ffe 862 crit_enter();
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863 stop_emulating();
864 /*
865 * Record new context early in case frstor causes an IRQ13.
866 */
a2a5ad0d 867 mdcpu->gd_npxthread = curthread;
65d6ce10 868 exstat = GET_FPU_EXSW_PTR(curthread);
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869 *exstat = 0;
870 /*
871 * The following frstor may cause an IRQ13 when the state being
872 * restored has a pending error. The error will appear to have been
873 * triggered by the current (npx) user instruction even when that
874 * instruction is a no-wait instruction that should not trigger an
875 * error (e.g., fnclex). On at least one 486 system all of the
876 * no-wait instructions are broken the same as frstor, so our
877 * treatment does not amplify the breakage. On at least one
878 * 386/Cyrix 387 system, fnclex works correctly while frstor and
879 * fnsave are broken, so our treatment breaks fnclex if it is the
880 * first FPU instruction after a context switch.
881 */
65d6ce10 882 fpurstor(curthread->td_savefpu);
bd331ffe 883 crit_exit();
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884
885 return (1);
886}
887
888/*
a02705a9 889 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
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890 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
891 * any IRQ13 to be handled immediately, and then ignore it. This routine is
892 * often called at splhigh so it must not use many system services. In
893 * particular, it's much easier to install a special handler than to
894 * guarantee that it's safe to use npxintr() and its supporting code.
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895 *
896 * WARNING! This call is made during a switch and the MP lock will be
897 * setup for the new target thread rather then the current thread, so we
898 * cannot do anything here that depends on the *_mplock() functions as
899 * we may trip over their assertions.
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900 *
901 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
902 * kernel will always assume that the FP state is 'safe' (will not cause
903 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
904 * setup a custom save area before actually using the FP unit, but it will
905 * not bother calling fninit. This greatly improves kernel performance when
906 * it wishes to use the FP unit.
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907 */
908void
a02705a9 909npxsave(union savefpu *addr)
984263bc 910{
642a6e88 911#if defined(SMP) || !defined(CPU_DISABLE_SSE)
984263bc 912
a02705a9 913 crit_enter();
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914 stop_emulating();
915 fpusave(addr);
a2a5ad0d 916 mdcpu->gd_npxthread = NULL;
a02705a9 917 fninit();
369f5065 918 start_emulating();
a02705a9 919 crit_exit();
984263bc 920
369f5065 921#else /* !SMP and CPU_DISABLE_SSE */
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922
923 u_char icu1_mask;
924 u_char icu2_mask;
925 u_char old_icu1_mask;
926 u_char old_icu2_mask;
927 struct gate_descriptor save_idt_npxintr;
8a8d5d85 928 u_long save_eflags;
984263bc 929
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930 save_eflags = read_eflags();
931 cpu_disable_intr();
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932 old_icu1_mask = inb(IO_ICU1 + 1);
933 old_icu2_mask = inb(IO_ICU2 + 1);
934 save_idt_npxintr = idt[npx_intrno];
935 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
936 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
937 idt[npx_intrno] = npx_idt_probeintr;
8a8d5d85 938 cpu_enable_intr();
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939 stop_emulating();
940 fnsave(addr);
941 fnop();
8a8d5d85 942 cpu_disable_intr();
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943 mdcpu->gd_npxthread = NULL;
944 start_emulating();
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945 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
946 icu2_mask = inb(IO_ICU2 + 1);
947 outb(IO_ICU1 + 1,
948 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
949 outb(IO_ICU2 + 1,
950 (icu2_mask & ~(npx0_imask >> 8))
951 | (old_icu2_mask & (npx0_imask >> 8)));
952 idt[npx_intrno] = save_idt_npxintr;
8a8d5d85 953 write_eflags(save_eflags); /* back to usual state */
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954
955#endif /* SMP */
956}
957
958static void
a02705a9 959fpusave(union savefpu *addr)
984263bc 960{
642a6e88 961#ifndef CPU_DISABLE_SSE
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962 if (cpu_fxsr)
963 fxsave(addr);
964 else
965#endif
966 fnsave(addr);
967}
968
969static void
a02705a9 970fpurstor(union savefpu *addr)
984263bc 971{
642a6e88 972#ifndef CPU_DISABLE_SSE
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973 if (cpu_fxsr)
974 fxrstor(addr);
975 else
976#endif
977 frstor(addr);
978}
979
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980static device_method_t npx_methods[] = {
981 /* Device interface */
982 DEVMETHOD(device_identify, npx_identify),
983 DEVMETHOD(device_probe, npx_probe),
984 DEVMETHOD(device_attach, npx_attach),
985 DEVMETHOD(device_detach, bus_generic_detach),
986 DEVMETHOD(device_shutdown, bus_generic_shutdown),
987 DEVMETHOD(device_suspend, bus_generic_suspend),
988 DEVMETHOD(device_resume, bus_generic_resume),
989
990 { 0, 0 }
991};
992
993static driver_t npx_driver = {
994 "npx",
995 npx_methods,
996 1, /* no softc */
997};
998
999static devclass_t npx_devclass;
1000
1001/*
1002 * We prefer to attach to the root nexus so that the usual case (exception 16)
1003 * doesn't describe the processor as being `on isa'.
1004 */
1005DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);