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[dragonfly.git] / sys / dev / atm / en / midway.c
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984263bc
MD		 1/* $NetBSD: midway.c,v 1.30 1997/09/29 17:40:38 chuck Exp $ */
2/* (sync'd to midway.c 1.68) */
3
4/*
5 *
6 * Copyright (c) 1996 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/en/midway.c,v 1.19.2.1 2003/01/23 21:06:42 sam Exp $
38e94a25 36 * $DragonFly: src/sys/dev/atm/en/midway.c,v 1.5 2003/08/27 10:35:15 rob Exp $
984263bc
MD		 37 */
38
39/*
40 *
41 * m i d w a y . c e n i 1 5 5 d r i v e r
42 *
43 * author: Chuck Cranor <chuck@ccrc.wustl.edu>
44 * started: spring, 1996 (written from scratch).
45 *
46 * notes from the author:
47 * Extra special thanks go to Werner Almesberger, EPFL LRC. Werner's
48 * ENI driver was especially useful in figuring out how this card works.
49 * I would also like to thank Werner for promptly answering email and being
50 * generally helpful.
51 */
52
53#undef EN_DEBUG
54#undef EN_DEBUG_RANGE /* check ranges on en_read/en_write's? */
55#define EN_MBUF_OPT /* try and put more stuff in mbuf? */
56#define EN_DIAG
57#define EN_STAT
58#ifndef EN_DMA
59#define EN_DMA 1 /* use dma? */
60#endif
61#define EN_NOTXDMA 0 /* hook to disable tx dma only */
62#define EN_NORXDMA 0 /* hook to disable rx dma only */
63#define EN_DDBHOOK 1 /* compile in ddb functions */
64#if defined(MIDWAY_ADPONLY)
65#define EN_ENIDMAFIX 0 /* no ENI cards to worry about */
66#else
67#define EN_ENIDMAFIX 1 /* avoid byte DMA on the ENI card (see below) */
68#endif
69
70/*
71 * note on EN_ENIDMAFIX: the byte aligner on the ENI version of the card
72 * appears to be broken. it works just fine if there is no load... however
73 * when the card is loaded the data get corrupted. to see this, one only
74 * has to use "telnet" over ATM. do the following command in "telnet":
75 * cat /usr/share/misc/termcap
76 * "telnet" seems to generate lots of 1023 byte mbufs (which make great
77 * use of the byte aligner). watch "netstat -s" for checksum errors.
78 *
79 * I further tested this by adding a function that compared the transmit
80 * data on the card's SRAM with the data in the mbuf chain _after_ the
81 * "transmit DMA complete" interrupt. using the "telnet" test I got data
82 * mismatches where the byte-aligned data should have been. using ddb
83 * and en_dumpmem() I verified that the DTQs fed into the card were
84 * absolutely correct. thus, we are forced to concluded that the ENI
85 * hardware is buggy. note that the Adaptec version of the card works
86 * just fine with byte DMA.
87 *
88 * bottom line: we set EN_ENIDMAFIX to 1 to avoid byte DMAs on the ENI
89 * card.
90 */
91
92#if defined(DIAGNOSTIC) && !defined(EN_DIAG)
93#define EN_DIAG /* link in with master DIAG option */
94#endif
95#ifdef EN_STAT
96#define EN_COUNT(X) (X)++
97#else
98#define EN_COUNT(X) /* nothing */
99#endif
100
101#ifdef EN_DEBUG
102#undef EN_DDBHOOK
103#define EN_DDBHOOK 1
104#define STATIC /* nothing */
105#define INLINE /* nothing */
106#else /* EN_DEBUG */
107#define STATIC static
108#define INLINE __inline
109#endif /* EN_DEBUG */
110
111#ifdef __FreeBSD__
1f2de5d4 112#include "use_en.h" /* XXX for midwayvar.h's NEN */
984263bc
MD		 113#include "opt_inet.h"
114#include "opt_natm.h"
115#include "opt_ddb.h"
116/* enable DDBHOOK when DDB is available */
117#undef EN_DDBHOOK
118#ifdef DDB
119#define EN_DDBHOOK 1
120#endif
121#endif
122
123#include <sys/param.h>
124#include <sys/systm.h>
125#include <sys/queue.h>
126#if defined(__NetBSD__) || defined(__OpenBSD__) || defined(__bsdi__)
127#include <sys/device.h>
128#endif
129#include <sys/sockio.h>
130#include <sys/mbuf.h>
131#include <sys/socket.h>
132#include <sys/proc.h>
133
134#include <net/if.h>
135#include <net/if_atm.h>
136
137#include <vm/vm.h>
138
139#if defined(INET) || defined(INET6)
140#include <netinet/in.h>
141#include <netinet/if_atm.h>
142#endif
143
144#ifdef NATM
d2438d69 145#include <netproto/natm/natm.h>
984263bc
MD		 146#endif
147
148#if !defined(sparc) && !defined(__FreeBSD__)
149#include <machine/bus.h>
150#endif
151
152#if defined(__NetBSD__) || defined(__OpenBSD__)
153#include <dev/ic/midwayreg.h>
154#include <dev/ic/midwayvar.h>
155#if defined(__alpha__)
156/* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
157#undef vtophys
158#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
159#endif
160#elif defined(__FreeBSD__)
161#include <machine/clock.h> /* for DELAY */
1f2de5d4
MD		 162#include "midwayreg.h"
163#include "midwayvar.h"
984263bc
MD		 164#include <vm/pmap.h> /* for vtophys proto */
165
166#ifndef IFF_NOTRAILERS
167#define IFF_NOTRAILERS 0
168#endif
169
170#endif /* __FreeBSD__ */
171
1f2de5d4 172#include "use_bpf.h"
984263bc
MD		 173#if NBPF > 0
174#include <net/bpf.h>
175#ifdef __FreeBSD__
176#define BPFATTACH(ifp, dlt, hlen) bpfattach((ifp), (dlt), (hlen))
177#define BPF_MTAP(ifp, m) bpf_mtap((ifp), (m))
178#else
179#define BPFATTACH(ifp, dlt, hlen) bpfattach(&(ifp)->if_bpf, (ifp), (dlt), (hlen))
180#define BPF_MTAP(ifp, m) bpf_mtap((ifp)->if_bpf, (m))
181#endif
182#endif /* NBPF > 0 */
183
184/*
185 * params
186 */
187
188#ifndef EN_TXHIWAT
189#define EN_TXHIWAT (64*1024) /* max 64 KB waiting to be DMAd out */
190#endif
191
192#ifndef EN_MINDMA
193#define EN_MINDMA 32 /* don't DMA anything less than this (bytes) */
194#endif
195
196#define RX_NONE 0xffff /* recv VC not in use */
197
198#define EN_OBHDR ATM_PH_DRIVER7 /* TBD in first mbuf ! */
199#define EN_OBTRL ATM_PH_DRIVER8 /* PDU trailier in last mbuf ! */
200
201#define ENOTHER_FREE 0x01 /* free rxslot */
202#define ENOTHER_DRAIN 0x02 /* almost free (drain DRQ dma) */
203#define ENOTHER_RAW 0x04 /* 'raw' access (aka boodi mode) */
204#define ENOTHER_SWSL 0x08 /* in software service list */
205
206static int en_dma = EN_DMA; /* use DMA (switch off for dbg) */
207
208/*
209 * autoconfig attachments
210 */
211
212struct cfdriver en_cd = {
213 0, "en", DV_IFNET,
214};
215
216/*
217 * local structures
218 */
219
220/*
221 * params to en_txlaunch() function
222 */
223
224struct en_launch {
225 u_int32_t tbd1; /* TBD 1 */
226 u_int32_t tbd2; /* TBD 2 */
227 u_int32_t pdu1; /* PDU 1 (aal5) */
228 int nodma; /* don't use DMA */
229 int need; /* total space we need (pad out if less data) */
230 int mlen; /* length of mbuf (for dtq) */
231 struct mbuf *t; /* data */
232 u_int32_t aal; /* aal code */
233 u_int32_t atm_vci; /* vci */
234 u_int8_t atm_flags; /* flags */
235};
236
237
238/*
239 * dma table (index by # of words)
240 *
241 * plan A: use WMAYBE (obsolete)
242 * plan B: avoid WMAYBE
243 */
244
245struct en_dmatab {
246 u_int8_t bcode; /* code */
247 u_int8_t divshift; /* byte divisor */
248};
249
250static struct en_dmatab en_dma_planB[] = {
251 { 0, 0 }, /* 0 */ { MIDDMA_WORD, 2}, /* 1 */
252 { MIDDMA_2WORD, 3}, /* 2 */ { MIDDMA_WORD, 2}, /* 3 */
253 { MIDDMA_4WORD, 4}, /* 4 */ { MIDDMA_WORD, 2}, /* 5 */
254 { MIDDMA_2WORD, 3}, /* 6 */ { MIDDMA_WORD, 2}, /* 7 */
255 { MIDDMA_8WORD, 5}, /* 8 */ { MIDDMA_WORD, 2}, /* 9 */
256 { MIDDMA_2WORD, 3}, /* 10 */ { MIDDMA_WORD, 2}, /* 11 */
257 { MIDDMA_4WORD, 4}, /* 12 */ { MIDDMA_WORD, 2}, /* 13 */
258 { MIDDMA_2WORD, 3}, /* 14 */ { MIDDMA_WORD, 2}, /* 15 */
259 { MIDDMA_16WORD, 6}, /* 16 */
260};
261
262static struct en_dmatab *en_dmaplan = en_dma_planB;
263
264/*
265 * prototypes
266 */
267
38e94a25 268STATIC INLINE int en_b2sz (int) __attribute__ ((unused));
984263bc 269#ifdef EN_DDBHOOK
38e94a25
RG		 270 int en_dump (int,int);
271 int en_dumpmem (int,int,int);
984263bc 272#endif
38e94a25
RG		 273STATIC void en_dmaprobe (struct en_softc *);
274STATIC int en_dmaprobe_doit (struct en_softc *, u_int8_t *,
275 u_int8_t *, int);
276STATIC INLINE int en_dqneed (struct en_softc *, caddr_t, u_int,
277 u_int) __attribute__ ((unused));
278STATIC void en_init (struct en_softc *);
279STATIC int en_ioctl (struct ifnet *, EN_IOCTL_CMDT, caddr_t);
280STATIC INLINE int en_k2sz (int) __attribute__ ((unused));
281STATIC void en_loadvc (struct en_softc *, int);
282STATIC int en_mfix (struct en_softc *, struct mbuf **,
283 struct mbuf *);
284STATIC INLINE struct mbuf *en_mget (struct en_softc *, u_int,
285 u_int *) __attribute__ ((unused));
286STATIC INLINE u_int32_t en_read (struct en_softc *,
287 u_int32_t) __attribute__ ((unused));
288STATIC int en_rxctl (struct en_softc *, struct atm_pseudoioctl *,
289 int);
290STATIC void en_txdma (struct en_softc *, int);
291STATIC void en_txlaunch (struct en_softc *, int,
292 struct en_launch *);
293STATIC void en_service (struct en_softc *);
294STATIC void en_start (struct ifnet *);
295STATIC INLINE int en_sz2b (int) __attribute__ ((unused));
296STATIC INLINE void en_write (struct en_softc *, u_int32_t,
297 u_int32_t) __attribute__ ((unused));
984263bc
MD		 298
299/*
300 * macros/inline
301 */
302
303/*
304 * raw read/write macros
305 */
306
307#define EN_READDAT(SC,R) en_read(SC,R)
308#define EN_WRITEDAT(SC,R,V) en_write(SC,R,V)
309
310/*
311 * cooked read/write macros
312 */
313
314#define EN_READ(SC,R) ntohl(en_read(SC,R))
315#define EN_WRITE(SC,R,V) en_write(SC,R, htonl(V))
316
317#define EN_WRAPADD(START,STOP,CUR,VAL) { \
318 (CUR) = (CUR) + (VAL); \
319 if ((CUR) >= (STOP)) \
320 (CUR) = (START) + ((CUR) - (STOP)); \
321 }
322
323#define WORD_IDX(START, X) (((X) - (START)) / sizeof(u_int32_t))
324
325/* we store sc->dtq and sc->drq data in the following format... */
326#define EN_DQ_MK(SLOT,LEN) (((SLOT) << 20)|(LEN)|(0x80000))
327 /* the 0x80000 ensures we != 0 */
328#define EN_DQ_SLOT(X) ((X) >> 20)
329#define EN_DQ_LEN(X) ((X) & 0x3ffff)
330
331/* format of DTQ/DRQ word 1 differs between ENI and ADP */
332#if defined(MIDWAY_ENIONLY)
333
334#define MID_MK_TXQ(SC,CNT,CHAN,END,BCODE) \
335 EN_WRITE((SC), (SC)->dtq_us, \
336 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (BCODE)));
337
338#define MID_MK_RXQ(SC,CNT,VCI,END,BCODE) \
339 EN_WRITE((SC), (SC)->drq_us, \
340 MID_MK_RXQ_ENI((CNT), (VCI), (END), (BCODE)));
341
342#elif defined(MIDWAY_ADPONLY)
343
344#define MID_MK_TXQ(SC,CNT,CHAN,END,JK) \
345 EN_WRITE((SC), (SC)->dtq_us, \
346 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK)));
347
348#define MID_MK_RXQ(SC,CNT,VCI,END,JK) \
349 EN_WRITE((SC), (SC)->drq_us, \
350 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK)));
351
352#else
353
354#define MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE) { \
355 if ((SC)->is_adaptec) \
356 EN_WRITE((SC), (SC)->dtq_us, \
357 MID_MK_TXQ_ADP((CNT), (CHAN), (END), (JK_OR_BCODE))); \
358 else \
359 EN_WRITE((SC), (SC)->dtq_us, \
360 MID_MK_TXQ_ENI((CNT), (CHAN), (END), (JK_OR_BCODE))); \
361 }
362
363#define MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE) { \
364 if ((SC)->is_adaptec) \
365 EN_WRITE((SC), (SC)->drq_us, \
366 MID_MK_RXQ_ADP((CNT), (VCI), (END), (JK_OR_BCODE))); \
367 else \
368 EN_WRITE((SC), (SC)->drq_us, \
369 MID_MK_RXQ_ENI((CNT), (VCI), (END), (JK_OR_BCODE))); \
370 }
371
372#endif
373
374/* add an item to the DTQ */
375#define EN_DTQADD(SC,CNT,CHAN,JK_OR_BCODE,ADDR,LEN,END) { \
376 if (END) \
377 (SC)->dtq[MID_DTQ_A2REG((SC)->dtq_us)] = EN_DQ_MK(CHAN,LEN); \
378 MID_MK_TXQ(SC,CNT,CHAN,END,JK_OR_BCODE); \
379 (SC)->dtq_us += 4; \
380 EN_WRITE((SC), (SC)->dtq_us, (ADDR)); \
381 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, (SC)->dtq_us, 4); \
382 (SC)->dtq_free--; \
383 if (END) \
384 EN_WRITE((SC), MID_DMA_WRTX, MID_DTQ_A2REG((SC)->dtq_us)); \
385}
386
387/* DRQ add macro */
388#define EN_DRQADD(SC,CNT,VCI,JK_OR_BCODE,ADDR,LEN,SLOT,END) { \
389 if (END) \
390 (SC)->drq[MID_DRQ_A2REG((SC)->drq_us)] = EN_DQ_MK(SLOT,LEN); \
391 MID_MK_RXQ(SC,CNT,VCI,END,JK_OR_BCODE); \
392 (SC)->drq_us += 4; \
393 EN_WRITE((SC), (SC)->drq_us, (ADDR)); \
394 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, (SC)->drq_us, 4); \
395 (SC)->drq_free--; \
396 if (END) \
397 EN_WRITE((SC), MID_DMA_WRRX, MID_DRQ_A2REG((SC)->drq_us)); \
398}
399
400/*
401 * the driver code
402 *
403 * the code is arranged in a specific way:
404 * [1] short/inline functions
405 * [2] autoconfig stuff
406 * [3] ioctl stuff
407 * [4] reset -> init -> trasmit -> intr -> receive functions
408 *
409 */
410
411/***********************************************************************/
412
413/*
414 * en_read: read a word from the card. this is the only function
415 * that reads from the card.
416 */
417
418STATIC INLINE u_int32_t en_read(sc, r)
419
420struct en_softc *sc;
421u_int32_t r;
422
423{
424
425#ifdef EN_DEBUG_RANGE
426 if (r > MID_MAXOFF || (r % 4))
427 panic("en_read out of range, r=0x%x", r);
428#endif
429
430 return(bus_space_read_4(sc->en_memt, sc->en_base, r));
431}
432
433/*
434 * en_write: write a word to the card. this is the only function that
435 * writes to the card.
436 */
437
438STATIC INLINE void en_write(sc, r, v)
439
440struct en_softc *sc;
441u_int32_t r, v;
442
443{
444#ifdef EN_DEBUG_RANGE
445 if (r > MID_MAXOFF || (r % 4))
446 panic("en_write out of range, r=0x%x", r);
447#endif
448
449 bus_space_write_4(sc->en_memt, sc->en_base, r, v);
450}
451
452/*
453 * en_k2sz: convert KBytes to a size parameter (a log2)
454 */
455
456STATIC INLINE int en_k2sz(k)
457
458int k;
459
460{
461 switch(k) {
462 case 1: return(0);
463 case 2: return(1);
464 case 4: return(2);
465 case 8: return(3);
466 case 16: return(4);
467 case 32: return(5);
468 case 64: return(6);
469 case 128: return(7);
470 default: panic("en_k2sz");
471 }
472 return(0);
473}
474#define en_log2(X) en_k2sz(X)
475
476
477/*
478 * en_b2sz: convert a DMA burst code to its byte size
479 */
480
481STATIC INLINE int en_b2sz(b)
482
483int b;
484
485{
486 switch (b) {
487 case MIDDMA_WORD: return(1*4);
488 case MIDDMA_2WMAYBE:
489 case MIDDMA_2WORD: return(2*4);
490 case MIDDMA_4WMAYBE:
491 case MIDDMA_4WORD: return(4*4);
492 case MIDDMA_8WMAYBE:
493 case MIDDMA_8WORD: return(8*4);
494 case MIDDMA_16WMAYBE:
495 case MIDDMA_16WORD: return(16*4);
496 default: panic("en_b2sz");
497 }
498 return(0);
499}
500
501
502/*
503 * en_sz2b: convert a burst size (bytes) to DMA burst code
504 */
505
506STATIC INLINE int en_sz2b(sz)
507
508int sz;
509
510{
511 switch (sz) {
512 case 1*4: return(MIDDMA_WORD);
513 case 2*4: return(MIDDMA_2WORD);
514 case 4*4: return(MIDDMA_4WORD);
515 case 8*4: return(MIDDMA_8WORD);
516 case 16*4: return(MIDDMA_16WORD);
517 default: panic("en_sz2b");
518 }
519 return(0);
520}
521
522
523/*
524 * en_dqneed: calculate number of DTQ/DRQ's needed for a buffer
525 */
526
527STATIC INLINE int en_dqneed(sc, data, len, tx)
528
529struct en_softc *sc;
530caddr_t data;
531u_int len, tx;
532
533{
534 int result, needalign, sz;
535
536#if !defined(MIDWAY_ENIONLY)
537#if !defined(MIDWAY_ADPONLY)
538 if (sc->is_adaptec)
539#endif /* !MIDWAY_ADPONLY */
540 return(1); /* adaptec can DMA anything in one go */
541#endif
542
543#if !defined(MIDWAY_ADPONLY)
544 result = 0;
545 if (len < EN_MINDMA) {
546 if (!tx) /* XXX: conservative */
547 return(1); /* will copy/DMA_JK */
548 }
549
550 if (tx) { /* byte burst? */
551 needalign = (((uintptr_t) (void *) data) % sizeof(u_int32_t));
552 if (needalign) {
553 result++;
554 sz = min(len, sizeof(u_int32_t) - needalign);
555 len -= sz;
556 data += sz;
557 }
558 }
559
560 if (sc->alburst && len) {
561 needalign = (((uintptr_t) (void *) data) & sc->bestburstmask);
562 if (needalign) {
563 result++; /* alburst */
564 sz = min(len, sc->bestburstlen - needalign);
565 len -= sz;
566 }
567 }
568
569 if (len >= sc->bestburstlen) {
570 sz = len / sc->bestburstlen;
571 sz = sz * sc->bestburstlen;
572 len -= sz;
573 result++; /* best shot */
574 }
575
576 if (len) {
577 result++; /* clean up */
578 if (tx && (len % sizeof(u_int32_t)) != 0)
579 result++; /* byte cleanup */
580 }
581
582 return(result);
583#endif /* !MIDWAY_ADPONLY */
584}
585
586
587/*
588 * en_mget: get an mbuf chain that can hold totlen bytes and return it
589 * (for recv) [based on am7990_get from if_le and ieget from if_ie]
590 * after this call the sum of all the m_len's in the chain will be totlen.
591 */
592
593STATIC INLINE struct mbuf *en_mget(sc, totlen, drqneed)
594
595struct en_softc *sc;
596u_int totlen, *drqneed;
597
598{
599 struct mbuf *m;
600 struct mbuf *top, **mp;
601 *drqneed = 0;
602
603 MGETHDR(m, M_DONTWAIT, MT_DATA);
604 if (m == NULL)
605 return(NULL);
606 m->m_pkthdr.rcvif = &sc->enif;
607 m->m_pkthdr.len = totlen;
608 m->m_len = MHLEN;
609 top = NULL;
610 mp = &top;
611
612 /* if (top != NULL) then we've already got 1 mbuf on the chain */
613 while (totlen > 0) {
614 if (top) {
615 MGET(m, M_DONTWAIT, MT_DATA);
616 if (!m) {
617 m_freem(top);
618 return(NULL); /* out of mbufs */
619 }
620 m->m_len = MLEN;
621 }
622 if (totlen >= MINCLSIZE) {
623 MCLGET(m, M_DONTWAIT);
624 if ((m->m_flags & M_EXT) == 0) {
625 m_free(m);
626 m_freem(top);
627 return(NULL); /* out of mbuf clusters */
628 }
629 m->m_len = MCLBYTES;
630 }
631 m->m_len = min(totlen, m->m_len);
632 totlen -= m->m_len;
633 *mp = m;
634 mp = &m->m_next;
635
636 *drqneed += en_dqneed(sc, m->m_data, m->m_len, 0);
637
638 }
639 return(top);
640}
641
642/***********************************************************************/
643
644/*
645 * autoconfig stuff
646 */
647
648void en_attach(sc)
649
650struct en_softc *sc;
651
652{
653 struct ifnet *ifp = &sc->enif;
654 int sz;
655 u_int32_t reg, lcv, check, ptr, sav, midvloc;
656
657 /*
658 * probe card to determine memory size. the stupid ENI card always
659 * reports to PCI that it needs 4MB of space (2MB regs and 2MB RAM).
660 * if it has less than 2MB RAM the addresses wrap in the RAM address space.
661 * (i.e. on a 512KB card addresses 0x3ffffc, 0x37fffc, and 0x2ffffc
662 * are aliases for 0x27fffc [note that RAM starts at offset 0x200000]).
663 */
664
665 if (sc->en_busreset)
666 sc->en_busreset(sc);
667 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
668 for (lcv = MID_PROBEOFF; lcv <= MID_MAXOFF ; lcv += MID_PROBSIZE) {
669 EN_WRITE(sc, lcv, lcv); /* data[address] = address */
670 for (check = MID_PROBEOFF ; check < lcv ; check += MID_PROBSIZE) {
671 reg = EN_READ(sc, check);
672 if (reg != check) { /* found an alias! */
673 goto done_probe; /* and quit */
674 }
675 }
676 }
677done_probe:
678 lcv -= MID_PROBSIZE; /* take one step back */
679 sc->en_obmemsz = (lcv + 4) - MID_RAMOFF;
680
681 /*
682 * determine the largest DMA burst supported
683 */
684
685 en_dmaprobe(sc);
686
687 /*
688 * "hello world"
689 */
690
691 if (sc->en_busreset)
692 sc->en_busreset(sc);
693 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
694 for (lcv = MID_RAMOFF ; lcv < MID_RAMOFF + sc->en_obmemsz ; lcv += 4)
695 EN_WRITE(sc, lcv, 0); /* zero memory */
696
697 reg = EN_READ(sc, MID_RESID);
698
699 printf("%s: ATM midway v%d, board IDs %d.%d, %s%s%s, %ldKB on-board RAM\n",
700 sc->sc_dev.dv_xname, MID_VER(reg), MID_MID(reg), MID_DID(reg),
701 (MID_IS_SABRE(reg)) ? "sabre controller, " : "",
702 (MID_IS_SUNI(reg)) ? "SUNI" : "Utopia",
703 (!MID_IS_SUNI(reg) && MID_IS_UPIPE(reg)) ? " (pipelined)" : "",
704 (long)(sc->en_obmemsz / 1024));
705
706 if (sc->is_adaptec) {
707 if (sc->bestburstlen == 64 && sc->alburst == 0)
708 printf("%s: passed 64 byte DMA test\n", sc->sc_dev.dv_xname);
709 else
710 printf("%s: FAILED DMA TEST: burst=%d, alburst=%d\n",
711 sc->sc_dev.dv_xname, sc->bestburstlen, sc->alburst);
712 } else {
713 printf("%s: maximum DMA burst length = %d bytes%s\n", sc->sc_dev.dv_xname,
714 sc->bestburstlen, (sc->alburst) ? " (must align)" : "");
715 }
716
717 /*
718 * link into network subsystem and prepare card
719 */
720
721#if defined(__NetBSD__) || defined(__OpenBSD__)
722 bcopy(sc->sc_dev.dv_xname, sc->enif.if_xname, IFNAMSIZ);
723#endif
724 sc->enif.if_softc = sc;
725 ifp->if_flags = IFF_SIMPLEX|IFF_NOTRAILERS;
726 ifp->if_ioctl = en_ioctl;
727 ifp->if_output = atm_output;
728 ifp->if_start = en_start;
729
730 /*
731 * init softc
732 */
733
734 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
735 sc->rxvc2slot[lcv] = RX_NONE;
736 sc->txspeed[lcv] = 0; /* full */
737 sc->txvc2slot[lcv] = 0; /* full speed == slot 0 */
738 }
739
740 sz = sc->en_obmemsz - (MID_BUFOFF - MID_RAMOFF);
741 ptr = sav = MID_BUFOFF;
742 ptr = roundup(ptr, EN_TXSZ * 1024); /* align */
743 sz = sz - (ptr - sav);
744 if (EN_TXSZ*1024 * EN_NTX > sz) {
745 printf("%s: EN_NTX/EN_TXSZ too big\n", sc->sc_dev.dv_xname);
746 return;
747 }
748 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
749 sc->txslot[lcv].mbsize = 0;
750 sc->txslot[lcv].start = ptr;
751 ptr += (EN_TXSZ * 1024);
752 sz -= (EN_TXSZ * 1024);
753 sc->txslot[lcv].stop = ptr;
754 sc->txslot[lcv].nref = 0;
755 bzero(&sc->txslot[lcv].indma, sizeof(sc->txslot[lcv].indma));
756 bzero(&sc->txslot[lcv].q, sizeof(sc->txslot[lcv].q));
757#ifdef EN_DEBUG
758 printf("%s: tx%d: start 0x%x, stop 0x%x\n", sc->sc_dev.dv_xname, lcv,
759 sc->txslot[lcv].start, sc->txslot[lcv].stop);
760#endif
761 }
762
763 sav = ptr;
764 ptr = roundup(ptr, EN_RXSZ * 1024); /* align */
765 sz = sz - (ptr - sav);
766 sc->en_nrx = sz / (EN_RXSZ * 1024);
767 if (sc->en_nrx <= 0) {
768 printf("%s: EN_NTX/EN_TXSZ/EN_RXSZ too big\n", sc->sc_dev.dv_xname);
769 return;
770 }
771
772 /*
773 * ensure that there is always one VC slot on the service list free
774 * so that we can tell the difference between a full and empty list.
775 */
776 if (sc->en_nrx >= MID_N_VC)
777 sc->en_nrx = MID_N_VC - 1;
778
779 for (lcv = 0 ; lcv < sc->en_nrx ; lcv++) {
780 sc->rxslot[lcv].rxhand = NULL;
781 sc->rxslot[lcv].oth_flags = ENOTHER_FREE;
782 bzero(&sc->rxslot[lcv].indma, sizeof(sc->rxslot[lcv].indma));
783 bzero(&sc->rxslot[lcv].q, sizeof(sc->rxslot[lcv].q));
784 midvloc = sc->rxslot[lcv].start = ptr;
785 ptr += (EN_RXSZ * 1024);
786 sz -= (EN_RXSZ * 1024);
787 sc->rxslot[lcv].stop = ptr;
788 midvloc = midvloc - MID_RAMOFF;
789 midvloc = (midvloc & ~((EN_RXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
790 midvloc = midvloc >> MIDV_LOCTOPSHFT; /* we only want the top 11 bits */
791 midvloc = (midvloc & MIDV_LOCMASK) << MIDV_LOCSHIFT;
792 sc->rxslot[lcv].mode = midvloc |
793 (en_k2sz(EN_RXSZ) << MIDV_SZSHIFT) | MIDV_TRASH;
794
795#ifdef EN_DEBUG
796 printf("%s: rx%d: start 0x%x, stop 0x%x, mode 0x%x\n", sc->sc_dev.dv_xname,
797 lcv, sc->rxslot[lcv].start, sc->rxslot[lcv].stop, sc->rxslot[lcv].mode);
798#endif
799 }
800
801#ifdef EN_STAT
802 sc->vtrash = sc->otrash = sc->mfix = sc->txmbovr = sc->dmaovr = 0;
803 sc->txoutspace = sc->txdtqout = sc->launch = sc->lheader = sc->ltail = 0;
804 sc->hwpull = sc->swadd = sc->rxqnotus = sc->rxqus = sc->rxoutboth = 0;
805 sc->rxdrqout = sc->ttrash = sc->rxmbufout = sc->mfixfail = 0;
806 sc->headbyte = sc->tailbyte = sc->tailflush = 0;
807#endif
808 sc->need_drqs = sc->need_dtqs = 0;
809
810 printf("%s: %d %dKB receive buffers, %d %dKB transmit buffers allocated\n",
811 sc->sc_dev.dv_xname, sc->en_nrx, EN_RXSZ, EN_NTX, EN_TXSZ);
812
813 printf("%s: End Station Identifier (mac address) %6D\n",
814 sc->sc_dev.dv_xname, sc->macaddr, ":");
815
816 /*
817 * final commit
818 */
819
820 if_attach(ifp);
821 atm_ifattach(ifp);
822
823#if NBPF > 0
824 BPFATTACH(ifp, DLT_ATM_RFC1483, sizeof(struct atmllc));
825#endif
826}
827
828
829/*
830 * en_dmaprobe: helper function for en_attach.
831 *
832 * see how the card handles DMA by running a few DMA tests. we need
833 * to figure out the largest number of bytes we can DMA in one burst
834 * ("bestburstlen"), and if the starting address for a burst needs to
835 * be aligned on any sort of boundary or not ("alburst").
836 *
837 * typical findings:
838 * sparc1: bestburstlen=4, alburst=0 (ick, broken DMA!)
839 * sparc2: bestburstlen=64, alburst=1
840 * p166: bestburstlen=64, alburst=0
841 */
842
843#if 1 /* __FreeBSD__ */
844#define NBURSTS 3 /* number of bursts to use for dmaprobe */
845#define BOUNDARY 1024 /* test misaligned dma crossing the bounday.
846 should be n * 64. at least 64*(NBURSTS+1).
847 dell P6 with EDO DRAM has 1K bounday problem */
848#endif
849
850STATIC void en_dmaprobe(sc)
851
852struct en_softc *sc;
853
854{
855#ifdef NBURSTS
856 /* be careful. kernel stack is only 8K */
857 u_int8_t buffer[BOUNDARY * 2 + 64 * (NBURSTS + 1)];
858#else
859 u_int32_t srcbuf[64], dstbuf[64];
860#endif
861 u_int8_t *sp, *dp;
862 int bestalgn, bestnotalgn, lcv, try;
863
864 sc->alburst = 0;
865
866#ifdef NBURSTS
867 /* setup src and dst buf at the end of the boundary */
868 sp = (u_int8_t *)roundup((uintptr_t)(void *)buffer, 64);
869 while (((uintptr_t)(void *)sp & (BOUNDARY - 1)) != (BOUNDARY - 64))
870 sp += 64;
871 dp = sp + BOUNDARY;
872
873 /*
874 * we can't dma across page boundary so that, if buf is at a page
875 * boundary, move it to the next page. but still either src or dst
876 * will be at the boundary, which should be ok.
877 */
878 if ((((uintptr_t)(void *)sp + 64) & PAGE_MASK) == 0)
879 sp += 64;
880 if ((((uintptr_t)(void *)dp + 64) & PAGE_MASK) == 0)
881 dp += 64;
882#else /* !NBURSTS */
883 sp = (u_int8_t *) srcbuf;
884 while ((((unsigned long) sp) % MIDDMA_MAXBURST) != 0)
885 sp += 4;
886 dp = (u_int8_t *) dstbuf;
887 while ((((unsigned long) dp) % MIDDMA_MAXBURST) != 0)
888 dp += 4;
889#endif /* !NBURSTS */
890
891 bestalgn = bestnotalgn = en_dmaprobe_doit(sc, sp, dp, 0);
892
893 for (lcv = 4 ; lcv < MIDDMA_MAXBURST ; lcv += 4) {
894 try = en_dmaprobe_doit(sc, sp+lcv, dp+lcv, 0);
895#ifdef NBURSTS
896 if (try < bestnotalgn) {
897 bestnotalgn = try;
898 break;
899 }
900#else
901 if (try < bestnotalgn)
902 bestnotalgn = try;
903#endif
904 }
905
906 if (bestalgn != bestnotalgn) /* need bursts aligned */
907 sc->alburst = 1;
908
909 sc->bestburstlen = bestalgn;
910 sc->bestburstshift = en_log2(bestalgn);
911 sc->bestburstmask = sc->bestburstlen - 1; /* must be power of 2 */
912 sc->bestburstcode = en_sz2b(bestalgn);
913
914#if 1 /* __FreeBSD__ */
915 /*
916 * correct pci chipsets should be able to handle misaligned-64-byte DMA.
917 * but there are too many broken chipsets around. we try to work around
918 * by finding the best workable dma size, but still some broken machines
919 * exhibit the problem later. so warn it here.
920 */
921 if (bestalgn != 64 || sc->alburst != 0) {
922 printf("%s: WARNING: DMA test detects a broken PCI chipset!\n",
923 sc->sc_dev.dv_xname);
924 printf(" trying to work around the problem... but if this doesn't\n");
925 printf(" work for you, you'd better switch to a newer motherboard.\n");
926 }
927#endif /* 1 */
928 return;
929}
930
931
932/*
933 * en_dmaprobe_doit: do actual testing
934 */
935
936static int
937en_dmaprobe_doit(sc, sp, dp, wmtry)
938
939struct en_softc *sc;
940u_int8_t *sp, *dp;
941int wmtry;
942
943{
944 int lcv, retval = 4, cnt, count;
945 u_int32_t reg, bcode, midvloc;
946
947 /*
948 * set up a 1k buffer at MID_BUFOFF
949 */
950
951 if (sc->en_busreset)
952 sc->en_busreset(sc);
953 EN_WRITE(sc, MID_RESID, 0x0); /* reset card before touching RAM */
954
955 midvloc = ((MID_BUFOFF - MID_RAMOFF) / sizeof(u_int32_t)) >> MIDV_LOCTOPSHFT;
956 EN_WRITE(sc, MIDX_PLACE(0), MIDX_MKPLACE(en_k2sz(1), midvloc));
957 EN_WRITE(sc, MID_VC(0), (midvloc << MIDV_LOCSHIFT)
958 | (en_k2sz(1) << MIDV_SZSHIFT) | MIDV_TRASH);
959 EN_WRITE(sc, MID_DST_RP(0), 0);
960 EN_WRITE(sc, MID_WP_ST_CNT(0), 0);
961
962#ifdef NBURSTS
963 for (lcv = 0 ; lcv < 64*NBURSTS; lcv++) /* set up sample data */
964#else
965 for (lcv = 0 ; lcv < 68 ; lcv++) /* set up sample data */
966#endif
967 sp[lcv] = lcv+1;
968 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* enable DMA (only) */
969
970 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
971 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
972
973 /*
974 * try it now . . . DMA it out, then DMA it back in and compare
975 *
976 * note: in order to get the dma stuff to reverse directions it wants
977 * the "end" flag set! since we are not dma'ing valid data we may
978 * get an ident mismatch interrupt (which we will ignore).
979 *
980 * note: we've got two different tests rolled up in the same loop
981 * if (wmtry)
982 * then we are doing a wmaybe test and wmtry is a byte count
983 * else we are doing a burst test
984 */
985
986 for (lcv = 8 ; lcv <= MIDDMA_MAXBURST ; lcv = lcv * 2) {
987
988#ifdef EN_DEBUG
989 printf("DMA test lcv=%d, sp=0x%x, dp=0x%x, wmtry=%d\n",
990 lcv, sp, dp, wmtry);
991#endif
992
993 /* zero SRAM and dest buffer */
994 for (cnt = 0 ; cnt < 1024; cnt += 4)
995 EN_WRITE(sc, MID_BUFOFF+cnt, 0); /* zero memory */
996#ifdef NBURSTS
997 for (cnt = 0 ; cnt < 64*NBURSTS; cnt++)
998#else
999 for (cnt = 0 ; cnt < 68 ; cnt++)
1000#endif
1001 dp[cnt] = 0;
1002
1003 if (wmtry) {
1004 count = (sc->bestburstlen - sizeof(u_int32_t)) / sizeof(u_int32_t);
1005 bcode = en_dmaplan[count].bcode;
1006 count = wmtry >> en_dmaplan[count].divshift;
1007 } else {
1008 bcode = en_sz2b(lcv);
1009 count = 1;
1010 }
1011#ifdef NBURSTS
1012 /* build lcv-byte-DMA x NBURSTS */
1013 if (sc->is_adaptec)
1014 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1015 else
1016 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1017 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1018 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1019 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip));
1020 cnt = 1000;
1021 while (EN_READ(sc, MID_DMA_RDTX) != MID_DTQ_A2REG(sc->dtq_chip)) {
1022 DELAY(1);
1023 cnt--;
1024 if (cnt == 0) {
1025 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1026/*
1027 printf(" alignment=0x%x, burst size=%d, dma addr reg=0x%x\n",
1028 (u_long)sp & 63, lcv, EN_READ(sc, MID_DMA_ADDR));
1029*/
1030 return(retval); /* timeout, give up */
1031 }
1032 }
1033#else /* !NBURSTS */
1034 if (sc->is_adaptec)
1035 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ADP(lcv, 0, MID_DMA_END, 0));
1036 else
1037 EN_WRITE(sc, sc->dtq_chip, MID_MK_TXQ_ENI(count, 0, MID_DMA_END, bcode));
1038 EN_WRITE(sc, sc->dtq_chip+4, vtophys(sp));
1039 EN_WRITE(sc, MID_DMA_WRTX, MID_DTQ_A2REG(sc->dtq_chip+8));
1040 cnt = 1000;
1041 while (EN_READ(sc, MID_DMA_RDTX) == MID_DTQ_A2REG(sc->dtq_chip)) {
1042 DELAY(1);
1043 cnt--;
1044 if (cnt == 0) {
1045 printf("%s: unexpected timeout in tx DMA test\n", sc->sc_dev.dv_xname);
1046 return(retval); /* timeout, give up */
1047 }
1048 }
1049 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, sc->dtq_chip, 8);
1050#endif /* !NBURSTS */
1051 reg = EN_READ(sc, MID_INTACK);
1052 if ((reg & MID_INT_DMA_TX) != MID_INT_DMA_TX) {
1053 printf("%s: unexpected status in tx DMA test: 0x%x\n",
1054 sc->sc_dev.dv_xname, reg);
1055 return(retval);
1056 }
1057 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1058
1059 /* "return to sender..." address is known ... */
1060
1061#ifdef NBURSTS
1062 /* build lcv-byte-DMA x NBURSTS */
1063 if (sc->is_adaptec)
1064 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv*NBURSTS, 0, MID_DMA_END, 0));
1065 else
1066 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count*NBURSTS, 0, MID_DMA_END, bcode));
1067 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1068 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1069 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1070 cnt = 1000;
1071 while (EN_READ(sc, MID_DMA_RDRX) != MID_DRQ_A2REG(sc->drq_chip)) {
1072 DELAY(1);
1073 cnt--;
1074 if (cnt == 0) {
1075 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1076 return(retval); /* timeout, give up */
1077 }
1078 }
1079#else /* !NBURSTS */
1080 if (sc->is_adaptec)
1081 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ADP(lcv, 0, MID_DMA_END, 0));
1082 else
1083 EN_WRITE(sc, sc->drq_chip, MID_MK_RXQ_ENI(count, 0, MID_DMA_END, bcode));
1084 EN_WRITE(sc, sc->drq_chip+4, vtophys(dp));
1085 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip+8));
1086 cnt = 1000;
1087 while (EN_READ(sc, MID_DMA_RDRX) == MID_DRQ_A2REG(sc->drq_chip)) {
1088 DELAY(1);
1089 cnt--;
1090 if (cnt == 0) {
1091 printf("%s: unexpected timeout in rx DMA test\n", sc->sc_dev.dv_xname);
1092 return(retval); /* timeout, give up */
1093 }
1094 }
1095 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, sc->drq_chip, 8);
1096#endif /* !NBURSTS */
1097 reg = EN_READ(sc, MID_INTACK);
1098 if ((reg & MID_INT_DMA_RX) != MID_INT_DMA_RX) {
1099 printf("%s: unexpected status in rx DMA test: 0x%x\n",
1100 sc->sc_dev.dv_xname, reg);
1101 return(retval);
1102 }
1103 EN_WRITE(sc, MID_MAST_CSR, MID_MCSR_ENDMA); /* re-enable DMA (only) */
1104
1105 if (wmtry) {
1106 return(bcmp(sp, dp, wmtry)); /* wmtry always exits here, no looping */
1107 }
1108
1109#ifdef NBURSTS
1110 if (bcmp(sp, dp, lcv * NBURSTS)) {
1111/* printf("DMA test failed! lcv=%d, sp=0x%x, dp=0x%x\n", lcv, sp, dp); */
1112 return(retval); /* failed, use last value */
1113 }
1114#else
1115 if (bcmp(sp, dp, lcv))
1116 return(retval); /* failed, use last value */
1117#endif
1118
1119 retval = lcv;
1120
1121 }
1122 return(retval); /* studly 64 byte DMA present! oh baby!! */
1123}
1124
1125/***********************************************************************/
1126
1127/*
1128 * en_ioctl: handle ioctl requests
1129 *
1130 * NOTE: if you add an ioctl to set txspeed, you should choose a new
1131 * TX channel/slot. Choose the one with the lowest sc->txslot[slot].nref
1132 * value, subtract one from sc->txslot[0].nref, add one to the
1133 * sc->txslot[slot].nref, set sc->txvc2slot[vci] = slot, and then set
1134 * txspeed[vci].
1135 */
1136
1137STATIC int en_ioctl(ifp, cmd, data)
1138
1139struct ifnet *ifp;
1140EN_IOCTL_CMDT cmd;
1141caddr_t data;
1142
1143{
1144 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1145 struct ifaddr *ifa = (struct ifaddr *) data;
1146 struct ifreq *ifr = (struct ifreq *) data;
1147 struct atm_pseudoioctl *api = (struct atm_pseudoioctl *)data;
1148#ifdef NATM
1149 struct atm_rawioctl *ario = (struct atm_rawioctl *)data;
1150 int slot;
1151#endif
1152 int s, error = 0;
1153
1154 s = splnet();
1155
1156 switch (cmd) {
1157 case SIOCATMENA: /* enable circuit for recv */
1158 error = en_rxctl(sc, api, 1);
1159 break;
1160
1161 case SIOCATMDIS: /* disable circuit for recv */
1162 error = en_rxctl(sc, api, 0);
1163 break;
1164
1165#ifdef NATM
1166 case SIOCXRAWATM:
1167 if ((slot = sc->rxvc2slot[ario->npcb->npcb_vci]) == RX_NONE) {
1168 error = EINVAL;
1169 break;
1170 }
1171 if (ario->rawvalue > EN_RXSZ*1024)
1172 ario->rawvalue = EN_RXSZ*1024;
1173 if (ario->rawvalue) {
1174 sc->rxslot[slot].oth_flags |= ENOTHER_RAW;
1175 sc->rxslot[slot].raw_threshold = ario->rawvalue;
1176 } else {
1177 sc->rxslot[slot].oth_flags &= (~ENOTHER_RAW);
1178 sc->rxslot[slot].raw_threshold = 0;
1179 }
1180#ifdef EN_DEBUG
1181 printf("%s: rxvci%d: turn %s raw (boodi) mode\n",
1182 sc->sc_dev.dv_xname, ario->npcb->npcb_vci,
1183 (ario->rawvalue) ? "on" : "off");
1184#endif
1185 break;
1186#endif
1187 case SIOCSIFADDR:
1188 ifp->if_flags |= IFF_UP;
1189#if defined(INET) || defined(INET6)
1190 if (ifa->ifa_addr->sa_family == AF_INET
1191 || ifa->ifa_addr->sa_family == AF_INET6) {
1192 en_reset(sc);
1193 en_init(sc);
1194 ifa->ifa_rtrequest = atm_rtrequest; /* ??? */
1195 break;
1196 }
1197#endif /* INET */
1198 /* what to do if not INET? */
1199 en_reset(sc);
1200 en_init(sc);
1201 break;
1202
1203 case SIOCGIFADDR:
1204 error = EINVAL;
1205 break;
1206
1207 case SIOCSIFFLAGS:
1208 error = EINVAL;
1209 break;
1210
1211#if defined(SIOCSIFMTU) /* ??? copied from if_de */
1212#if !defined(ifr_mtu)
1213#define ifr_mtu ifr_metric
1214#endif
1215 case SIOCSIFMTU:
1216 /*
1217 * Set the interface MTU.
1218 */
1219#ifdef notsure
1220 if (ifr->ifr_mtu > ATMMTU) {
1221 error = EINVAL;
1222 break;
1223 }
1224#endif
1225 ifp->if_mtu = ifr->ifr_mtu;
1226 /* XXXCDC: do we really need to reset on MTU size change? */
1227 en_reset(sc);
1228 en_init(sc);
1229 break;
1230#endif /* SIOCSIFMTU */
1231
1232 default:
1233 error = EINVAL;
1234 break;
1235 }
1236 splx(s);
1237 return error;
1238}
1239
1240
1241/*
1242 * en_rxctl: turn on and off VCs for recv.
1243 */
1244
1245STATIC int en_rxctl(sc, pi, on)
1246
1247struct en_softc *sc;
1248struct atm_pseudoioctl *pi;
1249int on;
1250
1251{
1252 u_int s, vci, flags, slot;
1253 u_int32_t oldmode, newmode;
1254
1255 vci = ATM_PH_VCI(&pi->aph);
1256 flags = ATM_PH_FLAGS(&pi->aph);
1257
1258#ifdef EN_DEBUG
1259 printf("%s: %s vpi=%d, vci=%d, flags=%d\n", sc->sc_dev.dv_xname,
1260 (on) ? "enable" : "disable", ATM_PH_VPI(&pi->aph), vci, flags);
1261#endif
1262
1263 if (ATM_PH_VPI(&pi->aph) || vci >= MID_N_VC)
1264 return(EINVAL);
1265
1266 /*
1267 * turn on VCI!
1268 */
1269
1270 if (on) {
1271 if (sc->rxvc2slot[vci] != RX_NONE)
1272 return(EINVAL);
1273 for (slot = 0 ; slot < sc->en_nrx ; slot++)
1274 if (sc->rxslot[slot].oth_flags & ENOTHER_FREE)
1275 break;
1276 if (slot == sc->en_nrx)
1277 return(ENOSPC);
1278 sc->rxvc2slot[vci] = slot;
1279 sc->rxslot[slot].rxhand = NULL;
1280 oldmode = sc->rxslot[slot].mode;
1281 newmode = (flags & ATM_PH_AAL5) ? MIDV_AAL5 : MIDV_NOAAL;
1282 sc->rxslot[slot].mode = MIDV_SETMODE(oldmode, newmode);
1283 sc->rxslot[slot].atm_vci = vci;
1284 sc->rxslot[slot].atm_flags = flags;
1285 sc->rxslot[slot].oth_flags = 0;
1286 sc->rxslot[slot].rxhand = pi->rxhand;
1287 if (sc->rxslot[slot].indma.ifq_head || sc->rxslot[slot].q.ifq_head)
1288 panic("en_rxctl: left over mbufs on enable");
1289 sc->txspeed[vci] = 0; /* full speed to start */
1290 sc->txvc2slot[vci] = 0; /* init value */
1291 sc->txslot[0].nref++; /* bump reference count */
1292 en_loadvc(sc, vci); /* does debug printf for us */
1293 return(0);
1294 }
1295
1296 /*
1297 * turn off VCI
1298 */
1299
1300 if (sc->rxvc2slot[vci] == RX_NONE)
1301 return(EINVAL);
1302 slot = sc->rxvc2slot[vci];
1303 if ((sc->rxslot[slot].oth_flags & (ENOTHER_FREE|ENOTHER_DRAIN)) != 0)
1304 return(EINVAL);
1305 s = splimp(); /* block out enintr() */
1306 oldmode = EN_READ(sc, MID_VC(vci));
1307 newmode = MIDV_SETMODE(oldmode, MIDV_TRASH) & ~MIDV_INSERVICE;
1308 EN_WRITE(sc, MID_VC(vci), (newmode | (oldmode & MIDV_INSERVICE)));
1309 /* halt in tracks, be careful to preserve inserivce bit */
1310 DELAY(27);
1311 sc->rxslot[slot].rxhand = NULL;
1312 sc->rxslot[slot].mode = newmode;
1313
1314 sc->txslot[sc->txvc2slot[vci]].nref--;
1315 sc->txspeed[vci] = 0;
1316 sc->txvc2slot[vci] = 0;
1317
1318 /* if stuff is still going on we are going to have to drain it out */
1319 if (sc->rxslot[slot].indma.ifq_head ||
1320 sc->rxslot[slot].q.ifq_head ||
1321 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) != 0) {
1322 sc->rxslot[slot].oth_flags |= ENOTHER_DRAIN;
1323 } else {
1324 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1325 sc->rxslot[slot].atm_vci = RX_NONE;
1326 sc->rxvc2slot[vci] = RX_NONE;
1327 }
1328 splx(s); /* enable enintr() */
1329#ifdef EN_DEBUG
1330 printf("%s: rx%d: VCI %d is now %s\n", sc->sc_dev.dv_xname, slot, vci,
1331 (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) ? "draining" : "free");
1332#endif
1333 return(0);
1334}
1335
1336/***********************************************************************/
1337
1338/*
1339 * en_reset: reset the board, throw away work in progress.
1340 * must en_init to recover.
1341 */
1342
1343void en_reset(sc)
1344
1345struct en_softc *sc;
1346
1347{
1348 struct mbuf *m;
1349 int lcv, slot;
1350
1351#ifdef EN_DEBUG
1352 printf("%s: reset\n", sc->sc_dev.dv_xname);
1353#endif
1354
1355 if (sc->en_busreset)
1356 sc->en_busreset(sc);
1357 EN_WRITE(sc, MID_RESID, 0x0); /* reset hardware */
1358
1359 /*
1360 * recv: dump any mbufs we are dma'ing into, if DRAINing, then a reset
1361 * will free us!
1362 */
1363
1364 for (lcv = 0 ; lcv < MID_N_VC ; lcv++) {
1365 if (sc->rxvc2slot[lcv] == RX_NONE)
1366 continue;
1367 slot = sc->rxvc2slot[lcv];
1368 while (1) {
1369 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
1370 if (m == NULL)
1371 break; /* >>> exit 'while(1)' here <<< */
1372 m_freem(m);
1373 }
1374 while (1) {
1375 IF_DEQUEUE(&sc->rxslot[slot].q, m);
1376 if (m == NULL)
1377 break; /* >>> exit 'while(1)' here <<< */
1378 m_freem(m);
1379 }
1380 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
1381 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) {
1382 sc->rxslot[slot].oth_flags = ENOTHER_FREE;
1383 sc->rxvc2slot[lcv] = RX_NONE;
1384#ifdef EN_DEBUG
1385 printf("%s: rx%d: VCI %d is now free\n", sc->sc_dev.dv_xname, slot, lcv);
1386#endif
1387 }
1388 }
1389
1390 /*
1391 * xmit: dump everything
1392 */
1393
1394 for (lcv = 0 ; lcv < EN_NTX ; lcv++) {
1395 while (1) {
1396 IF_DEQUEUE(&sc->txslot[lcv].indma, m);
1397 if (m == NULL)
1398 break; /* >>> exit 'while(1)' here <<< */
1399 m_freem(m);
1400 }
1401 while (1) {
1402 IF_DEQUEUE(&sc->txslot[lcv].q, m);
1403 if (m == NULL)
1404 break; /* >>> exit 'while(1)' here <<< */
1405 m_freem(m);
1406 }
1407
1408 sc->txslot[lcv].mbsize = 0;
1409 }
1410
1411 return;
1412}
1413
1414
1415/*
1416 * en_init: init board and sync the card with the data in the softc.
1417 */
1418
1419STATIC void en_init(sc)
1420
1421struct en_softc *sc;
1422
1423{
1424 int vc, slot;
1425 u_int32_t loc;
1426
1427 if ((sc->enif.if_flags & IFF_UP) == 0) {
1428#ifdef EN_DEBUG
1429 printf("%s: going down\n", sc->sc_dev.dv_xname);
1430#endif
1431 en_reset(sc); /* to be safe */
1432 sc->enif.if_flags &= ~IFF_RUNNING; /* disable */
1433 return;
1434 }
1435
1436#ifdef EN_DEBUG
1437 printf("%s: going up\n", sc->sc_dev.dv_xname);
1438#endif
1439 sc->enif.if_flags |= IFF_RUNNING; /* enable */
1440
1441 if (sc->en_busreset)
1442 sc->en_busreset(sc);
1443 EN_WRITE(sc, MID_RESID, 0x0); /* reset */
1444
1445 /*
1446 * init obmem data structures: vc tab, dma q's, slist.
1447 *
1448 * note that we set drq_free/dtq_free to one less than the total number
1449 * of DTQ/DRQs present. we do this because the card uses the condition
1450 * (drq_chip == drq_us) to mean "list is empty"... but if you allow the
1451 * circular list to be completely full then (drq_chip == drq_us) [i.e.
1452 * the drq_us pointer will wrap all the way around]. by restricting
1453 * the number of active requests to (N - 1) we prevent the list from
1454 * becoming completely full. note that the card will sometimes give
1455 * us an interrupt for a DTQ/DRQ we have already processes... this helps
1456 * keep that interrupt from messing us up.
1457 */
1458
1459 for (vc = 0 ; vc < MID_N_VC ; vc++)
1460 en_loadvc(sc, vc);
1461
1462 bzero(&sc->drq, sizeof(sc->drq));
1463 sc->drq_free = MID_DRQ_N - 1; /* N - 1 */
1464 sc->drq_chip = MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX));
1465 EN_WRITE(sc, MID_DMA_WRRX, MID_DRQ_A2REG(sc->drq_chip));
1466 /* ensure zero queue */
1467 sc->drq_us = sc->drq_chip;
1468
1469 bzero(&sc->dtq, sizeof(sc->dtq));
1470 sc->dtq_free = MID_DTQ_N - 1; /* N - 1 */
1471 sc->dtq_chip = MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX));
1472 EN_WRITE(sc, MID_DMA_WRTX, MID_DRQ_A2REG(sc->dtq_chip));
1473 /* ensure zero queue */
1474 sc->dtq_us = sc->dtq_chip;
1475
1476 sc->hwslistp = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
1477 sc->swsl_size = sc->swsl_head = sc->swsl_tail = 0;
1478
1479#ifdef EN_DEBUG
1480 printf("%s: drq free/chip: %d/0x%x, dtq free/chip: %d/0x%x, hwslist: 0x%x\n",
1481 sc->sc_dev.dv_xname, sc->drq_free, sc->drq_chip,
1482 sc->dtq_free, sc->dtq_chip, sc->hwslistp);
1483#endif
1484
1485 for (slot = 0 ; slot < EN_NTX ; slot++) {
1486 sc->txslot[slot].bfree = EN_TXSZ * 1024;
1487 EN_WRITE(sc, MIDX_READPTR(slot), 0);
1488 EN_WRITE(sc, MIDX_DESCSTART(slot), 0);
1489 loc = sc->txslot[slot].cur = sc->txslot[slot].start;
1490 loc = loc - MID_RAMOFF;
1491 loc = (loc & ~((EN_TXSZ*1024) - 1)) >> 2; /* mask, cvt to words */
1492 loc = loc >> MIDV_LOCTOPSHFT; /* top 11 bits */
1493 EN_WRITE(sc, MIDX_PLACE(slot), MIDX_MKPLACE(en_k2sz(EN_TXSZ), loc));
1494#ifdef EN_DEBUG
1495 printf("%s: tx%d: place 0x%x\n", sc->sc_dev.dv_xname, slot,
1496 EN_READ(sc, MIDX_PLACE(slot)));
1497#endif
1498 }
1499
1500 /*
1501 * enable!
1502 */
1503
1504 EN_WRITE(sc, MID_INTENA, MID_INT_TX|MID_INT_DMA_OVR|MID_INT_IDENT|
1505 MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_DMA_RX|MID_INT_DMA_TX|
1506 MID_INT_SERVICE| /* >>> MID_INT_SUNI| XXXCDC<<< */ MID_INT_STATS);
1507 EN_WRITE(sc, MID_MAST_CSR, MID_SETIPL(sc->ipl)|MID_MCSR_ENDMA|
1508 MID_MCSR_ENTX|MID_MCSR_ENRX);
1509
1510}
1511
1512
1513/*
1514 * en_loadvc: load a vc tab entry from a slot
1515 */
1516
1517STATIC void en_loadvc(sc, vc)
1518
1519struct en_softc *sc;
1520int vc;
1521
1522{
1523 int slot;
1524 u_int32_t reg = EN_READ(sc, MID_VC(vc));
1525
1526 reg = MIDV_SETMODE(reg, MIDV_TRASH);
1527 EN_WRITE(sc, MID_VC(vc), reg);
1528 DELAY(27);
1529
1530 if ((slot = sc->rxvc2slot[vc]) == RX_NONE)
1531 return;
1532
1533 /* no need to set CRC */
1534 EN_WRITE(sc, MID_DST_RP(vc), 0); /* read pointer = 0, desc. start = 0 */
1535 EN_WRITE(sc, MID_WP_ST_CNT(vc), 0); /* write pointer = 0 */
1536 EN_WRITE(sc, MID_VC(vc), sc->rxslot[slot].mode); /* set mode, size, loc */
1537 sc->rxslot[slot].cur = sc->rxslot[slot].start;
1538
1539#ifdef EN_DEBUG
1540 printf("%s: rx%d: assigned to VCI %d\n", sc->sc_dev.dv_xname, slot, vc);
1541#endif
1542}
1543
1544
1545/*
1546 * en_start: start transmitting the next packet that needs to go out
1547 * if there is one. note that atm_output() has already splimp()'d us.
1548 */
1549
1550STATIC void en_start(ifp)
1551
1552struct ifnet *ifp;
1553
1554{
1555 struct en_softc *sc = (struct en_softc *) ifp->if_softc;
1556 struct ifqueue *ifq = &ifp->if_snd; /* if INPUT QUEUE */
1557 struct mbuf *m, *lastm, *prev;
1558 struct atm_pseudohdr *ap, *new_ap;
1559 int txchan, mlen, got, need, toadd, cellcnt, first;
1560 u_int32_t atm_vpi, atm_vci, atm_flags, *dat, aal;
1561 u_int8_t *cp;
1562
1563 if ((ifp->if_flags & IFF_RUNNING) == 0)
1564 return;
1565
1566 /*
1567 * remove everything from interface queue since we handle all queueing
1568 * locally ...
1569 */
1570
1571 while (1) {
1572
1573 IF_DEQUEUE(ifq, m);
1574 if (m == NULL)
1575 return; /* EMPTY: >>> exit here <<< */
1576
1577 /*
1578 * calculate size of packet (in bytes)
1579 * also, if we are not doing transmit DMA we eliminate all stupid
1580 * (non-word) alignments here using en_mfix(). calls to en_mfix()
1581 * seem to be due to tcp retransmits for the most part.
1582 *
1583 * after this loop mlen total length of mbuf chain (including atm_ph),
1584 * and lastm is a pointer to the last mbuf on the chain.
1585 */
1586
1587 lastm = m;
1588 mlen = 0;
1589 prev = NULL;
1590 while (1) {
1591 /* no DMA? */
1592 if ((!sc->is_adaptec && EN_ENIDMAFIX) || EN_NOTXDMA || !en_dma) {
1593 if ( ((uintptr_t)mtod(lastm, void *) % sizeof(u_int32_t)) != 0 ||
1594 ((lastm->m_len % sizeof(u_int32_t)) != 0 && lastm->m_next)) {
1595 first = (lastm == m);
1596 if (en_mfix(sc, &lastm, prev) == 0) { /* failed? */
1597 m_freem(m);
1598 m = NULL;
1599 break;
1600 }
1601 if (first)
1602 m = lastm; /* update */
1603 }
1604 prev = lastm;
1605 }
1606
1607 mlen += lastm->m_len;
1608 if (lastm->m_next == NULL)
1609 break;
1610 lastm = lastm->m_next;
1611 }
1612
1613 if (m == NULL) /* happens only if mfix fails */
1614 continue;
1615
1616 ap = mtod(m, struct atm_pseudohdr *);
1617
1618 atm_vpi = ATM_PH_VPI(ap);
1619 atm_vci = ATM_PH_VCI(ap);
1620 atm_flags = ATM_PH_FLAGS(ap) & ~(EN_OBHDR|EN_OBTRL);
1621 aal = ((atm_flags & ATM_PH_AAL5) != 0)
1622 ? MID_TBD_AAL5 : MID_TBD_NOAAL5;
1623
1624 /*
1625 * check that vpi/vci is one we can use
1626 */
1627
1628 if (atm_vpi || atm_vci > MID_N_VC) {
1629 printf("%s: output vpi=%d, vci=%d out of card range, dropping...\n",
1630 sc->sc_dev.dv_xname, atm_vpi, atm_vci);
1631 m_freem(m);
1632 continue;
1633 }
1634
1635 /*
1636 * computing how much padding we need on the end of the mbuf, then
1637 * see if we can put the TBD at the front of the mbuf where the
1638 * link header goes (well behaved protocols will reserve room for us).
1639 * last, check if room for PDU tail.
1640 *
1641 * got = number of bytes of data we have
1642 * cellcnt = number of cells in this mbuf
1643 * need = number of bytes of data + padding we need (excludes TBD)
1644 * toadd = number of bytes of data we need to add to end of mbuf,
1645 * [including AAL5 PDU, if AAL5]
1646 */
1647
1648 got = mlen - sizeof(struct atm_pseudohdr *);
1649 toadd = (aal == MID_TBD_AAL5) ? MID_PDU_SIZE : 0; /* PDU */
1650 cellcnt = (got + toadd + (MID_ATMDATASZ - 1)) / MID_ATMDATASZ;
1651 need = cellcnt * MID_ATMDATASZ;
1652 toadd = need - got; /* recompute, including zero padding */
1653
1654#ifdef EN_DEBUG
1655 printf("%s: txvci%d: mlen=%d, got=%d, need=%d, toadd=%d, cell#=%d\n",
1656 sc->sc_dev.dv_xname, atm_vci, mlen, got, need, toadd, cellcnt);
1657 printf(" leading_space=%d, trailing_space=%d\n",
1658 M_LEADINGSPACE(m), M_TRAILINGSPACE(lastm));
1659#endif
1660
1661#ifdef EN_MBUF_OPT
1662
1663 /*
1664 * note: external storage (M_EXT) can be shared between mbufs
1665 * to avoid copying (see m_copym()). this means that the same
1666 * data buffer could be shared by several mbufs, and thus it isn't
1667 * a good idea to try and write TBDs or PDUs to M_EXT data areas.
1668 */
1669
1670 if (M_LEADINGSPACE(m) >= MID_TBD_SIZE && (m->m_flags & M_EXT) == 0) {
1671 m->m_data -= MID_TBD_SIZE;
1672 m->m_len += MID_TBD_SIZE;
1673 mlen += MID_TBD_SIZE;
1674 new_ap = mtod(m, struct atm_pseudohdr *);
1675 *new_ap = *ap; /* move it back */
1676 ap = new_ap;
1677 dat = ((u_int32_t *) ap) + 1;
1678 /* make sure the TBD is in proper byte order */
1679 *dat++ = htonl(MID_TBD_MK1(aal, sc->txspeed[atm_vci], cellcnt));
1680 *dat = htonl(MID_TBD_MK2(atm_vci, 0, 0));
1681 atm_flags |= EN_OBHDR;
1682 }
1683
1684 if (toadd && (lastm->m_flags & M_EXT) == 0 &&
1685 M_TRAILINGSPACE(lastm) >= toadd) {
1686 cp = mtod(lastm, u_int8_t *) + lastm->m_len;
1687 lastm->m_len += toadd;
1688 mlen += toadd;
1689 if (aal == MID_TBD_AAL5) {
1690 bzero(cp, toadd - MID_PDU_SIZE);
1691 dat = (u_int32_t *)(cp + toadd - MID_PDU_SIZE);
1692 /* make sure the PDU is in proper byte order */
1693 *dat = htonl(MID_PDU_MK1(0, 0, got));
1694 } else {
1695 bzero(cp, toadd);
1696 }
1697 atm_flags |= EN_OBTRL;
1698 }
1699 ATM_PH_FLAGS(ap) = atm_flags; /* update EN_OBHDR/EN_OBTRL bits */
1700#endif /* EN_MBUF_OPT */
1701
1702 /*
1703 * get assigned channel (will be zero unless txspeed[atm_vci] is set)
1704 */
1705
1706 txchan = sc->txvc2slot[atm_vci];
1707
1708 if (sc->txslot[txchan].mbsize > EN_TXHIWAT) {
1709 EN_COUNT(sc->txmbovr);
1710 m_freem(m);
1711#ifdef EN_DEBUG
1712 printf("%s: tx%d: buffer space shortage\n", sc->sc_dev.dv_xname,
1713 txchan);
1714#endif
1715 continue;
1716 }
1717
1718 sc->txslot[txchan].mbsize += mlen;
1719
1720#ifdef EN_DEBUG
1721 printf("%s: tx%d: VPI=%d, VCI=%d, FLAGS=0x%x, speed=0x%x\n",
1722 sc->sc_dev.dv_xname, txchan, atm_vpi, atm_vci, atm_flags,
1723 sc->txspeed[atm_vci]);
1724 printf(" adjusted mlen=%d, mbsize=%d\n", mlen,
1725 sc->txslot[txchan].mbsize);
1726#endif
1727
1728 IF_ENQUEUE(&sc->txslot[txchan].q, m);
1729
1730 en_txdma(sc, txchan);
1731
1732 }
1733 /*NOTREACHED*/
1734}
1735
1736
1737/*
1738 * en_mfix: fix a stupid mbuf
1739 */
1740
1741#ifndef __FreeBSD__
1742
1743STATIC int en_mfix(sc, mm, prev)
1744
1745struct en_softc *sc;
1746struct mbuf **mm, *prev;
1747
1748{
1749 struct mbuf *m, *new;
1750 u_char *d, *cp;
1751 int off;
1752 struct mbuf *nxt;
1753
1754 m = *mm;
1755
1756 EN_COUNT(sc->mfix); /* count # of calls */
1757#ifdef EN_DEBUG
1758 printf("%s: mfix mbuf m_data=%p, m_len=%d\n", sc->sc_dev.dv_xname,
1759 m->m_data, m->m_len);
1760#endif
1761
1762 d = mtod(m, u_char *);
1763 off = ((unsigned long) d) % sizeof(u_int32_t);
1764
1765 if (off) {
1766 if ((m->m_flags & M_EXT) == 0) {
1767 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1768 d -= off;
1769 m->m_data = (caddr_t)d;
1770 } else {
1771 /* can't write to an M_EXT mbuf since it may be shared */
1772 MGET(new, M_DONTWAIT, MT_DATA);
1773 if (!new) {
1774 EN_COUNT(sc->mfixfail);
1775 return(0);
1776 }
1777 MCLGET(new, M_DONTWAIT);
1778 if ((new->m_flags & M_EXT) == 0) {
1779 m_free(new);
1780 EN_COUNT(sc->mfixfail);
1781 return(0);
1782 }
1783 bcopy(d, new->m_data, m->m_len); /* ALIGN! (with costly data copy...) */
1784 new->m_len = m->m_len;
1785 new->m_next = m->m_next;
1786 if (prev)
1787 prev->m_next = new;
1788 m_free(m);
1789 *mm = m = new; /* note: 'd' now invalid */
1790 }
1791 }
1792
1793 off = m->m_len % sizeof(u_int32_t);
1794 if (off == 0)
1795 return(1);
1796
1797 d = mtod(m, u_char *) + m->m_len;
1798 off = sizeof(u_int32_t) - off;
1799
1800 nxt = m->m_next;
1801 while (off--) {
1802 for ( ; nxt != NULL && nxt->m_len == 0 ; nxt = nxt->m_next)
1803 /*null*/;
1804 if (nxt == NULL) { /* out of data, zero fill */
1805 *d++ = 0;
1806 continue; /* next "off" */
1807 }
1808 cp = mtod(nxt, u_char *);
1809 *d++ = *cp++;
1810 m->m_len++;
1811 nxt->m_len--;
1812 nxt->m_data = (caddr_t)cp;
1813 }
1814 return(1);
1815}
1816
1817#else /* __FreeBSD__ */
1818
1819STATIC int en_makeexclusive(struct en_softc *, struct mbuf **, struct mbuf *);
1820
1821STATIC int en_makeexclusive(sc, mm, prev)
1822 struct en_softc *sc;
1823 struct mbuf **mm, *prev;
1824{
1825 struct mbuf *m, *new;
1826
1827 m = *mm;
1828
1829 if (m->m_flags & M_EXT) {
1830 if (m->m_ext.ext_free) {
1831 /* external buffer isn't an ordinary mbuf cluster! */
1832 printf("%s: mfix: special buffer! can't make a copy!\n",
1833 sc->sc_dev.dv_xname);
1834 return (0);
1835 }
1836
1837 if (mclrefcnt[mtocl(m->m_ext.ext_buf)] > 1) {
1838 /* make a real copy of the M_EXT mbuf since it is shared */
1839 MGET(new, M_DONTWAIT, MT_DATA);
1840 if (!new) {
1841 EN_COUNT(sc->mfixfail);
1842 return(0);
1843 }
1844 if (m->m_flags & M_PKTHDR)
1845 M_MOVE_PKTHDR(new, m);
1846 MCLGET(new, M_DONTWAIT);
1847 if ((new->m_flags & M_EXT) == 0) {
1848 m_free(new);
1849 EN_COUNT(sc->mfixfail);
1850 return(0);
1851 }
1852 bcopy(m->m_data, new->m_data, m->m_len);
1853 new->m_len = m->m_len;
1854 new->m_next = m->m_next;
1855 if (prev)
1856 prev->m_next = new;
1857 m_free(m);
1858 *mm = new;
1859 }
1860 else {
1861 /* the buffer is not shared, align the data offset using
1862 this buffer. */
1863 u_char *d = mtod(m, u_char *);
1864 int off = ((uintptr_t)(void *)d) % sizeof(u_int32_t);
1865
1866 if (off > 0) {
1867 bcopy(d, d - off, m->m_len);
1868 m->m_data = (caddr_t)d - off;
1869 }
1870 }
1871 }
1872 return (1);
1873}
1874
1875STATIC int en_mfix(sc, mm, prev)
1876
1877struct en_softc *sc;
1878struct mbuf **mm, *prev;
1879
1880{
1881 struct mbuf *m;
1882 u_char *d, *cp;
1883 int off;
1884 struct mbuf *nxt;
1885
1886 m = *mm;
1887
1888 EN_COUNT(sc->mfix); /* count # of calls */
1889#ifdef EN_DEBUG
1890 printf("%s: mfix mbuf m_data=0x%x, m_len=%d\n", sc->sc_dev.dv_xname,
1891 m->m_data, m->m_len);
1892#endif
1893
1894 d = mtod(m, u_char *);
1895 off = ((uintptr_t) (void *) d) % sizeof(u_int32_t);
1896
1897 if (off) {
1898 if ((m->m_flags & M_EXT) == 0) {
1899 bcopy(d, d - off, m->m_len); /* ALIGN! (with costly data copy...) */
1900 d -= off;
1901 m->m_data = (caddr_t)d;
1902 } else {
1903 /* can't write to an M_EXT mbuf since it may be shared */
1904 if (en_makeexclusive(sc, &m, prev) == 0)
1905 return (0);
1906 *mm = m; /* note: 'd' now invalid */
1907 }
1908 }
1909
1910 off = m->m_len % sizeof(u_int32_t);
1911 if (off == 0)
1912 return(1);
1913
1914 if (m->m_flags & M_EXT) {
1915 /* can't write to an M_EXT mbuf since it may be shared */
1916 if (en_makeexclusive(sc, &m, prev) == 0)
1917 return (0);
1918 *mm = m; /* note: 'd' now invalid */
1919 }
1920
1921 d = mtod(m, u_char *) + m->m_len;
1922 off = sizeof(u_int32_t) - off;
1923
1924 nxt = m->m_next;
1925 while (off--) {
1926 if (nxt != NULL && nxt->m_len == 0) {
1927 /* remove an empty mbuf. this avoids odd byte padding to an empty
1928 last mbuf. */
1929 m->m_next = nxt = m_free(nxt);
1930 }
1931 if (nxt == NULL) { /* out of data, zero fill */
1932 *d++ = 0;
1933 continue; /* next "off" */
1934 }
1935 cp = mtod(nxt, u_char *);
1936 *d++ = *cp++;
1937 m->m_len++;
1938 nxt->m_len--;
1939 nxt->m_data = (caddr_t)cp;
1940 }
1941 if (nxt != NULL && nxt->m_len == 0)
1942 m->m_next = m_free(nxt);
1943 return(1);
1944}
1945
1946#endif /* __FreeBSD__ */
1947
1948/*
1949 * en_txdma: start trasmit DMA, if possible
1950 */
1951
1952STATIC void en_txdma(sc, chan)
1953
1954struct en_softc *sc;
1955int chan;
1956
1957{
1958 struct mbuf *tmp;
1959 struct atm_pseudohdr *ap;
1960 struct en_launch launch;
1961 int datalen = 0, dtqneed, len, ncells;
1962 u_int8_t *cp;
1963 struct ifnet *ifp;
1964
1965#ifdef EN_DEBUG
1966 printf("%s: tx%d: starting...\n", sc->sc_dev.dv_xname, chan);
1967#endif
1968
1969 /*
1970 * note: now that txlaunch handles non-word aligned/sized requests
1971 * the only time you can safely set launch.nodma is if you've en_mfix()'d
1972 * the mbuf chain. this happens only if EN_NOTXDMA || !en_dma.
1973 */
1974
1975 launch.nodma = (EN_NOTXDMA || !en_dma);
1976
1977again:
1978
1979 /*
1980 * get an mbuf waiting for DMA
1981 */
1982
1983 launch.t = sc->txslot[chan].q.ifq_head; /* peek at head of queue */
1984
1985 if (launch.t == NULL) {
1986#ifdef EN_DEBUG
1987 printf("%s: tx%d: ...done!\n", sc->sc_dev.dv_xname, chan);
1988#endif
1989 return; /* >>> exit here if no data waiting for DMA <<< */
1990 }
1991
1992 /*
1993 * get flags, vci
1994 *
1995 * note: launch.need = # bytes we need to get on the card
1996 * dtqneed = # of DTQs we need for this packet
1997 * launch.mlen = # of bytes in in mbuf chain (<= launch.need)
1998 */
1999
2000 ap = mtod(launch.t, struct atm_pseudohdr *);
2001 launch.atm_vci = ATM_PH_VCI(ap);
2002 launch.atm_flags = ATM_PH_FLAGS(ap);
2003 launch.aal = ((launch.atm_flags & ATM_PH_AAL5) != 0) ?
2004 MID_TBD_AAL5 : MID_TBD_NOAAL5;
2005
2006 /*
2007 * XXX: have to recompute the length again, even though we already did
2008 * it in en_start(). might as well compute dtqneed here as well, so
2009 * this isn't that bad.
2010 */
2011
2012 if ((launch.atm_flags & EN_OBHDR) == 0) {
2013 dtqneed = 1; /* header still needs to be added */
2014 launch.need = MID_TBD_SIZE; /* not includeded with mbuf */
2015 } else {
2016 dtqneed = 0; /* header on-board, dma with mbuf */
2017 launch.need = 0;
2018 }
2019
2020 launch.mlen = 0;
2021 for (tmp = launch.t ; tmp != NULL ; tmp = tmp->m_next) {
2022 len = tmp->m_len;
2023 launch.mlen += len;
2024 cp = mtod(tmp, u_int8_t *);
2025 if (tmp == launch.t) {
2026 len -= sizeof(struct atm_pseudohdr); /* don't count this! */
2027 cp += sizeof(struct atm_pseudohdr);
2028 }
2029 launch.need += len;
2030 if (len == 0)
2031 continue; /* atm_pseudohdr alone in first mbuf */
2032
2033 dtqneed += en_dqneed(sc, (caddr_t) cp, len, 1);
2034 }
2035
2036 if ((launch.need % sizeof(u_int32_t)) != 0)
2037 dtqneed++; /* need DTQ to FLUSH internal buffer */
2038
2039 if ((launch.atm_flags & EN_OBTRL) == 0) {
2040 if (launch.aal == MID_TBD_AAL5) {
2041 datalen = launch.need - MID_TBD_SIZE;
2042 launch.need += MID_PDU_SIZE; /* AAL5: need PDU tail */
2043 }
2044 dtqneed++; /* need to work on the end a bit */
2045 }
2046
2047 /*
2048 * finish calculation of launch.need (need to figure out how much padding
2049 * we will need). launch.need includes MID_TBD_SIZE, but we need to
2050 * remove that to so we can round off properly. we have to add
2051 * MID_TBD_SIZE back in after calculating ncells.
2052 */
2053
2054 launch.need = roundup(launch.need - MID_TBD_SIZE, MID_ATMDATASZ);
2055 ncells = launch.need / MID_ATMDATASZ;
2056 launch.need += MID_TBD_SIZE;
2057
2058 if (launch.need > EN_TXSZ * 1024) {
2059 printf("%s: tx%d: packet larger than xmit buffer (%d > %d)\n",
2060 sc->sc_dev.dv_xname, chan, launch.need, EN_TXSZ * 1024);
2061 goto dequeue_drop;
2062 }
2063
2064 /*
2065 * note: don't use the entire buffer space. if WRTX becomes equal
2066 * to RDTX, the transmitter stops assuming the buffer is empty! --kjc
2067 */
2068 if (launch.need >= sc->txslot[chan].bfree) {
2069 EN_COUNT(sc->txoutspace);
2070#ifdef EN_DEBUG
2071 printf("%s: tx%d: out of transmit space\n", sc->sc_dev.dv_xname, chan);
2072#endif
2073 return; /* >>> exit here if out of obmem buffer space <<< */
2074 }
2075
2076 /*
2077 * ensure we have enough dtqs to go, if not, wait for more.
2078 */
2079
2080 if (launch.nodma) {
2081 dtqneed = 1;
2082 }
2083 if (dtqneed > sc->dtq_free) {
2084 sc->need_dtqs = 1;
2085 EN_COUNT(sc->txdtqout);
2086#ifdef EN_DEBUG
2087 printf("%s: tx%d: out of transmit DTQs\n", sc->sc_dev.dv_xname, chan);
2088#endif
2089 return; /* >>> exit here if out of dtqs <<< */
2090 }
2091
2092 /*
2093 * it is a go, commit! dequeue mbuf start working on the xfer.
2094 */
2095
2096 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2097#ifdef EN_DIAG
2098 if (launch.t != tmp)
2099 panic("en dequeue");
2100#endif /* EN_DIAG */
2101
2102 /*
2103 * launch!
2104 */
2105
2106 EN_COUNT(sc->launch);
2107 ifp = &sc->enif;
2108 ifp->if_opackets++;
2109
2110 if ((launch.atm_flags & EN_OBHDR) == 0) {
2111 EN_COUNT(sc->lheader);
2112 /* store tbd1/tbd2 in host byte order */
2113 launch.tbd1 = MID_TBD_MK1(launch.aal, sc->txspeed[launch.atm_vci], ncells);
2114 launch.tbd2 = MID_TBD_MK2(launch.atm_vci, 0, 0);
2115 }
2116 if ((launch.atm_flags & EN_OBTRL) == 0 && launch.aal == MID_TBD_AAL5) {
2117 EN_COUNT(sc->ltail);
2118 launch.pdu1 = MID_PDU_MK1(0, 0, datalen); /* host byte order */
2119 }
2120
2121 en_txlaunch(sc, chan, &launch);
2122
2123#if NBPF > 0
2124 if (ifp->if_bpf) {
2125 /*
2126 * adjust the top of the mbuf to skip the pseudo atm header
2127 * (and TBD, if present) before passing the packet to bpf,
2128 * restore it afterwards.
2129 */
2130 int size = sizeof(struct atm_pseudohdr);
2131 if (launch.atm_flags & EN_OBHDR)
2132 size += MID_TBD_SIZE;
2133
2134 launch.t->m_data += size;
2135 launch.t->m_len -= size;
2136
2137 BPF_MTAP(ifp, launch.t);
2138
2139 launch.t->m_data -= size;
2140 launch.t->m_len += size;
2141 }
2142#endif /* NBPF > 0 */
2143 /*
2144 * do some housekeeping and get the next packet
2145 */
2146
2147 sc->txslot[chan].bfree -= launch.need;
2148 IF_ENQUEUE(&sc->txslot[chan].indma, launch.t);
2149 goto again;
2150
2151 /*
2152 * END of txdma loop!
2153 */
2154
2155 /*
2156 * error handles
2157 */
2158
2159dequeue_drop:
2160 IF_DEQUEUE(&sc->txslot[chan].q, tmp);
2161 if (launch.t != tmp)
2162 panic("en dequeue drop");
2163 m_freem(launch.t);
2164 sc->txslot[chan].mbsize -= launch.mlen;
2165 goto again;
2166}
2167
2168
2169/*
2170 * en_txlaunch: launch an mbuf into the dma pool!
2171 */
2172
2173STATIC void en_txlaunch(sc, chan, l)
2174
2175struct en_softc *sc;
2176int chan;
2177struct en_launch *l;
2178
2179{
2180 struct mbuf *tmp;
2181 u_int32_t cur = sc->txslot[chan].cur,
2182 start = sc->txslot[chan].start,
2183 stop = sc->txslot[chan].stop,
2184 dma, *data, *datastop, count, bcode;
2185 int pad, addtail, need, len, needalign, cnt, end, mx;
2186
2187
2188 /*
2189 * vars:
2190 * need = # bytes card still needs (decr. to zero)
2191 * len = # of bytes left in current mbuf
2192 * cur = our current pointer
2193 * dma = last place we programmed into the DMA
2194 * data = pointer into data area of mbuf that needs to go next
2195 * cnt = # of bytes to transfer in this DTQ
2196 * bcode/count = DMA burst code, and chip's version of cnt
2197 *
2198 * a single buffer can require up to 5 DTQs depending on its size
2199 * and alignment requirements. the 5 possible requests are:
2200 * [1] 1, 2, or 3 byte DMA to align src data pointer to word boundary
2201 * [2] alburst DMA to align src data pointer to bestburstlen
2202 * [3] 1 or more bestburstlen DMAs
2203 * [4] clean up burst (to last word boundary)
2204 * [5] 1, 2, or 3 byte final clean up DMA
2205 */
2206
2207 need = l->need;
2208 dma = cur;
2209 addtail = (l->atm_flags & EN_OBTRL) == 0; /* add a tail? */
2210
2211#ifdef EN_DIAG
2212 if ((need - MID_TBD_SIZE) % MID_ATMDATASZ)
2213 printf("%s: tx%d: bogus trasmit needs (%d)\n", sc->sc_dev.dv_xname, chan,
2214 need);
2215#endif
2216#ifdef EN_DEBUG
2217 printf("%s: tx%d: launch mbuf %p! cur=0x%x[%d], need=%d, addtail=%d\n",
2218 sc->sc_dev.dv_xname, chan, l->t, cur, (cur-start)/4, need, addtail);
2219 count = EN_READ(sc, MIDX_PLACE(chan));
2220 printf(" HW: base_address=0x%x, size=%d, read=%d, descstart=%d\n",
2221 MIDX_BASE(count), MIDX_SZ(count), EN_READ(sc, MIDX_READPTR(chan)),
2222 EN_READ(sc, MIDX_DESCSTART(chan)));
2223#endif
2224
2225 /*
2226 * do we need to insert the TBD by hand?
2227 * note that tbd1/tbd2/pdu1 are in host byte order.
2228 */
2229
2230 if ((l->atm_flags & EN_OBHDR) == 0) {
2231#ifdef EN_DEBUG
2232 printf("%s: tx%d: insert header 0x%x 0x%x\n", sc->sc_dev.dv_xname,
2233 chan, l->tbd1, l->tbd2);
2234#endif
2235 EN_WRITE(sc, cur, l->tbd1);
2236 EN_WRAPADD(start, stop, cur, 4);
2237 EN_WRITE(sc, cur, l->tbd2);
2238 EN_WRAPADD(start, stop, cur, 4);
2239 need -= 8;
2240 }
2241
2242 /*
2243 * now do the mbufs...
2244 */
2245
2246 for (tmp = l->t ; tmp != NULL ; tmp = tmp->m_next) {
2247
2248 /* get pointer to data and length */
2249 data = mtod(tmp, u_int32_t *);
2250 len = tmp->m_len;
2251 if (tmp == l->t) {
2252 data += sizeof(struct atm_pseudohdr)/sizeof(u_int32_t);
2253 len -= sizeof(struct atm_pseudohdr);
2254 }
2255
2256 /* now, determine if we should copy it */
2257 if (l->nodma || (len < EN_MINDMA &&
2258 (len % 4) == 0 && ((uintptr_t) (void *) data % 4) == 0 &&
2259 (cur % 4) == 0)) {
2260
2261 /*
2262 * roundup len: the only time this will change the value of len
2263 * is when l->nodma is true, tmp is the last mbuf, and there is
2264 * a non-word number of bytes to transmit. in this case it is
2265 * safe to round up because we've en_mfix'd the mbuf (so the first
2266 * byte is word aligned there must be enough free bytes at the end
2267 * to round off to the next word boundary)...
2268 */
2269 len = roundup(len, sizeof(u_int32_t));
2270 datastop = data + (len / sizeof(u_int32_t));
2271 /* copy loop: preserve byte order!!! use WRITEDAT */
2272 while (data != datastop) {
2273 EN_WRITEDAT(sc, cur, *data);
2274 data++;
2275 EN_WRAPADD(start, stop, cur, 4);
2276 }
2277 need -= len;
2278#ifdef EN_DEBUG
2279 printf("%s: tx%d: copied %d bytes (%d left, cur now 0x%x)\n",
2280 sc->sc_dev.dv_xname, chan, len, need, cur);
2281#endif
2282 continue; /* continue on to next mbuf */
2283 }
2284
2285 /* going to do DMA, first make sure the dtq is in sync. */
2286 if (dma != cur) {
2287 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0, 0, 0);
2288#ifdef EN_DEBUG
2289 printf("%s: tx%d: dtq_sync: advance pointer to %d\n",
2290 sc->sc_dev.dv_xname, chan, cur);
2291#endif
2292 }
2293
2294 /*
2295 * if this is the last buffer, and it looks like we are going to need to
2296 * flush the internal buffer, can we extend the length of this mbuf to
2297 * avoid the FLUSH?
2298 */
2299
2300 if (tmp->m_next == NULL) {
2301 cnt = (need - len) % sizeof(u_int32_t);
2302 if (cnt && M_TRAILINGSPACE(tmp) >= cnt)
2303 len += cnt; /* pad for FLUSH */
2304 }
2305
2306#if !defined(MIDWAY_ENIONLY)
2307
2308 /*
2309 * the adaptec DMA engine is smart and handles everything for us.
2310 */
2311
2312 if (sc->is_adaptec) {
2313 /* need to DMA "len" bytes out to card */
2314 need -= len;
2315 EN_WRAPADD(start, stop, cur, len);
2316#ifdef EN_DEBUG
2317 printf("%s: tx%d: adp_dma %d bytes (%d left, cur now 0x%x)\n",
2318 sc->sc_dev.dv_xname, chan, len, need, cur);
2319#endif
2320 end = (need == 0) ? MID_DMA_END : 0;
2321 EN_DTQADD(sc, len, chan, 0, vtophys(data), l->mlen, end);
2322 if (end)
2323 goto done;
2324 dma = cur; /* update dma pointer */
2325 continue;
2326 }
2327#endif /* !MIDWAY_ENIONLY */
2328
2329#if !defined(MIDWAY_ADPONLY)
2330
2331 /*
2332 * the ENI DMA engine is not so smart and need more help from us
2333 */
2334
2335 /* do we need to do a DMA op to align to word boundary? */
2336 needalign = (uintptr_t) (void *) data % sizeof(u_int32_t);
2337 if (needalign) {
2338 EN_COUNT(sc->headbyte);
2339 cnt = sizeof(u_int32_t) - needalign;
2340 if (cnt == 2 && len >= cnt) {
2341 count = 1;
2342 bcode = MIDDMA_2BYTE;
2343 } else {
2344 cnt = min(cnt, len); /* prevent overflow */
2345 count = cnt;
2346 bcode = MIDDMA_BYTE;
2347 }
2348 need -= cnt;
2349 EN_WRAPADD(start, stop, cur, cnt);
2350#ifdef EN_DEBUG
2351 printf("%s: tx%d: small al_dma %d bytes (%d left, cur now 0x%x)\n",
2352 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2353#endif
2354 len -= cnt;
2355 end = (need == 0) ? MID_DMA_END : 0;
2356 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2357 if (end)
2358 goto done;
2359 data = (u_int32_t *) ((u_char *)data + cnt);
2360 }
2361
2362 /* do we need to do a DMA op to align? */
2363 if (sc->alburst &&
2364 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0
2365 && len >= sizeof(u_int32_t)) {
2366 cnt = sc->bestburstlen - needalign;
2367 mx = len & ~(sizeof(u_int32_t)-1); /* don't go past end */
2368 if (cnt > mx) {
2369 cnt = mx;
2370 count = cnt / sizeof(u_int32_t);
2371 bcode = MIDDMA_WORD;
2372 } else {
2373 count = cnt / sizeof(u_int32_t);
2374 bcode = en_dmaplan[count].bcode;
2375 count = cnt >> en_dmaplan[count].divshift;
2376 }
2377 need -= cnt;
2378 EN_WRAPADD(start, stop, cur, cnt);
2379#ifdef EN_DEBUG
2380 printf("%s: tx%d: al_dma %d bytes (%d left, cur now 0x%x)\n",
2381 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2382#endif
2383 len -= cnt;
2384 end = (need == 0) ? MID_DMA_END : 0;
2385 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2386 if (end)
2387 goto done;
2388 data = (u_int32_t *) ((u_char *)data + cnt);
2389 }
2390
2391 /* do we need to do a max-sized burst? */
2392 if (len >= sc->bestburstlen) {
2393 count = len >> sc->bestburstshift;
2394 cnt = count << sc->bestburstshift;
2395 bcode = sc->bestburstcode;
2396 need -= cnt;
2397 EN_WRAPADD(start, stop, cur, cnt);
2398#ifdef EN_DEBUG
2399 printf("%s: tx%d: best_dma %d bytes (%d left, cur now 0x%x)\n",
2400 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2401#endif
2402 len -= cnt;
2403 end = (need == 0) ? MID_DMA_END : 0;
2404 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2405 if (end)
2406 goto done;
2407 data = (u_int32_t *) ((u_char *)data + cnt);
2408 }
2409
2410 /* do we need to do a cleanup burst? */
2411 cnt = len & ~(sizeof(u_int32_t)-1);
2412 if (cnt) {
2413 count = cnt / sizeof(u_int32_t);
2414 bcode = en_dmaplan[count].bcode;
2415 count = cnt >> en_dmaplan[count].divshift;
2416 need -= cnt;
2417 EN_WRAPADD(start, stop, cur, cnt);
2418#ifdef EN_DEBUG
2419 printf("%s: tx%d: cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2420 sc->sc_dev.dv_xname, chan, cnt, need, cur);
2421#endif
2422 len -= cnt;
2423 end = (need == 0) ? MID_DMA_END : 0;
2424 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2425 if (end)
2426 goto done;
2427 data = (u_int32_t *) ((u_char *)data + cnt);
2428 }
2429
2430 /* any word fragments left? */
2431 if (len) {
2432 EN_COUNT(sc->tailbyte);
2433 if (len == 2) {
2434 count = 1;
2435 bcode = MIDDMA_2BYTE; /* use 2byte mode */
2436 } else {
2437 count = len;
2438 bcode = MIDDMA_BYTE; /* use 1 byte mode */
2439 }
2440 need -= len;
2441 EN_WRAPADD(start, stop, cur, len);
2442#ifdef EN_DEBUG
2443 printf("%s: tx%d: byte cleanup_dma %d bytes (%d left, cur now 0x%x)\n",
2444 sc->sc_dev.dv_xname, chan, len, need, cur);
2445#endif
2446 end = (need == 0) ? MID_DMA_END : 0;
2447 EN_DTQADD(sc, count, chan, bcode, vtophys(data), l->mlen, end);
2448 if (end)
2449 goto done;
2450 }
2451
2452 dma = cur; /* update dma pointer */
2453#endif /* !MIDWAY_ADPONLY */
2454
2455 } /* next mbuf, please */
2456
2457 /*
2458 * all mbuf data has been copied out to the obmem (or set up to be DMAd).
2459 * if the trailer or padding needs to be put in, do it now.
2460 *
2461 * NOTE: experimental results reveal the following fact:
2462 * if you DMA "X" bytes to the card, where X is not a multiple of 4,
2463 * then the card will internally buffer the last (X % 4) bytes (in
2464 * hopes of getting (4 - (X % 4)) more bytes to make a complete word).
2465 * it is imporant to make sure we don't leave any important data in
2466 * this internal buffer because it is discarded on the last (end) DTQ.
2467 * one way to do this is to DMA in (4 - (X % 4)) more bytes to flush
2468 * the darn thing out.
2469 */
2470
2471 if (addtail) {
2472
2473 pad = need % sizeof(u_int32_t);
2474 if (pad) {
2475 /*
2476 * FLUSH internal data buffer. pad out with random data from the front
2477 * of the mbuf chain...
2478 */
2479 bcode = (sc->is_adaptec) ? 0 : MIDDMA_BYTE;
2480 EN_COUNT(sc->tailflush);
2481 EN_WRAPADD(start, stop, cur, pad);
2482 EN_DTQADD(sc, pad, chan, bcode, vtophys(l->t->m_data), 0, 0);
2483 need -= pad;
2484#ifdef EN_DEBUG
2485 printf("%s: tx%d: pad/FLUSH dma %d bytes (%d left, cur now 0x%x)\n",
2486 sc->sc_dev.dv_xname, chan, pad, need, cur);
2487#endif
2488 }
2489
2490 /* copy data */
2491 pad = need / sizeof(u_int32_t); /* round *down* */
2492 if (l->aal == MID_TBD_AAL5)
2493 pad -= 2;
2494#ifdef EN_DEBUG
2495 printf("%s: tx%d: padding %d bytes (cur now 0x%x)\n",
2496 sc->sc_dev.dv_xname, chan, pad * sizeof(u_int32_t), cur);
2497#endif
2498 while (pad--) {
2499 EN_WRITEDAT(sc, cur, 0); /* no byte order issues with zero */
2500 EN_WRAPADD(start, stop, cur, 4);
2501 }
2502 if (l->aal == MID_TBD_AAL5) {
2503 EN_WRITE(sc, cur, l->pdu1); /* in host byte order */
2504 EN_WRAPADD(start, stop, cur, 8);
2505 }
2506 }
2507
2508 if (addtail || dma != cur) {
2509 /* write final descritor */
2510 EN_DTQADD(sc, WORD_IDX(start,cur), chan, MIDDMA_JK, 0,
2511 l->mlen, MID_DMA_END);
2512 /* dma = cur; */ /* not necessary since we are done */
2513 }
2514
2515done:
2516 /* update current pointer */
2517 sc->txslot[chan].cur = cur;
2518#ifdef EN_DEBUG
2519 printf("%s: tx%d: DONE! cur now = 0x%x\n",
2520 sc->sc_dev.dv_xname, chan, cur);
2521#endif
2522
2523 return;
2524}
2525
2526
2527/*
2528 * interrupt handler
2529 */
2530
2531EN_INTR_TYPE en_intr(arg)
2532
2533void *arg;
2534
2535{
2536 struct en_softc *sc = (struct en_softc *) arg;
2537 struct mbuf *m;
2538 struct atm_pseudohdr ah;
2539 struct ifnet *ifp;
2540 u_int32_t reg, kick, val, mask, chip, vci, slot, dtq, drq;
2541 int lcv, idx, need_softserv = 0;
2542
2543 reg = EN_READ(sc, MID_INTACK);
2544
2545 if ((reg & MID_INT_ANY) == 0)
2546 EN_INTR_RET(0); /* not us */
2547
2548#ifdef EN_DEBUG
2549 printf("%s: interrupt=0x%b\n", sc->sc_dev.dv_xname, reg, MID_INTBITS);
2550#endif
2551
2552 /*
2553 * unexpected errors that need a reset
2554 */
2555
2556 if ((reg & (MID_INT_IDENT|MID_INT_LERR|MID_INT_DMA_ERR|MID_INT_SUNI)) != 0) {
2557 printf("%s: unexpected interrupt=0x%b, resetting card\n",
2558 sc->sc_dev.dv_xname, reg, MID_INTBITS);
2559#ifdef EN_DEBUG
2560#ifdef DDB
2561#ifdef __FreeBSD__
2562 Debugger("en: unexpected error");
2563#else
2564 Debugger();
2565#endif
2566#endif /* DDB */
2567 sc->enif.if_flags &= ~IFF_RUNNING; /* FREEZE! */
2568#else
2569 en_reset(sc);
2570 en_init(sc);
2571#endif
2572 EN_INTR_RET(1); /* for us */
2573 }
2574
2575 /*******************
2576 * xmit interrupts *
2577 ******************/
2578
2579 kick = 0; /* bitmask of channels to kick */
2580 if (reg & MID_INT_TX) { /* TX done! */
2581
2582 /*
2583 * check for tx complete, if detected then this means that some space
2584 * has come free on the card. we must account for it and arrange to
2585 * kick the channel to life (in case it is stalled waiting on the card).
2586 */
2587 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2588 if (reg & MID_TXCHAN(lcv)) {
2589 kick = kick | mask; /* want to kick later */
2590 val = EN_READ(sc, MIDX_READPTR(lcv)); /* current read pointer */
2591 val = (val * sizeof(u_int32_t)) + sc->txslot[lcv].start;
2592 /* convert to offset */
2593 if (val > sc->txslot[lcv].cur)
2594 sc->txslot[lcv].bfree = val - sc->txslot[lcv].cur;
2595 else
2596 sc->txslot[lcv].bfree = (val + (EN_TXSZ*1024)) - sc->txslot[lcv].cur;
2597#ifdef EN_DEBUG
2598 printf("%s: tx%d: trasmit done. %d bytes now free in buffer\n",
2599 sc->sc_dev.dv_xname, lcv, sc->txslot[lcv].bfree);
2600#endif
2601 }
2602 }
2603 }
2604
2605 if (reg & MID_INT_DMA_TX) { /* TX DMA done! */
2606
2607 /*
2608 * check for TX DMA complete, if detected then this means that some DTQs
2609 * are now free. it also means some indma mbufs can be freed.
2610 * if we needed DTQs, kick all channels.
2611 */
2612 val = EN_READ(sc, MID_DMA_RDTX); /* chip's current location */
2613 idx = MID_DTQ_A2REG(sc->dtq_chip);/* where we last saw chip */
2614 if (sc->need_dtqs) {
2615 kick = MID_NTX_CH - 1; /* assume power of 2, kick all! */
2616 sc->need_dtqs = 0; /* recalculated in "kick" loop below */
2617#ifdef EN_DEBUG
2618 printf("%s: cleared need DTQ condition\n", sc->sc_dev.dv_xname);
2619#endif
2620 }
2621 while (idx != val) {
2622 sc->dtq_free++;
2623 if ((dtq = sc->dtq[idx]) != 0) {
2624 sc->dtq[idx] = 0; /* don't forget to zero it out when done */
2625 slot = EN_DQ_SLOT(dtq);
2626 IF_DEQUEUE(&sc->txslot[slot].indma, m);
2627 if (!m) panic("enintr: dtqsync");
2628 sc->txslot[slot].mbsize -= EN_DQ_LEN(dtq);
2629#ifdef EN_DEBUG
2630 printf("%s: tx%d: free %d dma bytes, mbsize now %d\n",
2631 sc->sc_dev.dv_xname, slot, EN_DQ_LEN(dtq),
2632 sc->txslot[slot].mbsize);
2633#endif
2634 m_freem(m);
2635 }
2636 EN_WRAPADD(0, MID_DTQ_N, idx, 1);
2637 };
2638 sc->dtq_chip = MID_DTQ_REG2A(val); /* sync softc */
2639 }
2640
2641
2642 /*
2643 * kick xmit channels as needed
2644 */
2645
2646 if (kick) {
2647#ifdef EN_DEBUG
2648 printf("%s: tx kick mask = 0x%x\n", sc->sc_dev.dv_xname, kick);
2649#endif
2650 for (mask = 1, lcv = 0 ; lcv < EN_NTX ; lcv++, mask = mask * 2) {
2651 if ((kick & mask) && sc->txslot[lcv].q.ifq_head) {
2652 en_txdma(sc, lcv); /* kick it! */
2653 }
2654 } /* for each slot */
2655 } /* if kick */
2656
2657
2658 /*******************
2659 * recv interrupts *
2660 ******************/
2661
2662 /*
2663 * check for RX DMA complete, and pass the data "upstairs"
2664 */
2665
2666 if (reg & MID_INT_DMA_RX) {
2667 val = EN_READ(sc, MID_DMA_RDRX); /* chip's current location */
2668 idx = MID_DRQ_A2REG(sc->drq_chip);/* where we last saw chip */
2669 while (idx != val) {
2670 sc->drq_free++;
2671 if ((drq = sc->drq[idx]) != 0) {
2672 sc->drq[idx] = 0; /* don't forget to zero it out when done */
2673 slot = EN_DQ_SLOT(drq);
2674 if (EN_DQ_LEN(drq) == 0) { /* "JK" trash DMA? */
2675 m = NULL;
2676 } else {
2677 IF_DEQUEUE(&sc->rxslot[slot].indma, m);
2678 if (!m)
2679 panic("enintr: drqsync: %s: lost mbuf in slot %d!",
2680 sc->sc_dev.dv_xname, slot);
2681 }
2682 /* do something with this mbuf */
2683 if (sc->rxslot[slot].oth_flags & ENOTHER_DRAIN) { /* drain? */
2684 if (m)
2685 m_freem(m);
2686 vci = sc->rxslot[slot].atm_vci;
2687 if (sc->rxslot[slot].indma.ifq_head == NULL &&
2688 sc->rxslot[slot].q.ifq_head == NULL &&
2689 (EN_READ(sc, MID_VC(vci)) & MIDV_INSERVICE) == 0 &&
2690 (sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2691 sc->rxslot[slot].oth_flags = ENOTHER_FREE; /* done drain */
2692 sc->rxslot[slot].atm_vci = RX_NONE;
2693 sc->rxvc2slot[vci] = RX_NONE;
2694#ifdef EN_DEBUG
2695 printf("%s: rx%d: VCI %d now free\n", sc->sc_dev.dv_xname,
2696 slot, vci);
2697#endif
2698 }
2699 } else if (m != NULL) {
2700 ATM_PH_FLAGS(&ah) = sc->rxslot[slot].atm_flags;
2701 ATM_PH_VPI(&ah) = 0;
2702 ATM_PH_SETVCI(&ah, sc->rxslot[slot].atm_vci);
2703#ifdef EN_DEBUG
2704 printf("%s: rx%d: rxvci%d: atm_input, mbuf %p, len %d, hand %p\n",
2705 sc->sc_dev.dv_xname, slot, sc->rxslot[slot].atm_vci, m,
2706 EN_DQ_LEN(drq), sc->rxslot[slot].rxhand);
2707#endif
2708
2709 ifp = &sc->enif;
2710 ifp->if_ipackets++;
2711
2712#if NBPF > 0
2713 if (ifp->if_bpf)
2714 BPF_MTAP(ifp, m);
2715#endif
2716
2717 atm_input(ifp, &ah, m, sc->rxslot[slot].rxhand);
2718 }
2719
2720 }
2721 EN_WRAPADD(0, MID_DRQ_N, idx, 1);
2722 };
2723 sc->drq_chip = MID_DRQ_REG2A(val); /* sync softc */
2724
2725 if (sc->need_drqs) { /* true if we had a DRQ shortage */
2726 need_softserv = 1;
2727 sc->need_drqs = 0;
2728#ifdef EN_DEBUG
2729 printf("%s: cleared need DRQ condition\n", sc->sc_dev.dv_xname);
2730#endif
2731 }
2732 }
2733
2734 /*
2735 * handle service interrupts
2736 */
2737
2738 if (reg & MID_INT_SERVICE) {
2739 chip = MID_SL_REG2A(EN_READ(sc, MID_SERV_WRITE));
2740
2741 while (sc->hwslistp != chip) {
2742
2743 /* fetch and remove it from hardware service list */
2744 vci = EN_READ(sc, sc->hwslistp);
2745 EN_WRAPADD(MID_SLOFF, MID_SLEND, sc->hwslistp, 4);/* advance hw ptr */
2746 slot = sc->rxvc2slot[vci];
2747 if (slot == RX_NONE) {
2748#ifdef EN_DEBUG
2749 printf("%s: unexpected rx interrupt on VCI %d\n",
2750 sc->sc_dev.dv_xname, vci);
2751#endif
2752 EN_WRITE(sc, MID_VC(vci), MIDV_TRASH); /* rx off, damn it! */
2753 continue; /* next */
2754 }
2755 EN_WRITE(sc, MID_VC(vci), sc->rxslot[slot].mode); /* remove from hwsl */
2756 EN_COUNT(sc->hwpull);
2757
2758#ifdef EN_DEBUG
2759 printf("%s: pulled VCI %d off hwslist\n", sc->sc_dev.dv_xname, vci);
2760#endif
2761
2762 /* add it to the software service list (if needed) */
2763 if ((sc->rxslot[slot].oth_flags & ENOTHER_SWSL) == 0) {
2764 EN_COUNT(sc->swadd);
2765 need_softserv = 1;
2766 sc->rxslot[slot].oth_flags |= ENOTHER_SWSL;
2767 sc->swslist[sc->swsl_tail] = slot;
2768 EN_WRAPADD(0, MID_SL_N, sc->swsl_tail, 1);
2769 sc->swsl_size++;
2770#ifdef EN_DEBUG
2771 printf("%s: added VCI %d to swslist\n", sc->sc_dev.dv_xname, vci);
2772#endif
2773 }
2774 };
2775 }
2776
2777 /*
2778 * now service (function too big to include here)
2779 */
2780
2781 if (need_softserv)
2782 en_service(sc);
2783
2784 /*
2785 * keep our stats
2786 */
2787
2788 if (reg & MID_INT_DMA_OVR) {
2789 EN_COUNT(sc->dmaovr);
2790#ifdef EN_DEBUG
2791 printf("%s: MID_INT_DMA_OVR\n", sc->sc_dev.dv_xname);
2792#endif
2793 }
2794 reg = EN_READ(sc, MID_STAT);
2795#ifdef EN_STAT
2796 sc->otrash += MID_OTRASH(reg);
2797 sc->vtrash += MID_VTRASH(reg);
2798#endif
2799
2800 EN_INTR_RET(1); /* for us */
2801}
2802
2803
2804/*
2805 * en_service: handle a service interrupt
2806 *
2807 * Q: why do we need a software service list?
2808 *
2809 * A: if we remove a VCI from the hardware list and we find that we are
2810 * out of DRQs we must defer processing until some DRQs become free.
2811 * so we must remember to look at this RX VCI/slot later, but we can't
2812 * put it back on the hardware service list (since that isn't allowed).
2813 * so we instead save it on the software service list. it would be nice
2814 * if we could peek at the VCI on top of the hwservice list without removing
2815 * it, however this leads to a race condition: if we peek at it and
2816 * decide we are done with it new data could come in before we have a
2817 * chance to remove it from the hwslist. by the time we get it out of
2818 * the list the interrupt for the new data will be lost. oops!
2819 *
2820 */
2821
2822STATIC void en_service(sc)
2823
2824struct en_softc *sc;
2825
2826{
2827 struct mbuf *m, *tmp;
2828 u_int32_t cur, dstart, rbd, pdu, *sav, dma, bcode, count, *data, *datastop;
2829 u_int32_t start, stop, cnt, needalign;
2830 int slot, raw, aal5, llc, vci, fill, mlen, tlen, drqneed, need, needfill, end;
2831
2832 aal5 = 0; /* Silence gcc */
2833next_vci:
2834 if (sc->swsl_size == 0) {
2835#ifdef EN_DEBUG
2836 printf("%s: en_service done\n", sc->sc_dev.dv_xname);
2837#endif
2838 return; /* >>> exit here if swsl now empty <<< */
2839 }
2840
2841 /*
2842 * get slot/vci to service
2843 */
2844
2845 slot = sc->swslist[sc->swsl_head];
2846 vci = sc->rxslot[slot].atm_vci;
2847#ifdef EN_DIAG
2848 if (sc->rxvc2slot[vci] != slot) panic("en_service rx slot/vci sync");
2849#endif
2850
2851 /*
2852 * determine our mode and if we've got any work to do
2853 */
2854
2855 raw = sc->rxslot[slot].oth_flags & ENOTHER_RAW;
2856 start= sc->rxslot[slot].start;
2857 stop= sc->rxslot[slot].stop;
2858 cur = sc->rxslot[slot].cur;
2859
2860#ifdef EN_DEBUG
2861 printf("%s: rx%d: service vci=%d raw=%d start/stop/cur=0x%x 0x%x 0x%x\n",
2862 sc->sc_dev.dv_xname, slot, vci, raw, start, stop, cur);
2863#endif
2864
2865same_vci:
2866 dstart = MIDV_DSTART(EN_READ(sc, MID_DST_RP(vci)));
2867 dstart = (dstart * sizeof(u_int32_t)) + start;
2868
2869 /* check to see if there is any data at all */
2870 if (dstart == cur) {
2871defer: /* defer processing */
2872 EN_WRAPADD(0, MID_SL_N, sc->swsl_head, 1);
2873 sc->rxslot[slot].oth_flags &= ~ENOTHER_SWSL;
2874 sc->swsl_size--;
2875 /* >>> remove from swslist <<< */
2876#ifdef EN_DEBUG
2877 printf("%s: rx%d: remove vci %d from swslist\n",
2878 sc->sc_dev.dv_xname, slot, vci);
2879#endif
2880 goto next_vci;
2881 }
2882
2883 /*
2884 * figure out how many bytes we need
2885 * [mlen = # bytes to go in mbufs, fill = # bytes to dump (MIDDMA_JK)]
2886 */
2887
2888 if (raw) {
2889
2890 /* raw mode (aka boodi mode) */
2891 fill = 0;
2892 if (dstart > cur)
2893 mlen = dstart - cur;
2894 else
2895 mlen = (dstart + (EN_RXSZ*1024)) - cur;
2896
2897 if (mlen < sc->rxslot[slot].raw_threshold)
2898 goto defer; /* too little data to deal with */
2899
2900 } else {
2901
2902 /* normal mode */
2903 aal5 = (sc->rxslot[slot].atm_flags & ATM_PH_AAL5);
2904 llc = (aal5 && (sc->rxslot[slot].atm_flags & ATM_PH_LLCSNAP)) ? 1 : 0;
2905 rbd = EN_READ(sc, cur);
2906 if (MID_RBD_ID(rbd) != MID_RBD_STDID)
2907 panic("en_service: id mismatch");
2908
2909 if (rbd & MID_RBD_T) {
2910 mlen = 0; /* we've got trash */
2911 fill = MID_RBD_SIZE;
2912 EN_COUNT(sc->ttrash);
2913#ifdef EN_DEBUG
2914 printf("RX overflow lost %d cells!\n", MID_RBD_CNT(rbd));
2915#endif
2916 } else if (!aal5) {
2917 mlen = MID_RBD_SIZE + MID_CHDR_SIZE + MID_ATMDATASZ; /* 1 cell (ick!) */
2918 fill = 0;
2919 } else {
2920 struct ifnet *ifp;
2921
2922 tlen = (MID_RBD_CNT(rbd) * MID_ATMDATASZ) + MID_RBD_SIZE;
2923 pdu = cur + tlen - MID_PDU_SIZE;
2924 if (pdu >= stop)
2925 pdu -= (EN_RXSZ*1024);
2926 pdu = EN_READ(sc, pdu); /* get PDU in correct byte order */
2927 fill = tlen - MID_RBD_SIZE - MID_PDU_LEN(pdu);
2928 if (fill < 0 || (rbd & MID_RBD_CRCERR) != 0) {
2929 static int first = 1;
2930
2931 if (first) {
2932 printf("%s: %s, dropping frame\n", sc->sc_dev.dv_xname,
2933 (rbd & MID_RBD_CRCERR) ?
2934 "CRC error" : "invalid AAL5 PDU length");
2935 printf("%s: got %d cells (%d bytes), AAL5 len is %d bytes (pdu=0x%x)\n",
2936 sc->sc_dev.dv_xname, MID_RBD_CNT(rbd),
2937 tlen - MID_RBD_SIZE, MID_PDU_LEN(pdu), pdu);
2938#ifndef EN_DEBUG
2939 printf("CRC error report disabled from now on!\n");
2940 first = 0;
2941#endif
2942 }
2943 fill = tlen;
2944
2945 ifp = &sc->enif;
2946 ifp->if_ierrors++;
2947
2948 }
2949 mlen = tlen - fill;
2950 }
2951
2952 }
2953
2954 /*
2955 * now allocate mbufs for mlen bytes of data, if out of mbufs, trash all
2956 *
2957 * notes:
2958 * 1. it is possible that we've already allocated an mbuf for this pkt
2959 * but ran out of DRQs, in which case we saved the allocated mbuf on
2960 * "q".
2961 * 2. if we save an mbuf in "q" we store the "cur" (pointer) in the front
2962 * of the mbuf as an identity (that we can check later), and we also
2963 * store drqneed (so we don't have to recompute it).
2964 * 3. after this block of code, if m is still NULL then we ran out of mbufs
2965 */
2966
2967 m = sc->rxslot[slot].q.ifq_head;
2968 drqneed = 1;
2969 if (m) {
2970 sav = mtod(m, u_int32_t *);
2971 if (sav[0] != cur) {
2972#ifdef EN_DEBUG
2973 printf("%s: rx%d: q'ed mbuf %p not ours\n",
2974 sc->sc_dev.dv_xname, slot, m);
2975#endif
2976 m = NULL; /* wasn't ours */
2977 EN_COUNT(sc->rxqnotus);
2978 } else {
2979 EN_COUNT(sc->rxqus);
2980 IF_DEQUEUE(&sc->rxslot[slot].q, m);
2981 drqneed = sav[1];
2982#ifdef EN_DEBUG
2983 printf("%s: rx%d: recovered q'ed mbuf %p (drqneed=%d)\n",
2984 sc->sc_dev.dv_xname, slot, m, drqneed);
2985#endif
2986 }
2987 }
2988
2989 if (mlen != 0 && m == NULL) {
2990 m = en_mget(sc, mlen, &drqneed); /* allocate! */
2991 if (m == NULL) {
2992 fill += mlen;
2993 mlen = 0;
2994 EN_COUNT(sc->rxmbufout);
2995#ifdef EN_DEBUG
2996 printf("%s: rx%d: out of mbufs\n", sc->sc_dev.dv_xname, slot);
2997#endif
2998 }
2999#ifdef EN_DEBUG
3000 printf("%s: rx%d: allocate mbuf %p, mlen=%d, drqneed=%d\n",
3001 sc->sc_dev.dv_xname, slot, m, mlen, drqneed);
3002#endif
3003 }
3004
3005#ifdef EN_DEBUG
3006 printf("%s: rx%d: VCI %d, mbuf_chain %p, mlen %d, fill %d\n",
3007 sc->sc_dev.dv_xname, slot, vci, m, mlen, fill);
3008#endif
3009
3010 /*
3011 * now check to see if we've got the DRQs needed. if we are out of
3012 * DRQs we must quit (saving our mbuf, if we've got one).
3013 */
3014
3015 needfill = (fill) ? 1 : 0;
3016 if (drqneed + needfill > sc->drq_free) {
3017 sc->need_drqs = 1; /* flag condition */
3018 if (m == NULL) {
3019 EN_COUNT(sc->rxoutboth);
3020#ifdef EN_DEBUG
3021 printf("%s: rx%d: out of DRQs *and* mbufs!\n", sc->sc_dev.dv_xname, slot);
3022#endif
3023 return; /* >>> exit here if out of both mbufs and DRQs <<< */
3024 }
3025 sav = mtod(m, u_int32_t *);
3026 sav[0] = cur;
3027 sav[1] = drqneed;
3028 IF_ENQUEUE(&sc->rxslot[slot].q, m);
3029 EN_COUNT(sc->rxdrqout);
3030#ifdef EN_DEBUG
3031 printf("%s: rx%d: out of DRQs\n", sc->sc_dev.dv_xname, slot);
3032#endif
3033 return; /* >>> exit here if out of DRQs <<< */
3034 }
3035
3036 /*
3037 * at this point all resources have been allocated and we are commited
3038 * to servicing this slot.
3039 *
3040 * dma = last location we told chip about
3041 * cur = current location
3042 * mlen = space in the mbuf we want
3043 * need = bytes to xfer in (decrs to zero)
3044 * fill = how much fill we need
3045 * tlen = how much data to transfer to this mbuf
3046 * cnt/bcode/count = <same as xmit>
3047 *
3048 * 'needfill' not used after this point
3049 */
3050
3051 dma = cur; /* dma = last location we told chip about */
3052 need = roundup(mlen, sizeof(u_int32_t));
3053 fill = fill - (need - mlen); /* note: may invalidate 'needfill' */
3054
3055 for (tmp = m ; tmp != NULL && need > 0 ; tmp = tmp->m_next) {
3056 tlen = roundup(tmp->m_len, sizeof(u_int32_t)); /* m_len set by en_mget */
3057 data = mtod(tmp, u_int32_t *);
3058
3059#ifdef EN_DEBUG
3060 printf("%s: rx%d: load mbuf %p, m_len=%d, m_data=%p, tlen=%d\n",
3061 sc->sc_dev.dv_xname, slot, tmp, tmp->m_len, tmp->m_data, tlen);
3062#endif
3063
3064 /* copy data */
3065 if (EN_NORXDMA || !en_dma || tlen < EN_MINDMA) {
3066 datastop = (u_int32_t *)((u_char *) data + tlen);
3067 /* copy loop: preserve byte order!!! use READDAT */
3068 while (data != datastop) {
3069 *data = EN_READDAT(sc, cur);
3070 data++;
3071 EN_WRAPADD(start, stop, cur, 4);
3072 }
3073 need -= tlen;
3074#ifdef EN_DEBUG
3075 printf("%s: rx%d: vci%d: copied %d bytes (%d left)\n",
3076 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3077#endif
3078 continue;
3079 }
3080
3081 /* DMA data (check to see if we need to sync DRQ first) */
3082 if (dma != cur) {
3083 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, 0, 0, 0);
3084#ifdef EN_DEBUG
3085 printf("%s: rx%d: vci%d: drq_sync: advance pointer to %d\n",
3086 sc->sc_dev.dv_xname, slot, vci, cur);
3087#endif
3088 }
3089
3090#if !defined(MIDWAY_ENIONLY)
3091
3092 /*
3093 * the adaptec DMA engine is smart and handles everything for us.
3094 */
3095
3096 if (sc->is_adaptec) {
3097 need -= tlen;
3098 EN_WRAPADD(start, stop, cur, tlen);
3099#ifdef EN_DEBUG
3100 printf("%s: rx%d: vci%d: adp_dma %d bytes (%d left)\n",
3101 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3102#endif
3103 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3104 EN_DRQADD(sc, tlen, vci, 0, vtophys(data), mlen, slot, end);
3105 if (end)
3106 goto done;
3107 dma = cur; /* update dma pointer */
3108 continue;
3109 }
3110#endif /* !MIDWAY_ENIONLY */
3111
3112
3113#if !defined(MIDWAY_ADPONLY)
3114
3115 /*
3116 * the ENI DMA engine is not so smart and need more help from us
3117 */
3118
3119 /* do we need to do a DMA op to align? */
3120 if (sc->alburst &&
3121 (needalign = (((uintptr_t) (void *) data) & sc->bestburstmask)) != 0) {
3122 cnt = sc->bestburstlen - needalign;
3123 if (cnt > tlen) {
3124 cnt = tlen;
3125 count = cnt / sizeof(u_int32_t);
3126 bcode = MIDDMA_WORD;
3127 } else {
3128 count = cnt / sizeof(u_int32_t);
3129 bcode = en_dmaplan[count].bcode;
3130 count = cnt >> en_dmaplan[count].divshift;
3131 }
3132 need -= cnt;
3133 EN_WRAPADD(start, stop, cur, cnt);
3134#ifdef EN_DEBUG
3135 printf("%s: rx%d: vci%d: al_dma %d bytes (%d left)\n",
3136 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3137#endif
3138 tlen -= cnt;
3139 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3140 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3141 if (end)
3142 goto done;
3143 data = (u_int32_t *)((u_char *) data + cnt);
3144 }
3145
3146 /* do we need a max-sized burst? */
3147 if (tlen >= sc->bestburstlen) {
3148 count = tlen >> sc->bestburstshift;
3149 cnt = count << sc->bestburstshift;
3150 bcode = sc->bestburstcode;
3151 need -= cnt;
3152 EN_WRAPADD(start, stop, cur, cnt);
3153#ifdef EN_DEBUG
3154 printf("%s: rx%d: vci%d: best_dma %d bytes (%d left)\n",
3155 sc->sc_dev.dv_xname, slot, vci, cnt, need);
3156#endif
3157 tlen -= cnt;
3158 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3159 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3160 if (end)
3161 goto done;
3162 data = (u_int32_t *)((u_char *) data + cnt);
3163 }
3164
3165 /* do we need to do a cleanup burst? */
3166 if (tlen) {
3167 count = tlen / sizeof(u_int32_t);
3168 bcode = en_dmaplan[count].bcode;
3169 count = tlen >> en_dmaplan[count].divshift;
3170 need -= tlen;
3171 EN_WRAPADD(start, stop, cur, tlen);
3172#ifdef EN_DEBUG
3173 printf("%s: rx%d: vci%d: cleanup_dma %d bytes (%d left)\n",
3174 sc->sc_dev.dv_xname, slot, vci, tlen, need);
3175#endif
3176 end = (need == 0 && !fill) ? MID_DMA_END : 0;
3177 EN_DRQADD(sc, count, vci, bcode, vtophys(data), mlen, slot, end);
3178 if (end)
3179 goto done;
3180 }
3181
3182 dma = cur; /* update dma pointer */
3183
3184#endif /* !MIDWAY_ADPONLY */
3185
3186 }
3187
3188 /* skip the end */
3189 if (fill || dma != cur) {
3190#ifdef EN_DEBUG
3191 if (fill)
3192 printf("%s: rx%d: vci%d: skipping %d bytes of fill\n",
3193 sc->sc_dev.dv_xname, slot, vci, fill);
3194 else
3195 printf("%s: rx%d: vci%d: syncing chip from 0x%x to 0x%x [cur]\n",
3196 sc->sc_dev.dv_xname, slot, vci, dma, cur);
3197#endif
3198 EN_WRAPADD(start, stop, cur, fill);
3199 EN_DRQADD(sc, WORD_IDX(start,cur), vci, MIDDMA_JK, 0, mlen,
3200 slot, MID_DMA_END);
3201 /* dma = cur; */ /* not necessary since we are done */
3202 }
3203
3204 /*
3205 * done, remove stuff we don't want to pass up:
3206 * raw mode (boodi mode): pass everything up for later processing
3207 * aal5: remove RBD
3208 * aal0: remove RBD + cell header
3209 */
3210
3211done:
3212 if (m) {
3213 if (!raw) {
3214 cnt = MID_RBD_SIZE;
3215 if (!aal5) cnt += MID_CHDR_SIZE;
3216 m->m_len -= cnt; /* chop! */
3217 m->m_pkthdr.len -= cnt;
3218 m->m_data += cnt;
3219 }
3220 IF_ENQUEUE(&sc->rxslot[slot].indma, m);
3221 }
3222 sc->rxslot[slot].cur = cur; /* update master copy of 'cur' */
3223
3224#ifdef EN_DEBUG
3225 printf("%s: rx%d: vci%d: DONE! cur now =0x%x\n",
3226 sc->sc_dev.dv_xname, slot, vci, cur);
3227#endif
3228
3229 goto same_vci; /* get next packet in this slot */
3230}
3231
3232
3233#ifdef EN_DDBHOOK
3234/*
3235 * functions we can call from ddb
3236 */
3237
3238/*
3239 * en_dump: dump the state
3240 */
3241
3242#define END_SWSL 0x00000040 /* swsl state */
3243#define END_DRQ 0x00000020 /* drq state */
3244#define END_DTQ 0x00000010 /* dtq state */
3245#define END_RX 0x00000008 /* rx state */
3246#define END_TX 0x00000004 /* tx state */
3247#define END_MREGS 0x00000002 /* registers */
3248#define END_STATS 0x00000001 /* dump stats */
3249
3250#define END_BITS "\20\7SWSL\6DRQ\5DTQ\4RX\3TX\2MREGS\1STATS"
3251
3252/* Do not staticize - meant for calling from DDB! */
3253int en_dump(unit, level)
3254
3255int unit, level;
3256
3257{
3258 struct en_softc *sc;
3259 int lcv, cnt, slot;
3260 u_int32_t ptr, reg;
3261
3262 for (lcv = 0 ; lcv < en_cd.cd_ndevs ; lcv++) {
3263 sc = (struct en_softc *) en_cd.cd_devs[lcv];
3264 if (sc == NULL) continue;
3265 if (unit != -1 && unit != lcv)
3266 continue;
3267
3268 printf("dumping device %s at level 0x%b\n", sc->sc_dev.dv_xname, level,
3269 END_BITS);
3270
3271 if (sc->dtq_us == 0) {
3272 printf("<hasn't been en_init'd yet>\n");
3273 continue;
3274 }
3275
3276 if (level & END_STATS) {
3277 printf(" en_stats:\n");
3278 printf(" %d mfix (%d failed); %d/%d head/tail byte DMAs, %d flushes\n",
3279 sc->mfix, sc->mfixfail, sc->headbyte, sc->tailbyte, sc->tailflush);
3280 printf(" %d rx dma overflow interrupts\n", sc->dmaovr);
3281 printf(" %d times we ran out of TX space and stalled\n",
3282 sc->txoutspace);
3283 printf(" %d times we ran out of DTQs\n", sc->txdtqout);
3284 printf(" %d times we launched a packet\n", sc->launch);
3285 printf(" %d times we launched without on-board header\n", sc->lheader);
3286 printf(" %d times we launched without on-board tail\n", sc->ltail);
3287 printf(" %d times we pulled the hw service list\n", sc->hwpull);
3288 printf(" %d times we pushed a vci on the sw service list\n",
3289 sc->swadd);
3290 printf(" %d times RX pulled an mbuf from Q that wasn't ours\n",
3291 sc->rxqnotus);
3292 printf(" %d times RX pulled a good mbuf from Q\n", sc->rxqus);
3293 printf(" %d times we ran out of mbufs *and* DRQs\n", sc->rxoutboth);
3294 printf(" %d times we ran out of DRQs\n", sc->rxdrqout);
3295
3296 printf(" %d trasmit packets dropped due to mbsize\n", sc->txmbovr);
3297 printf(" %d cells trashed due to turned off rxvc\n", sc->vtrash);
3298 printf(" %d cells trashed due to totally full buffer\n", sc->otrash);
3299 printf(" %d cells trashed due almost full buffer\n", sc->ttrash);
3300 printf(" %d rx mbuf allocation failures\n", sc->rxmbufout);
3301#ifdef NATM
3302 printf(" %d drops at natmintrq\n", natmintrq.ifq_drops);
3303#ifdef NATM_STAT
3304 printf(" natmintr so_rcv: ok/drop cnt: %d/%d, ok/drop bytes: %d/%d\n",
3305 natm_sookcnt, natm_sodropcnt, natm_sookbytes, natm_sodropbytes);
3306#endif
3307#endif
3308 }
3309
3310 if (level & END_MREGS) {
3311 printf("mregs:\n");
3312 printf("resid = 0x%lx\n", (u_long)EN_READ(sc, MID_RESID));
3313 printf("interrupt status = 0x%b\n",
3314 (int)EN_READ(sc, MID_INTSTAT), MID_INTBITS);
3315 printf("interrupt enable = 0x%b\n",
3316 (int)EN_READ(sc, MID_INTENA), MID_INTBITS);
3317 printf("mcsr = 0x%b\n", (int)EN_READ(sc, MID_MAST_CSR), MID_MCSRBITS);
3318 printf("serv_write = [chip=%ld] [us=%d]\n",
3319 (long)EN_READ(sc, MID_SERV_WRITE),
3320 MID_SL_A2REG(sc->hwslistp));
3321 printf("dma addr = 0x%lx\n", (u_long)EN_READ(sc, MID_DMA_ADDR));
3322 printf("DRQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3323 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_RDRX)),
3324 (u_long)MID_DRQ_REG2A(EN_READ(sc, MID_DMA_WRRX)),
3325 sc->drq_chip, sc->drq_us);
3326 printf("DTQ: chip[rd=0x%lx,wr=0x%lx], sc[chip=0x%x,us=0x%x]\n",
3327 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_RDTX)),
3328 (u_long)MID_DTQ_REG2A(EN_READ(sc, MID_DMA_WRTX)),
3329 sc->dtq_chip, sc->dtq_us);
3330
3331 printf(" unusal txspeeds: ");
3332 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3333 if (sc->txspeed[cnt])
3334 printf(" vci%d=0x%x", cnt, sc->txspeed[cnt]);
3335 printf("\n");
3336
3337 printf(" rxvc slot mappings: ");
3338 for (cnt = 0 ; cnt < MID_N_VC ; cnt++)
3339 if (sc->rxvc2slot[cnt] != RX_NONE)
3340 printf(" %d->%d", cnt, sc->rxvc2slot[cnt]);
3341 printf("\n");
3342
3343 }
3344
3345 if (level & END_TX) {
3346 printf("tx:\n");
3347 for (slot = 0 ; slot < EN_NTX; slot++) {
3348 printf("tx%d: start/stop/cur=0x%x/0x%x/0x%x [%d] ", slot,
3349 sc->txslot[slot].start, sc->txslot[slot].stop, sc->txslot[slot].cur,
3350 (sc->txslot[slot].cur - sc->txslot[slot].start)/4);
3351 printf("mbsize=%d, bfree=%d\n", sc->txslot[slot].mbsize,
3352 sc->txslot[slot].bfree);
3353 printf("txhw: base_address=0x%lx, size=%ld, read=%ld, descstart=%ld\n",
3354 (u_long)MIDX_BASE(EN_READ(sc, MIDX_PLACE(slot))),
3355 (u_long)MIDX_SZ(EN_READ(sc, MIDX_PLACE(slot))),
3356 (long)EN_READ(sc, MIDX_READPTR(slot)),
3357 (long)EN_READ(sc, MIDX_DESCSTART(slot)));
3358 }
3359 }
3360
3361 if (level & END_RX) {
3362 printf(" recv slots:\n");
3363 for (slot = 0 ; slot < sc->en_nrx; slot++) {
3364 printf("rx%d: vci=%d: start/stop/cur=0x%x/0x%x/0x%x ", slot,
3365 sc->rxslot[slot].atm_vci, sc->rxslot[slot].start,
3366 sc->rxslot[slot].stop, sc->rxslot[slot].cur);
3367 printf("mode=0x%x, atm_flags=0x%x, oth_flags=0x%x\n",
3368 sc->rxslot[slot].mode, sc->rxslot[slot].atm_flags,
3369 sc->rxslot[slot].oth_flags);
3370 printf("RXHW: mode=0x%lx, DST_RP=0x%lx, WP_ST_CNT=0x%lx\n",
3371 (u_long)EN_READ(sc, MID_VC(sc->rxslot[slot].atm_vci)),
3372 (u_long)EN_READ(sc, MID_DST_RP(sc->rxslot[slot].atm_vci)),
3373 (u_long)EN_READ(sc, MID_WP_ST_CNT(sc->rxslot[slot].atm_vci)));
3374 }
3375 }
3376
3377 if (level & END_DTQ) {
3378 printf(" dtq [need_dtqs=%d,dtq_free=%d]:\n",
3379 sc->need_dtqs, sc->dtq_free);
3380 ptr = sc->dtq_chip;
3381 while (ptr != sc->dtq_us) {
3382 reg = EN_READ(sc, ptr);
3383 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3384 sc->dtq[MID_DTQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_TXCHAN(reg),
3385 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3386 (u_long)EN_READ(sc, ptr+4));
3387 EN_WRAPADD(MID_DTQOFF, MID_DTQEND, ptr, 8);
3388 }
3389 }
3390
3391 if (level & END_DRQ) {
3392 printf(" drq [need_drqs=%d,drq_free=%d]:\n",
3393 sc->need_drqs, sc->drq_free);
3394 ptr = sc->drq_chip;
3395 while (ptr != sc->drq_us) {
3396 reg = EN_READ(sc, ptr);
3397 printf("\t0x%x=[cnt=%d, chan=%d, end=%d, type=%d @ 0x%lx]\n",
3398 sc->drq[MID_DRQ_A2REG(ptr)], MID_DMA_CNT(reg), MID_DMA_RXVCI(reg),
3399 (reg & MID_DMA_END) != 0, MID_DMA_TYPE(reg),
3400 (u_long)EN_READ(sc, ptr+4));
3401 EN_WRAPADD(MID_DRQOFF, MID_DRQEND, ptr, 8);
3402 }
3403 }
3404
3405 if (level & END_SWSL) {
3406 printf(" swslist [size=%d]: ", sc->swsl_size);
3407 for (cnt = sc->swsl_head ; cnt != sc->swsl_tail ;
3408 cnt = (cnt + 1) % MID_SL_N)
3409 printf("0x%x ", sc->swslist[cnt]);
3410 printf("\n");
3411 }
3412 }
3413 return(0);
3414}
3415
3416/*
3417 * en_dumpmem: dump the memory
3418 */
3419
3420/* Do not staticize - meant for calling from DDB! */
3421int en_dumpmem(unit, addr, len)
3422
3423int unit, addr, len;
3424
3425{
3426 struct en_softc *sc;
3427 u_int32_t reg;
3428
3429 if (unit < 0 || unit > en_cd.cd_ndevs ||
3430 (sc = (struct en_softc *) en_cd.cd_devs[unit]) == NULL) {
3431 printf("invalid unit number: %d\n", unit);
3432 return(0);
3433 }
3434 addr = addr & ~3;
3435 if (addr < MID_RAMOFF || addr + len*4 > MID_MAXOFF || len <= 0) {
3436 printf("invalid addr/len number: %d, %d\n", addr, len);
3437 return(0);
3438 }
3439 printf("dumping %d words starting at offset 0x%x\n", len, addr);
3440 while (len--) {
3441 reg = EN_READ(sc, addr);
3442 printf("mem[0x%x] = 0x%x\n", addr, reg);
3443 addr += 4;
3444 }
3445 return(0);
3446}
3447#endif
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