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[dragonfly.git] / sys / dev / disk / i386 / bs / bshw.h
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1/* $NecBSD: bshw.h,v 1.2 1997/10/31 17:43:38 honda Exp $ */
2/* $NetBSD$ */
38e94a25 3/* $DragonFly: src/sys/dev/disk/i386/bs/Attic/bshw.h,v 1.2 2003/08/27 10:35:16 rob Exp $ */
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4/*
5 * [NetBSD for NEC PC98 series]
6 * Copyright (c) 1994, 1995, 1996 NetBSD/pc98 porting staff.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32/*
33 * Copyright (c) 1994, 1995, 1996 Naofumi HONDA. All rights reserved.
34 */
35
36/* NEC port offsets */
37#define BSHW_DEFAULT_PORT 0xcc0
38#define BSHW_IOSZ 5
39
40#define addr_port 0
41#define stat_port 0
42#define ctrl_port 2
43#define cmd_port 4
44
45#define BSHW_MAX_OFFSET 12
46#define BSHW_SEL_TIMEOUT 0x80
47
48#define BSHW_READ BSR_IOR
49#define BSHW_WRITE 0x0
50
51#define BSHW_SMITFIFO_OFFSET 0x1000
52
53#define BSHW_CMD_CHECK(CCB, CAT) (bshw_cmd[(CCB)->cmd[0]] & (CAT))
54/*********************************************************
55 * static inline declare.
56 *********************************************************/
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57static BS_INLINE void write_wd33c93 (struct bs_softc *, u_int, u_int8_t);
58static BS_INLINE u_int8_t read_wd33c93 (struct bs_softc *, u_int);
59static BS_INLINE u_int8_t bshw_get_auxstat (struct bs_softc *);
60static BS_INLINE u_int8_t bshw_get_busstat (struct bs_softc *);
61static BS_INLINE u_int8_t bshw_get_status_insat (struct bs_softc *);
62static BS_INLINE u_int8_t bshw_read_data (struct bs_softc *);
63static BS_INLINE void bshw_write_data (struct bs_softc *, u_int8_t);
64static BS_INLINE void bshw_set_count (struct bs_softc *, u_int);
65static BS_INLINE u_int bshw_get_count (struct bs_softc *);
66static BS_INLINE void bshw_set_dst_id (struct bs_softc *, u_int, u_int);
67static BS_INLINE void bshw_set_lun (struct bs_softc *, u_int);
68static BS_INLINE u_int bshw_get_src_id (struct bs_softc *);
69static BS_INLINE void bshw_negate_ack (struct bs_softc *);
70static BS_INLINE void bshw_assert_atn (struct bs_softc *);
71static BS_INLINE void bshw_assert_select (struct bs_softc *);
72static BS_INLINE void bshw_start_xfer (struct bs_softc *);
73static BS_INLINE void bshw_start_sxfer (struct bs_softc *);
74static BS_INLINE void bshw_cmd_pass (struct bs_softc *, u_int);
75static BS_INLINE void bshw_start_sat (struct bs_softc *, u_int);
76static BS_INLINE void bshw_abort_cmd (struct bs_softc *);
77static BS_INLINE void bshw_set_sync_reg (struct bs_softc *, u_int);
78static BS_INLINE void bshw_set_poll_trans (struct bs_softc *, u_int);
79static BS_INLINE void bshw_set_dma_trans (struct bs_softc *, u_int);
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80
81/*********************************************************
82 * global declare
83 *********************************************************/
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84void bs_dma_xfer (struct targ_info *, u_int);
85void bs_dma_xfer_end (struct targ_info *);
86void bshw_dmaabort (struct bs_softc *, struct targ_info *);
984263bc 87
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88void bshw_adj_syncdata (struct syncdata *);
89void bshw_set_synchronous (struct bs_softc *, struct targ_info *);
984263bc 90
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91void bs_smit_xfer_end (struct targ_info *);
92void bshw_smitabort (struct bs_softc *);
984263bc 93
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94void bshw_setup_ctrl_reg (struct bs_softc *, u_int);
95int bshw_chip_reset (struct bs_softc *);
96void bshw_bus_reset (struct bs_softc *);
97int bshw_board_probe (struct bs_softc *, u_int *, u_int *);
98void bshw_lock (struct bs_softc *);
99void bshw_unlock (struct bs_softc *);
100void bshw_get_syncreg (struct bs_softc *);
101void bshw_issue_satcmd (struct bs_softc *, struct bsccb *, int);
102void bshw_print_port (struct bs_softc *);
984263bc 103
38e94a25 104void bs_lc_smit_xfer (struct targ_info *, u_int);
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105
106extern struct dvcfg_hwsel bshw_hwsel;
107extern u_int8_t bshw_cmd[];
108
109/*********************************************************
110 * hw
111 *********************************************************/
112struct bshw {
113#define BSHW_SYNC_RELOAD 0x01
114#define BSHW_SMFIFO 0x02
115#define BSHW_DOUBLE_DMACHAN 0x04
116 u_int hw_flags;
117
118 u_int sregaddr;
119
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120 int ((*dma_init) (struct bs_softc *));
121 void ((*dma_start) (struct bs_softc *));
122 void ((*dma_stop) (struct bs_softc *));
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123};
124
125/*********************************************************
126 * inline funcs.
127 *********************************************************/
128/*
129 * XXX: If your board does not work well, Please try BS_NEEDS_WEIGHT.
130 */
131static BS_INLINE void
132write_wd33c93(bsc, addr, data)
133 struct bs_softc *bsc;
134 u_int addr;
135 u_int8_t data;
136{
137
138 BUS_IOW(addr_port, addr);
139 BUS_IOW(ctrl_port, data);
140}
141
142static BS_INLINE u_int8_t
143read_wd33c93(bsc, addr)
144 struct bs_softc *bsc;
145 u_int addr;
146{
147
148 BUS_IOW(addr_port, addr);
149 return BUS_IOR(ctrl_port);
150}
151
152/* status */
153static BS_INLINE u_int8_t
154bshw_get_auxstat(bsc)
155 struct bs_softc *bsc;
156{
157
158 return BUS_IOR(stat_port);
159}
160
161static BS_INLINE u_int8_t
162bshw_get_busstat(bsc)
163 struct bs_softc *bsc;
164{
165
166 return read_wd33c93(bsc, wd3s_stat);
167}
168
169static BS_INLINE u_int8_t
170bshw_get_status_insat(bsc)
171 struct bs_softc *bsc;
172{
173
174 return read_wd33c93(bsc, wd3s_lun);
175}
176
177/* data */
178static BS_INLINE u_int8_t
179bshw_read_data(bsc)
180 struct bs_softc *bsc;
181{
182
183 return read_wd33c93(bsc, wd3s_data);
184}
185
186static BS_INLINE void
187bshw_write_data(bsc, data)
188 struct bs_softc *bsc;
189 u_int8_t data;
190{
191
192 write_wd33c93(bsc, wd3s_data, data);
193}
194
195/* counter */
196static BS_INLINE void
197bshw_set_count(bsc, count)
198 struct bs_softc *bsc;
199 u_int count;
200{
201
202 BUS_IOW(addr_port, wd3s_cnt);
203 BUS_IOW(ctrl_port, count >> 16);
204 BUS_IOW(ctrl_port, count >> 8);
205 BUS_IOW(ctrl_port, count);
206}
207
208static BS_INLINE u_int
209bshw_get_count(bsc)
210 struct bs_softc *bsc;
211{
212 u_int count;
213
214 BUS_IOW(addr_port, wd3s_cnt);
215 count = (((u_int) BUS_IOR(ctrl_port)) << 16);
216 count += (((u_int) BUS_IOR(ctrl_port)) << 8);
217 count += ((u_int) BUS_IOR(ctrl_port));
218 return count;
219}
220
221/* ID */
222static BS_INLINE void
223bshw_set_lun(bsc, lun)
224 struct bs_softc *bsc;
225 u_int lun;
226{
227
228 write_wd33c93(bsc, wd3s_lun, lun);
229}
230
231static BS_INLINE void
232bshw_set_dst_id(bsc, target, lun)
233 struct bs_softc *bsc;
234 u_int target, lun;
235{
236
237 write_wd33c93(bsc, wd3s_did, target);
238 write_wd33c93(bsc, wd3s_lun, lun);
239}
240
241static BS_INLINE u_int
242bshw_get_src_id(bsc)
243 struct bs_softc *bsc;
244{
245
246 return (read_wd33c93(bsc, wd3s_sid) & SIDR_IDM);
247}
248
249/* phase */
250static BS_INLINE void
251bshw_negate_ack(bsc)
252 struct bs_softc *bsc;
253{
254
255 write_wd33c93(bsc, wd3s_cmd, WD3S_NEGATE_ACK);
256}
257
258static BS_INLINE void
259bshw_assert_atn(bsc)
260 struct bs_softc *bsc;
261{
262
263 write_wd33c93(bsc, wd3s_cmd, WD3S_ASSERT_ATN);
264}
265
266static BS_INLINE void
267bshw_assert_select(bsc)
268 struct bs_softc *bsc;
269{
270
271 write_wd33c93(bsc, wd3s_cmd, WD3S_SELECT_ATN);
272}
273
274static BS_INLINE void
275bshw_start_xfer(bsc)
276 struct bs_softc *bsc;
277{
278
279 write_wd33c93(bsc, wd3s_cmd, WD3S_TFR_INFO);
280}
281
282static BS_INLINE void
283bshw_start_sxfer(bsc)
284 struct bs_softc *bsc;
285{
286
287 write_wd33c93(bsc, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
288}
289
290static BS_INLINE void
291bshw_cmd_pass(bsc, ph)
292 struct bs_softc *bsc;
293 u_int ph;
294{
295
296 write_wd33c93(bsc, wd3s_cph, ph);
297}
298
299static BS_INLINE void
300bshw_start_sat(bsc, flag)
301 struct bs_softc *bsc;
302 u_int flag;
303{
304
305 write_wd33c93(bsc, wd3s_cmd,
306 (flag ? WD3S_SELECT_ATN_TFR : WD3S_SELECT_NO_ATN_TFR));
307}
308
309
310static BS_INLINE void
311bshw_abort_cmd(bsc)
312 struct bs_softc *bsc;
313{
314
315 write_wd33c93(bsc, wd3s_cmd, WD3S_ABORT);
316}
317
318/* transfer mode */
319static BS_INLINE void
320bshw_set_sync_reg(bsc, val)
321 struct bs_softc *bsc;
322 u_int val;
323{
324
325 write_wd33c93(bsc, wd3s_synch, val);
326}
327
328static BS_INLINE void
329bshw_set_poll_trans(bsc, flags)
330 struct bs_softc *bsc;
331 u_int flags;
332{
333
334 if (bsc->sc_flags & BSDMATRANSFER)
335 {
336 bsc->sc_flags &= ~BSDMATRANSFER;
337 bshw_setup_ctrl_reg(bsc, flags);
338 }
339}
340
341static BS_INLINE void
342bshw_set_dma_trans(bsc, flags)
343 struct bs_softc *bsc;
344 u_int flags;
345{
346
347 if ((bsc->sc_flags & BSDMATRANSFER) == 0)
348 {
349 bsc->sc_flags |= BSDMATRANSFER;
350 bshw_setup_ctrl_reg(bsc, flags);
351 }
352}