Cleanup some of the newbus infrastructure.
[dragonfly.git] / sys / bus / pci / i386 / pcibus.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
0502b524 26 * $FreeBSD: src/sys/i386/isa/pcibus.c,v 1.57.2.12 2003/08/07 06:19:26 imp Exp $
39b5d600 27 * $DragonFly: src/sys/bus/pci/i386/pcibus.c,v 1.13 2005/10/28 03:25:36 dillon Exp $
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28 *
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
024db3fc 35#include <sys/malloc.h>
984263bc 36
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37#include <bus/pci/pcivar.h>
38#include <bus/pci/pcireg.h>
024db3fc 39#include <bus/pci/i386/pcibus.h>
67eccedb 40#include <bus/isa/isavar.h>
bbca97bc 41#include <bus/pci/i386/pci_cfgreg.h>
984263bc 42#include <machine/md_var.h>
024db3fc 43#include <machine/nexusvar.h>
984263bc 44
67eccedb 45#include "pcib_if.h"
984263bc 46
67eccedb
JS
47static int
48nexus_pcib_maxslots(device_t dev)
49{
50 return 31;
51}
52
53/*
54 * Read configuration space register.
55 */
56static u_int32_t
57nexus_pcib_read_config(device_t dev, int bus, int slot, int func,
58 int reg, int bytes)
59{
60 return (pci_cfgregread(bus, slot, func, reg, bytes));
61}
62
60b8dfac
JS
63/*
64 * Write configuration space register.
65 */
67eccedb
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66static void
67nexus_pcib_write_config(device_t dev, int bus, int slot, int func,
68 int reg, u_int32_t data, int bytes)
69{
70 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
71}
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72
73static devclass_t pcib_devclass;
74
75static const char *
024db3fc 76nexus_pcib_is_host_bridge(int bus, int slot, int func,
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77 u_int32_t id, u_int8_t class, u_int8_t subclass,
78 u_int8_t *busnum)
79{
80 const char *s = NULL;
81 static u_int8_t pxb[4]; /* hack for 450nx */
82
83 *busnum = 0;
84
85 switch (id) {
86 case 0x12258086:
87 s = "Intel 824?? host to PCI bridge";
88 /* XXX This is a guess */
024db3fc
JS
89 /* *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x41, 1); */
90 *busnum = bus;
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91 break;
92 case 0x71208086:
93 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
94 break;
95 case 0x71228086:
96 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
97 break;
98 case 0x71248086:
99 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
100 break;
101 case 0x71808086:
102 s = "Intel 82443LX (440 LX) host to PCI bridge";
103 break;
104 case 0x71908086:
105 s = "Intel 82443BX (440 BX) host to PCI bridge";
106 break;
107 case 0x71928086:
108 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
109 break;
110 case 0x71948086:
111 s = "Intel 82443MX host to PCI bridge";
112 break;
113 case 0x71a08086:
114 s = "Intel 82443GX host to PCI bridge";
115 break;
116 case 0x71a18086:
117 s = "Intel 82443GX host to AGP bridge";
118 break;
119 case 0x71a28086:
120 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
121 break;
122 case 0x84c48086:
123 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
024db3fc 124 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x4a, 1);
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125 break;
126 case 0x84ca8086:
127 /*
128 * For the 450nx chipset, there is a whole bundle of
129 * things pretending to be host bridges. The MIOC will
130 * be seen first and isn't really a pci bridge (the
131 * actual busses are attached to the PXB's). We need to
132 * read the registers of the MIOC to figure out the
133 * bus numbers for the PXB channels.
134 *
135 * Since the MIOC doesn't have a pci bus attached, we
136 * pretend it wasn't there.
137 */
024db3fc
JS
138 pxb[0] = nexus_pcib_read_config(0, bus, slot, func,
139 0xd0, 1); /* BUSNO[0] */
140 pxb[1] = nexus_pcib_read_config(0, bus, slot, func,
141 0xd1, 1) + 1; /* SUBA[0]+1 */
142 pxb[2] = nexus_pcib_read_config(0, bus, slot, func,
143 0xd3, 1); /* BUSNO[1] */
144 pxb[3] = nexus_pcib_read_config(0, bus, slot, func,
145 0xd4, 1) + 1; /* SUBA[1]+1 */
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146 return NULL;
147 case 0x84cb8086:
024db3fc 148 switch (slot) {
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149 case 0x12:
150 s = "Intel 82454NX PXB#0, Bus#A";
151 *busnum = pxb[0];
152 break;
153 case 0x13:
154 s = "Intel 82454NX PXB#0, Bus#B";
155 *busnum = pxb[1];
156 break;
157 case 0x14:
158 s = "Intel 82454NX PXB#1, Bus#A";
159 *busnum = pxb[2];
160 break;
161 case 0x15:
162 s = "Intel 82454NX PXB#1, Bus#B";
163 *busnum = pxb[3];
164 break;
165 }
166 break;
167 case 0x1A308086:
168 s = "Intel 82845 Host to PCI bridge";
169 break;
170
171 /* AMD -- vendor 0x1022 */
172 case 0x30001022:
173 s = "AMD Elan SC520 host to PCI bridge";
174#ifdef CPU_ELAN
175 init_AMD_Elan_sc520();
176#else
177 printf("*** WARNING: kernel option CPU_ELAN missing");
178 printf("-- timekeeping may be wrong\n");
179#endif
180 break;
181 case 0x70061022:
182 s = "AMD-751 host to PCI bridge";
183 break;
184 case 0x700e1022:
185 s = "AMD-761 host to PCI bridge";
186 break;
187
188 /* SiS -- vendor 0x1039 */
189 case 0x04961039:
190 s = "SiS 85c496";
191 break;
192 case 0x04061039:
193 s = "SiS 85c501";
194 break;
195 case 0x06011039:
196 s = "SiS 85c601";
197 break;
198 case 0x55911039:
199 s = "SiS 5591 host to PCI bridge";
200 break;
201 case 0x00011039:
202 s = "SiS 5591 host to AGP bridge";
203 break;
204
205 /* VLSI -- vendor 0x1004 */
206 case 0x00051004:
207 s = "VLSI 82C592 Host to PCI bridge";
208 break;
209
210 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
211 /* totally. Please let me know if anything wrong. -F */
212 /* XXX need info on the MVP3 -- any takers? */
213 case 0x05981106:
214 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
215 break;
216
217 /* AcerLabs -- vendor 0x10b9 */
218 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
219 /* id is '10b9" but the register always shows "10b9". -Foxfair */
220 case 0x154110b9:
221 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
222 break;
223
224 /* OPTi -- vendor 0x1045 */
024db3fc
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225 case 0xc7011045:
226 s = "OPTi 82C700 host to PCI bridge";
227 break;
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228 case 0xc8221045:
229 s = "OPTi 82C822 host to PCI Bridge";
230 break;
231
232 /* ServerWorks -- vendor 0x1166 */
233 case 0x00051166:
234 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
024db3fc 235 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
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236 break;
237
238 case 0x00061166:
239 /* FALLTHROUGH */
240 case 0x00081166:
f1f0bfb2
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241 /* FALLTHROUGH */
242 case 0x02011166:
243 /* FALLTHROUGH */
244 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
245 /* FALLTHROUGH */
984263bc 246 s = "ServerWorks host to PCI bridge";
024db3fc 247 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
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248 break;
249
250 case 0x00091166:
251 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
024db3fc 252 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
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253 break;
254
255 case 0x00101166:
256 s = "ServerWorks CIOB30 host to PCI bridge";
024db3fc 257 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
984263bc
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258 break;
259
f1f0bfb2
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260 case 0x00111166:
261 /* FALLTHROUGH */
262 case 0x03021014: /* IBM re-badged ServerWorks chipset */
263 s = "ServerWorks CMIC-HE host to PCI-X bridge";
264 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
265 break;
266
984263bc
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267 /* XXX unknown chipset, but working */
268 case 0x00171166:
269 /* FALLTHROUGH */
270 case 0x01011166:
271 s = "ServerWorks host to PCI bridge(unknown chipset)";
024db3fc 272 *busnum = nexus_pcib_read_config(0, bus, slot, func, 0x44, 1);
984263bc
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273 break;
274
275 /* Integrated Micro Solutions -- vendor 0x10e0 */
276 case 0x884910e0:
277 s = "Integrated Micro Solutions VL Bridge";
278 break;
279
280 default:
281 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
282 s = "Host to PCI bridge";
283 break;
284 }
285
286 return s;
287}
288
289/*
290 * Scan the first pci bus for host-pci bridges and add pcib instances
291 * to the nexus for each bridge.
292 */
39b5d600 293static int
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294nexus_pcib_identify(driver_t *driver, device_t parent)
295{
024db3fc 296 int bus, slot, func;
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297 u_int8_t hdrtype;
298 int found = 0;
299 int pcifunchigh;
300 int found824xx = 0;
024db3fc
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301 device_t child;
302 devclass_t pci_devclass;
984263bc 303
39b5d600
MD
304 /*
305 * XXX currently do not support rescanning the pci bus
306 */
307 if (device_get_state(parent) == DS_ATTACHED)
308 return (0);
309
984263bc 310 if (pci_cfgregopen() == 0)
39b5d600
MD
311 return (ENXIO);
312
024db3fc
JS
313 /*
314 * Check to see if we haven't already had a PCI bus added
315 * via some other means. If we have, bail since otherwise
316 * we're going to end up duplicating it.
317 */
318 if ((pci_devclass = devclass_find("pci")) &&
39b5d600
MD
319 devclass_get_device(pci_devclass,0)) {
320 return (ENXIO);
321 }
024db3fc
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322
323 bus = 0;
984263bc 324 retry:
024db3fc
JS
325 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
326 func = 0;
327 hdrtype = nexus_pcib_read_config(0, bus, slot, func,
e126caf1 328 PCIR_HDRTYPE, 1);
0502b524
HP
329 if ((hdrtype & ~PCIM_MFDEV) > 2)
330 continue;
024db3fc 331 if (hdrtype & PCIM_MFDEV)
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332 pcifunchigh = 7;
333 else
334 pcifunchigh = 0;
024db3fc 335 for (func = 0; func <= pcifunchigh; func++) {
984263bc
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336 /*
337 * Read the IDs and class from the device.
338 */
339 u_int32_t id;
340 u_int8_t class, subclass, busnum;
984263bc 341 const char *s;
024db3fc
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342 device_t *devs;
343 int ndevs, i;
984263bc 344
024db3fc
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345 id = nexus_pcib_read_config(0, bus, slot, func,
346 PCIR_DEVVENDOR, 4);
984263bc
MD
347 if (id == -1)
348 continue;
024db3fc
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349 class = nexus_pcib_read_config(0, bus, slot, func,
350 PCIR_CLASS, 1);
351 subclass = nexus_pcib_read_config(0, bus, slot, func,
352 PCIR_SUBCLASS, 1);
984263bc 353
024db3fc
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354 s = nexus_pcib_is_host_bridge(bus, slot, func,
355 id, class, subclass,
984263bc 356 &busnum);
024db3fc
JS
357 if (s == NULL)
358 continue;
359
360 /*
361 * Check to see if the physical bus has already
362 * been seen. Eg: hybrid 32 and 64 bit host
363 * bridges to the same logical bus.
364 */
365 if (device_get_children(parent, &devs, &ndevs) == 0) {
366 for (i = 0; s != NULL && i < ndevs; i++) {
367 if (strcmp(device_get_name(devs[i]),
368 "pcib") != 0)
369 continue;
370 if (nexus_get_pcibus(devs[i]) == busnum)
371 s = NULL;
372 }
373 free(devs, M_TEMP);
984263bc 374 }
024db3fc
JS
375
376 if (s == NULL)
377 continue;
378 /*
cff9a4dc
MD
379 * Add at priority 100+busnum to make sure we
380 * go after any motherboard resources. This also
381 * causes us to scan the pci bridges in bus order,
382 * for debug output sanity.
024db3fc 383 */
cff9a4dc 384 child = BUS_ADD_CHILD(parent, 100 + busnum,
024db3fc
JS
385 "pcib", busnum);
386 device_set_desc(child, s);
387 nexus_set_pcibus(child, busnum);
388
389 found = 1;
390 if (id == 0x12258086)
391 found824xx = 1;
984263bc
MD
392 }
393 }
024db3fc
JS
394 if (found824xx && bus == 0) {
395 bus++;
984263bc
MD
396 goto retry;
397 }
398
399 /*
400 * Make sure we add at least one bridge since some old
401 * hardware doesn't actually have a host-pci bridge device.
402 * Note that pci_cfgregopen() thinks we have PCI devices..
403 */
404 if (!found) {
405 if (bootverbose)
406 printf(
407 "nexus_pcib_identify: no bridge found, adding pcib0 anyway\n");
024db3fc
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408 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
409 nexus_set_pcibus(child, 0);
984263bc 410 }
39b5d600 411 return (0);
984263bc
MD
412}
413
414static int
415nexus_pcib_probe(device_t dev)
416{
024db3fc
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417 devclass_t pci_devclass;
418
419 if (pci_cfgregopen() == 0)
420 return (ENXIO);
421 /*
422 * Check to see if we haven't already had a PCI bus added
423 * via some other means. If we have, bail since otherwise
424 * we're going to end up duplicating it.
425 */
426 if ((pci_devclass = devclass_find("pci")) &&
427 devclass_get_device(pci_devclass, device_get_unit(dev)))
428 return (ENXIO);
429
430 return (0);
431}
432
433static int
434nexus_pcib_attach(device_t dev)
435{
436 device_t child;
437
438 child = device_add_child(dev, "pci", device_get_unit(dev));
439
440 return (bus_generic_attach(dev));
441}
442
443static int
444nexus_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
445{
446 switch (which) {
447 case PCIB_IVAR_BUS:
448 *result = nexus_get_pcibus(dev);
449 return (0);
450 }
451 return (ENOENT);
452}
453
454static int
455nexus_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
456{
457 switch (which) {
458 case PCIB_IVAR_BUS:
459 nexus_set_pcibus(dev, value);
460 return (0);
984263bc 461 }
024db3fc 462 return (ENOENT);
984263bc
MD
463}
464
465/* route interrupt */
466
467static int
468nexus_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
469{
bbca97bc
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470 return(pci_cfgintr(pci_get_bus(dev), pci_get_slot(dev), pin,
471 pci_get_irq(dev)));
984263bc
MD
472}
473
474static device_method_t nexus_pcib_methods[] = {
475 /* Device interface */
476 DEVMETHOD(device_identify, nexus_pcib_identify),
477 DEVMETHOD(device_probe, nexus_pcib_probe),
024db3fc 478 DEVMETHOD(device_attach, nexus_pcib_attach),
984263bc
MD
479 DEVMETHOD(device_shutdown, bus_generic_shutdown),
480 DEVMETHOD(device_suspend, bus_generic_suspend),
481 DEVMETHOD(device_resume, bus_generic_resume),
482
483 /* Bus interface */
484 DEVMETHOD(bus_print_child, bus_generic_print_child),
024db3fc
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485 DEVMETHOD(bus_read_ivar, nexus_pcib_read_ivar),
486 DEVMETHOD(bus_write_ivar, nexus_pcib_write_ivar),
984263bc
MD
487 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
488 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
489 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
490 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
491 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
492 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
493
67eccedb
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494 /* pcib interface */
495 DEVMETHOD(pcib_maxslots, nexus_pcib_maxslots),
496 DEVMETHOD(pcib_read_config, nexus_pcib_read_config),
497 DEVMETHOD(pcib_write_config, nexus_pcib_write_config),
498 DEVMETHOD(pcib_route_interrupt, nexus_pcib_route_interrupt),
499
984263bc
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500 { 0, 0 }
501};
502
39b5d600
MD
503/*
504 * This causes nexus_pcib_identify() to automatically be called when
505 * nexus is attaching.
506 */
984263bc
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507static driver_t nexus_pcib_driver = {
508 "pcib",
509 nexus_pcib_methods,
510 1,
511};
512
513DRIVER_MODULE(pcib, nexus, nexus_pcib_driver, pcib_devclass, 0, 0);
67eccedb
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514
515
516/*
8eb64136
MD
517 * XXX may have to disable the registration entirely to support module-loaded
518 * bridges such as agp.ko.
519 *
67eccedb
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520 * Provide a device to "eat" the host->pci bridges that we dug up above
521 * and stop them showing up twice on the probes. This also stops them
522 * showing up as 'none' in pciconf -l.
8eb64136
MD
523 *
524 * Return an ultra-low priority so other devices can attach the bus before
525 * our dummy attach.
67eccedb
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526 */
527static int
528pci_hostb_probe(device_t dev)
529{
530 if (pci_get_class(dev) == PCIC_BRIDGE &&
531 pci_get_subclass(dev) == PCIS_BRIDGE_HOST) {
532 device_set_desc(dev, "Host to PCI bridge");
533 device_quiet(dev);
8eb64136 534 return -10000;
67eccedb
JS
535 }
536 return (ENXIO);
537}
538
539static int
540pci_hostb_attach(device_t dev)
541{
542 return (0);
543}
544
545static device_method_t pci_hostb_methods[] = {
546 /* Device interface */
547 DEVMETHOD(device_probe, pci_hostb_probe),
548 DEVMETHOD(device_attach, pci_hostb_attach),
549 DEVMETHOD(device_shutdown, bus_generic_shutdown),
550 DEVMETHOD(device_suspend, bus_generic_suspend),
551 DEVMETHOD(device_resume, bus_generic_resume),
552
553 { 0, 0 }
554};
555static driver_t pci_hostb_driver = {
556 "hostb",
557 pci_hostb_methods,
558 1,
559};
560static devclass_t pci_hostb_devclass;
561
562DRIVER_MODULE(hostb, pci, pci_hostb_driver, pci_hostb_devclass, 0, 0);
563
564
565/*
566 * Install placeholder to claim the resources owned by the
567 * PCI bus interface. This could be used to extract the
568 * config space registers in the extreme case where the PnP
569 * ID is available and the PCI BIOS isn't, but for now we just
570 * eat the PnP ID and do nothing else.
571 *
572 * XXX we should silence this probe, as it will generally confuse
573 * people.
574 */
575static struct isa_pnp_id pcibus_pnp_ids[] = {
576 { 0x030ad041 /* PNP030A */, "PCI Bus" },
577 { 0 }
578};
579
580static int
581pcibus_pnp_probe(device_t dev)
582{
583 int result;
584
585 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
586 device_quiet(dev);
587 return (result);
588}
589
590static int
591pcibus_pnp_attach(device_t dev)
592{
593 return(0);
594}
595
596static device_method_t pcibus_pnp_methods[] = {
597 /* Device interface */
598 DEVMETHOD(device_probe, pcibus_pnp_probe),
599 DEVMETHOD(device_attach, pcibus_pnp_attach),
600 DEVMETHOD(device_detach, bus_generic_detach),
601 DEVMETHOD(device_shutdown, bus_generic_shutdown),
602 DEVMETHOD(device_suspend, bus_generic_suspend),
603 DEVMETHOD(device_resume, bus_generic_resume),
604 { 0, 0 }
605};
606
607static driver_t pcibus_pnp_driver = {
608 "pcibus_pnp",
609 pcibus_pnp_methods,
610 1, /* no softc */
611};
612
613static devclass_t pcibus_pnp_devclass;
614
615DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);