Cleanup some of the newbus infrastructure.
[dragonfly.git] / sys / platform / pc32 / isa / npx.c
CommitLineData
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1/*-
2 * Copyright (c) 1990 William Jolitz.
3 * Copyright (c) 1991 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 * $FreeBSD: src/sys/i386/isa/npx.c,v 1.80.2.3 2001/10/20 19:04:38 tegge Exp $
39b5d600 36 * $DragonFly: src/sys/platform/pc32/isa/npx.c,v 1.26 2005/10/28 03:25:57 dillon Exp $
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37 */
38
39#include "opt_cpu.h"
40#include "opt_debug_npx.h"
41#include "opt_math_emulate.h"
42
43#include <sys/param.h>
44#include <sys/systm.h>
45#include <sys/bus.h>
46#include <sys/kernel.h>
47#include <sys/malloc.h>
48#include <sys/module.h>
49#include <sys/sysctl.h>
50#include <sys/proc.h>
51#include <machine/bus.h>
52#include <sys/rman.h>
53#ifdef NPX_DEBUG
54#include <sys/syslog.h>
55#endif
56#include <sys/signalvar.h>
bd331ffe 57#include <sys/thread2.h>
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58
59#ifndef SMP
60#include <machine/asmacros.h>
61#endif
62#include <machine/cputypes.h>
63#include <machine/frame.h>
64#include <machine/ipl.h>
65#include <machine/md_var.h>
66#include <machine/pcb.h>
67#include <machine/psl.h>
68#ifndef SMP
69#include <machine/clock.h>
70#endif
71#include <machine/resource.h>
72#include <machine/specialreg.h>
73#include <machine/segments.h>
85100692 74#include <machine/globaldata.h>
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75
76#ifndef SMP
77#include <i386/isa/icu.h>
78#include <i386/isa/intr_machdep.h>
1f2de5d4 79#include <bus/isa/i386/isa.h>
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80#endif
81
82/*
83 * 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
84 */
85
86/* Configuration flags. */
87#define NPX_DISABLE_I586_OPTIMIZED_BCOPY (1 << 0)
88#define NPX_DISABLE_I586_OPTIMIZED_BZERO (1 << 1)
89#define NPX_DISABLE_I586_OPTIMIZED_COPYIO (1 << 2)
90#define NPX_PREFER_EMULATOR (1 << 3)
91
92#ifdef __GNUC__
93
94#define fldcw(addr) __asm("fldcw %0" : : "m" (*(addr)))
95#define fnclex() __asm("fnclex")
96#define fninit() __asm("fninit")
97#define fnop() __asm("fnop")
98#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
99#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
100#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
101#define fp_divide_by_0() __asm("fldz; fld1; fdiv %st,%st(1); fnop")
102#define frstor(addr) __asm("frstor %0" : : "m" (*(addr)))
642a6e88 103#ifndef CPU_DISABLE_SSE
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104#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
105#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
106#endif
107#define start_emulating() __asm("smsw %%ax; orb %0,%%al; lmsw %%ax" \
108 : : "n" (CR0_TS) : "ax")
109#define stop_emulating() __asm("clts")
110
111#else /* not __GNUC__ */
112
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113void fldcw (caddr_t addr);
114void fnclex (void);
115void fninit (void);
116void fnop (void);
117void fnsave (caddr_t addr);
118void fnstcw (caddr_t addr);
119void fnstsw (caddr_t addr);
120void fp_divide_by_0 (void);
121void frstor (caddr_t addr);
642a6e88 122#ifndef CPU_DISABLE_SSE
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123void fxsave (caddr_t addr);
124void fxrstor (caddr_t addr);
984263bc 125#endif
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126void start_emulating (void);
127void stop_emulating (void);
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128
129#endif /* __GNUC__ */
130
642a6e88 131#ifndef CPU_DISABLE_SSE
65d6ce10 132#define GET_FPU_EXSW_PTR(td) \
984263bc 133 (cpu_fxsr ? \
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134 &(td)->td_savefpu->sv_xmm.sv_ex_sw : \
135 &(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 136#else /* CPU_DISABLE_SSE */
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137#define GET_FPU_EXSW_PTR(td) \
138 (&(td)->td_savefpu->sv_87.sv_ex_sw)
642a6e88 139#endif /* CPU_DISABLE_SSE */
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140
141typedef u_char bool_t;
142
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143static int npx_attach (device_t dev);
144 void npx_intr (void *);
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145static int npx_probe (device_t dev);
146static int npx_probe1 (device_t dev);
147static void fpusave (union savefpu *);
148static void fpurstor (union savefpu *);
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149
150int hw_float; /* XXX currently just alias for npx_exists */
151
152SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
153 CTLFLAG_RD, &hw_float, 0,
154 "Floatingpoint instructions executed in hardware");
629f74cc 155#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
29ad119f 156int mmxopt = 1;
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157SYSCTL_INT(_kern, OID_AUTO, mmxopt, CTLFLAG_RD, &mmxopt, 0,
158 "MMX/XMM optimized bcopy/copyin/copyout support");
159#endif
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160
161#ifndef SMP
38787eef 162static u_int npx0_imask;
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163static struct gate_descriptor npx_idt_probeintr;
164static int npx_intrno;
165static volatile u_int npx_intrs_while_probing;
166static volatile u_int npx_traps_while_probing;
167#endif
168
169static bool_t npx_ex16;
170static bool_t npx_exists;
171static bool_t npx_irq13;
172static int npx_irq; /* irq number */
173
174#ifndef SMP
175/*
176 * Special interrupt handlers. Someday intr0-intr15 will be used to count
177 * interrupts. We'll still need a special exception 16 handler. The busy
178 * latch stuff in probeintr() can be moved to npxprobe().
179 */
180inthand_t probeintr;
181__asm(" \n\
182 .text \n\
183 .p2align 2,0x90 \n\
184 .type " __XSTRING(CNAME(probeintr)) ",@function \n\
185" __XSTRING(CNAME(probeintr)) ": \n\
186 ss \n\
187 incl " __XSTRING(CNAME(npx_intrs_while_probing)) " \n\
188 pushl %eax \n\
189 movb $0x20,%al # EOI (asm in strings loses cpp features) \n\
190 outb %al,$0xa0 # IO_ICU2 \n\
191 outb %al,$0x20 # IO_ICU1 \n\
192 movb $0,%al \n\
193 outb %al,$0xf0 # clear BUSY# latch \n\
194 popl %eax \n\
195 iret \n\
196");
197
198inthand_t probetrap;
199__asm(" \n\
200 .text \n\
201 .p2align 2,0x90 \n\
202 .type " __XSTRING(CNAME(probetrap)) ",@function \n\
203" __XSTRING(CNAME(probetrap)) ": \n\
204 ss \n\
205 incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
206 fnclex \n\
207 iret \n\
208");
209#endif /* SMP */
210
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211/*
212 * Probe routine. Initialize cr0 to give correct behaviour for [f]wait
213 * whether the device exists or not (XXX should be elsewhere). Set flags
214 * to tell npxattach() what to do. Modify device struct if npx doesn't
215 * need to use interrupts. Return 1 if device exists.
216 */
217static int
a02705a9 218npx_probe(device_t dev)
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219{
220#ifdef SMP
221
222 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
223 npx_irq = 13;
224 return npx_probe1(dev);
225
226#else /* SMP */
227
228 int result;
229 u_long save_eflags;
230 u_char save_icu1_mask;
231 u_char save_icu2_mask;
232 struct gate_descriptor save_idt_npxintr;
233 struct gate_descriptor save_idt_npxtrap;
234 /*
235 * This routine is now just a wrapper for npxprobe1(), to install
236 * special npx interrupt and trap handlers, to enable npx interrupts
237 * and to disable other interrupts. Someday isa_configure() will
238 * install suitable handlers and run with interrupts enabled so we
239 * won't need to do so much here.
240 */
241 if (resource_int_value("npx", 0, "irq", &npx_irq) != 0)
242 npx_irq = 13;
243 npx_intrno = NRSVIDT + npx_irq;
244 save_eflags = read_eflags();
8a8d5d85 245 cpu_disable_intr();
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246 save_icu1_mask = inb(IO_ICU1 + 1);
247 save_icu2_mask = inb(IO_ICU2 + 1);
248 save_idt_npxintr = idt[npx_intrno];
249 save_idt_npxtrap = idt[16];
250 outb(IO_ICU1 + 1, ~IRQ_SLAVE);
251 outb(IO_ICU2 + 1, ~(1 << (npx_irq - 8)));
252 setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
253 setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
254 npx_idt_probeintr = idt[npx_intrno];
8a8d5d85 255 cpu_enable_intr();
984263bc 256 result = npx_probe1(dev);
8a8d5d85 257 cpu_disable_intr();
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258 outb(IO_ICU1 + 1, save_icu1_mask);
259 outb(IO_ICU2 + 1, save_icu2_mask);
260 idt[npx_intrno] = save_idt_npxintr;
261 idt[16] = save_idt_npxtrap;
262 write_eflags(save_eflags);
263 return (result);
264
265#endif /* SMP */
266}
267
268static int
a02705a9 269npx_probe1(device_t dev)
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270{
271#ifndef SMP
272 u_short control;
273 u_short status;
274#endif
275
276 /*
277 * Partially reset the coprocessor, if any. Some BIOS's don't reset
278 * it after a warm boot.
279 */
280 outb(0xf1, 0); /* full reset on some systems, NOP on others */
281 outb(0xf0, 0); /* clear BUSY# latch */
282 /*
283 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT
284 * instructions. We must set the CR0_MP bit and use the CR0_TS
285 * bit to control the trap, because setting the CR0_EM bit does
286 * not cause WAIT instructions to trap. It's important to trap
287 * WAIT instructions - otherwise the "wait" variants of no-wait
288 * control instructions would degenerate to the "no-wait" variants
289 * after FP context switches but work correctly otherwise. It's
290 * particularly important to trap WAITs when there is no NPX -
291 * otherwise the "wait" variants would always degenerate.
292 *
293 * Try setting CR0_NE to get correct error reporting on 486DX's.
294 * Setting it should fail or do nothing on lesser processors.
295 */
296 load_cr0(rcr0() | CR0_MP | CR0_NE);
297 /*
298 * But don't trap while we're probing.
299 */
300 stop_emulating();
301 /*
302 * Finish resetting the coprocessor, if any. If there is an error
303 * pending, then we may get a bogus IRQ13, but probeintr() will handle
304 * it OK. Bogus halts have never been observed, but we enabled
305 * IRQ13 and cleared the BUSY# latch early to handle them anyway.
306 */
307 fninit();
308
309#ifdef SMP
310 /*
311 * Exception 16 MUST work for SMP.
312 */
313 npx_irq13 = 0;
314 npx_ex16 = hw_float = npx_exists = 1;
315 device_set_desc(dev, "math processor");
316 return (0);
317
318#else /* !SMP */
319 device_set_desc(dev, "math processor");
320
321 /*
322 * Don't use fwait here because it might hang.
323 * Don't use fnop here because it usually hangs if there is no FPU.
324 */
325 DELAY(1000); /* wait for any IRQ13 */
326#ifdef DIAGNOSTIC
327 if (npx_intrs_while_probing != 0)
328 printf("fninit caused %u bogus npx interrupt(s)\n",
329 npx_intrs_while_probing);
330 if (npx_traps_while_probing != 0)
331 printf("fninit caused %u bogus npx trap(s)\n",
332 npx_traps_while_probing);
333#endif
334 /*
335 * Check for a status of mostly zero.
336 */
337 status = 0x5a5a;
338 fnstsw(&status);
339 if ((status & 0xb8ff) == 0) {
340 /*
341 * Good, now check for a proper control word.
342 */
343 control = 0x5a5a;
344 fnstcw(&control);
345 if ((control & 0x1f3f) == 0x033f) {
346 hw_float = npx_exists = 1;
347 /*
348 * We have an npx, now divide by 0 to see if exception
349 * 16 works.
350 */
351 control &= ~(1 << 2); /* enable divide by 0 trap */
352 fldcw(&control);
353 npx_traps_while_probing = npx_intrs_while_probing = 0;
354 fp_divide_by_0();
355 if (npx_traps_while_probing != 0) {
356 /*
357 * Good, exception 16 works.
358 */
359 npx_ex16 = 1;
360 return (0);
361 }
362 if (npx_intrs_while_probing != 0) {
363 int rid;
364 struct resource *r;
365 void *intr;
366 /*
367 * Bad, we are stuck with IRQ13.
368 */
369 npx_irq13 = 1;
370 /*
371 * npxattach would be too late to set npx0_imask
372 */
373 npx0_imask |= (1 << npx_irq);
374
375 /*
376 * We allocate these resources permanently,
377 * so there is no need to keep track of them.
378 */
379 rid = 0;
380 r = bus_alloc_resource(dev, SYS_RES_IOPORT,
381 &rid, IO_NPX, IO_NPX,
382 IO_NPXSIZE, RF_ACTIVE);
383 if (r == 0)
384 panic("npx: can't get ports");
385 rid = 0;
386 r = bus_alloc_resource(dev, SYS_RES_IRQ,
387 &rid, npx_irq, npx_irq,
388 1, RF_ACTIVE);
389 if (r == 0)
390 panic("npx: can't get IRQ");
391 BUS_SETUP_INTR(device_get_parent(dev),
ee61f228 392 dev, r, 0,
e9cb6d99 393 npx_intr, 0, &intr, NULL);
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394 if (intr == 0)
395 panic("npx: can't create intr");
396
397 return (0);
398 }
399 /*
400 * Worse, even IRQ13 is broken. Use emulator.
401 */
402 }
403 }
404 /*
405 * Probe failed, but we want to get to npxattach to initialize the
406 * emulator and say that it has been installed. XXX handle devices
407 * that aren't really devices better.
408 */
409 return (0);
410#endif /* SMP */
411}
412
413/*
414 * Attach routine - announce which it is, and wire into system
415 */
416int
a02705a9 417npx_attach(device_t dev)
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418{
419 int flags;
420
421 if (resource_int_value("npx", 0, "flags", &flags) != 0)
422 flags = 0;
423
424 if (flags)
425 device_printf(dev, "flags 0x%x ", flags);
426 if (npx_irq13) {
427 device_printf(dev, "using IRQ 13 interface\n");
428 } else {
6f535fd5 429#if defined(MATH_EMULATE)
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430 if (npx_ex16) {
431 if (!(flags & NPX_PREFER_EMULATOR))
432 device_printf(dev, "INT 16 interface\n");
433 else {
434 device_printf(dev, "FPU exists, but flags request "
435 "emulator\n");
436 hw_float = npx_exists = 0;
437 }
438 } else if (npx_exists) {
439 device_printf(dev, "error reporting broken; using 387 emulator\n");
440 hw_float = npx_exists = 0;
441 } else
442 device_printf(dev, "387 emulator\n");
443#else
444 if (npx_ex16) {
445 device_printf(dev, "INT 16 interface\n");
446 if (flags & NPX_PREFER_EMULATOR) {
447 device_printf(dev, "emulator requested, but none compiled "
448 "into kernel, using FPU\n");
449 }
450 } else
451 device_printf(dev, "no 387 emulator in kernel and no FPU!\n");
452#endif
453 }
454 npxinit(__INITIAL_NPXCW__);
455
bd331ffe 456#if (defined(I586_CPU) || defined(I686_CPU)) && !defined(CPU_DISABLE_SSE)
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457 /*
458 * The asm_mmx_*() routines actually use XMM as well, so only
459 * enable them if we have SSE2 and are using FXSR (fxsave/fxrstore).
460 */
461 TUNABLE_INT_FETCH("kern.mmxopt", &mmxopt);
462 if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
463 (cpu_feature & CPUID_SSE2) &&
464 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
465 ) {
466 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
467 bcopy_vector = (void **)asm_xmm_bcopy;
468 ovbcopy_vector = (void **)asm_xmm_bcopy;
469 memcpy_vector = (void **)asm_xmm_memcpy;
470 printf("Using XMM optimized bcopy/copyin/copyout\n");
471 }
472 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
473 /* XXX */
474 }
475 } else if ((cpu_feature & CPUID_MMX) && (cpu_feature & CPUID_SSE) &&
476 npx_ex16 && npx_exists && mmxopt && cpu_fxsr
477 ) {
478 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY) == 0) {
479 bcopy_vector = (void **)asm_mmx_bcopy;
480 ovbcopy_vector = (void **)asm_mmx_bcopy;
481 memcpy_vector = (void **)asm_mmx_memcpy;
482 printf("Using MMX optimized bcopy/copyin/copyout\n");
483 }
484 if ((flags & NPX_DISABLE_I586_OPTIMIZED_BZERO) == 0) {
485 /* XXX */
486 }
487 }
488#endif
489#if 0
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490 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists &&
491 timezero("i586_bzero()", i586_bzero) <
492 timezero("bzero()", bzero) * 4 / 5) {
493 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) {
494 bcopy_vector = i586_bcopy;
495 ovbcopy_vector = i586_bcopy;
496 }
497 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO))
498 bzero = i586_bzero;
499 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) {
500 copyin_vector = i586_copyin;
501 copyout_vector = i586_copyout;
502 }
503 }
504#endif
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505 return (0); /* XXX unused */
506}
507
508/*
a02705a9 509 * Initialize the floating point unit.
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510 */
511void
a02705a9 512npxinit(u_short control)
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513{
514 static union savefpu dummy;
515
516 if (!npx_exists)
517 return;
518 /*
519 * fninit has the same h/w bugs as fnsave. Use the detoxified
520 * fnsave to throw away any junk in the fpu. npxsave() initializes
af0bff84 521 * the fpu and sets npxthread = NULL as important side effects.
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522 */
523 npxsave(&dummy);
a02705a9 524 crit_enter();
984263bc 525 stop_emulating();
984263bc 526 fldcw(&control);
65d6ce10 527 fpusave(curthread->td_savefpu);
a02705a9 528 mdcpu->gd_npxthread = NULL;
984263bc 529 start_emulating();
a02705a9 530 crit_exit();
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531}
532
533/*
534 * Free coprocessor (if we have it).
535 */
536void
85100692 537npxexit(struct proc *p)
984263bc 538{
a2a5ad0d 539 if (p->p_thread == mdcpu->gd_npxthread)
65d6ce10 540 npxsave(curthread->td_savefpu);
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541#ifdef NPX_DEBUG
542 if (npx_exists) {
543 u_int masked_exceptions;
544
b7c628e4 545 masked_exceptions =
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546 curthread->td_savefpu->sv_87.sv_env.en_cw
547 & curthread->td_savefpu->sv_87.sv_env.en_sw & 0x7f;
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548 /*
549 * Log exceptions that would have trapped with the old
550 * control word (overflow, divide by 0, and invalid operand).
551 */
552 if (masked_exceptions & 0x0d)
553 log(LOG_ERR,
554 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
555 p->p_pid, p->p_comm, masked_exceptions);
556 }
557#endif
558}
559
560/*
561 * The following mechanism is used to ensure that the FPE_... value
562 * that is passed as a trapcode to the signal handler of the user
563 * process does not have more than one bit set.
564 *
565 * Multiple bits may be set if the user process modifies the control
566 * word while a status word bit is already set. While this is a sign
567 * of bad coding, we have no choise than to narrow them down to one
568 * bit, since we must not send a trapcode that is not exactly one of
569 * the FPE_ macros.
570 *
571 * The mechanism has a static table with 127 entries. Each combination
572 * of the 7 FPU status word exception bits directly translates to a
573 * position in this table, where a single FPE_... value is stored.
574 * This FPE_... value stored there is considered the "most important"
575 * of the exception bits and will be sent as the signal code. The
576 * precedence of the bits is based upon Intel Document "Numerical
577 * Applications", Chapter "Special Computational Situations".
578 *
579 * The macro to choose one of these values does these steps: 1) Throw
580 * away status word bits that cannot be masked. 2) Throw away the bits
581 * currently masked in the control word, assuming the user isn't
582 * interested in them anymore. 3) Reinsert status word bit 7 (stack
583 * fault) if it is set, which cannot be masked but must be presered.
584 * 4) Use the remaining bits to point into the trapcode table.
585 *
586 * The 6 maskable bits in order of their preference, as stated in the
587 * above referenced Intel manual:
588 * 1 Invalid operation (FP_X_INV)
589 * 1a Stack underflow
590 * 1b Stack overflow
591 * 1c Operand of unsupported format
592 * 1d SNaN operand.
593 * 2 QNaN operand (not an exception, irrelavant here)
594 * 3 Any other invalid-operation not mentioned above or zero divide
595 * (FP_X_INV, FP_X_DZ)
596 * 4 Denormal operand (FP_X_DNML)
597 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
598 * 6 Inexact result (FP_X_IMP)
599 */
600static char fpetable[128] = {
601 0,
602 FPE_FLTINV, /* 1 - INV */
603 FPE_FLTUND, /* 2 - DNML */
604 FPE_FLTINV, /* 3 - INV | DNML */
605 FPE_FLTDIV, /* 4 - DZ */
606 FPE_FLTINV, /* 5 - INV | DZ */
607 FPE_FLTDIV, /* 6 - DNML | DZ */
608 FPE_FLTINV, /* 7 - INV | DNML | DZ */
609 FPE_FLTOVF, /* 8 - OFL */
610 FPE_FLTINV, /* 9 - INV | OFL */
611 FPE_FLTUND, /* A - DNML | OFL */
612 FPE_FLTINV, /* B - INV | DNML | OFL */
613 FPE_FLTDIV, /* C - DZ | OFL */
614 FPE_FLTINV, /* D - INV | DZ | OFL */
615 FPE_FLTDIV, /* E - DNML | DZ | OFL */
616 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
617 FPE_FLTUND, /* 10 - UFL */
618 FPE_FLTINV, /* 11 - INV | UFL */
619 FPE_FLTUND, /* 12 - DNML | UFL */
620 FPE_FLTINV, /* 13 - INV | DNML | UFL */
621 FPE_FLTDIV, /* 14 - DZ | UFL */
622 FPE_FLTINV, /* 15 - INV | DZ | UFL */
623 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
624 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
625 FPE_FLTOVF, /* 18 - OFL | UFL */
626 FPE_FLTINV, /* 19 - INV | OFL | UFL */
627 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
628 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
629 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
630 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
631 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
632 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
633 FPE_FLTRES, /* 20 - IMP */
634 FPE_FLTINV, /* 21 - INV | IMP */
635 FPE_FLTUND, /* 22 - DNML | IMP */
636 FPE_FLTINV, /* 23 - INV | DNML | IMP */
637 FPE_FLTDIV, /* 24 - DZ | IMP */
638 FPE_FLTINV, /* 25 - INV | DZ | IMP */
639 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
640 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
641 FPE_FLTOVF, /* 28 - OFL | IMP */
642 FPE_FLTINV, /* 29 - INV | OFL | IMP */
643 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
644 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
645 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
646 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
647 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
648 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
649 FPE_FLTUND, /* 30 - UFL | IMP */
650 FPE_FLTINV, /* 31 - INV | UFL | IMP */
651 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
652 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
653 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
654 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
655 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
656 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
657 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
658 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
659 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
660 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
661 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
662 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
663 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
664 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
665 FPE_FLTSUB, /* 40 - STK */
666 FPE_FLTSUB, /* 41 - INV | STK */
667 FPE_FLTUND, /* 42 - DNML | STK */
668 FPE_FLTSUB, /* 43 - INV | DNML | STK */
669 FPE_FLTDIV, /* 44 - DZ | STK */
670 FPE_FLTSUB, /* 45 - INV | DZ | STK */
671 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
672 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
673 FPE_FLTOVF, /* 48 - OFL | STK */
674 FPE_FLTSUB, /* 49 - INV | OFL | STK */
675 FPE_FLTUND, /* 4A - DNML | OFL | STK */
676 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
677 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
678 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
679 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
680 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
681 FPE_FLTUND, /* 50 - UFL | STK */
682 FPE_FLTSUB, /* 51 - INV | UFL | STK */
683 FPE_FLTUND, /* 52 - DNML | UFL | STK */
684 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
685 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
686 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
687 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
688 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
689 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
690 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
691 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
692 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
693 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
694 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
695 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
696 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
697 FPE_FLTRES, /* 60 - IMP | STK */
698 FPE_FLTSUB, /* 61 - INV | IMP | STK */
699 FPE_FLTUND, /* 62 - DNML | IMP | STK */
700 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
701 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
702 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
703 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
704 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
705 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
706 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
707 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
708 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
709 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
710 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
711 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
712 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
713 FPE_FLTUND, /* 70 - UFL | IMP | STK */
714 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
715 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
716 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
717 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
718 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
719 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
720 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
721 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
722 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
723 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
724 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
725 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
726 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
727 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
728 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
729};
730
731/*
732 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE.
733 *
734 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now
735 * depend on longjmp() restoring a usable state. Restoring the state
736 * or examining it might fail if we didn't clear exceptions.
737 *
738 * The error code chosen will be one of the FPE_... macros. It will be
739 * sent as the second argument to old BSD-style signal handlers and as
740 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers.
741 *
742 * XXX the FP state is not preserved across signal handlers. So signal
743 * handlers cannot afford to do FP unless they preserve the state or
744 * longjmp() out. Both preserving the state and longjmp()ing may be
745 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable
746 * solution for signals other than SIGFPE.
8a8d5d85
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747 *
748 * The MP lock is not held on entry (see i386/i386/exception.s) and
749 * should not be held on exit.
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750 */
751void
a02705a9 752npx_intr(void *dummy)
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753{
754 int code;
755 u_short control;
756 struct intrframe *frame;
757 u_long *exstat;
758
a2a5ad0d 759 if (mdcpu->gd_npxthread == NULL || !npx_exists) {
8a8d5d85 760 get_mplock();
af0bff84 761 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 762 mdcpu->gd_npxthread, curthread, npx_exists);
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763 panic("npxintr from nowhere");
764 }
a2a5ad0d 765 if (mdcpu->gd_npxthread != curthread) {
8a8d5d85 766 get_mplock();
af0bff84 767 printf("npxintr: npxthread = %p, curthread = %p, npx_exists = %d\n",
a2a5ad0d 768 mdcpu->gd_npxthread, curthread, npx_exists);
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769 panic("npxintr from non-current process");
770 }
771
65d6ce10 772 exstat = GET_FPU_EXSW_PTR(curthread);
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773 outb(0xf0, 0);
774 fnstsw(exstat);
775 fnstcw(&control);
776 fnclex();
777
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778 get_mplock();
779
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780 /*
781 * Pass exception to process.
782 */
783 frame = (struct intrframe *)&dummy; /* XXX */
784 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) {
785 /*
786 * Interrupt is essentially a trap, so we can afford to call
787 * the SIGFPE handler (if any) as soon as the interrupt
788 * returns.
789 *
790 * XXX little or nothing is gained from this, and plenty is
791 * lost - the interrupt frame has to contain the trap frame
792 * (this is otherwise only necessary for the rescheduling trap
793 * in doreti, and the frame for that could easily be set up
794 * just before it is used).
795 */
796 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame);
797 /*
798 * Encode the appropriate code for detailed information on
799 * this exception.
800 */
801 code =
802 fpetable[(*exstat & ~control & 0x3f) | (*exstat & 0x40)];
803 trapsignal(curproc, SIGFPE, code);
804 } else {
805 /*
806 * Nested interrupt. These losers occur when:
807 * o an IRQ13 is bogusly generated at a bogus time, e.g.:
808 * o immediately after an fnsave or frstor of an
809 * error state.
810 * o a couple of 386 instructions after
811 * "fstpl _memvar" causes a stack overflow.
812 * These are especially nasty when combined with a
813 * trace trap.
814 * o an IRQ13 occurs at the same time as another higher-
815 * priority interrupt.
816 *
817 * Treat them like a true async interrupt.
818 */
819 psignal(curproc, SIGFPE);
820 }
8a8d5d85 821 rel_mplock();
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822}
823
824/*
a02705a9
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825 * Implement the device not available (DNA) exception. gd_npxthread had
826 * better be NULL. Restore the current thread's FP state and set gd_npxthread
827 * to curthread.
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828 */
829int
a02705a9 830npxdna(void)
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831{
832 u_long *exstat;
833
834 if (!npx_exists)
835 return (0);
a2a5ad0d 836 if (mdcpu->gd_npxthread != NULL) {
af0bff84 837 printf("npxdna: npxthread = %p, curthread = %p\n",
a2a5ad0d 838 mdcpu->gd_npxthread, curthread);
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839 panic("npxdna");
840 }
a02705a9
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841 /*
842 * The setting of gd_npxthread and the call to fpurstor() must not
843 * be preempted by an interrupt thread or we will take an npxdna
844 * trap and potentially save our current fpstate (which is garbage)
845 * and then restore the garbage rather then the originally saved
846 * fpstate.
847 */
bd331ffe 848 crit_enter();
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849 stop_emulating();
850 /*
851 * Record new context early in case frstor causes an IRQ13.
852 */
a2a5ad0d 853 mdcpu->gd_npxthread = curthread;
65d6ce10 854 exstat = GET_FPU_EXSW_PTR(curthread);
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855 *exstat = 0;
856 /*
857 * The following frstor may cause an IRQ13 when the state being
858 * restored has a pending error. The error will appear to have been
859 * triggered by the current (npx) user instruction even when that
860 * instruction is a no-wait instruction that should not trigger an
861 * error (e.g., fnclex). On at least one 486 system all of the
862 * no-wait instructions are broken the same as frstor, so our
863 * treatment does not amplify the breakage. On at least one
864 * 386/Cyrix 387 system, fnclex works correctly while frstor and
865 * fnsave are broken, so our treatment breaks fnclex if it is the
866 * first FPU instruction after a context switch.
867 */
65d6ce10 868 fpurstor(curthread->td_savefpu);
bd331ffe 869 crit_exit();
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870
871 return (1);
872}
873
874/*
a02705a9 875 * Wrapper for the fnsave instruction to handle h/w bugs. If there is an error
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876 * pending, then fnsave generates a bogus IRQ13 on some systems. Force
877 * any IRQ13 to be handled immediately, and then ignore it. This routine is
878 * often called at splhigh so it must not use many system services. In
879 * particular, it's much easier to install a special handler than to
880 * guarantee that it's safe to use npxintr() and its supporting code.
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881 *
882 * WARNING! This call is made during a switch and the MP lock will be
883 * setup for the new target thread rather then the current thread, so we
884 * cannot do anything here that depends on the *_mplock() functions as
885 * we may trip over their assertions.
a02705a9
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886 *
887 * WARNING! When using fxsave we MUST fninit after saving the FP state. The
888 * kernel will always assume that the FP state is 'safe' (will not cause
889 * exceptions) for mmx/xmm use if npxthread is NULL. The kernel must still
890 * setup a custom save area before actually using the FP unit, but it will
891 * not bother calling fninit. This greatly improves kernel performance when
892 * it wishes to use the FP unit.
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893 */
894void
a02705a9 895npxsave(union savefpu *addr)
984263bc 896{
642a6e88 897#if defined(SMP) || !defined(CPU_DISABLE_SSE)
984263bc 898
a02705a9 899 crit_enter();
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900 stop_emulating();
901 fpusave(addr);
a2a5ad0d 902 mdcpu->gd_npxthread = NULL;
a02705a9 903 fninit();
369f5065 904 start_emulating();
a02705a9 905 crit_exit();
984263bc 906
369f5065 907#else /* !SMP and CPU_DISABLE_SSE */
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908
909 u_char icu1_mask;
910 u_char icu2_mask;
911 u_char old_icu1_mask;
912 u_char old_icu2_mask;
913 struct gate_descriptor save_idt_npxintr;
8a8d5d85 914 u_long save_eflags;
984263bc 915
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916 save_eflags = read_eflags();
917 cpu_disable_intr();
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918 old_icu1_mask = inb(IO_ICU1 + 1);
919 old_icu2_mask = inb(IO_ICU2 + 1);
920 save_idt_npxintr = idt[npx_intrno];
921 outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
922 outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
923 idt[npx_intrno] = npx_idt_probeintr;
8a8d5d85 924 cpu_enable_intr();
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925 stop_emulating();
926 fnsave(addr);
927 fnop();
8a8d5d85 928 cpu_disable_intr();
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929 mdcpu->gd_npxthread = NULL;
930 start_emulating();
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931 icu1_mask = inb(IO_ICU1 + 1); /* masks may have changed */
932 icu2_mask = inb(IO_ICU2 + 1);
933 outb(IO_ICU1 + 1,
934 (icu1_mask & ~npx0_imask) | (old_icu1_mask & npx0_imask));
935 outb(IO_ICU2 + 1,
936 (icu2_mask & ~(npx0_imask >> 8))
937 | (old_icu2_mask & (npx0_imask >> 8)));
938 idt[npx_intrno] = save_idt_npxintr;
8a8d5d85 939 write_eflags(save_eflags); /* back to usual state */
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940
941#endif /* SMP */
942}
943
944static void
a02705a9 945fpusave(union savefpu *addr)
984263bc 946{
642a6e88 947#ifndef CPU_DISABLE_SSE
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948 if (cpu_fxsr)
949 fxsave(addr);
950 else
951#endif
952 fnsave(addr);
953}
954
955static void
a02705a9 956fpurstor(union savefpu *addr)
984263bc 957{
642a6e88 958#ifndef CPU_DISABLE_SSE
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959 if (cpu_fxsr)
960 fxrstor(addr);
961 else
962#endif
963 frstor(addr);
964}
965
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966/*
967 * Because npx is a static device that always exists under nexus,
968 * and is not scanned by the nexus device, we need an identify
969 * function to install the device.
970 */
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971static device_method_t npx_methods[] = {
972 /* Device interface */
39b5d600 973 DEVMETHOD(device_identify, bus_generic_identify),
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974 DEVMETHOD(device_probe, npx_probe),
975 DEVMETHOD(device_attach, npx_attach),
976 DEVMETHOD(device_detach, bus_generic_detach),
977 DEVMETHOD(device_shutdown, bus_generic_shutdown),
978 DEVMETHOD(device_suspend, bus_generic_suspend),
979 DEVMETHOD(device_resume, bus_generic_resume),
980
981 { 0, 0 }
982};
983
984static driver_t npx_driver = {
985 "npx",
986 npx_methods,
987 1, /* no softc */
988};
989
990static devclass_t npx_devclass;
991
992/*
993 * We prefer to attach to the root nexus so that the usual case (exception 16)
994 * doesn't describe the processor as being `on isa'.
995 */
996DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0);