what the heck one last one before i go take a nap...
[dragonfly.git] / sys / i386 / isa / intr_machdep.h
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1/*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
3ae0cd58 34 * $DragonFly: src/sys/i386/isa/Attic/intr_machdep.h,v 1.8 2003/08/26 21:42:19 rob Exp $
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35 */
36
37#ifndef _I386_ISA_INTR_MACHDEP_H_
38#define _I386_ISA_INTR_MACHDEP_H_
39
ef0fdad1 40#ifndef _SYS_INTERRUPT_H_
8a8d5d85 41#ifndef LOCORE
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42#include <sys/interrupt.h>
43#endif
8a8d5d85 44#endif
ef0fdad1 45
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46/*
47 * Low level interrupt code.
48 */
49
50#ifdef _KERNEL
51
52#if defined(SMP) || defined(APIC_IO)
53/*
54 * XXX FIXME: rethink location for all IPI vectors.
55 */
56
57/*
58 APIC TPR priority vector levels:
59
60 0xff (255) +-------------+
61 | | 15 (IPIs: Xspuriousint)
62 0xf0 (240) +-------------+
63 | | 14
64 0xe0 (224) +-------------+
65 | | 13
66 0xd0 (208) +-------------+
67 | | 12
68 0xc0 (192) +-------------+
69 | | 11
70 0xb0 (176) +-------------+
71 | | 10 (IPIs: Xcpustop)
72 0xa0 (160) +-------------+
73 | | 9 (IPIs: Xinvltlb)
74 0x90 (144) +-------------+
75 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
76 0x80 (128) +-------------+
77 | | 7 (FAST_INTR 16-23)
78 0x70 (112) +-------------+
79 | | 6 (FAST_INTR 0-15)
80 0x60 (96) +-------------+
81 | | 5 (IGNORE HW INTS)
82 0x50 (80) +-------------+
83 | | 4 (2nd IO APIC)
84 0x40 (64) +------+------+
85 | | | 3 (upper APIC hardware INTs: PCI)
86 0x30 (48) +------+------+
87 | | 2 (start of hardware INTs: ISA)
88 0x20 (32) +-------------+
89 | | 1 (exceptions, traps, etc.)
90 0x10 (16) +-------------+
91 | | 0 (exceptions, traps, etc.)
92 0x00 (0) +-------------+
93 */
94
95/* IDT vector base for regular (aka. slow) and fast interrupts */
96#define TPR_SLOW_INTS 0x20
97#define TPR_FAST_INTS 0x60
98
99/* blocking values for local APIC Task Priority Register */
100#define TPR_BLOCK_HWI 0x4f /* hardware INTs */
101#define TPR_IGNORE_HWI 0x5f /* ignore INTs */
102#define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
103#define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
8a8d5d85 104#define TPR_IPI_ONLY 0x8f /* ignore FAST INTs */
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105#define TPR_BLOCK_XINVLTLB 0x9f /* */
106#define TPR_BLOCK_XCPUSTOP 0xaf /* */
107#define TPR_BLOCK_ALL 0xff /* all INTs */
108
109
110#ifdef TEST_TEST1
111/* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
112#define XTEST1_OFFSET (ICU_OFFSET + 31)
113#endif /** TEST_TEST1 */
114
115/* TLB shootdowns */
116#define XINVLTLB_OFFSET (ICU_OFFSET + 112)
117
118#ifdef BETTER_CLOCK
119/* inter-cpu clock handling */
120#define XCPUCHECKSTATE_OFFSET (ICU_OFFSET + 113)
121#endif
122
123/* inter-CPU rendezvous */
124#define XRENDEZVOUS_OFFSET (ICU_OFFSET + 114)
125
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126/* IPIQ rendezvous */
127#define XIPIQ_OFFSET (ICU_OFFSET + 115)
128
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129/* IPI to signal CPUs to stop and wait for another CPU to restart them */
130#define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
131
132/*
133 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
134 */
135#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
136
137#endif /* SMP || APIC_IO */
138
139#ifndef LOCORE
140
141/*
142 * Type of the first (asm) part of an interrupt handler.
143 */
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144typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
145typedef void unpendhand_t(void);
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146
147#define IDTVEC(name) __CONCAT(X,name)
148
149extern u_long *intr_countp[]; /* pointers into intrcnt[] */
ef0fdad1 150extern inthand2_t *intr_handler[]; /* C entry points for FAST ints */
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151extern u_int intr_mask[]; /* sets of intrs masked during handling of 1 */
152extern void *intr_unit[]; /* cookies to pass to intr handlers */
153
154inthand_t
155 IDTVEC(fastintr0), IDTVEC(fastintr1),
156 IDTVEC(fastintr2), IDTVEC(fastintr3),
157 IDTVEC(fastintr4), IDTVEC(fastintr5),
158 IDTVEC(fastintr6), IDTVEC(fastintr7),
159 IDTVEC(fastintr8), IDTVEC(fastintr9),
160 IDTVEC(fastintr10), IDTVEC(fastintr11),
161 IDTVEC(fastintr12), IDTVEC(fastintr13),
162 IDTVEC(fastintr14), IDTVEC(fastintr15);
163inthand_t
164 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
165 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
166 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
167 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
168
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169unpendhand_t
170 IDTVEC(fastunpend0), IDTVEC(fastunpend1),
171 IDTVEC(fastunpend2), IDTVEC(fastunpend3),
172 IDTVEC(fastunpend4), IDTVEC(fastunpend5),
173 IDTVEC(fastunpend6), IDTVEC(fastunpend7),
174 IDTVEC(fastunpend8), IDTVEC(fastunpend9),
175 IDTVEC(fastunpend10), IDTVEC(fastunpend11),
176 IDTVEC(fastunpend12), IDTVEC(fastunpend13),
177 IDTVEC(fastunpend14), IDTVEC(fastunpend15);
178
179#if defined(APIC_IO)
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180inthand_t
181 IDTVEC(fastintr16), IDTVEC(fastintr17),
182 IDTVEC(fastintr18), IDTVEC(fastintr19),
183 IDTVEC(fastintr20), IDTVEC(fastintr21),
184 IDTVEC(fastintr22), IDTVEC(fastintr23);
185inthand_t
186 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
187 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
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188unpendhand_t
189 IDTVEC(fastunpend16), IDTVEC(fastunpend17),
190 IDTVEC(fastunpend18), IDTVEC(fastunpend19),
191 IDTVEC(fastunpend20), IDTVEC(fastunpend21),
192 IDTVEC(fastunpend22), IDTVEC(fastunpend23);
193#endif
984263bc 194
ef0fdad1 195#if defined(SMP)
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196inthand_t
197 Xinvltlb, /* TLB shootdowns */
198#ifdef BETTER_CLOCK
199 Xcpucheckstate, /* Check cpu state */
200#endif
201 Xcpuast, /* Additional software trap on other cpu */
202 Xforward_irq, /* Forward irq to cpu holding ISR lock */
203 Xcpustop, /* CPU stops & waits for another CPU to restart it */
204 Xspuriousint, /* handle APIC "spurious INTs" */
96728c05 205 Xipiq, /* handle lwkt_send_ipiq() requests */
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206 Xrendezvous; /* handle CPU rendezvous */
207
208#ifdef TEST_TEST1
209inthand_t
210 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
211#endif /** TEST_TEST1 */
ef0fdad1 212#endif /* SMP */
984263bc 213
ef0fdad1 214void call_fast_unpend(int irq);
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215void isa_defaultirq (void);
216int isa_nmi (int cd);
217int icu_setup (int intr, inthand2_t *func, void *arg,
218 u_int *maskptr, int flags);
219int icu_unset (int intr, inthand2_t *handler);
220int update_intr_masks (void);
221
222intrmask_t splq (intrmask_t mask);
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223
224#define INTR_FAST 0x00000001 /* fast interrupt handler */
225#define INTR_EXCL 0x00010000 /* excl. intr, default is shared */
226
227/*
228 * WARNING: These are internal functions and not to be used by device drivers!
229 * They are subject to change without notice.
230 */
231struct intrec *inthand_add(const char *name, int irq, inthand2_t handler,
232 void *arg, intrmask_t *maskptr, int flags);
233
234int inthand_remove(struct intrec *idesc);
545a1cd3 235void forward_fastint_remote(void *arg);
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236
237#endif /* LOCORE */
238
239#endif /* _KERNEL */
240
241#endif /* !_I386_ISA_INTR_MACHDEP_H_ */