jme: Option file adjustment
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
CommitLineData
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1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
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28 */
29
9de40864 30#include "opt_polling.h"
93bfe1b8 31#include "opt_jme.h"
9de40864 32
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33#include <sys/param.h>
34#include <sys/endian.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/interrupt.h>
38#include <sys/malloc.h>
39#include <sys/proc.h>
40#include <sys/rman.h>
41#include <sys/serialize.h>
31f0d5a2 42#include <sys/serialize2.h>
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43#include <sys/socket.h>
44#include <sys/sockio.h>
45#include <sys/sysctl.h>
46
47#include <net/ethernet.h>
48#include <net/if.h>
49#include <net/bpf.h>
50#include <net/if_arp.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/ifq_var.h>
24dd1705 54#include <net/toeplitz.h>
a6acc6e2 55#include <net/toeplitz2.h>
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56#include <net/vlan/if_vlan_var.h>
57#include <net/vlan/if_vlan_ether.h>
58
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59#include <netinet/in.h>
60
76fbb0b9 61#include <dev/netif/mii_layer/miivar.h>
dbe37f03 62#include <dev/netif/mii_layer/jmphyreg.h>
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63
64#include <bus/pci/pcireg.h>
65#include <bus/pci/pcivar.h>
66#include <bus/pci/pcidevs.h>
67
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68#include <dev/netif/jme/if_jmereg.h>
69#include <dev/netif/jme/if_jmevar.h>
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70
71#include "miibus_if.h"
72
73/* Define the following to disable printing Rx errors. */
74#undef JME_SHOW_ERRORS
75
76#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
77
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78#ifdef JME_RSS_DEBUG
79#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
80do { \
66f75939 81 if ((sc)->jme_rss_debug >= (lvl)) \
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82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
83} while (0)
84#else /* !JME_RSS_DEBUG */
85#define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86#endif /* JME_RSS_DEBUG */
87
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88static int jme_probe(device_t);
89static int jme_attach(device_t);
90static int jme_detach(device_t);
91static int jme_shutdown(device_t);
92static int jme_suspend(device_t);
93static int jme_resume(device_t);
94
95static int jme_miibus_readreg(device_t, int, int);
96static int jme_miibus_writereg(device_t, int, int, int);
97static void jme_miibus_statchg(device_t);
98
99static void jme_init(void *);
100static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101static void jme_start(struct ifnet *);
102static void jme_watchdog(struct ifnet *);
103static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104static int jme_mediachange(struct ifnet *);
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105#ifdef DEVICE_POLLING
106static void jme_poll(struct ifnet *, enum poll_cmd, int);
107#endif
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108static void jme_serialize(struct ifnet *, enum ifnet_serialize);
109static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
110static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
111#ifdef INVARIANTS
112static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
113 boolean_t);
114#endif
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115
116static void jme_intr(void *);
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117static void jme_msix_tx(void *);
118static void jme_msix_rx(void *);
76fbb0b9 119static void jme_txeof(struct jme_softc *);
dea2452a 120static void jme_rxeof(struct jme_rxdata *, int);
4447c752 121static void jme_rx_intr(struct jme_softc *, uint32_t);
76fbb0b9 122
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123static int jme_msix_setup(device_t);
124static void jme_msix_teardown(device_t, int);
125static int jme_intr_setup(device_t);
126static void jme_intr_teardown(device_t);
127static void jme_msix_try_alloc(device_t);
128static void jme_msix_free(device_t);
129static int jme_intr_alloc(device_t);
130static void jme_intr_free(device_t);
76fbb0b9 131static int jme_dma_alloc(struct jme_softc *);
0b3414d9 132static void jme_dma_free(struct jme_softc *);
dea2452a 133static int jme_init_rx_ring(struct jme_rxdata *);
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134static void jme_init_tx_ring(struct jme_softc *);
135static void jme_init_ssb(struct jme_softc *);
dea2452a 136static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
76fbb0b9 137static int jme_encap(struct jme_softc *, struct mbuf **);
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138static void jme_rxpkt(struct jme_rxdata *);
139static int jme_rxring_dma_alloc(struct jme_rxdata *);
140static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
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141
142static void jme_tick(void *);
143static void jme_stop(struct jme_softc *);
144static void jme_reset(struct jme_softc *);
58880b0d 145static void jme_set_msinum(struct jme_softc *);
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146static void jme_set_vlan(struct jme_softc *);
147static void jme_set_filter(struct jme_softc *);
148static void jme_stop_tx(struct jme_softc *);
149static void jme_stop_rx(struct jme_softc *);
150static void jme_mac_config(struct jme_softc *);
151static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
152static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
153static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
154#ifdef notyet
155static void jme_setwol(struct jme_softc *);
156static void jme_setlinkspeed(struct jme_softc *);
157#endif
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158static void jme_set_tx_coal(struct jme_softc *);
159static void jme_set_rx_coal(struct jme_softc *);
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160static void jme_enable_rss(struct jme_softc *);
161static void jme_disable_rss(struct jme_softc *);
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162
163static void jme_sysctl_node(struct jme_softc *);
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164static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
165static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
166static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
167static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
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168
169/*
170 * Devices supported by this driver.
171 */
172static const struct jme_dev {
173 uint16_t jme_vendorid;
174 uint16_t jme_deviceid;
3a5f3f36 175 uint32_t jme_caps;
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176 const char *jme_name;
177} jme_devs[] = {
44e8c66c 178 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
3a5f3f36 179 JME_CAP_JUMBO,
76fbb0b9 180 "JMicron Inc, JMC250 Gigabit Ethernet" },
44e8c66c 181 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
3a5f3f36 182 JME_CAP_FASTETH,
76fbb0b9 183 "JMicron Inc, JMC260 Fast Ethernet" },
3a5f3f36 184 { 0, 0, 0, NULL }
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185};
186
187static device_method_t jme_methods[] = {
188 /* Device interface. */
189 DEVMETHOD(device_probe, jme_probe),
190 DEVMETHOD(device_attach, jme_attach),
191 DEVMETHOD(device_detach, jme_detach),
192 DEVMETHOD(device_shutdown, jme_shutdown),
193 DEVMETHOD(device_suspend, jme_suspend),
194 DEVMETHOD(device_resume, jme_resume),
195
196 /* Bus interface. */
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
199
200 /* MII interface. */
201 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
202 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
203 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
204
205 { NULL, NULL }
206};
207
208static driver_t jme_driver = {
209 "jme",
210 jme_methods,
211 sizeof(struct jme_softc)
212};
213
214static devclass_t jme_devclass;
215
216DECLARE_DUMMY_MODULE(if_jme);
217MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
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218DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
219DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
76fbb0b9 220
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221static const struct {
222 uint32_t jme_coal;
223 uint32_t jme_comp;
58880b0d 224 uint32_t jme_empty;
4447c752 225} jme_rx_status[JME_NRXRING_MAX] = {
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226 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
227 INTR_RXQ0_DESC_EMPTY },
228 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
229 INTR_RXQ1_DESC_EMPTY },
230 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
231 INTR_RXQ2_DESC_EMPTY },
232 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
233 INTR_RXQ3_DESC_EMPTY }
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234};
235
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236static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
237static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
46ce9dcc 238static int jme_rx_ring_count = 1;
3eba890a 239static int jme_msi_enable = 1;
58880b0d 240static int jme_msix_enable = 1;
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241
242TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
243TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
413d06bb 244TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
3eba890a 245TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
58880b0d 246TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
83b03786 247
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248/*
249 * Read a PHY register on the MII of the JMC250.
250 */
251static int
252jme_miibus_readreg(device_t dev, int phy, int reg)
253{
254 struct jme_softc *sc = device_get_softc(dev);
255 uint32_t val;
256 int i;
257
258 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 259 if (sc->jme_caps & JME_CAP_FPGA) {
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260 if (phy == 0)
261 return (0);
262 } else {
263 if (sc->jme_phyaddr != phy)
264 return (0);
265 }
266
267 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
268 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
269
270 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
271 DELAY(1);
272 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
273 break;
274 }
275 if (i == 0) {
276 device_printf(sc->jme_dev, "phy read timeout: "
277 "phy %d, reg %d\n", phy, reg);
278 return (0);
279 }
280
281 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
282}
283
284/*
285 * Write a PHY register on the MII of the JMC250.
286 */
287static int
288jme_miibus_writereg(device_t dev, int phy, int reg, int val)
289{
290 struct jme_softc *sc = device_get_softc(dev);
291 int i;
292
293 /* For FPGA version, PHY address 0 should be ignored. */
ec7e787b 294 if (sc->jme_caps & JME_CAP_FPGA) {
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295 if (phy == 0)
296 return (0);
297 } else {
298 if (sc->jme_phyaddr != phy)
299 return (0);
300 }
301
302 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
303 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
304 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
305
306 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
307 DELAY(1);
308 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
309 break;
310 }
311 if (i == 0) {
312 device_printf(sc->jme_dev, "phy write timeout: "
313 "phy %d, reg %d\n", phy, reg);
314 }
315
316 return (0);
317}
318
319/*
320 * Callback from MII layer when media changes.
321 */
322static void
323jme_miibus_statchg(device_t dev)
324{
325 struct jme_softc *sc = device_get_softc(dev);
326 struct ifnet *ifp = &sc->arpcom.ac_if;
327 struct mii_data *mii;
328 struct jme_txdesc *txd;
329 bus_addr_t paddr;
4447c752 330 int i, r;
76fbb0b9 331
31f0d5a2 332 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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333
334 if ((ifp->if_flags & IFF_RUNNING) == 0)
335 return;
336
337 mii = device_get_softc(sc->jme_miibus);
338
339 sc->jme_flags &= ~JME_FLAG_LINK;
340 if ((mii->mii_media_status & IFM_AVALID) != 0) {
341 switch (IFM_SUBTYPE(mii->mii_media_active)) {
342 case IFM_10_T:
343 case IFM_100_TX:
344 sc->jme_flags |= JME_FLAG_LINK;
345 break;
346 case IFM_1000_T:
ec7e787b 347 if (sc->jme_caps & JME_CAP_FASTETH)
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348 break;
349 sc->jme_flags |= JME_FLAG_LINK;
350 break;
351 default:
352 break;
353 }
354 }
355
356 /*
357 * Disabling Rx/Tx MACs have a side-effect of resetting
358 * JME_TXNDA/JME_RXNDA register to the first address of
359 * Tx/Rx descriptor address. So driver should reset its
360 * internal procucer/consumer pointer and reclaim any
361 * allocated resources. Note, just saving the value of
362 * JME_TXNDA and JME_RXNDA registers before stopping MAC
363 * and restoring JME_TXNDA/JME_RXNDA register is not
364 * sufficient to make sure correct MAC state because
365 * stopping MAC operation can take a while and hardware
366 * might have updated JME_TXNDA/JME_RXNDA registers
367 * during the stop operation.
368 */
369
370 /* Disable interrupts */
371 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
372
373 /* Stop driver */
374 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
375 ifp->if_timer = 0;
376 callout_stop(&sc->jme_tick_ch);
377
378 /* Stop receiver/transmitter. */
379 jme_stop_rx(sc);
380 jme_stop_tx(sc);
381
7b040092 382 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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383 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
384
dea2452a 385 jme_rxeof(rdata, -1);
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386 if (rdata->jme_rxhead != NULL)
387 m_freem(rdata->jme_rxhead);
dea2452a 388 JME_RXCHAIN_RESET(rdata);
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389
390 /*
391 * Reuse configured Rx descriptors and reset
392 * procuder/consumer index.
393 */
394 rdata->jme_rx_cons = 0;
395 }
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396
397 jme_txeof(sc);
398 if (sc->jme_cdata.jme_tx_cnt != 0) {
399 /* Remove queued packets for transmit. */
69325526 400 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
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401 txd = &sc->jme_cdata.jme_txdesc[i];
402 if (txd->tx_m != NULL) {
403 bus_dmamap_unload(
404 sc->jme_cdata.jme_tx_tag,
405 txd->tx_dmamap);
406 m_freem(txd->tx_m);
407 txd->tx_m = NULL;
408 txd->tx_ndesc = 0;
409 ifp->if_oerrors++;
410 }
411 }
412 }
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413 jme_init_tx_ring(sc);
414
415 /* Initialize shadow status block. */
416 jme_init_ssb(sc);
417
418 /* Program MAC with resolved speed/duplex/flow-control. */
419 if (sc->jme_flags & JME_FLAG_LINK) {
420 jme_mac_config(sc);
421
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422 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
423
424 /* Set Tx ring address to the hardware. */
7405bec3 425 paddr = sc->jme_cdata.jme_tx_ring_paddr;
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426 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
427 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
428
7b040092 429 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
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430 CSR_WRITE_4(sc, JME_RXCSR,
431 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
432
433 /* Set Rx ring address to the hardware. */
434 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
435 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
436 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
437 }
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438
439 /* Restart receiver/transmitter. */
440 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
441 RXCSR_RXQ_START);
442 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
443 }
444
445 ifp->if_flags |= IFF_RUNNING;
446 ifp->if_flags &= ~IFF_OACTIVE;
447 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
448
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449#ifdef DEVICE_POLLING
450 if (!(ifp->if_flags & IFF_POLLING))
451#endif
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452 /* Reenable interrupts. */
453 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
454}
455
456/*
457 * Get the current interface media status.
458 */
459static void
460jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
461{
462 struct jme_softc *sc = ifp->if_softc;
463 struct mii_data *mii = device_get_softc(sc->jme_miibus);
464
31f0d5a2 465 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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466
467 mii_pollstat(mii);
468 ifmr->ifm_status = mii->mii_media_status;
469 ifmr->ifm_active = mii->mii_media_active;
470}
471
472/*
473 * Set hardware to newly-selected media.
474 */
475static int
476jme_mediachange(struct ifnet *ifp)
477{
478 struct jme_softc *sc = ifp->if_softc;
479 struct mii_data *mii = device_get_softc(sc->jme_miibus);
480 int error;
481
31f0d5a2 482 ASSERT_IFNET_SERIALIZED_ALL(ifp);
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483
484 if (mii->mii_instance != 0) {
485 struct mii_softc *miisc;
486
487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
488 mii_phy_reset(miisc);
489 }
490 error = mii_mediachg(mii);
491
492 return (error);
493}
494
495static int
496jme_probe(device_t dev)
497{
498 const struct jme_dev *sp;
499 uint16_t vid, did;
500
501 vid = pci_get_vendor(dev);
502 did = pci_get_device(dev);
503 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
504 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
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505 struct jme_softc *sc = device_get_softc(dev);
506
507 sc->jme_caps = sp->jme_caps;
76fbb0b9 508 device_set_desc(dev, sp->jme_name);
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509 return (0);
510 }
511 }
512 return (ENXIO);
513}
514
515static int
516jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
517{
518 uint32_t reg;
519 int i;
520
521 *val = 0;
522 for (i = JME_TIMEOUT; i > 0; i--) {
523 reg = CSR_READ_4(sc, JME_SMBCSR);
524 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
525 break;
526 DELAY(1);
527 }
528
529 if (i == 0) {
530 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
531 return (ETIMEDOUT);
532 }
533
534 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
535 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
536 for (i = JME_TIMEOUT; i > 0; i--) {
537 DELAY(1);
538 reg = CSR_READ_4(sc, JME_SMBINTF);
539 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
540 break;
541 }
542
543 if (i == 0) {
544 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
545 return (ETIMEDOUT);
546 }
547
548 reg = CSR_READ_4(sc, JME_SMBINTF);
549 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
550
551 return (0);
552}
553
554static int
555jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
556{
557 uint8_t fup, reg, val;
558 uint32_t offset;
559 int match;
560
561 offset = 0;
562 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
563 fup != JME_EEPROM_SIG0)
564 return (ENOENT);
565 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
566 fup != JME_EEPROM_SIG1)
567 return (ENOENT);
568 match = 0;
569 do {
570 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
571 break;
09927fe6
SZ
572 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
573 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
76fbb0b9
SZ
574 if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
575 break;
576 if (reg >= JME_PAR0 &&
577 reg < JME_PAR0 + ETHER_ADDR_LEN) {
578 if (jme_eeprom_read_byte(sc, offset + 2,
579 &val) != 0)
580 break;
581 eaddr[reg - JME_PAR0] = val;
582 match++;
583 }
584 }
09927fe6
SZ
585 /* Check for the end of EEPROM descriptor. */
586 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
587 break;
76fbb0b9
SZ
588 /* Try next eeprom descriptor. */
589 offset += JME_EEPROM_DESC_BYTES;
590 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
591
592 if (match == ETHER_ADDR_LEN)
593 return (0);
594
595 return (ENOENT);
596}
597
598static void
599jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
600{
601 uint32_t par0, par1;
602
603 /* Read station address. */
604 par0 = CSR_READ_4(sc, JME_PAR0);
605 par1 = CSR_READ_4(sc, JME_PAR1);
606 par1 &= 0xFFFF;
607 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
608 device_printf(sc->jme_dev,
609 "generating fake ethernet address.\n");
610 par0 = karc4random();
611 /* Set OUI to JMicron. */
612 eaddr[0] = 0x00;
613 eaddr[1] = 0x1B;
614 eaddr[2] = 0x8C;
615 eaddr[3] = (par0 >> 16) & 0xff;
616 eaddr[4] = (par0 >> 8) & 0xff;
617 eaddr[5] = par0 & 0xff;
618 } else {
619 eaddr[0] = (par0 >> 0) & 0xFF;
620 eaddr[1] = (par0 >> 8) & 0xFF;
621 eaddr[2] = (par0 >> 16) & 0xFF;
622 eaddr[3] = (par0 >> 24) & 0xFF;
623 eaddr[4] = (par1 >> 0) & 0xFF;
624 eaddr[5] = (par1 >> 8) & 0xFF;
625 }
626}
627
628static int
629jme_attach(device_t dev)
630{
631 struct jme_softc *sc = device_get_softc(dev);
632 struct ifnet *ifp = &sc->arpcom.ac_if;
633 uint32_t reg;
b249905b
SZ
634 uint16_t did;
635 uint8_t pcie_ptr, rev;
7b040092 636 int error = 0, i, j, rx_desc_cnt;
76fbb0b9
SZ
637 uint8_t eaddr[ETHER_ADDR_LEN];
638
31f0d5a2
SZ
639 lwkt_serialize_init(&sc->jme_serialize);
640 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
641 for (i = 0; i < JME_NRXRING_MAX; ++i) {
642 lwkt_serialize_init(
643 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
644 }
645
7b040092 646 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
1cc217a9 647 jme_rx_desc_count);
7b040092
SZ
648 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
649 if (rx_desc_cnt > JME_NDESC_MAX)
650 rx_desc_cnt = JME_NDESC_MAX;
69325526 651
1cc217a9
SZ
652 sc->jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
653 jme_tx_desc_count);
654 sc->jme_tx_desc_cnt = roundup(sc->jme_tx_desc_cnt, JME_NDESC_ALIGN);
69325526
SZ
655 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
656 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
83b03786 657
9389fe19 658 /*
a317449e 659 * Calculate rx rings
9389fe19 660 */
7b040092 661 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
1cc217a9 662 jme_rx_ring_count);
7b040092
SZ
663 sc->jme_cdata.jme_rx_ring_cnt =
664 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
4447c752 665
31f0d5a2
SZ
666 i = 0;
667 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
668 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
7b040092 669 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
31f0d5a2
SZ
670 sc->jme_serialize_arr[i++] =
671 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
672 }
673 KKASSERT(i <= JME_NSERIALIZE);
674 sc->jme_serialize_cnt = i;
675
58880b0d 676 sc->jme_cdata.jme_sc = sc;
7b040092 677 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
58880b0d
SZ
678 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
679
680 rdata->jme_sc = sc;
681 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
682 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
683 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
684 rdata->jme_rx_idx = i;
7b040092 685 rdata->jme_rx_desc_cnt = rx_desc_cnt;
58880b0d
SZ
686 }
687
76fbb0b9 688 sc->jme_dev = dev;
b249905b
SZ
689 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
690
76fbb0b9
SZ
691 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
692
693 callout_init(&sc->jme_tick_ch);
694
695#ifndef BURN_BRIDGES
696 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
697 uint32_t irq, mem;
698
699 irq = pci_read_config(dev, PCIR_INTLINE, 4);
700 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
701
702 device_printf(dev, "chip is in D%d power mode "
703 "-- setting to D0\n", pci_get_powerstate(dev));
704
705 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
706
707 pci_write_config(dev, PCIR_INTLINE, irq, 4);
708 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
709 }
710#endif /* !BURN_BRIDGE */
711
712 /* Enable bus mastering */
713 pci_enable_busmaster(dev);
714
715 /*
716 * Allocate IO memory
717 *
718 * JMC250 supports both memory mapped and I/O register space
719 * access. Because I/O register access should use different
720 * BARs to access registers it's waste of time to use I/O
721 * register spce access. JMC250 uses 16K to map entire memory
722 * space.
723 */
724 sc->jme_mem_rid = JME_PCIR_BAR;
725 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
726 &sc->jme_mem_rid, RF_ACTIVE);
727 if (sc->jme_mem_res == NULL) {
728 device_printf(dev, "can't allocate IO memory\n");
729 return ENXIO;
730 }
731 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
732 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
733
734 /*
735 * Allocate IRQ
736 */
58880b0d
SZ
737 error = jme_intr_alloc(dev);
738 if (error)
76fbb0b9 739 goto fail;
76fbb0b9
SZ
740
741 /*
b249905b 742 * Extract revisions
76fbb0b9
SZ
743 */
744 reg = CSR_READ_4(sc, JME_CHIPMODE);
745 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
746 CHIPMODE_NOT_FPGA) {
ec7e787b 747 sc->jme_caps |= JME_CAP_FPGA;
76fbb0b9 748 if (bootverbose) {
b249905b 749 device_printf(dev, "FPGA revision: 0x%04x\n",
76fbb0b9
SZ
750 (reg & CHIPMODE_FPGA_REV_MASK) >>
751 CHIPMODE_FPGA_REV_SHIFT);
752 }
753 }
754
b249905b
SZ
755 /* NOTE: FM revision is put in the upper 4 bits */
756 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
757 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
758 if (bootverbose)
759 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
760
761 did = pci_get_device(dev);
762 switch (did) {
763 case PCI_PRODUCT_JMICRON_JMC250:
764 if (rev == JME_REV1_A2)
765 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
766 break;
767
768 case PCI_PRODUCT_JMICRON_JMC260:
769 if (rev == JME_REV2)
770 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
771 break;
772
773 default:
774 panic("unknown device id 0x%04x\n", did);
775 }
776 if (rev >= JME_REV2) {
777 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
778 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
779 GHC_TXMAC_CLKSRC_1000;
780 }
781
76fbb0b9
SZ
782 /* Reset the ethernet controller. */
783 jme_reset(sc);
784
58880b0d
SZ
785 /* Map MSI/MSI-X vectors */
786 jme_set_msinum(sc);
787
76fbb0b9
SZ
788 /* Get station address. */
789 reg = CSR_READ_4(sc, JME_SMBCSR);
790 if (reg & SMBCSR_EEPROM_PRESENT)
791 error = jme_eeprom_macaddr(sc, eaddr);
792 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
793 if (error != 0 && (bootverbose)) {
794 device_printf(dev, "ethernet hardware address "
795 "not found in EEPROM.\n");
796 }
797 jme_reg_macaddr(sc, eaddr);
798 }
799
800 /*
801 * Save PHY address.
802 * Integrated JR0211 has fixed PHY address whereas FPGA version
803 * requires PHY probing to get correct PHY address.
804 */
ec7e787b 805 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
76fbb0b9
SZ
806 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
807 GPREG0_PHY_ADDR_MASK;
808 if (bootverbose) {
809 device_printf(dev, "PHY is at address %d.\n",
810 sc->jme_phyaddr);
811 }
812 } else {
813 sc->jme_phyaddr = 0;
814 }
815
816 /* Set max allowable DMA size. */
817 pcie_ptr = pci_get_pciecap_ptr(dev);
818 if (pcie_ptr != 0) {
819 uint16_t ctrl;
820
ec7e787b 821 sc->jme_caps |= JME_CAP_PCIE;
76fbb0b9
SZ
822 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
823 if (bootverbose) {
824 device_printf(dev, "Read request size : %d bytes.\n",
825 128 << ((ctrl >> 12) & 0x07));
826 device_printf(dev, "TLP payload size : %d bytes.\n",
827 128 << ((ctrl >> 5) & 0x07));
828 }
829 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
830 case PCIEM_DEVCTL_MAX_READRQ_128:
831 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
832 break;
833 case PCIEM_DEVCTL_MAX_READRQ_256:
834 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
835 break;
836 default:
837 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
838 break;
839 }
840 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
841 } else {
842 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
843 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
844 }
845
846#ifdef notyet
847 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
ec7e787b 848 sc->jme_caps |= JME_CAP_PMCAP;
76fbb0b9
SZ
849#endif
850
851 /*
852 * Create sysctl tree
853 */
854 jme_sysctl_node(sc);
855
856 /* Allocate DMA stuffs */
857 error = jme_dma_alloc(sc);
858 if (error)
859 goto fail;
860
861 ifp->if_softc = sc;
862 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
863 ifp->if_init = jme_init;
864 ifp->if_ioctl = jme_ioctl;
865 ifp->if_start = jme_start;
9de40864
SZ
866#ifdef DEVICE_POLLING
867 ifp->if_poll = jme_poll;
868#endif
76fbb0b9 869 ifp->if_watchdog = jme_watchdog;
31f0d5a2
SZ
870 ifp->if_serialize = jme_serialize;
871 ifp->if_deserialize = jme_deserialize;
872 ifp->if_tryserialize = jme_tryserialize;
873#ifdef INVARIANTS
874 ifp->if_serialize_assert = jme_serialize_assert;
875#endif
cfff3793 876 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
76fbb0b9
SZ
877 ifq_set_ready(&ifp->if_snd);
878
879 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
880 ifp->if_capabilities = IFCAP_HWCSUM |
881 IFCAP_VLAN_MTU |
882 IFCAP_VLAN_HWTAGGING;
7b040092 883 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
d585233c 884 ifp->if_capabilities |= IFCAP_RSS;
76fbb0b9
SZ
885 ifp->if_capenable = ifp->if_capabilities;
886
3d2aeb15
SZ
887 /*
888 * Disable TXCSUM by default to improve bulk data
889 * transmit performance (+20Mbps improvement).
890 */
891 ifp->if_capenable &= ~IFCAP_TXCSUM;
892
893 if (ifp->if_capenable & IFCAP_TXCSUM)
894 ifp->if_hwassist = JME_CSUM_FEATURES;
895
76fbb0b9
SZ
896 /* Set up MII bus. */
897 error = mii_phy_probe(dev, &sc->jme_miibus,
898 jme_mediachange, jme_mediastatus);
899 if (error) {
900 device_printf(dev, "no PHY found!\n");
901 goto fail;
902 }
903
904 /*
905 * Save PHYADDR for FPGA mode PHY.
906 */
ec7e787b 907 if (sc->jme_caps & JME_CAP_FPGA) {
76fbb0b9
SZ
908 struct mii_data *mii = device_get_softc(sc->jme_miibus);
909
910 if (mii->mii_instance != 0) {
911 struct mii_softc *miisc;
912
913 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
914 if (miisc->mii_phy != 0) {
915 sc->jme_phyaddr = miisc->mii_phy;
916 break;
917 }
918 }
919 if (sc->jme_phyaddr != 0) {
920 device_printf(sc->jme_dev,
921 "FPGA PHY is at %d\n", sc->jme_phyaddr);
922 /* vendor magic. */
dbe37f03
SZ
923 jme_miibus_writereg(dev, sc->jme_phyaddr,
924 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
925
ad22907f 926 /* XXX should we clear JME_WA_EXTFIFO */
76fbb0b9
SZ
927 }
928 }
929 }
930
931 ether_ifattach(ifp, eaddr, NULL);
932
933 /* Tell the upper layer(s) we support long frames. */
934 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
935
58880b0d 936 error = jme_intr_setup(dev);
76fbb0b9 937 if (error) {
76fbb0b9
SZ
938 ether_ifdetach(ifp);
939 goto fail;
940 }
941
76fbb0b9
SZ
942 return 0;
943fail:
944 jme_detach(dev);
945 return (error);
946}
947
948static int
949jme_detach(device_t dev)
950{
951 struct jme_softc *sc = device_get_softc(dev);
952
953 if (device_is_attached(dev)) {
954 struct ifnet *ifp = &sc->arpcom.ac_if;
955
31f0d5a2 956 ifnet_serialize_all(ifp);
76fbb0b9 957 jme_stop(sc);
58880b0d 958 jme_intr_teardown(dev);
31f0d5a2 959 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
960
961 ether_ifdetach(ifp);
962 }
963
964 if (sc->jme_sysctl_tree != NULL)
965 sysctl_ctx_free(&sc->jme_sysctl_ctx);
966
967 if (sc->jme_miibus != NULL)
968 device_delete_child(dev, sc->jme_miibus);
969 bus_generic_detach(dev);
970
58880b0d 971 jme_intr_free(dev);
76fbb0b9
SZ
972
973 if (sc->jme_mem_res != NULL) {
974 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
975 sc->jme_mem_res);
976 }
977
0b3414d9 978 jme_dma_free(sc);
76fbb0b9
SZ
979
980 return (0);
981}
982
983static void
984jme_sysctl_node(struct jme_softc *sc)
985{
83b03786 986 int coal_max;
760c056c 987#ifdef JME_RSS_DEBUG
760c056c
SZ
988 int r;
989#endif
83b03786 990
76fbb0b9
SZ
991 sysctl_ctx_init(&sc->jme_sysctl_ctx);
992 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
993 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
994 device_get_nameunit(sc->jme_dev),
995 CTLFLAG_RD, 0, "");
996 if (sc->jme_sysctl_tree == NULL) {
997 device_printf(sc->jme_dev, "can't add sysctl node\n");
998 return;
999 }
1000
1001 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1002 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1003 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1004 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
76fbb0b9
SZ
1005
1006 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1007 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1008 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1009 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
76fbb0b9
SZ
1010
1011 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1012 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1013 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1014 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
76fbb0b9
SZ
1015
1016 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1017 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
2870abc4
SZ
1018 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1019 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
76fbb0b9 1020
83b03786
SZ
1021 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1022 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1023 "rx_desc_count", CTLFLAG_RD,
1024 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
83b03786
SZ
1025 0, "RX desc count");
1026 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1027 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
69325526 1028 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
83b03786 1029 0, "TX desc count");
760c056c
SZ
1030 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1031 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
7b040092
SZ
1032 "rx_ring_count", CTLFLAG_RD,
1033 &sc->jme_cdata.jme_rx_ring_cnt,
760c056c 1034 0, "RX ring count");
760c056c
SZ
1035#ifdef JME_RSS_DEBUG
1036 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1037 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
24dd1705 1038 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
760c056c 1039 0, "RSS debug level");
7b040092
SZ
1040 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1041 char rx_ring_pkt[32];
1042
760c056c 1043 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
7b040092
SZ
1044 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1045 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1046 rx_ring_pkt, CTLFLAG_RW,
1047 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
760c056c
SZ
1048 }
1049#endif
83b03786
SZ
1050
1051 /*
1052 * Set default coalesce valves
1053 */
76fbb0b9 1054 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
76fbb0b9 1055 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
76fbb0b9 1056 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
76fbb0b9 1057 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
83b03786
SZ
1058
1059 /*
1060 * Adjust coalesce valves, in case that the number of TX/RX
1061 * descs are set to small values by users.
1062 *
1063 * NOTE: coal_max will not be zero, since number of descs
1064 * must aligned by JME_NDESC_ALIGN (16 currently)
1065 */
69325526 1066 coal_max = sc->jme_tx_desc_cnt / 6;
83b03786
SZ
1067 if (coal_max < sc->jme_tx_coal_pkt)
1068 sc->jme_tx_coal_pkt = coal_max;
1069
7b040092 1070 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
83b03786
SZ
1071 if (coal_max < sc->jme_rx_coal_pkt)
1072 sc->jme_rx_coal_pkt = coal_max;
76fbb0b9
SZ
1073}
1074
76fbb0b9
SZ
1075static int
1076jme_dma_alloc(struct jme_softc *sc)
1077{
1078 struct jme_txdesc *txd;
1128a202 1079 bus_dmamem_t dmem;
76fbb0b9
SZ
1080 int error, i;
1081
83b03786 1082 sc->jme_cdata.jme_txdesc =
69325526 1083 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
83b03786 1084 M_DEVBUF, M_WAITOK | M_ZERO);
7b040092
SZ
1085 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1086 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1087
1088 rdata->jme_rxdesc =
1089 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
4447c752
SZ
1090 M_DEVBUF, M_WAITOK | M_ZERO);
1091 }
83b03786 1092
76fbb0b9
SZ
1093 /* Create parent ring tag. */
1094 error = bus_dma_tag_create(NULL,/* parent */
a7547dad
SZ
1095 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1096 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ
1097 BUS_SPACE_MAXADDR, /* highaddr */
1098 NULL, NULL, /* filter, filterarg */
1099 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1100 0, /* nsegments */
1101 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1102 0, /* flags */
1103 &sc->jme_cdata.jme_ring_tag);
1104 if (error) {
1105 device_printf(sc->jme_dev,
1106 "could not create parent ring DMA tag.\n");
1107 return error;
1108 }
1109
1110 /*
1111 * Create DMA stuffs for TX ring
1112 */
1128a202
SZ
1113 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1114 JME_TX_RING_ALIGN, 0,
0eb220ec 1115 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1128a202
SZ
1116 JME_TX_RING_SIZE(sc),
1117 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9 1118 if (error) {
1128a202 1119 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
76fbb0b9
SZ
1120 return error;
1121 }
1128a202
SZ
1122 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1123 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1124 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1125 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ
1126
1127 /*
1128a202 1128 * Create DMA stuffs for RX rings
76fbb0b9 1129 */
7b040092 1130 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1131 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752
SZ
1132 if (error)
1133 return error;
76fbb0b9 1134 }
76fbb0b9 1135
76fbb0b9
SZ
1136 /* Create parent buffer tag. */
1137 error = bus_dma_tag_create(NULL,/* parent */
1138 1, 0, /* algnmnt, boundary */
b249905b 1139 sc->jme_lowaddr, /* lowaddr */
76fbb0b9
SZ
1140 BUS_SPACE_MAXADDR, /* highaddr */
1141 NULL, NULL, /* filter, filterarg */
1142 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1143 0, /* nsegments */
1144 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1145 0, /* flags */
1146 &sc->jme_cdata.jme_buffer_tag);
1147 if (error) {
1148 device_printf(sc->jme_dev,
1149 "could not create parent buffer DMA tag.\n");
1150 return error;
1151 }
1152
1153 /*
1154 * Create DMA stuffs for shadow status block
1155 */
1128a202 1156 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
0eb220ec 1157 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1128a202 1158 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
76fbb0b9
SZ
1159 if (error) {
1160 device_printf(sc->jme_dev,
1128a202 1161 "could not create shadow status block.\n");
76fbb0b9
SZ
1162 return error;
1163 }
1128a202
SZ
1164 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1165 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1166 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1167 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
76fbb0b9
SZ
1168
1169 /*
1170 * Create DMA stuffs for TX buffers
1171 */
1172
1173 /* Create tag for Tx buffers. */
1174 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1175 1, 0, /* algnmnt, boundary */
0eb220ec 1176 BUS_SPACE_MAXADDR, /* lowaddr */
76fbb0b9
SZ
1177 BUS_SPACE_MAXADDR, /* highaddr */
1178 NULL, NULL, /* filter, filterarg */
9d424cee 1179 JME_JUMBO_FRAMELEN, /* maxsize */
76fbb0b9 1180 JME_MAXTXSEGS, /* nsegments */
9d424cee
SZ
1181 JME_MAXSEGSIZE, /* maxsegsize */
1182 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
76fbb0b9
SZ
1183 &sc->jme_cdata.jme_tx_tag);
1184 if (error != 0) {
1185 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1186 return error;
1187 }
1188
1189 /* Create DMA maps for Tx buffers. */
69325526 1190 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
76fbb0b9 1191 txd = &sc->jme_cdata.jme_txdesc[i];
9d424cee
SZ
1192 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1193 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1194 &txd->tx_dmamap);
76fbb0b9
SZ
1195 if (error) {
1196 int j;
1197
1198 device_printf(sc->jme_dev,
1199 "could not create %dth Tx dmamap.\n", i);
1200
1201 for (j = 0; j < i; ++j) {
1202 txd = &sc->jme_cdata.jme_txdesc[j];
1203 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1204 txd->tx_dmamap);
1205 }
1206 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1207 sc->jme_cdata.jme_tx_tag = NULL;
1208 return error;
1209 }
1210 }
1211
1212 /*
1213 * Create DMA stuffs for RX buffers
1214 */
7b040092 1215 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
dea2452a 1216 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
4447c752 1217 if (error)
76fbb0b9 1218 return error;
76fbb0b9
SZ
1219 }
1220 return 0;
1221}
1222
1223static void
0b3414d9 1224jme_dma_free(struct jme_softc *sc)
76fbb0b9
SZ
1225{
1226 struct jme_txdesc *txd;
1227 struct jme_rxdesc *rxd;
4447c752
SZ
1228 struct jme_rxdata *rdata;
1229 int i, r;
76fbb0b9
SZ
1230
1231 /* Tx ring */
1232 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1233 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1234 sc->jme_cdata.jme_tx_ring_map);
1235 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
560616bf 1236 sc->jme_cdata.jme_tx_ring,
76fbb0b9
SZ
1237 sc->jme_cdata.jme_tx_ring_map);
1238 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1239 sc->jme_cdata.jme_tx_ring_tag = NULL;
1240 }
1241
1242 /* Rx ring */
7b040092 1243 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1244 rdata = &sc->jme_cdata.jme_rx_data[r];
1245 if (rdata->jme_rx_ring_tag != NULL) {
1246 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1247 rdata->jme_rx_ring_map);
1248 bus_dmamem_free(rdata->jme_rx_ring_tag,
1249 rdata->jme_rx_ring,
1250 rdata->jme_rx_ring_map);
1251 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1252 rdata->jme_rx_ring_tag = NULL;
1253 }
76fbb0b9
SZ
1254 }
1255
1256 /* Tx buffers */
1257 if (sc->jme_cdata.jme_tx_tag != NULL) {
69325526 1258 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
76fbb0b9
SZ
1259 txd = &sc->jme_cdata.jme_txdesc[i];
1260 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1261 txd->tx_dmamap);
1262 }
1263 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1264 sc->jme_cdata.jme_tx_tag = NULL;
1265 }
1266
1267 /* Rx buffers */
7b040092 1268 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1269 rdata = &sc->jme_cdata.jme_rx_data[r];
1270 if (rdata->jme_rx_tag != NULL) {
7b040092 1271 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
1272 rxd = &rdata->jme_rxdesc[i];
1273 bus_dmamap_destroy(rdata->jme_rx_tag,
1274 rxd->rx_dmamap);
1275 }
1276 bus_dmamap_destroy(rdata->jme_rx_tag,
1277 rdata->jme_rx_sparemap);
1278 bus_dma_tag_destroy(rdata->jme_rx_tag);
1279 rdata->jme_rx_tag = NULL;
76fbb0b9 1280 }
76fbb0b9
SZ
1281 }
1282
1283 /* Shadow status block. */
1284 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1285 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1286 sc->jme_cdata.jme_ssb_map);
1287 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
560616bf 1288 sc->jme_cdata.jme_ssb_block,
76fbb0b9
SZ
1289 sc->jme_cdata.jme_ssb_map);
1290 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1291 sc->jme_cdata.jme_ssb_tag = NULL;
1292 }
1293
1294 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1295 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1296 sc->jme_cdata.jme_buffer_tag = NULL;
1297 }
1298 if (sc->jme_cdata.jme_ring_tag != NULL) {
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1300 sc->jme_cdata.jme_ring_tag = NULL;
1301 }
83b03786 1302
0b3414d9
SZ
1303 if (sc->jme_cdata.jme_txdesc != NULL) {
1304 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1305 sc->jme_cdata.jme_txdesc = NULL;
1306 }
7b040092 1307 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
0b3414d9
SZ
1308 rdata = &sc->jme_cdata.jme_rx_data[r];
1309 if (rdata->jme_rxdesc != NULL) {
1310 kfree(rdata->jme_rxdesc, M_DEVBUF);
1311 rdata->jme_rxdesc = NULL;
83b03786
SZ
1312 }
1313 }
76fbb0b9
SZ
1314}
1315
1316/*
1317 * Make sure the interface is stopped at reboot time.
1318 */
1319static int
1320jme_shutdown(device_t dev)
1321{
1322 return jme_suspend(dev);
1323}
1324
1325#ifdef notyet
1326/*
1327 * Unlike other ethernet controllers, JMC250 requires
1328 * explicit resetting link speed to 10/100Mbps as gigabit
1329 * link will cunsume more power than 375mA.
1330 * Note, we reset the link speed to 10/100Mbps with
1331 * auto-negotiation but we don't know whether that operation
1332 * would succeed or not as we have no control after powering
1333 * off. If the renegotiation fail WOL may not work. Running
1334 * at 1Gbps draws more power than 375mA at 3.3V which is
1335 * specified in PCI specification and that would result in
1336 * complete shutdowning power to ethernet controller.
1337 *
1338 * TODO
1339 * Save current negotiated media speed/duplex/flow-control
1340 * to softc and restore the same link again after resuming.
1341 * PHY handling such as power down/resetting to 100Mbps
1342 * may be better handled in suspend method in phy driver.
1343 */
1344static void
1345jme_setlinkspeed(struct jme_softc *sc)
1346{
1347 struct mii_data *mii;
1348 int aneg, i;
1349
1350 JME_LOCK_ASSERT(sc);
1351
1352 mii = device_get_softc(sc->jme_miibus);
1353 mii_pollstat(mii);
1354 aneg = 0;
1355 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1356 switch IFM_SUBTYPE(mii->mii_media_active) {
1357 case IFM_10_T:
1358 case IFM_100_TX:
1359 return;
1360 case IFM_1000_T:
1361 aneg++;
1362 default:
1363 break;
1364 }
1365 }
1366 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1367 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1368 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1369 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1370 BMCR_AUTOEN | BMCR_STARTNEG);
1371 DELAY(1000);
1372 if (aneg != 0) {
1373 /* Poll link state until jme(4) get a 10/100 link. */
1374 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1375 mii_pollstat(mii);
1376 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1377 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1378 case IFM_10_T:
1379 case IFM_100_TX:
1380 jme_mac_config(sc);
1381 return;
1382 default:
1383 break;
1384 }
1385 }
1386 JME_UNLOCK(sc);
1387 pause("jmelnk", hz);
1388 JME_LOCK(sc);
1389 }
1390 if (i == MII_ANEGTICKS_GIGE)
1391 device_printf(sc->jme_dev, "establishing link failed, "
1392 "WOL may not work!");
1393 }
1394 /*
1395 * No link, force MAC to have 100Mbps, full-duplex link.
1396 * This is the last resort and may/may not work.
1397 */
1398 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1399 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1400 jme_mac_config(sc);
1401}
1402
1403static void
1404jme_setwol(struct jme_softc *sc)
1405{
1406 struct ifnet *ifp = &sc->arpcom.ac_if;
1407 uint32_t gpr, pmcs;
1408 uint16_t pmstat;
1409 int pmc;
1410
1411 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1412 /* No PME capability, PHY power down. */
1413 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1414 MII_BMCR, BMCR_PDOWN);
1415 return;
1416 }
1417
1418 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1419 pmcs = CSR_READ_4(sc, JME_PMCS);
1420 pmcs &= ~PMCS_WOL_ENB_MASK;
1421 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1422 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1423 /* Enable PME message. */
1424 gpr |= GPREG0_PME_ENB;
1425 /* For gigabit controllers, reset link speed to 10/100. */
ec7e787b 1426 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
76fbb0b9
SZ
1427 jme_setlinkspeed(sc);
1428 }
1429
1430 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1431 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1432
1433 /* Request PME. */
1434 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1435 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1436 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1437 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1438 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1439 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1440 /* No WOL, PHY power down. */
1441 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1442 MII_BMCR, BMCR_PDOWN);
1443 }
1444}
1445#endif
1446
1447static int
1448jme_suspend(device_t dev)
1449{
1450 struct jme_softc *sc = device_get_softc(dev);
1451 struct ifnet *ifp = &sc->arpcom.ac_if;
1452
31f0d5a2 1453 ifnet_serialize_all(ifp);
76fbb0b9
SZ
1454 jme_stop(sc);
1455#ifdef notyet
1456 jme_setwol(sc);
1457#endif
31f0d5a2 1458 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
1459
1460 return (0);
1461}
1462
1463static int
1464jme_resume(device_t dev)
1465{
1466 struct jme_softc *sc = device_get_softc(dev);
1467 struct ifnet *ifp = &sc->arpcom.ac_if;
1468#ifdef notyet
1469 int pmc;
1470#endif
1471
31f0d5a2 1472 ifnet_serialize_all(ifp);
76fbb0b9
SZ
1473
1474#ifdef notyet
1475 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1476 uint16_t pmstat;
1477
1478 pmstat = pci_read_config(sc->jme_dev,
1479 pmc + PCIR_POWER_STATUS, 2);
1480 /* Disable PME clear PME status. */
1481 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1482 pci_write_config(sc->jme_dev,
1483 pmc + PCIR_POWER_STATUS, pmstat, 2);
1484 }
1485#endif
1486
1487 if (ifp->if_flags & IFF_UP)
1488 jme_init(sc);
1489
31f0d5a2 1490 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
1491
1492 return (0);
1493}
1494
1495static int
1496jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1497{
1498 struct jme_txdesc *txd;
1499 struct jme_desc *desc;
1500 struct mbuf *m;
76fbb0b9 1501 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
b0ba1747 1502 int maxsegs, nsegs;
9b3ee148 1503 int error, i, prod, symbol_desc;
7228f061 1504 uint32_t cflags, flag64;
76fbb0b9
SZ
1505
1506 M_ASSERTPKTHDR((*m_head));
1507
1508 prod = sc->jme_cdata.jme_tx_prod;
1509 txd = &sc->jme_cdata.jme_txdesc[prod];
1510
9b3ee148
SZ
1511 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1512 symbol_desc = 1;
1513 else
1514 symbol_desc = 0;
1515
69325526 1516 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
9b3ee148 1517 (JME_TXD_RSVD + symbol_desc);
76fbb0b9
SZ
1518 if (maxsegs > JME_MAXTXSEGS)
1519 maxsegs = JME_MAXTXSEGS;
9b3ee148 1520 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
76fbb0b9
SZ
1521 ("not enough segments %d\n", maxsegs));
1522
b0ba1747
SZ
1523 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1524 txd->tx_dmamap, m_head,
1525 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1526 if (error)
ecc6de9e 1527 goto fail;
76fbb0b9 1528
4458ee95
SZ
1529 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1530 BUS_DMASYNC_PREWRITE);
1531
76fbb0b9
SZ
1532 m = *m_head;
1533 cflags = 0;
1534
1535 /* Configure checksum offload. */
1536 if (m->m_pkthdr.csum_flags & CSUM_IP)
1537 cflags |= JME_TD_IPCSUM;
1538 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1539 cflags |= JME_TD_TCPCSUM;
1540 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1541 cflags |= JME_TD_UDPCSUM;
1542
1543 /* Configure VLAN. */
1544 if (m->m_flags & M_VLANTAG) {
1545 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1546 cflags |= JME_TD_VLAN_TAG;
1547 }
1548
560616bf 1549 desc = &sc->jme_cdata.jme_tx_ring[prod];
76fbb0b9 1550 desc->flags = htole32(cflags);
76fbb0b9 1551 desc->addr_hi = htole32(m->m_pkthdr.len);
7228f061
SZ
1552 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1553 /*
1554 * Use 64bits TX desc chain format.
1555 *
1556 * The first TX desc of the chain, which is setup here,
1557 * is just a symbol TX desc carrying no payload.
1558 */
1559 flag64 = JME_TD_64BIT;
1560 desc->buflen = 0;
1561 desc->addr_lo = 0;
1562
1563 /* No effective TX desc is consumed */
1564 i = 0;
1565 } else {
1566 /*
1567 * Use 32bits TX desc chain format.
1568 *
1569 * The first TX desc of the chain, which is setup here,
1570 * is an effective TX desc carrying the first segment of
1571 * the mbuf chain.
1572 */
1573 flag64 = 0;
1574 desc->buflen = htole32(txsegs[0].ds_len);
1575 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1576
1577 /* One effective TX desc is consumed */
1578 i = 1;
1579 }
76fbb0b9 1580 sc->jme_cdata.jme_tx_cnt++;
9de40864
SZ
1581 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1582 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
69325526 1583 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
7228f061
SZ
1584
1585 txd->tx_ndesc = 1 - i;
b0ba1747 1586 for (; i < nsegs; i++) {
560616bf 1587 desc = &sc->jme_cdata.jme_tx_ring[prod];
7228f061 1588 desc->flags = htole32(JME_TD_OWN | flag64);
76fbb0b9
SZ
1589 desc->buflen = htole32(txsegs[i].ds_len);
1590 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1591 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1592
1593 sc->jme_cdata.jme_tx_cnt++;
1594 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
69325526
SZ
1595 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1596 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
76fbb0b9
SZ
1597 }
1598
1599 /* Update producer index. */
1600 sc->jme_cdata.jme_tx_prod = prod;
1601 /*
1602 * Finally request interrupt and give the first descriptor
1603 * owenership to hardware.
1604 */
1605 desc = txd->tx_desc;
1606 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1607
1608 txd->tx_m = m;
b0ba1747 1609 txd->tx_ndesc += nsegs;
76fbb0b9 1610
ecc6de9e
SZ
1611 return 0;
1612fail:
1613 m_freem(*m_head);
1614 *m_head = NULL;
1615 return error;
76fbb0b9
SZ
1616}
1617
1618static void
1619jme_start(struct ifnet *ifp)
1620{
1621 struct jme_softc *sc = ifp->if_softc;
1622 struct mbuf *m_head;
1623 int enq = 0;
1624
31f0d5a2 1625 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1626
1627 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1628 ifq_purge(&ifp->if_snd);
1629 return;
1630 }
1631
1632 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1633 return;
1634
83b03786 1635 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
76fbb0b9
SZ
1636 jme_txeof(sc);
1637
1638 while (!ifq_is_empty(&ifp->if_snd)) {
1639 /*
1640 * Check number of available TX descs, always
1641 * leave JME_TXD_RSVD free TX descs.
1642 */
1643 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
69325526 1644 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
76fbb0b9
SZ
1645 ifp->if_flags |= IFF_OACTIVE;
1646 break;
1647 }
1648
1649 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1650 if (m_head == NULL)
1651 break;
1652
1653 /*
1654 * Pack the data into the transmit ring. If we
1655 * don't have room, set the OACTIVE flag and wait
1656 * for the NIC to drain the ring.
1657 */
1658 if (jme_encap(sc, &m_head)) {
ecc6de9e
SZ
1659 KKASSERT(m_head == NULL);
1660 ifp->if_oerrors++;
76fbb0b9
SZ
1661 ifp->if_flags |= IFF_OACTIVE;
1662 break;
1663 }
1664 enq++;
1665
1666 /*
1667 * If there's a BPF listener, bounce a copy of this frame
1668 * to him.
1669 */
1670 ETHER_BPF_MTAP(ifp, m_head);
1671 }
1672
1673 if (enq > 0) {
1674 /*
1675 * Reading TXCSR takes very long time under heavy load
1676 * so cache TXCSR value and writes the ORed value with
1677 * the kick command to the TXCSR. This saves one register
1678 * access cycle.
1679 */
1680 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1681 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1682 /* Set a timeout in case the chip goes out to lunch. */
1683 ifp->if_timer = JME_TX_TIMEOUT;
1684 }
1685}
1686
1687static void
1688jme_watchdog(struct ifnet *ifp)
1689{
1690 struct jme_softc *sc = ifp->if_softc;
1691
31f0d5a2 1692 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
1693
1694 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1695 if_printf(ifp, "watchdog timeout (missed link)\n");
1696 ifp->if_oerrors++;
1697 jme_init(sc);
1698 return;
1699 }
1700
1701 jme_txeof(sc);
1702 if (sc->jme_cdata.jme_tx_cnt == 0) {
1703 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1704 "-- recovering\n");
1705 if (!ifq_is_empty(&ifp->if_snd))
1706 if_devstart(ifp);
1707 return;
1708 }
1709
1710 if_printf(ifp, "watchdog timeout\n");
1711 ifp->if_oerrors++;
1712 jme_init(sc);
1713 if (!ifq_is_empty(&ifp->if_snd))
1714 if_devstart(ifp);
1715}
1716
1717static int
1718jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1719{
1720 struct jme_softc *sc = ifp->if_softc;
1721 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1722 struct ifreq *ifr = (struct ifreq *)data;
1723 int error = 0, mask;
1724
31f0d5a2 1725 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
1726
1727 switch (cmd) {
1728 case SIOCSIFMTU:
1729 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
3a5f3f36 1730 (!(sc->jme_caps & JME_CAP_JUMBO) &&
76fbb0b9
SZ
1731 ifr->ifr_mtu > JME_MAX_MTU)) {
1732 error = EINVAL;
1733 break;
1734 }
1735
1736 if (ifp->if_mtu != ifr->ifr_mtu) {
1737 /*
1738 * No special configuration is required when interface
1739 * MTU is changed but availability of Tx checksum
1740 * offload should be chcked against new MTU size as
1741 * FIFO size is just 2K.
1742 */
1743 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1744 ifp->if_capenable &= ~IFCAP_TXCSUM;
1745 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1746 }
1747 ifp->if_mtu = ifr->ifr_mtu;
1748 if (ifp->if_flags & IFF_RUNNING)
1749 jme_init(sc);
1750 }
1751 break;
1752
1753 case SIOCSIFFLAGS:
1754 if (ifp->if_flags & IFF_UP) {
1755 if (ifp->if_flags & IFF_RUNNING) {
1756 if ((ifp->if_flags ^ sc->jme_if_flags) &
1757 (IFF_PROMISC | IFF_ALLMULTI))
1758 jme_set_filter(sc);
1759 } else {
1760 jme_init(sc);
1761 }
1762 } else {
1763 if (ifp->if_flags & IFF_RUNNING)
1764 jme_stop(sc);
1765 }
1766 sc->jme_if_flags = ifp->if_flags;
1767 break;
1768
1769 case SIOCADDMULTI:
1770 case SIOCDELMULTI:
1771 if (ifp->if_flags & IFF_RUNNING)
1772 jme_set_filter(sc);
1773 break;
1774
1775 case SIOCSIFMEDIA:
1776 case SIOCGIFMEDIA:
1777 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1778 break;
1779
1780 case SIOCSIFCAP:
1781 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1782
1783 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
e4616e94
SZ
1784 ifp->if_capenable ^= IFCAP_TXCSUM;
1785 if (IFCAP_TXCSUM & ifp->if_capenable)
1786 ifp->if_hwassist |= JME_CSUM_FEATURES;
1787 else
1788 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
76fbb0b9 1789 }
e4616e94 1790 if (mask & IFCAP_RXCSUM) {
76fbb0b9
SZ
1791 uint32_t reg;
1792
1793 ifp->if_capenable ^= IFCAP_RXCSUM;
1794 reg = CSR_READ_4(sc, JME_RXMAC);
1795 reg &= ~RXMAC_CSUM_ENB;
1796 if (ifp->if_capenable & IFCAP_RXCSUM)
1797 reg |= RXMAC_CSUM_ENB;
1798 CSR_WRITE_4(sc, JME_RXMAC, reg);
1799 }
1800
e4616e94 1801 if (mask & IFCAP_VLAN_HWTAGGING) {
76fbb0b9
SZ
1802 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1803 jme_set_vlan(sc);
1804 }
e4616e94 1805
9f20b7b3 1806 if (mask & IFCAP_RSS)
d585233c 1807 ifp->if_capenable ^= IFCAP_RSS;
76fbb0b9
SZ
1808 break;
1809
1810 default:
1811 error = ether_ioctl(ifp, cmd, data);
1812 break;
1813 }
1814 return (error);
1815}
1816
1817static void
1818jme_mac_config(struct jme_softc *sc)
1819{
1820 struct mii_data *mii;
3b3da110
SZ
1821 uint32_t ghc, rxmac, txmac, txpause, gp1;
1822 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
76fbb0b9
SZ
1823
1824 mii = device_get_softc(sc->jme_miibus);
1825
1826 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1827 DELAY(10);
1828 CSR_WRITE_4(sc, JME_GHC, 0);
1829 ghc = 0;
1830 rxmac = CSR_READ_4(sc, JME_RXMAC);
1831 rxmac &= ~RXMAC_FC_ENB;
1832 txmac = CSR_READ_4(sc, JME_TXMAC);
1833 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1834 txpause = CSR_READ_4(sc, JME_TXPFC);
1835 txpause &= ~TXPFC_PAUSE_ENB;
1836 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1837 ghc |= GHC_FULL_DUPLEX;
1838 rxmac &= ~RXMAC_COLL_DET_ENB;
1839 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1840 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1841 TXMAC_FRAME_BURST);
1842#ifdef notyet
1843 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1844 txpause |= TXPFC_PAUSE_ENB;
1845 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1846 rxmac |= RXMAC_FC_ENB;
1847#endif
1848 /* Disable retry transmit timer/retry limit. */
1849 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1850 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1851 } else {
1852 rxmac |= RXMAC_COLL_DET_ENB;
1853 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1854 /* Enable retry transmit timer/retry limit. */
1855 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1856 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1857 }
1858
3b3da110
SZ
1859 /*
1860 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1861 */
1862 gp1 = CSR_READ_4(sc, JME_GPREG1);
1863 gp1 &= ~GPREG1_WA_HDX;
1864
1865 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1866 hdx = 1;
1867
76fbb0b9
SZ
1868 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1869 case IFM_10_T:
b249905b 1870 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
3b3da110
SZ
1871 if (hdx)
1872 gp1 |= GPREG1_WA_HDX;
76fbb0b9 1873 break;
dbe37f03 1874
76fbb0b9 1875 case IFM_100_TX:
b249905b 1876 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
3b3da110
SZ
1877 if (hdx)
1878 gp1 |= GPREG1_WA_HDX;
dbe37f03
SZ
1879
1880 /*
1881 * Use extended FIFO depth to workaround CRC errors
1882 * emitted by chips before JMC250B
1883 */
1884 phyconf = JMPHY_CONF_EXTFIFO;
76fbb0b9 1885 break;
dbe37f03 1886
76fbb0b9 1887 case IFM_1000_T:
ec7e787b 1888 if (sc->jme_caps & JME_CAP_FASTETH)
76fbb0b9 1889 break;
dbe37f03 1890
b249905b 1891 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
3b3da110 1892 if (hdx)
76fbb0b9
SZ
1893 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1894 break;
dbe37f03 1895
76fbb0b9
SZ
1896 default:
1897 break;
1898 }
1899 CSR_WRITE_4(sc, JME_GHC, ghc);
1900 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1901 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1902 CSR_WRITE_4(sc, JME_TXPFC, txpause);
dbe37f03 1903
ad22907f 1904 if (sc->jme_workaround & JME_WA_EXTFIFO) {
dbe37f03
SZ
1905 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1906 JMPHY_CONF, phyconf);
1907 }
3b3da110
SZ
1908 if (sc->jme_workaround & JME_WA_HDX)
1909 CSR_WRITE_4(sc, JME_GPREG1, gp1);
76fbb0b9
SZ
1910}
1911
1912static void
1913jme_intr(void *xsc)
1914{
1915 struct jme_softc *sc = xsc;
1916 struct ifnet *ifp = &sc->arpcom.ac_if;
1917 uint32_t status;
4447c752 1918 int r;
76fbb0b9 1919
31f0d5a2 1920 ASSERT_SERIALIZED(&sc->jme_serialize);
76fbb0b9
SZ
1921
1922 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1923 if (status == 0 || status == 0xFFFFFFFF)
1924 return;
1925
1926 /* Disable interrupts. */
1927 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1928
1929 status = CSR_READ_4(sc, JME_INTR_STATUS);
1930 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1931 goto back;
1932
1933 /* Reset PCC counter/timer and Ack interrupts. */
1934 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
4447c752 1935
76fbb0b9
SZ
1936 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1937 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
4447c752 1938
7b040092 1939 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
1940 if (status & jme_rx_status[r].jme_coal) {
1941 status |= jme_rx_status[r].jme_coal |
1942 jme_rx_status[r].jme_comp;
1943 }
1944 }
1945
76fbb0b9
SZ
1946 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1947
1948 if (ifp->if_flags & IFF_RUNNING) {
1949 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
4447c752 1950 jme_rx_intr(sc, status);
76fbb0b9
SZ
1951
1952 if (status & INTR_RXQ_DESC_EMPTY) {
1953 /*
1954 * Notify hardware availability of new Rx buffers.
1955 * Reading RXCSR takes very long time under heavy
1956 * load so cache RXCSR value and writes the ORed
1957 * value with the kick command to the RXCSR. This
1958 * saves one register access cycle.
1959 */
1960 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1961 RXCSR_RX_ENB | RXCSR_RXQ_START);
1962 }
1963
1964 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
31f0d5a2 1965 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1966 jme_txeof(sc);
1967 if (!ifq_is_empty(&ifp->if_snd))
1968 if_devstart(ifp);
31f0d5a2 1969 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
76fbb0b9
SZ
1970 }
1971 }
1972back:
1973 /* Reenable interrupts. */
1974 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1975}
1976
1977static void
1978jme_txeof(struct jme_softc *sc)
1979{
1980 struct ifnet *ifp = &sc->arpcom.ac_if;
1981 struct jme_txdesc *txd;
1982 uint32_t status;
1983 int cons, nsegs;
1984
1985 cons = sc->jme_cdata.jme_tx_cons;
1986 if (cons == sc->jme_cdata.jme_tx_prod)
1987 return;
1988
76fbb0b9
SZ
1989 /*
1990 * Go through our Tx list and free mbufs for those
1991 * frames which have been transmitted.
1992 */
1993 while (cons != sc->jme_cdata.jme_tx_prod) {
1994 txd = &sc->jme_cdata.jme_txdesc[cons];
1995 KASSERT(txd->tx_m != NULL,
1996 ("%s: freeing NULL mbuf!\n", __func__));
1997
1998 status = le32toh(txd->tx_desc->flags);
1999 if ((status & JME_TD_OWN) == JME_TD_OWN)
2000 break;
2001
2002 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2003 ifp->if_oerrors++;
2004 } else {
2005 ifp->if_opackets++;
2006 if (status & JME_TD_COLLISION) {
2007 ifp->if_collisions +=
2008 le32toh(txd->tx_desc->buflen) &
2009 JME_TD_BUF_LEN_MASK;
2010 }
2011 }
2012
2013 /*
2014 * Only the first descriptor of multi-descriptor
2015 * transmission is updated so driver have to skip entire
2016 * chained buffers for the transmiited frame. In other
2017 * words, JME_TD_OWN bit is valid only at the first
2018 * descriptor of a multi-descriptor transmission.
2019 */
2020 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
560616bf 2021 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
69325526 2022 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
76fbb0b9
SZ
2023 }
2024
2025 /* Reclaim transferred mbufs. */
2026 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2027 m_freem(txd->tx_m);
2028 txd->tx_m = NULL;
2029 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2030 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2031 ("%s: Active Tx desc counter was garbled\n", __func__));
2032 txd->tx_ndesc = 0;
2033 }
2034 sc->jme_cdata.jme_tx_cons = cons;
2035
2036 if (sc->jme_cdata.jme_tx_cnt == 0)
2037 ifp->if_timer = 0;
2038
2039 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
69325526 2040 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
76fbb0b9 2041 ifp->if_flags &= ~IFF_OACTIVE;
76fbb0b9
SZ
2042}
2043
2044static __inline void
dea2452a 2045jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
76fbb0b9
SZ
2046{
2047 int i;
2048
2049 for (i = 0; i < count; ++i) {
4447c752 2050 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
76fbb0b9
SZ
2051
2052 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2053 desc->buflen = htole32(MCLBYTES);
7b040092 2054 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
76fbb0b9
SZ
2055 }
2056}
2057
a6acc6e2
SZ
2058static __inline struct pktinfo *
2059jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2060{
2061 if (flags & JME_RD_IPV4)
2062 pi->pi_netisr = NETISR_IP;
2063 else if (flags & JME_RD_IPV6)
2064 pi->pi_netisr = NETISR_IPV6;
2065 else
2066 return NULL;
2067
2068 pi->pi_flags = 0;
2069 pi->pi_l3proto = IPPROTO_UNKNOWN;
2070
2071 if (flags & JME_RD_MORE_FRAG)
2072 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2073 else if (flags & JME_RD_TCP)
2074 pi->pi_l3proto = IPPROTO_TCP;
2075 else if (flags & JME_RD_UDP)
2076 pi->pi_l3proto = IPPROTO_UDP;
7345eb80
SZ
2077 else
2078 pi = NULL;
a6acc6e2
SZ
2079 return pi;
2080}
2081
76fbb0b9
SZ
2082/* Receive a frame. */
2083static void
dea2452a 2084jme_rxpkt(struct jme_rxdata *rdata)
76fbb0b9 2085{
dea2452a 2086 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
76fbb0b9
SZ
2087 struct jme_desc *desc;
2088 struct jme_rxdesc *rxd;
2089 struct mbuf *mp, *m;
a6acc6e2 2090 uint32_t flags, status, hash, hashinfo;
76fbb0b9
SZ
2091 int cons, count, nsegs;
2092
4447c752
SZ
2093 cons = rdata->jme_rx_cons;
2094 desc = &rdata->jme_rx_ring[cons];
76fbb0b9
SZ
2095 flags = le32toh(desc->flags);
2096 status = le32toh(desc->buflen);
a6acc6e2
SZ
2097 hash = le32toh(desc->addr_hi);
2098 hashinfo = le32toh(desc->addr_lo);
76fbb0b9
SZ
2099 nsegs = JME_RX_NSEGS(status);
2100
7b040092 2101 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
a6acc6e2 2102 "hash 0x%08x, hash info 0x%08x\n",
7b040092 2103 rdata->jme_rx_idx, flags, hash, hashinfo);
760c056c 2104
76fbb0b9
SZ
2105 if (status & JME_RX_ERR_STAT) {
2106 ifp->if_ierrors++;
dea2452a 2107 jme_discard_rxbufs(rdata, cons, nsegs);
76fbb0b9 2108#ifdef JME_SHOW_ERRORS
7b040092 2109 if_printf(ifp, "%s : receive error = 0x%b\n",
76fbb0b9
SZ
2110 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2111#endif
4447c752 2112 rdata->jme_rx_cons += nsegs;
7b040092 2113 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2114 return;
2115 }
2116
4447c752 2117 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
76fbb0b9 2118 for (count = 0; count < nsegs; count++,
7b040092 2119 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
4447c752 2120 rxd = &rdata->jme_rxdesc[cons];
76fbb0b9
SZ
2121 mp = rxd->rx_m;
2122
2123 /* Add a new receive buffer to the ring. */
dea2452a 2124 if (jme_newbuf(rdata, rxd, 0) != 0) {
76fbb0b9
SZ
2125 ifp->if_iqdrops++;
2126 /* Reuse buffer. */
dea2452a 2127 jme_discard_rxbufs(rdata, cons, nsegs - count);
4447c752
SZ
2128 if (rdata->jme_rxhead != NULL) {
2129 m_freem(rdata->jme_rxhead);
dea2452a 2130 JME_RXCHAIN_RESET(rdata);
76fbb0b9
SZ
2131 }
2132 break;
2133 }
2134
2135 /*
2136 * Assume we've received a full sized frame.
2137 * Actual size is fixed when we encounter the end of
2138 * multi-segmented frame.
2139 */
2140 mp->m_len = MCLBYTES;
2141
2142 /* Chain received mbufs. */
4447c752
SZ
2143 if (rdata->jme_rxhead == NULL) {
2144 rdata->jme_rxhead = mp;
2145 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2146 } else {
2147 /*
2148 * Receive processor can receive a maximum frame
2149 * size of 65535 bytes.
2150 */
4447c752
SZ
2151 rdata->jme_rxtail->m_next = mp;
2152 rdata->jme_rxtail = mp;
76fbb0b9
SZ
2153 }
2154
2155 if (count == nsegs - 1) {
a6acc6e2
SZ
2156 struct pktinfo pi0, *pi;
2157
76fbb0b9 2158 /* Last desc. for this frame. */
4447c752 2159 m = rdata->jme_rxhead;
4447c752 2160 m->m_pkthdr.len = rdata->jme_rxlen;
76fbb0b9
SZ
2161 if (nsegs > 1) {
2162 /* Set first mbuf size. */
2163 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2164 /* Set last mbuf size. */
4447c752 2165 mp->m_len = rdata->jme_rxlen -
76fbb0b9
SZ
2166 ((MCLBYTES - JME_RX_PAD_BYTES) +
2167 (MCLBYTES * (nsegs - 2)));
2168 } else {
4447c752 2169 m->m_len = rdata->jme_rxlen;
76fbb0b9
SZ
2170 }
2171 m->m_pkthdr.rcvif = ifp;
2172
2173 /*
2174 * Account for 10bytes auto padding which is used
2175 * to align IP header on 32bit boundary. Also note,
2176 * CRC bytes is automatically removed by the
2177 * hardware.
2178 */
2179 m->m_data += JME_RX_PAD_BYTES;
2180
2181 /* Set checksum information. */
2182 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2183 (flags & JME_RD_IPV4)) {
2184 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2185 if (flags & JME_RD_IPCSUM)
2186 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2187 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2188 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2189 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2190 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2191 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2192 m->m_pkthdr.csum_flags |=
2193 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2194 m->m_pkthdr.csum_data = 0xffff;
2195 }
2196 }
2197
2198 /* Check for VLAN tagged packets. */
2199 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2200 (flags & JME_RD_VLAN_TAG)) {
2201 m->m_pkthdr.ether_vlantag =
2202 flags & JME_RD_VLAN_MASK;
2203 m->m_flags |= M_VLANTAG;
2204 }
2205
2206 ifp->if_ipackets++;
a6acc6e2
SZ
2207
2208 if (ifp->if_capenable & IFCAP_RSS)
2209 pi = jme_pktinfo(&pi0, flags);
2210 else
2211 pi = NULL;
2212
2213 if (pi != NULL &&
2214 (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2215 m->m_flags |= M_HASH;
2216 m->m_pkthdr.hash = toeplitz_hash(hash);
2217 }
2218
2219#ifdef JME_RSS_DEBUG
2220 if (pi != NULL) {
7b040092 2221 JME_RSS_DPRINTF(rdata->jme_sc, 10,
a6acc6e2
SZ
2222 "isr %d flags %08x, l3 %d %s\n",
2223 pi->pi_netisr, pi->pi_flags,
2224 pi->pi_l3proto,
2225 (m->m_flags & M_HASH) ? "hash" : "");
2226 }
2227#endif
2228
76fbb0b9 2229 /* Pass it on. */
eda7db08 2230 ether_input_pkt(ifp, m, pi);
76fbb0b9
SZ
2231
2232 /* Reset mbuf chains. */
dea2452a 2233 JME_RXCHAIN_RESET(rdata);
760c056c 2234#ifdef JME_RSS_DEBUG
7b040092 2235 rdata->jme_rx_pkt++;
760c056c 2236#endif
76fbb0b9
SZ
2237 }
2238 }
2239
4447c752 2240 rdata->jme_rx_cons += nsegs;
7b040092 2241 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
76fbb0b9
SZ
2242}
2243
eda7db08 2244static void
dea2452a 2245jme_rxeof(struct jme_rxdata *rdata, int count)
76fbb0b9
SZ
2246{
2247 struct jme_desc *desc;
eda7db08 2248 int nsegs, pktlen;
76fbb0b9 2249
76fbb0b9 2250 for (;;) {
3fa06afc
SZ
2251#ifdef DEVICE_POLLING
2252 if (count >= 0 && count-- == 0)
2253 break;
2254#endif
4447c752 2255 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
76fbb0b9
SZ
2256 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2257 break;
2258 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2259 break;
2260
2261 /*
2262 * Check number of segments against received bytes.
2263 * Non-matching value would indicate that hardware
2264 * is still trying to update Rx descriptors. I'm not
2265 * sure whether this check is needed.
2266 */
2267 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2268 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2269 if (nsegs != howmany(pktlen, MCLBYTES)) {
dea2452a
SZ
2270 if_printf(&rdata->jme_sc->arpcom.ac_if,
2271 "RX fragment count(%d) and "
2272 "packet size(%d) mismach\n", nsegs, pktlen);
76fbb0b9
SZ
2273 break;
2274 }
2275
2276 /* Received a frame. */
dea2452a 2277 jme_rxpkt(rdata);
76fbb0b9 2278 }
76fbb0b9
SZ
2279}
2280
2281static void
2282jme_tick(void *xsc)
2283{
2284 struct jme_softc *sc = xsc;
2285 struct ifnet *ifp = &sc->arpcom.ac_if;
2286 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2287
31f0d5a2 2288 ifnet_serialize_all(ifp);
76fbb0b9
SZ
2289
2290 mii_tick(mii);
2291 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2292
31f0d5a2 2293 ifnet_deserialize_all(ifp);
76fbb0b9
SZ
2294}
2295
2296static void
2297jme_reset(struct jme_softc *sc)
2298{
409fe405
SZ
2299 uint32_t val;
2300
2301 /* Make sure that TX and RX are stopped */
76fbb0b9 2302 jme_stop_tx(sc);
409fe405
SZ
2303 jme_stop_rx(sc);
2304
2305 /* Start reset */
76fbb0b9 2306 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
409fe405
SZ
2307 DELAY(20);
2308
2309 /*
2310 * Hold reset bit before stop reset
2311 */
2312
2313 /* Disable TXMAC and TXOFL clock sources */
2314 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2315 /* Disable RXMAC clock source */
2316 val = CSR_READ_4(sc, JME_GPREG1);
2317 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2318 /* Flush */
2319 CSR_READ_4(sc, JME_GHC);
2320
2321 /* Stop reset */
2322 CSR_WRITE_4(sc, JME_GHC, 0);
2323 /* Flush */
2324 CSR_READ_4(sc, JME_GHC);
2325
2326 /*
2327 * Clear reset bit after stop reset
2328 */
2329
2330 /* Enable TXMAC and TXOFL clock sources */
2331 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2332 /* Enable RXMAC clock source */
2333 val = CSR_READ_4(sc, JME_GPREG1);
2334 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2335 /* Flush */
2336 CSR_READ_4(sc, JME_GHC);
2337
2338 /* Disable TXMAC and TXOFL clock sources */
76fbb0b9 2339 CSR_WRITE_4(sc, JME_GHC, 0);
409fe405
SZ
2340 /* Disable RXMAC clock source */
2341 val = CSR_READ_4(sc, JME_GPREG1);
2342 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2343 /* Flush */
2344 CSR_READ_4(sc, JME_GHC);
2345
2346 /* Enable TX and RX */
2347 val = CSR_READ_4(sc, JME_TXCSR);
2348 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2349 val = CSR_READ_4(sc, JME_RXCSR);
2350 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2351 /* Flush */
2352 CSR_READ_4(sc, JME_TXCSR);
2353 CSR_READ_4(sc, JME_RXCSR);
2354
2355 /* Enable TXMAC and TXOFL clock sources */
2356 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2357 /* Eisable RXMAC clock source */
2358 val = CSR_READ_4(sc, JME_GPREG1);
2359 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2360 /* Flush */
2361 CSR_READ_4(sc, JME_GHC);
2362
2363 /* Stop TX and RX */
2364 jme_stop_tx(sc);
2365 jme_stop_rx(sc);
76fbb0b9
SZ
2366}
2367
2368static void
2369jme_init(void *xsc)
2370{
2371 struct jme_softc *sc = xsc;
2372 struct ifnet *ifp = &sc->arpcom.ac_if;
2373 struct mii_data *mii;
2374 uint8_t eaddr[ETHER_ADDR_LEN];
2375 bus_addr_t paddr;
2376 uint32_t reg;
4447c752 2377 int error, r;
76fbb0b9 2378
31f0d5a2 2379 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2380
2381 /*
2382 * Cancel any pending I/O.
2383 */
2384 jme_stop(sc);
2385
2386 /*
2387 * Reset the chip to a known state.
2388 */
2389 jme_reset(sc);
2390
58880b0d
SZ
2391 /*
2392 * Setup MSI/MSI-X vectors to interrupts mapping
2393 */
2394 jme_set_msinum(sc);
2395
9b3ee148
SZ
2396 sc->jme_txd_spare =
2397 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2398 KKASSERT(sc->jme_txd_spare >= 1);
2399
76fbb0b9 2400 /*
9b3ee148
SZ
2401 * If we use 64bit address mode for transmitting, each Tx request
2402 * needs one more symbol descriptor.
76fbb0b9 2403 */
9b3ee148
SZ
2404 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2405 sc->jme_txd_spare += 1;
76fbb0b9 2406
7b040092 2407 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
760c056c
SZ
2408 jme_enable_rss(sc);
2409 else
2410 jme_disable_rss(sc);
4447c752
SZ
2411
2412 /* Init RX descriptors */
7b040092 2413 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
dea2452a 2414 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
4447c752
SZ
2415 if (error) {
2416 if_printf(ifp, "initialization failed: "
2417 "no memory for %dth RX ring.\n", r);
2418 jme_stop(sc);
2419 return;
2420 }
2421 }
2422
2423 /* Init TX descriptors */
76fbb0b9
SZ
2424 jme_init_tx_ring(sc);
2425
2426 /* Initialize shadow status block. */
2427 jme_init_ssb(sc);
2428
2429 /* Reprogram the station address. */
2430 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2431 CSR_WRITE_4(sc, JME_PAR0,
2432 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2433 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2434
2435 /*
2436 * Configure Tx queue.
2437 * Tx priority queue weight value : 0
2438 * Tx FIFO threshold for processing next packet : 16QW
2439 * Maximum Tx DMA length : 512
2440 * Allow Tx DMA burst.
2441 */
2442 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2443 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2444 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2445 sc->jme_txcsr |= sc->jme_tx_dma_size;
2446 sc->jme_txcsr |= TXCSR_DMA_BURST;
2447 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2448
2449 /* Set Tx descriptor counter. */
69325526 2450 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
76fbb0b9
SZ
2451
2452 /* Set Tx ring address to the hardware. */
7405bec3 2453 paddr = sc->jme_cdata.jme_tx_ring_paddr;
76fbb0b9
SZ
2454 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2455 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2456
2457 /* Configure TxMAC parameters. */
2458 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2459 reg |= TXMAC_THRESH_1_PKT;
2460 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2461 CSR_WRITE_4(sc, JME_TXMAC, reg);
2462
2463 /*
2464 * Configure Rx queue.
2465 * FIFO full threshold for transmitting Tx pause packet : 128T
2466 * FIFO threshold for processing next packet : 128QW
2467 * Rx queue 0 select
2468 * Max Rx DMA length : 128
2469 * Rx descriptor retry : 32
2470 * Rx descriptor retry time gap : 256ns
2471 * Don't receive runt/bad frame.
2472 */
2473 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
223cfc2f 2474#if 0
76fbb0b9
SZ
2475 /*
2476 * Since Rx FIFO size is 4K bytes, receiving frames larger
2477 * than 4K bytes will suffer from Rx FIFO overruns. So
2478 * decrease FIFO threshold to reduce the FIFO overruns for
2479 * frames larger than 4000 bytes.
2480 * For best performance of standard MTU sized frames use
2481 * maximum allowable FIFO threshold, 128QW.
2482 */
2483 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2484 JME_RX_FIFO_SIZE)
2485 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2486 else
2487 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
223cfc2f
SZ
2488#else
2489 /* Improve PCI Express compatibility */
2490 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2491#endif
2492 sc->jme_rxcsr |= sc->jme_rx_dma_size;
76fbb0b9
SZ
2493 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2494 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2495 /* XXX TODO DROP_BAD */
76fbb0b9 2496
7b040092
SZ
2497 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2498 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2499
4447c752
SZ
2500 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2501
2502 /* Set Rx descriptor counter. */
7b040092 2503 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
76fbb0b9 2504
4447c752 2505 /* Set Rx ring address to the hardware. */
7b040092 2506 paddr = rdata->jme_rx_ring_paddr;
4447c752
SZ
2507 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2508 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2509 }
76fbb0b9
SZ
2510
2511 /* Clear receive filter. */
2512 CSR_WRITE_4(sc, JME_RXMAC, 0);
2513
2514 /* Set up the receive filter. */
2515 jme_set_filter(sc);
2516 jme_set_vlan(sc);
2517
2518 /*
2519 * Disable all WOL bits as WOL can interfere normal Rx
2520 * operation. Also clear WOL detection status bits.
2521 */
2522 reg = CSR_READ_4(sc, JME_PMCS);
2523 reg &= ~PMCS_WOL_ENB_MASK;
2524 CSR_WRITE_4(sc, JME_PMCS, reg);
2525
2526 /*
2527 * Pad 10bytes right before received frame. This will greatly
2528 * help Rx performance on strict-alignment architectures as
2529 * it does not need to copy the frame to align the payload.
2530 */
2531 reg = CSR_READ_4(sc, JME_RXMAC);
2532 reg |= RXMAC_PAD_10BYTES;
2533
2534 if (ifp->if_capenable & IFCAP_RXCSUM)
2535 reg |= RXMAC_CSUM_ENB;
2536 CSR_WRITE_4(sc, JME_RXMAC, reg);
2537
2538 /* Configure general purpose reg0 */
2539 reg = CSR_READ_4(sc, JME_GPREG0);
2540 reg &= ~GPREG0_PCC_UNIT_MASK;
2541 /* Set PCC timer resolution to micro-seconds unit. */
2542 reg |= GPREG0_PCC_UNIT_US;
2543 /*
2544 * Disable all shadow register posting as we have to read
2545 * JME_INTR_STATUS register in jme_intr. Also it seems
2546 * that it's hard to synchronize interrupt status between
2547 * hardware and software with shadow posting due to
2548 * requirements of bus_dmamap_sync(9).
2549 */
2550 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2551 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2552 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2553 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2554 /* Disable posting of DW0. */
2555 reg &= ~GPREG0_POST_DW0_ENB;
2556 /* Clear PME message. */
2557 reg &= ~GPREG0_PME_ENB;
2558 /* Set PHY address. */
2559 reg &= ~GPREG0_PHY_ADDR_MASK;
2560 reg |= sc->jme_phyaddr;
2561 CSR_WRITE_4(sc, JME_GPREG0, reg);
2562
2563 /* Configure Tx queue 0 packet completion coalescing. */
2870abc4 2564 jme_set_tx_coal(sc);
76fbb0b9 2565
dea2452a 2566 /* Configure Rx queues packet completion coalescing. */
2870abc4 2567 jme_set_rx_coal(sc);
76fbb0b9
SZ
2568
2569 /* Configure shadow status block but don't enable posting. */
560616bf 2570 paddr = sc->jme_cdata.jme_ssb_block_paddr;
76fbb0b9
SZ
2571 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2572 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2573
2574 /* Disable Timer 1 and Timer 2. */
2575 CSR_WRITE_4(sc, JME_TIMER1, 0);
2576 CSR_WRITE_4(sc, JME_TIMER2, 0);
2577
2578 /* Configure retry transmit period, retry limit value. */
2579 CSR_WRITE_4(sc, JME_TXTRHD,
2580 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2581 TXTRHD_RT_PERIOD_MASK) |
2582 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2583 TXTRHD_RT_LIMIT_SHIFT));
2584
9de40864
SZ
2585#ifdef DEVICE_POLLING
2586 if (!(ifp->if_flags & IFF_POLLING))
2587#endif
76fbb0b9
SZ
2588 /* Initialize the interrupt mask. */
2589 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2590 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2591
2592 /*
2593 * Enabling Tx/Rx DMA engines and Rx queue processing is
2594 * done after detection of valid link in jme_miibus_statchg.
2595 */
2596 sc->jme_flags &= ~JME_FLAG_LINK;
2597
2598 /* Set the current media. */
2599 mii = device_get_softc(sc->jme_miibus);
2600 mii_mediachg(mii);
2601
2602 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2603
2604 ifp->if_flags |= IFF_RUNNING;
2605 ifp->if_flags &= ~IFF_OACTIVE;
2606}
2607
2608static void
2609jme_stop(struct jme_softc *sc)
2610{
2611 struct ifnet *ifp = &sc->arpcom.ac_if;
2612 struct jme_txdesc *txd;
2613 struct jme_rxdesc *rxd;
4447c752
SZ
2614 struct jme_rxdata *rdata;
2615 int i, r;
76fbb0b9 2616
31f0d5a2 2617 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2618
2619 /*
2620 * Mark the interface down and cancel the watchdog timer.
2621 */
2622 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2623 ifp->if_timer = 0;
2624
2625 callout_stop(&sc->jme_tick_ch);
2626 sc->jme_flags &= ~JME_FLAG_LINK;
2627
2628 /*
2629 * Disable interrupts.
2630 */
2631 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2632 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2633
2634 /* Disable updating shadow status block. */
2635 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2636 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2637
2638 /* Stop receiver, transmitter. */
2639 jme_stop_rx(sc);
2640 jme_stop_tx(sc);
2641
76fbb0b9
SZ
2642 /*
2643 * Free partial finished RX segments
2644 */
7b040092 2645 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752
SZ
2646 rdata = &sc->jme_cdata.jme_rx_data[r];
2647 if (rdata->jme_rxhead != NULL)
2648 m_freem(rdata->jme_rxhead);
dea2452a 2649 JME_RXCHAIN_RESET(rdata);
4447c752 2650 }
76fbb0b9
SZ
2651
2652 /*
2653 * Free RX and TX mbufs still in the queues.
2654 */
7b040092 2655 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
4447c752 2656 rdata = &sc->jme_cdata.jme_rx_data[r];
7b040092 2657 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
2658 rxd = &rdata->jme_rxdesc[i];
2659 if (rxd->rx_m != NULL) {
2660 bus_dmamap_unload(rdata->jme_rx_tag,
2661 rxd->rx_dmamap);
2662 m_freem(rxd->rx_m);
2663 rxd->rx_m = NULL;
2664 }
76fbb0b9 2665 }
4447c752 2666 }
69325526 2667 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
76fbb0b9
SZ
2668 txd = &sc->jme_cdata.jme_txdesc[i];
2669 if (txd->tx_m != NULL) {
2670 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2671 txd->tx_dmamap);
2672 m_freem(txd->tx_m);
2673 txd->tx_m = NULL;
2674 txd->tx_ndesc = 0;
2675 }
2676 }
2677}
2678
2679static void
2680jme_stop_tx(struct jme_softc *sc)
2681{
2682 uint32_t reg;
2683 int i;
2684
2685 reg = CSR_READ_4(sc, JME_TXCSR);
2686 if ((reg & TXCSR_TX_ENB) == 0)
2687 return;
2688 reg &= ~TXCSR_TX_ENB;
2689 CSR_WRITE_4(sc, JME_TXCSR, reg);
2690 for (i = JME_TIMEOUT; i > 0; i--) {
2691 DELAY(1);
2692 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2693 break;
2694 }
2695 if (i == 0)
2696 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2697}
2698
2699static void
2700jme_stop_rx(struct jme_softc *sc)
2701{
2702 uint32_t reg;
2703 int i;
2704
2705 reg = CSR_READ_4(sc, JME_RXCSR);
2706 if ((reg & RXCSR_RX_ENB) == 0)
2707 return;
2708 reg &= ~RXCSR_RX_ENB;
2709 CSR_WRITE_4(sc, JME_RXCSR, reg);
2710 for (i = JME_TIMEOUT; i > 0; i--) {
2711 DELAY(1);
2712 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2713 break;
2714 }
2715 if (i == 0)
2716 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2717}
2718
2719static void
2720jme_init_tx_ring(struct jme_softc *sc)
2721{
560616bf 2722 struct jme_chain_data *cd;
76fbb0b9
SZ
2723 struct jme_txdesc *txd;
2724 int i;
2725
2726 sc->jme_cdata.jme_tx_prod = 0;
2727 sc->jme_cdata.jme_tx_cons = 0;
2728 sc->jme_cdata.jme_tx_cnt = 0;
2729
560616bf
SZ
2730 cd = &sc->jme_cdata;
2731 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
69325526 2732 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
76fbb0b9
SZ
2733 txd = &sc->jme_cdata.jme_txdesc[i];
2734 txd->tx_m = NULL;
560616bf 2735 txd->tx_desc = &cd->jme_tx_ring[i];
76fbb0b9
SZ
2736 txd->tx_ndesc = 0;
2737 }
76fbb0b9
SZ
2738}
2739
2740static void
2741jme_init_ssb(struct jme_softc *sc)
2742{
560616bf 2743 struct jme_chain_data *cd;
76fbb0b9 2744
560616bf
SZ
2745 cd = &sc->jme_cdata;
2746 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
76fbb0b9
SZ
2747}
2748
2749static int
dea2452a 2750jme_init_rx_ring(struct jme_rxdata *rdata)
76fbb0b9 2751{
76fbb0b9
SZ
2752 struct jme_rxdesc *rxd;
2753 int i;
2754
4447c752
SZ
2755 KKASSERT(rdata->jme_rxhead == NULL &&
2756 rdata->jme_rxtail == NULL &&
2757 rdata->jme_rxlen == 0);
2758 rdata->jme_rx_cons = 0;
76fbb0b9 2759
7b040092
SZ
2760 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2761 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
76fbb0b9
SZ
2762 int error;
2763
4447c752 2764 rxd = &rdata->jme_rxdesc[i];
76fbb0b9 2765 rxd->rx_m = NULL;
4447c752 2766 rxd->rx_desc = &rdata->jme_rx_ring[i];
dea2452a 2767 error = jme_newbuf(rdata, rxd, 1);
76fbb0b9 2768 if (error)
4447c752 2769 return error;
76fbb0b9 2770 }
4447c752 2771 return 0;
76fbb0b9
SZ
2772}
2773
2774static int
dea2452a 2775jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
76fbb0b9
SZ
2776{
2777 struct jme_desc *desc;
2778 struct mbuf *m;
76fbb0b9
SZ
2779 bus_dma_segment_t segs;
2780 bus_dmamap_t map;
b0ba1747 2781 int error, nsegs;
76fbb0b9
SZ
2782
2783 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2784 if (m == NULL)
4447c752 2785 return ENOBUFS;
76fbb0b9
SZ
2786 /*
2787 * JMC250 has 64bit boundary alignment limitation so jme(4)
2788 * takes advantage of 10 bytes padding feature of hardware
2789 * in order not to copy entire frame to align IP header on
2790 * 32bit boundary.
2791 */
2792 m->m_len = m->m_pkthdr.len = MCLBYTES;
2793
b0ba1747
SZ
2794 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2795 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2796 BUS_DMA_NOWAIT);
2797 if (error) {
76fbb0b9 2798 m_freem(m);
dea2452a
SZ
2799 if (init) {
2800 if_printf(&rdata->jme_sc->arpcom.ac_if,
2801 "can't load RX mbuf\n");
2802 }
4447c752 2803 return error;
76fbb0b9
SZ
2804 }
2805
2806 if (rxd->rx_m != NULL) {
4447c752 2807 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
76fbb0b9 2808 BUS_DMASYNC_POSTREAD);
4447c752 2809 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
76fbb0b9
SZ
2810 }
2811 map = rxd->rx_dmamap;
4447c752
SZ
2812 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2813 rdata->jme_rx_sparemap = map;
76fbb0b9
SZ
2814 rxd->rx_m = m;
2815
2816 desc = rxd->rx_desc;
2817 desc->buflen = htole32(segs.ds_len);
2818 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2819 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2820 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2821
4447c752 2822 return 0;
76fbb0b9
SZ
2823}
2824
2825static void
2826jme_set_vlan(struct jme_softc *sc)
2827{
2828 struct ifnet *ifp = &sc->arpcom.ac_if;
2829 uint32_t reg;
2830
31f0d5a2 2831 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2832
2833 reg = CSR_READ_4(sc, JME_RXMAC);
2834 reg &= ~RXMAC_VLAN_ENB;
2835 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2836 reg |= RXMAC_VLAN_ENB;
2837 CSR_WRITE_4(sc, JME_RXMAC, reg);
2838}
2839
2840static void
2841jme_set_filter(struct jme_softc *sc)
2842{
2843 struct ifnet *ifp = &sc->arpcom.ac_if;
2844 struct ifmultiaddr *ifma;
2845 uint32_t crc;
2846 uint32_t mchash[2];
2847 uint32_t rxcfg;
2848
31f0d5a2 2849 ASSERT_IFNET_SERIALIZED_ALL(ifp);
76fbb0b9
SZ
2850
2851 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2852 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2853 RXMAC_ALLMULTI);
2854
2855 /*
2856 * Always accept frames destined to our station address.
2857 * Always accept broadcast frames.
2858 */
2859 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2860
2861 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2862 if (ifp->if_flags & IFF_PROMISC)
2863 rxcfg |= RXMAC_PROMISC;
2864 if (ifp->if_flags & IFF_ALLMULTI)
2865 rxcfg |= RXMAC_ALLMULTI;
2866 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2867 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2868 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2869 return;
2870 }
2871
2872 /*
2873 * Set up the multicast address filter by passing all multicast
2874 * addresses through a CRC generator, and then using the low-order
2875 * 6 bits as an index into the 64 bit multicast hash table. The
2876 * high order bits select the register, while the rest of the bits
2877 * select the bit within the register.
2878 */
2879 rxcfg |= RXMAC_MULTICAST;
2880 bzero(mchash, sizeof(mchash));
2881
441d34b2 2882 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
76fbb0b9
SZ
2883 if (ifma->ifma_addr->sa_family != AF_LINK)
2884 continue;
2885 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2886 ifma->ifma_addr), ETHER_ADDR_LEN);
2887
2888 /* Just want the 6 least significant bits. */
2889 crc &= 0x3f;
2890
2891 /* Set the corresponding bit in the hash table. */
2892 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2893 }
2894
2895 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2896 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2897 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2898}
2899
76fbb0b9 2900static int
2870abc4 2901jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 2902{
2870abc4
SZ
2903 struct jme_softc *sc = arg1;
2904 struct ifnet *ifp = &sc->arpcom.ac_if;
2905 int error, v;
2906
31f0d5a2 2907 ifnet_serialize_all(ifp);
2870abc4
SZ
2908
2909 v = sc->jme_tx_coal_to;
2910 error = sysctl_handle_int(oidp, &v, 0, req);
2911 if (error || req->newptr == NULL)
2912 goto back;
2913
2914 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2915 error = EINVAL;
2916 goto back;
2917 }
2918
2919 if (v != sc->jme_tx_coal_to) {
2920 sc->jme_tx_coal_to = v;
2921 if (ifp->if_flags & IFF_RUNNING)
2922 jme_set_tx_coal(sc);
2923 }
2924back:
31f0d5a2 2925 ifnet_deserialize_all(ifp);
2870abc4 2926 return error;
76fbb0b9
SZ
2927}
2928
2929static int
2870abc4 2930jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
76fbb0b9 2931{
2870abc4
SZ
2932 struct jme_softc *sc = arg1;
2933 struct ifnet *ifp = &sc->arpcom.ac_if;
2934 int error, v;
2935
31f0d5a2 2936 ifnet_serialize_all(ifp);
2870abc4
SZ
2937
2938 v = sc->jme_tx_coal_pkt;
2939 error = sysctl_handle_int(oidp, &v, 0, req);
2940 if (error || req->newptr == NULL)
2941 goto back;
2942
2943 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2944 error = EINVAL;
2945 goto back;
2946 }
2947
2948 if (v != sc->jme_tx_coal_pkt) {
2949 sc->jme_tx_coal_pkt = v;
2950 if (ifp->if_flags & IFF_RUNNING)
2951 jme_set_tx_coal(sc);
2952 }
2953back:
31f0d5a2 2954 ifnet_deserialize_all(ifp);
2870abc4 2955 return error;
76fbb0b9
SZ
2956}
2957
2958static int
2870abc4 2959jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
76fbb0b9 2960{
2870abc4
SZ
2961 struct jme_softc *sc = arg1;
2962 struct ifnet *ifp = &sc->arpcom.ac_if;
2963 int error, v;
2964
31f0d5a2 2965 ifnet_serialize_all(ifp);
2870abc4
SZ
2966
2967 v = sc->jme_rx_coal_to;
2968 error = sysctl_handle_int(oidp, &v, 0, req);
2969 if (error || req->newptr == NULL)
2970 goto back;
2971
2972 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2973 error = EINVAL;
2974 goto back;
2975 }
2976
2977 if (v != sc->jme_rx_coal_to) {
2978 sc->jme_rx_coal_to = v;
2979 if (ifp->if_flags & IFF_RUNNING)
2980 jme_set_rx_coal(sc);
2981 }
2982back:
31f0d5a2 2983 ifnet_deserialize_all(ifp);
2870abc4 2984 return error;
76fbb0b9
SZ
2985}
2986
2987static int
2870abc4
SZ
2988jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2989{
2990 struct jme_softc *sc = arg1;
2991 struct ifnet *ifp = &sc->arpcom.ac_if;
2992 int error, v;
2993
31f0d5a2 2994 ifnet_serialize_all(ifp);
2870abc4
SZ
2995
2996 v = sc->jme_rx_coal_pkt;
2997 error = sysctl_handle_int(oidp, &v, 0, req);
2998 if (error || req->newptr == NULL)
2999 goto back;
3000
3001 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3002 error = EINVAL;
3003 goto back;
3004 }
3005
3006 if (v != sc->jme_rx_coal_pkt) {
3007 sc->jme_rx_coal_pkt = v;
3008 if (ifp->if_flags & IFF_RUNNING)
3009 jme_set_rx_coal(sc);
3010 }
3011back:
31f0d5a2 3012 ifnet_deserialize_all(ifp);
2870abc4
SZ
3013 return error;
3014}
3015
3016static void
3017jme_set_tx_coal(struct jme_softc *sc)
3018{
3019 uint32_t reg;
3020
3021 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3022 PCCTX_COAL_TO_MASK;
3023 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3024 PCCTX_COAL_PKT_MASK;
3025 reg |= PCCTX_COAL_TXQ0;
3026 CSR_WRITE_4(sc, JME_PCCTX, reg);
3027}
3028
3029static void
3030jme_set_rx_coal(struct jme_softc *sc)
76fbb0b9 3031{
2870abc4 3032 uint32_t reg;
4447c752 3033 int r;
2870abc4
SZ
3034
3035 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3036 PCCRX_COAL_TO_MASK;
3037 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3038 PCCRX_COAL_PKT_MASK;
7b040092 3039 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
9f20b7b3 3040 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
76fbb0b9 3041}
9de40864
SZ
3042
3043#ifdef DEVICE_POLLING
3044
3045static void
3046jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3047{
3048 struct jme_softc *sc = ifp->if_softc;
3049 uint32_t status;
eda7db08 3050 int r;
9de40864 3051
31f0d5a2 3052 ASSERT_SERIALIZED(&sc->jme_serialize);
9de40864
SZ
3053
3054 switch (cmd) {
3055 case POLL_REGISTER:
3056 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3057 break;
3058
3059 case POLL_DEREGISTER:
3060 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3061 break;
3062
3063 case POLL_AND_CHECK_STATUS:
3064 case POLL_ONLY:
3065 status = CSR_READ_4(sc, JME_INTR_STATUS);
0e7f1e6f 3066
7b040092 3067 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31f0d5a2
SZ
3068 struct jme_rxdata *rdata =
3069 &sc->jme_cdata.jme_rx_data[r];
3070
3071 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3072 jme_rxeof(rdata, count);
31f0d5a2
SZ
3073 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3074 }
9de40864
SZ
3075
3076 if (status & INTR_RXQ_DESC_EMPTY) {
3077 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3078 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3079 RXCSR_RX_ENB | RXCSR_RXQ_START);
3080 }
3081
31f0d5a2 3082 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ
3083 jme_txeof(sc);
3084 if (!ifq_is_empty(&ifp->if_snd))
3085 if_devstart(ifp);
31f0d5a2 3086 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
9de40864
SZ
3087 break;
3088 }
3089}
3090
3091#endif /* DEVICE_POLLING */
4447c752
SZ
3092
3093static int
dea2452a 3094jme_rxring_dma_alloc(struct jme_rxdata *rdata)
4447c752 3095{
1128a202 3096 bus_dmamem_t dmem;
4447c752
SZ
3097 int error;
3098
dea2452a 3099 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
1128a202 3100 JME_RX_RING_ALIGN, 0,
0eb220ec 3101 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
7b040092 3102 JME_RX_RING_SIZE(rdata),
1128a202 3103 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4447c752 3104 if (error) {
dea2452a
SZ
3105 device_printf(rdata->jme_sc->jme_dev,
3106 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
4447c752
SZ
3107 return error;
3108 }
1128a202
SZ
3109 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3110 rdata->jme_rx_ring_map = dmem.dmem_map;
3111 rdata->jme_rx_ring = dmem.dmem_addr;
3112 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
4447c752
SZ
3113
3114 return 0;
3115}
3116
3117static int
dea2452a 3118jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
4447c752 3119{
4447c752
SZ
3120 int i, error;
3121
3122 /* Create tag for Rx buffers. */
dea2452a
SZ
3123 error = bus_dma_tag_create(
3124 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
4447c752 3125 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
0eb220ec 3126 BUS_SPACE_MAXADDR, /* lowaddr */
4447c752
SZ
3127 BUS_SPACE_MAXADDR, /* highaddr */
3128 NULL, NULL, /* filter, filterarg */
3129 MCLBYTES, /* maxsize */
3130 1, /* nsegments */
3131 MCLBYTES, /* maxsegsize */
9d424cee 3132 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
4447c752
SZ
3133 &rdata->jme_rx_tag);
3134 if (error) {
dea2452a
SZ
3135 device_printf(rdata->jme_sc->jme_dev,
3136 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
4447c752
SZ
3137 return error;
3138 }
3139
3140 /* Create DMA maps for Rx buffers. */
9d424cee 3141 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3142 &rdata->jme_rx_sparemap);
3143 if (error) {
dea2452a
SZ
3144 device_printf(rdata->jme_sc->jme_dev,
3145 "could not create %dth spare Rx dmamap.\n",
3146 rdata->jme_rx_idx);
4447c752
SZ
3147 bus_dma_tag_destroy(rdata->jme_rx_tag);
3148 rdata->jme_rx_tag = NULL;
3149 return error;
3150 }
7b040092 3151 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
4447c752
SZ
3152 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3153
9d424cee 3154 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
4447c752
SZ
3155 &rxd->rx_dmamap);
3156 if (error) {
3157 int j;
3158
dea2452a 3159 device_printf(rdata->jme_sc->jme_dev,
4447c752 3160 "could not create %dth Rx dmamap "
dea2452a 3161 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
4447c752
SZ
3162
3163 for (j = 0; j < i; ++j) {
3164 rxd = &rdata->jme_rxdesc[j];
3165 bus_dmamap_destroy(rdata->jme_rx_tag,
3166 rxd->rx_dmamap);
3167 }
3168 bus_dmamap_destroy(rdata->jme_rx_tag,
3169 rdata->jme_rx_sparemap);
3170 bus_dma_tag_destroy(rdata->jme_rx_tag);
3171 rdata->jme_rx_tag = NULL;
3172 return error;
3173 }
3174 }
3175 return 0;
3176}
3177
3178static void
3179jme_rx_intr(struct jme_softc *sc, uint32_t status)
3180{
eda7db08 3181 int r;
4447c752 3182
7b040092 3183 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
31810fb8 3184 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
31f0d5a2 3185
31810fb8 3186 if (status & rdata->jme_rx_coal) {
31f0d5a2 3187 lwkt_serialize_enter(&rdata->jme_rx_serialize);
dea2452a 3188 jme_rxeof(rdata, -1);
31f0d5a2
SZ
3189 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3190 }
4447c752
SZ
3191 }
3192}
760c056c
SZ
3193
3194static void
3195jme_enable_rss(struct jme_softc *sc)
3196{
24dd1705
SZ
3197 uint32_t rssc, ind;
3198 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
760c056c
SZ
3199 int i;
3200
9f20b7b3
SZ
3201 KASSERT(sc->jme_rx_ring_cnt == JME_NRXRING_2 ||
3202 sc->jme_rx_ring_cnt == JME_NRXRING_4,
66f75939 3203 ("%s: invalid # of RX rings (%d)\n",
9f20b7b3 3204 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_cnt));
66f75939 3205
760c056c
SZ
3206 rssc = RSSC_HASH_64_ENTRY;
3207 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
7b040092 3208 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
760c056c
SZ
3209 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3210 CSR_WRITE_4(sc, JME_RSSC, rssc);
3211
24dd1705
SZ
3212 toeplitz_get_key(key, sizeof(key));
3213 for (i = 0; i < RSSKEY_NREGS; ++i) {
3214 uint32_t keyreg;
3215
3216 keyreg = RSSKEY_REGVAL(key, i);
3217 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3218
3219 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3220 }
760c056c 3221
66f75939
SZ
3222 /*
3223 * Create redirect table in following fashion:
3224 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3225 */
760c056c 3226 ind = 0;
66f75939
SZ
3227 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3228 int q;
3229
7b040092 3230 q = i % sc->jme_cdata.jme_rx_ring_cnt;
66f75939 3231 ind |= q << (i * 8);
760c056c
SZ
3232 }
3233 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
66f75939 3234
760c056c
SZ
3235 for (i = 0; i < RSSTBL_NREGS; ++i)
3236 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3237}
3238
3239static void
3240jme_disable_rss(struct jme_softc *sc)
3241{
760c056c
SZ
3242 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3243}
31f0d5a2
SZ
3244
3245static void
3246jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3247{
3248 struct jme_softc *sc = ifp->if_softc;
3249
3250 switch (slz) {
3251 case IFNET_SERIALIZE_ALL:
3252 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3253 sc->jme_serialize_cnt, 0);
3254 break;
3255
3256 case IFNET_SERIALIZE_MAIN:
3257 lwkt_serialize_enter(&sc->jme_serialize);
3258 break;
3259
3260 case IFNET_SERIALIZE_TX:
3261 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3262 break;
3263
3264 case IFNET_SERIALIZE_RX(0):
3265 lwkt_serialize_enter(
3266 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3267 break;
3268
3269 case IFNET_SERIALIZE_RX(1):
3270 lwkt_serialize_enter(
3271 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3272 break;
3273
3274 case IFNET_SERIALIZE_RX(2):
3275 lwkt_serialize_enter(
3276 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3277 break;
3278
3279 case IFNET_SERIALIZE_RX(3):
3280 lwkt_serialize_enter(
3281 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3282 break;
3283
3284 default:
3285 panic("%s unsupported serialize type\n", ifp->if_xname);
3286 }
3287}
3288
3289static void
3290jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3291{
3292 struct jme_softc *sc = ifp->if_softc;
3293
3294 switch (slz) {
3295 case IFNET_SERIALIZE_ALL:
3296 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3297 sc->jme_serialize_cnt, 0);
3298 break;
3299
3300 case IFNET_SERIALIZE_MAIN:
3301 lwkt_serialize_exit(&sc->jme_serialize);
3302 break;
3303
3304 case IFNET_SERIALIZE_TX:
3305 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3306 break;
3307
3308 case IFNET_SERIALIZE_RX(0):
3309 lwkt_serialize_exit(
3310 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3311 break;
3312
3313 case IFNET_SERIALIZE_RX(1):
3314 lwkt_serialize_exit(
3315 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3316 break;
3317
3318 case IFNET_SERIALIZE_RX(2):
3319 lwkt_serialize_exit(
3320 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3321 break;
3322
3323 case IFNET_SERIALIZE_RX(3):
3324 lwkt_serialize_exit(
3325 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3326 break;
3327
3328 default:
3329 panic("%s unsupported serialize type\n", ifp->if_xname);
3330 }
3331}
3332
3333static int
3334jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3335{
3336 struct jme_softc *sc = ifp->if_softc;
3337
3338 switch (slz) {
3339 case IFNET_SERIALIZE_ALL:
3340 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3341 sc->jme_serialize_cnt, 0);
3342
3343 case IFNET_SERIALIZE_MAIN:
3344 return lwkt_serialize_try(&sc->jme_serialize);
3345
3346 case IFNET_SERIALIZE_TX:
3347 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3348
3349 case IFNET_SERIALIZE_RX(0):
3350 return lwkt_serialize_try(
3351 &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3352
3353 case IFNET_SERIALIZE_RX(1):
3354 return lwkt_serialize_try(
3355 &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3356
3357 case IFNET_SERIALIZE_RX(2):
3358 return lwkt_serialize_try(
3359 &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3360
3361 case IFNET_SERIALIZE_RX(3):
3362 return lwkt_serialize_try(
3363 &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3364
3365 default:
3366 panic("%s unsupported serialize type\n", ifp->if_xname);
3367 }
3368}
3369
3370#ifdef INVARIANTS
3371
3372static void
3373jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3374 boolean_t serialized)
3375{
3376 struct jme_softc *sc = ifp->if_softc;
3377 struct jme_rxdata *rdata;
3378 int i;
3379
3380 switch (slz) {
3381 case IFNET_SERIALIZE_ALL:
3382 if (serialized) {
3383 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3384 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3385 } else {
3386 for (i = 0; i < sc->jme_serialize_cnt; ++i)
3387 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3388 }
3389 break;
3390
3391 case IFNET_SERIALIZE_MAIN:
3392 if (serialized)
3393 ASSERT_SERIALIZED(&sc->jme_serialize);
3394 else
3395 ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3396 break;
3397
3398 case IFNET_SERIALIZE_TX:
3399 if (serialized)
3400 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3401 else
3402 ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3403 break;
3404
3405 case IFNET_SERIALIZE_RX(0):
3406 rdata = &sc->jme_cdata.jme_rx_data[0];
3407 if (serialized)
3408 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3409 else
3410 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3411 break;
3412
3413 case IFNET_SERIALIZE_RX(1):
3414 rdata = &sc->jme_cdata.jme_rx_data[1];
3415 if (serialized)
3416 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3417 else
3418 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3419 break;
3420
3421 case IFNET_SERIALIZE_RX(2):
3422 rdata = &sc->jme_cdata.jme_rx_data[2];
3423 if (serialized)
3424 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3425 else
3426 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3427 break;
3428
3429 case IFNET_SERIALIZE_RX(3):
3430 rdata = &sc->jme_cdata.jme_rx_data[3];
3431 if (serialized)
3432 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3433 else
3434 ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3435 break;
3436
3437 default:
3438 panic("%s unsupported serialize type\n", ifp->if_xname);
3439 }
3440}
3441
3442#endif /* INVARIANTS */
58880b0d
SZ
3443
3444static void
3445jme_msix_try_alloc(device_t dev)
3446{
3447 struct jme_softc *sc = device_get_softc(dev);
3448 struct jme_msix_data *msix;
3449 int error, i, r, msix_enable, msix_count;
58880b0d 3450
7b040092 3451 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
58880b0d
SZ
3452 KKASSERT(msix_count <= JME_NMSIX);
3453
1cc217a9 3454 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
58880b0d
SZ
3455
3456 /*
3457 * We leave the 1st MSI-X vector unused, so we
3458 * actually need msix_count + 1 MSI-X vectors.
3459 */
3460 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3461 return;
3462
3463 for (i = 0; i < msix_count; ++i)
3464 sc->jme_msix[i].jme_msix_rid = -1;
3465
3466 i = 0;
3467
3468 msix = &sc->jme_msix[i++];
3469 msix->jme_msix_cpuid = 0; /* XXX Put TX to cpu0 */
3470 msix->jme_msix_arg = &sc->jme_cdata;
3471 msix->jme_msix_func = jme_msix_tx;
3472 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3473 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3474 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3475 device_get_nameunit(dev));
3476
7b040092 3477 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
58880b0d
SZ
3478 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3479
3480 msix = &sc->jme_msix[i++];
3481 msix->jme_msix_cpuid = r; /* XXX Put RX to cpuX */
3482 msix->jme_msix_arg = rdata;
3483 msix->jme_msix_func = jme_msix_rx;
3484 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3485 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3486 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3487 "%s rx%d", device_get_nameunit(dev), r);
3488 }
3489
3490 KKASSERT(i == msix_count);
3491
3492 error = pci_setup_msix(dev);
3493 if (error)
3494 return;
3495
3496 /* Setup jme_msix_cnt early, so we could cleanup */
3497 sc->jme_msix_cnt = msix_count;
3498
3499 for (i = 0; i < msix_count; ++i) {
3500 msix = &sc->jme_msix[i];
3501
3502 msix->jme_msix_vector = i + 1;
3503 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3504 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3505 if (error)
3506 goto back;
3507
3508 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3509 &msix->jme_msix_rid, RF_ACTIVE);
3510 if (msix->jme_msix_res == NULL) {
3511 error = ENOMEM;
3512 goto back;
3513 }
3514 }
3515
3516 for (i = 0; i < JME_INTR_CNT; ++i) {
3517 uint32_t intr_mask = (1 << i);
3518 int x;
3519
3520 if ((JME_INTRS & intr_mask) == 0)
3521 continue;
3522
3523 for (x = 0; x < msix_count; ++x) {
3524 msix = &sc->jme_msix[x];
3525 if (msix->jme_msix_intrs & intr_mask) {
3526 int reg, shift;
3527
3528 reg = i / JME_MSINUM_FACTOR;
3529 KKASSERT(reg < JME_MSINUM_CNT);
3530
3531 shift = (i % JME_MSINUM_FACTOR) * 4;
3532
3533 sc->jme_msinum[reg] |=
3534 (msix->jme_msix_vector << shift);
3535
3536 break;
3537 }
3538 }
3539 }
3540
3541 if (bootverbose) {
3542 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3543 device_printf(dev, "MSINUM%d: %#x\n", i,
3544 sc->jme_msinum[i]);
3545 }
3546 }
3547
3548 pci_enable_msix(dev);
3549 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3550
3551back:
3552 if (error)
3553 jme_msix_free(dev);
3554}
3555
3556static int
3557jme_intr_alloc(device_t dev)
3558{
3559 struct jme_softc *sc = device_get_softc(dev);
3560 u_int irq_flags;
3561
3562 jme_msix_try_alloc(dev);
3563
3564 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3565 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3566 &sc->jme_irq_rid, &irq_flags);
3567
3568 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3569 &sc->jme_irq_rid, irq_flags);
3570 if (sc->jme_irq_res == NULL) {
3571 device_printf(dev, "can't allocate irq\n");
3572 return ENXIO;
3573 }
3574 }
3575 return 0;
3576}
3577
3578static void
3579jme_msix_free(device_t dev)
3580{
3581 struct jme_softc *sc = device_get_softc(dev);
3582 int i;
3583
3584 KKASSERT(sc->jme_msix_cnt > 1);
3585
3586 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3587 struct jme_msix_data *msix = &sc->jme_msix[i];
3588
3589 if (msix->jme_msix_res != NULL) {
3590 bus_release_resource(dev, SYS_RES_IRQ,
3591 msix->jme_msix_rid, msix->jme_msix_res);
3592 msix->jme_msix_res = NULL;
3593 }
3594 if (msix->jme_msix_rid >= 0) {
3595 pci_release_msix_vector(dev, msix->jme_msix_rid);
3596 msix->jme_msix_rid = -1;
3597 }
3598 }
3599 pci_teardown_msix(dev);
3600}
3601
3602static void
3603jme_intr_free(device_t dev)
3604{
3605 struct jme_softc *sc = device_get_softc(dev);
3606
3607 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3608 if (sc->jme_irq_res != NULL) {
3609 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3610 sc->jme_irq_res);
3611 }
3612 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3613 pci_release_msi(dev);
3614 } else {
3615 jme_msix_free(dev);
3616 }
3617}
3618
3619static void
3620jme_msix_tx(void *xcd)
3621{
3622 struct jme_chain_data *cd = xcd;
3623 struct jme_softc *sc = cd->jme_sc;
3624 struct ifnet *ifp = &sc->arpcom.ac_if;
3625
3626 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3627
875547c0
SZ
3628 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3629
58880b0d
SZ
3630 CSR_WRITE_4(sc, JME_INTR_STATUS,
3631 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3632
3633 if (ifp->if_flags & IFF_RUNNING) {
3634 jme_txeof(sc);
3635 if (!ifq_is_empty(&ifp->if_snd))
3636 if_devstart(ifp);
3637 }
875547c0
SZ
3638
3639 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
58880b0d
SZ
3640}
3641
3642static void
3643jme_msix_rx(void *xrdata)
3644{
3645 struct jme_rxdata *rdata = xrdata;
3646 struct jme_softc *sc = rdata->jme_sc;
3647 struct ifnet *ifp = &sc->arpcom.ac_if;
3648 uint32_t status;
3649
3650 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3651
875547c0
SZ
3652 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3653 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3654
58880b0d
SZ
3655 status = CSR_READ_4(sc, JME_INTR_STATUS);
3656 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3657
875547c0 3658 if (status & rdata->jme_rx_coal)
58880b0d 3659 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
875547c0 3660 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
58880b0d
SZ
3661
3662 if (ifp->if_flags & IFF_RUNNING) {
eda7db08 3663 if (status & rdata->jme_rx_coal)