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iwn - Port to DragonFly BSD
[dragonfly.git] / sys / dev / netif / iwn / if_iwn.c
CommitLineData
ffd7c74a
JT		 1/*-
2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
4 * Copyright (c) 2008
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/*
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
23 * adapters.
24 */
25
3db796ac 26/* $FreeBSD$ */
ffd7c74a
JT		 27
28#include <sys/param.h>
29#include <sys/sockio.h>
30#include <sys/sysctl.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/bus.h>
37#include <sys/rman.h>
38#include <sys/endian.h>
39#include <sys/firmware.h>
40#include <sys/limits.h>
41#include <sys/module.h>
42#include <sys/queue.h>
43#include <sys/taskqueue.h>
3db796ac 44#include <sys/libkern.h>
ffd7c74a 45
3db796ac
JT		 46#include <sys/bus.h>
47#include <sys/resource.h>
ffd7c74a
JT		 48#include <machine/clock.h>
49
3db796ac
JT		 50#include <bus/pci/pcireg.h>
51#include <bus/pci/pcivar.h>
ffd7c74a
JT		 52
53#include <net/bpf.h>
54#include <net/if.h>
55#include <net/if_arp.h>
3db796ac 56#include <net/ifq_var.h>
ffd7c74a
JT		 57#include <net/ethernet.h>
58#include <net/if_dl.h>
59#include <net/if_media.h>
60#include <net/if_types.h>
61
62#include <netinet/in.h>
63#include <netinet/in_systm.h>
64#include <netinet/in_var.h>
65#include <netinet/if_ether.h>
66#include <netinet/ip.h>
67
3db796ac
JT		 68#include <netproto/802_11/ieee80211_var.h>
69#include <netproto/802_11/ieee80211_radiotap.h>
70#include <netproto/802_11/ieee80211_regdomain.h>
71#include <netproto/802_11/ieee80211_ratectl.h>
ffd7c74a 72
3db796ac
JT		 73#include "if_iwnreg.h"
74#include "if_iwnvar.h"
ffd7c74a
JT		 75
76static int iwn_probe(device_t);
77static int iwn_attach(device_t);
78static const struct iwn_hal *iwn_hal_attach(struct iwn_softc *);
79static void iwn_radiotap_attach(struct iwn_softc *);
80static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
81 const char name[IFNAMSIZ], int unit, int opmode,
82 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
83 const uint8_t mac[IEEE80211_ADDR_LEN]);
84static void iwn_vap_delete(struct ieee80211vap *);
85static int iwn_cleanup(device_t);
86static int iwn_detach(device_t);
87static int iwn_nic_lock(struct iwn_softc *);
88static int iwn_eeprom_lock(struct iwn_softc *);
89static int iwn_init_otprom(struct iwn_softc *);
90static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
91static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
92static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
93 void **, bus_size_t, bus_size_t, int);
94static void iwn_dma_contig_free(struct iwn_dma_info *);
95static int iwn_alloc_sched(struct iwn_softc *);
96static void iwn_free_sched(struct iwn_softc *);
97static int iwn_alloc_kw(struct iwn_softc *);
98static void iwn_free_kw(struct iwn_softc *);
99static int iwn_alloc_ict(struct iwn_softc *);
100static void iwn_free_ict(struct iwn_softc *);
101static int iwn_alloc_fwmem(struct iwn_softc *);
102static void iwn_free_fwmem(struct iwn_softc *);
103static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
104static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
105static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
106static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
107 int);
108static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
109static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
110static void iwn5000_ict_reset(struct iwn_softc *);
111static int iwn_read_eeprom(struct iwn_softc *,
112 uint8_t macaddr[IEEE80211_ADDR_LEN]);
113static void iwn4965_read_eeprom(struct iwn_softc *);
114static void iwn4965_print_power_group(struct iwn_softc *, int);
115static void iwn5000_read_eeprom(struct iwn_softc *);
116static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
117static void iwn_read_eeprom_band(struct iwn_softc *, int);
118#if 0 /* HT */
119static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
120#endif
121static void iwn_read_eeprom_channels(struct iwn_softc *, int,
122 uint32_t);
123static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
124static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
125 const uint8_t mac[IEEE80211_ADDR_LEN]);
126static void iwn_newassoc(struct ieee80211_node *, int);
127static int iwn_media_change(struct ifnet *);
128static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
129static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
130 struct iwn_rx_data *);
131static void iwn_timer_timeout(void *);
132static void iwn_calib_reset(struct iwn_softc *);
133static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
134 struct iwn_rx_data *);
135#if 0 /* HT */
136static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
137 struct iwn_rx_data *);
138#endif
139static void iwn5000_rx_calib_results(struct iwn_softc *,
140 struct iwn_rx_desc *, struct iwn_rx_data *);
141static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
142 struct iwn_rx_data *);
143static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
144 struct iwn_rx_data *);
145static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
146 struct iwn_rx_data *);
147static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
148 uint8_t);
149static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
150static void iwn_notif_intr(struct iwn_softc *);
151static void iwn_wakeup_intr(struct iwn_softc *);
152static void iwn_rftoggle_intr(struct iwn_softc *);
153static void iwn_fatal_intr(struct iwn_softc *);
154static void iwn_intr(void *);
155static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
156 uint16_t);
157static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
158 uint16_t);
159#ifdef notyet
160static void iwn5000_reset_sched(struct iwn_softc *, int, int);
161#endif
162static uint8_t iwn_plcp_signal(int);
163static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
164 struct ieee80211_node *, struct iwn_tx_ring *);
165static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
166 const struct ieee80211_bpf_params *);
167static void iwn_start(struct ifnet *);
168static void iwn_start_locked(struct ifnet *);
169static void iwn_watchdog(struct iwn_softc *sc);
3db796ac 170static int iwn_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
ffd7c74a
JT		 171static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
172static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
173 int);
174static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
175 int);
176static int iwn_set_link_quality(struct iwn_softc *, uint8_t, int);
177static int iwn_add_broadcast_node(struct iwn_softc *, int);
178static int iwn_wme_update(struct ieee80211com *);
179static void iwn_update_mcast(struct ifnet *);
180static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
181static int iwn_set_critical_temp(struct iwn_softc *);
182static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
183static void iwn4965_power_calibration(struct iwn_softc *, int);
184static int iwn4965_set_txpower(struct iwn_softc *,
185 struct ieee80211_channel *, int);
186static int iwn5000_set_txpower(struct iwn_softc *,
187 struct ieee80211_channel *, int);
188static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
189static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
190static int iwn_get_noise(const struct iwn_rx_general_stats *);
191static int iwn4965_get_temperature(struct iwn_softc *);
192static int iwn5000_get_temperature(struct iwn_softc *);
193static int iwn_init_sensitivity(struct iwn_softc *);
194static void iwn_collect_noise(struct iwn_softc *,
195 const struct iwn_rx_general_stats *);
196static int iwn4965_init_gains(struct iwn_softc *);
197static int iwn5000_init_gains(struct iwn_softc *);
198static int iwn4965_set_gains(struct iwn_softc *);
199static int iwn5000_set_gains(struct iwn_softc *);
200static void iwn_tune_sensitivity(struct iwn_softc *,
201 const struct iwn_rx_stats *);
202static int iwn_send_sensitivity(struct iwn_softc *);
203static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
204static int iwn_config(struct iwn_softc *);
205static int iwn_scan(struct iwn_softc *);
206static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
207static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
208#if 0 /* HT */
209static int iwn_ampdu_rx_start(struct ieee80211com *,
210 struct ieee80211_node *, uint8_t);
211static void iwn_ampdu_rx_stop(struct ieee80211com *,
212 struct ieee80211_node *, uint8_t);
213static int iwn_ampdu_tx_start(struct ieee80211com *,
214 struct ieee80211_node *, uint8_t);
215static void iwn_ampdu_tx_stop(struct ieee80211com *,
216 struct ieee80211_node *, uint8_t);
217static void iwn4965_ampdu_tx_start(struct iwn_softc *,
218 struct ieee80211_node *, uint8_t, uint16_t);
219static void iwn4965_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
220static void iwn5000_ampdu_tx_start(struct iwn_softc *,
221 struct ieee80211_node *, uint8_t, uint16_t);
222static void iwn5000_ampdu_tx_stop(struct iwn_softc *, uint8_t, uint16_t);
223#endif
224static int iwn5000_query_calibration(struct iwn_softc *);
225static int iwn5000_send_calibration(struct iwn_softc *);
226static int iwn5000_send_wimax_coex(struct iwn_softc *);
227static int iwn4965_post_alive(struct iwn_softc *);
228static int iwn5000_post_alive(struct iwn_softc *);
229static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
230 int);
231static int iwn4965_load_firmware(struct iwn_softc *);
232static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
233 const uint8_t *, int);
234static int iwn5000_load_firmware(struct iwn_softc *);
235static int iwn_read_firmware(struct iwn_softc *);
236static int iwn_clock_wait(struct iwn_softc *);
237static int iwn_apm_init(struct iwn_softc *);
238static void iwn_apm_stop_master(struct iwn_softc *);
239static void iwn_apm_stop(struct iwn_softc *);
240static int iwn4965_nic_config(struct iwn_softc *);
241static int iwn5000_nic_config(struct iwn_softc *);
242static int iwn_hw_prepare(struct iwn_softc *);
243static int iwn_hw_init(struct iwn_softc *);
244static void iwn_hw_stop(struct iwn_softc *);
245static void iwn_init_locked(struct iwn_softc *);
246static void iwn_init(void *);
247static void iwn_stop_locked(struct iwn_softc *);
248static void iwn_stop(struct iwn_softc *);
249static void iwn_scan_start(struct ieee80211com *);
250static void iwn_scan_end(struct ieee80211com *);
251static void iwn_set_channel(struct ieee80211com *);
252static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
253static void iwn_scan_mindwell(struct ieee80211_scan_state *);
254static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
255 struct ieee80211_channel *);
256static int iwn_setregdomain(struct ieee80211com *,
257 struct ieee80211_regdomain *, int,
258 struct ieee80211_channel []);
259static void iwn_hw_reset(void *, int);
260static void iwn_radio_on(void *, int);
261static void iwn_radio_off(void *, int);
262static void iwn_sysctlattach(struct iwn_softc *);
263static int iwn_shutdown(device_t);
264static int iwn_suspend(device_t);
265static int iwn_resume(device_t);
266
267#define IWN_DEBUG
268#ifdef IWN_DEBUG
269enum {
270 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
271 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
272 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
273 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
274 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
275 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
276 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
277 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
278 IWN_DEBUG_INTR = 0x00000100, /* ISR */
279 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
280 IWN_DEBUG_NODE = 0x00000400, /* node management */
281 IWN_DEBUG_LED = 0x00000800, /* led management */
282 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
283 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
284 IWN_DEBUG_ANY = 0xffffffff
285};
286
287#define DPRINTF(sc, m, fmt, ...) do { \
288 if (sc->sc_debug & (m)) \
3db796ac 289 kprintf(fmt, __VA_ARGS__); \
ffd7c74a
JT		 290} while (0)
291
292static const char *iwn_intr_str(uint8_t);
293#else
294#define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
295#endif
296
297struct iwn_ident {
298 uint16_t vendor;
299 uint16_t device;
300 const char *name;
301};
302
303static const struct iwn_ident iwn_ident_table [] = {
304 { 0x8086, 0x4229, "Intel(R) PRO/Wireless 4965BGN" },
305 { 0x8086, 0x422D, "Intel(R) PRO/Wireless 4965BGN" },
306 { 0x8086, 0x4230, "Intel(R) PRO/Wireless 4965BGN" },
307 { 0x8086, 0x4233, "Intel(R) PRO/Wireless 4965BGN" },
308 { 0x8086, 0x4232, "Intel(R) PRO/Wireless 5100" },
309 { 0x8086, 0x4237, "Intel(R) PRO/Wireless 5100" },
310 { 0x8086, 0x423C, "Intel(R) PRO/Wireless 5150" },
311 { 0x8086, 0x423D, "Intel(R) PRO/Wireless 5150" },
312 { 0x8086, 0x4235, "Intel(R) PRO/Wireless 5300" },
313 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5300" },
314 { 0x8086, 0x4236, "Intel(R) PRO/Wireless 5350" },
315 { 0x8086, 0x423A, "Intel(R) PRO/Wireless 5350" },
316 { 0x8086, 0x423B, "Intel(R) PRO/Wireless 5350" },
317 { 0x8086, 0x0083, "Intel(R) PRO/Wireless 1000" },
318 { 0x8086, 0x0084, "Intel(R) PRO/Wireless 1000" },
319 { 0x8086, 0x008D, "Intel(R) PRO/Wireless 6000" },
320 { 0x8086, 0x008E, "Intel(R) PRO/Wireless 6000" },
321 { 0x8086, 0x4238, "Intel(R) PRO/Wireless 6000" },
322 { 0x8086, 0x4239, "Intel(R) PRO/Wireless 6000" },
323 { 0x8086, 0x422B, "Intel(R) PRO/Wireless 6000" },
324 { 0x8086, 0x422C, "Intel(R) PRO/Wireless 6000" },
325 { 0x8086, 0x0086, "Intel(R) PRO/Wireless 6050" },
326 { 0x8086, 0x0087, "Intel(R) PRO/Wireless 6050" },
327 { 0, 0, NULL }
328};
329
330static const struct iwn_hal iwn4965_hal = {
331 iwn4965_load_firmware,
332 iwn4965_read_eeprom,
333 iwn4965_post_alive,
334 iwn4965_nic_config,
335 iwn4965_update_sched,
336 iwn4965_get_temperature,
337 iwn4965_get_rssi,
338 iwn4965_set_txpower,
339 iwn4965_init_gains,
340 iwn4965_set_gains,
341 iwn4965_add_node,
342 iwn4965_tx_done,
343#if 0 /* HT */
344 iwn4965_ampdu_tx_start,
345 iwn4965_ampdu_tx_stop,
346#endif
347 IWN4965_NTXQUEUES,
348 IWN4965_NDMACHNLS,
349 IWN4965_ID_BROADCAST,
350 IWN4965_RXONSZ,
351 IWN4965_SCHEDSZ,
352 IWN4965_FW_TEXT_MAXSZ,
353 IWN4965_FW_DATA_MAXSZ,
354 IWN4965_FWSZ,
355 IWN4965_SCHED_TXFACT
356};
357
358static const struct iwn_hal iwn5000_hal = {
359 iwn5000_load_firmware,
360 iwn5000_read_eeprom,
361 iwn5000_post_alive,
362 iwn5000_nic_config,
363 iwn5000_update_sched,
364 iwn5000_get_temperature,
365 iwn5000_get_rssi,
366 iwn5000_set_txpower,
367 iwn5000_init_gains,
368 iwn5000_set_gains,
369 iwn5000_add_node,
370 iwn5000_tx_done,
371#if 0 /* HT */
372 iwn5000_ampdu_tx_start,
373 iwn5000_ampdu_tx_stop,
374#endif
375 IWN5000_NTXQUEUES,
376 IWN5000_NDMACHNLS,
377 IWN5000_ID_BROADCAST,
378 IWN5000_RXONSZ,
379 IWN5000_SCHEDSZ,
380 IWN5000_FW_TEXT_MAXSZ,
381 IWN5000_FW_DATA_MAXSZ,
382 IWN5000_FWSZ,
383 IWN5000_SCHED_TXFACT
384};
385
386static int
387iwn_probe(device_t dev)
388{
389 const struct iwn_ident *ident;
390
391 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
392 if (pci_get_vendor(dev) == ident->vendor &&
393 pci_get_device(dev) == ident->device) {
394 device_set_desc(dev, ident->name);
395 return 0;
396 }
397 }
398 return ENXIO;
399}
400
401static int
402iwn_attach(device_t dev)
403{
404 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
405 struct ieee80211com *ic;
406 struct ifnet *ifp;
407 const struct iwn_hal *hal;
408 uint32_t tmp;
409 int i, error, result;
410 uint8_t macaddr[IEEE80211_ADDR_LEN];
411
412 sc->sc_dev = dev;
3db796ac
JT		 413 sc->sc_dmat = NULL;
414
415 if (bus_dma_tag_create(sc->sc_dmat,
416 1, 0,
417 BUS_SPACE_MAXADDR_32BIT,
418 BUS_SPACE_MAXADDR,
419 NULL, NULL,
420 BUS_SPACE_MAXSIZE,
421 IWN_MAX_SCATTER,
422 BUS_SPACE_MAXSIZE,
423 BUS_DMA_ALLOCNOW,
424 &sc->sc_dmat)) {
425 device_printf(dev, "cannot allocate DMA tag\n");
426 error = ENOMEM;
427 goto fail;
428 }
429
430
431
432 /* prepare sysctl tree for use in sub modules */
433 sysctl_ctx_init(&sc->sc_sysctl_ctx);
434 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
435 SYSCTL_STATIC_CHILDREN(_hw),
436 OID_AUTO,
437 device_get_nameunit(sc->sc_dev),
438 CTLFLAG_RD, 0, "");
ffd7c74a
JT		 439
440 /*
441 * Get the offset of the PCI Express Capability Structure in PCI
442 * Configuration Space.
443 */
444 error = pci_find_extcap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
445 if (error != 0) {
446 device_printf(dev, "PCIe capability structure not found!\n");
447 return error;
448 }
449
450 /* Clear device-specific "PCI retry timeout" register (41h). */
451 pci_write_config(dev, 0x41, 0, 1);
452
453 /* Hardware bug workaround. */
454 tmp = pci_read_config(dev, PCIR_COMMAND, 1);
455 if (tmp & PCIM_CMD_INTxDIS) {
456 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
457 __func__);
458 tmp &= ~PCIM_CMD_INTxDIS;
459 pci_write_config(dev, PCIR_COMMAND, tmp, 1);
460 }
461
462 /* Enable bus-mastering. */
463 pci_enable_busmaster(dev);
464
465 sc->mem_rid = PCIR_BAR(0);
466 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
467 RF_ACTIVE);
468 if (sc->mem == NULL ) {
469 device_printf(dev, "could not allocate memory resources\n");
470 error = ENOMEM;
471 return error;
472 }
473
474 sc->sc_st = rman_get_bustag(sc->mem);
475 sc->sc_sh = rman_get_bushandle(sc->mem);
476 sc->irq_rid = 0;
477 if ((result = pci_msi_count(dev)) == 1 &&
478 pci_alloc_msi(dev, &result) == 0)
479 sc->irq_rid = 1;
480 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
481 RF_ACTIVE | RF_SHAREABLE);
482 if (sc->irq == NULL) {
483 device_printf(dev, "could not allocate interrupt resource\n");
484 error = ENOMEM;
485 goto fail;
486 }
487
488 IWN_LOCK_INIT(sc);
3db796ac 489 callout_init(&sc->sc_timer_to);
ffd7c74a
JT		 490 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc );
491 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc );
492 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc );
493
494 /* Attach Hardware Abstraction Layer. */
495 hal = iwn_hal_attach(sc);
496 if (hal == NULL) {
497 error = ENXIO; /* XXX: Wrong error code? */
498 goto fail;
499 }
500
501 error = iwn_hw_prepare(sc);
502 if (error != 0) {
503 device_printf(dev, "hardware not ready, error %d\n", error);
504 goto fail;
505 }
506
507 /* Allocate DMA memory for firmware transfers. */
508 error = iwn_alloc_fwmem(sc);
509 if (error != 0) {
510 device_printf(dev,
511 "could not allocate memory for firmware, error %d\n",
512 error);
513 goto fail;
514 }
515
516 /* Allocate "Keep Warm" page. */
517 error = iwn_alloc_kw(sc);
518 if (error != 0) {
519 device_printf(dev,
520 "could not allocate \"Keep Warm\" page, error %d\n", error);
521 goto fail;
522 }
523
524 /* Allocate ICT table for 5000 Series. */
525 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
526 (error = iwn_alloc_ict(sc)) != 0) {
527 device_printf(dev,
528 "%s: could not allocate ICT table, error %d\n",
529 __func__, error);
530 goto fail;
531 }
532
533 /* Allocate TX scheduler "rings". */
534 error = iwn_alloc_sched(sc);
535 if (error != 0) {
536 device_printf(dev,
537 "could not allocate TX scheduler rings, error %d\n",
538 error);
539 goto fail;
540 }
541
542 /* Allocate TX rings (16 on 4965AGN, 20 on 5000). */
543 for (i = 0; i < hal->ntxqs; i++) {
544 error = iwn_alloc_tx_ring(sc, &sc->txq[i], i);
545 if (error != 0) {
546 device_printf(dev,
547 "could not allocate Tx ring %d, error %d\n",
548 i, error);
549 goto fail;
550 }
551 }
552
553 /* Allocate RX ring. */
554 error = iwn_alloc_rx_ring(sc, &sc->rxq);
555 if (error != 0 ){
556 device_printf(dev,
557 "could not allocate Rx ring, error %d\n", error);
558 goto fail;
559 }
560
561 /* Clear pending interrupts. */
562 IWN_WRITE(sc, IWN_INT, 0xffffffff);
563
564 /* Count the number of available chains. */
565 sc->ntxchains =
566 ((sc->txchainmask >> 2) & 1) +
567 ((sc->txchainmask >> 1) & 1) +
568 ((sc->txchainmask >> 0) & 1);
569 sc->nrxchains =
570 ((sc->rxchainmask >> 2) & 1) +
571 ((sc->rxchainmask >> 1) & 1) +
572 ((sc->rxchainmask >> 0) & 1);
573
574 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
575 if (ifp == NULL) {
576 device_printf(dev, "can not allocate ifnet structure\n");
577 goto fail;
578 }
579 ic = ifp->if_l2com;
580
581 ic->ic_ifp = ifp;
582 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
583 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
584
585 /* Set device capabilities. */
586 ic->ic_caps =
587 IEEE80211_C_STA /* station mode supported */
588 | IEEE80211_C_MONITOR /* monitor mode supported */
589 | IEEE80211_C_TXPMGT /* tx power management */
590 | IEEE80211_C_SHSLOT /* short slot time supported */
591 | IEEE80211_C_WPA
592 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
593 | IEEE80211_C_BGSCAN /* background scanning */
594#if 0
595 | IEEE80211_C_IBSS /* ibss/adhoc mode */
596#endif
597 | IEEE80211_C_WME /* WME */
598 ;
599#if 0 /* HT */
600 /* XXX disable until HT channel setup works */
601 ic->ic_htcaps =
602 IEEE80211_HTCAP_SMPS_ENA /* SM PS mode enabled */
603 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width */
604 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
605 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
606 | IEEE80211_HTCAP_RXSTBC_2STREAM/* 1-2 spatial streams */
607 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
608 /* s/w capabilities */
609 | IEEE80211_HTC_HT /* HT operation */
610 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
611 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
612 ;
613
614 /* Set HT capabilities. */
615 ic->ic_htcaps =
616#if IWN_RBUF_SIZE == 8192
617 IEEE80211_HTCAP_AMSDU7935 |
618#endif
619 IEEE80211_HTCAP_CBW20_40 |
620 IEEE80211_HTCAP_SGI20 |
621 IEEE80211_HTCAP_SGI40;
622 if (sc->hw_type != IWN_HW_REV_TYPE_4965)
623 ic->ic_htcaps |= IEEE80211_HTCAP_GF;
624 if (sc->hw_type == IWN_HW_REV_TYPE_6050)
625 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DYN;
626 else
627 ic->ic_htcaps |= IEEE80211_HTCAP_SMPS_DIS;
628#endif
629
630 /* Read MAC address, channels, etc from EEPROM. */
631 error = iwn_read_eeprom(sc, macaddr);
632 if (error != 0) {
633 device_printf(dev, "could not read EEPROM, error %d\n",
634 error);
635 goto fail;
636 }
637
638 device_printf(sc->sc_dev, "MIMO %dT%dR, %.4s, address %6D\n",
639 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
640 macaddr, ":");
641
642#if 0 /* HT */
643 /* Set supported HT rates. */
644 ic->ic_sup_mcs[0] = 0xff;
645 if (sc->nrxchains > 1)
646 ic->ic_sup_mcs[1] = 0xff;
647 if (sc->nrxchains > 2)
648 ic->ic_sup_mcs[2] = 0xff;
649#endif
650
651 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
652 ifp->if_softc = sc;
653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
654 ifp->if_init = iwn_init;
655 ifp->if_ioctl = iwn_ioctl;
656 ifp->if_start = iwn_start;
3db796ac
JT		 657 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
658 ifq_set_ready(&ifp->if_snd);
ffd7c74a
JT		 659
660 ieee80211_ifattach(ic, macaddr);
661 ic->ic_vap_create = iwn_vap_create;
662 ic->ic_vap_delete = iwn_vap_delete;
663 ic->ic_raw_xmit = iwn_raw_xmit;
664 ic->ic_node_alloc = iwn_node_alloc;
665 ic->ic_newassoc = iwn_newassoc;
666 ic->ic_wme.wme_update = iwn_wme_update;
667 ic->ic_update_mcast = iwn_update_mcast;
668 ic->ic_scan_start = iwn_scan_start;
669 ic->ic_scan_end = iwn_scan_end;
670 ic->ic_set_channel = iwn_set_channel;
671 ic->ic_scan_curchan = iwn_scan_curchan;
672 ic->ic_scan_mindwell = iwn_scan_mindwell;
673 ic->ic_setregdomain = iwn_setregdomain;
674#if 0 /* HT */
675 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
676 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
677 ic->ic_ampdu_tx_start = iwn_ampdu_tx_start;
678 ic->ic_ampdu_tx_stop = iwn_ampdu_tx_stop;
679#endif
680
681 iwn_radiotap_attach(sc);
682 iwn_sysctlattach(sc);
683
684 /*
685 * Hook our interrupt after all initialization is complete.
686 */
3db796ac
JT		 687 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
688 iwn_intr, sc, &sc->sc_ih, ifp->if_serializer);
ffd7c74a
JT		 689 if (error != 0) {
690 device_printf(dev, "could not set up interrupt, error %d\n",
691 error);
692 goto fail;
693 }
694
695 ieee80211_announce(ic);
696 return 0;
697fail:
698 iwn_cleanup(dev);
699 return error;
700}
701
702static const struct iwn_hal *
703iwn_hal_attach(struct iwn_softc *sc)
704{
705 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
706
707 switch (sc->hw_type) {
708 case IWN_HW_REV_TYPE_4965:
709 sc->sc_hal = &iwn4965_hal;
710 sc->limits = &iwn4965_sensitivity_limits;
711 sc->fwname = "iwn4965fw";
712 sc->txchainmask = IWN_ANT_AB;
713 sc->rxchainmask = IWN_ANT_ABC;
714 break;
715 case IWN_HW_REV_TYPE_5100:
716 sc->sc_hal = &iwn5000_hal;
717 sc->limits = &iwn5000_sensitivity_limits;
718 sc->fwname = "iwn5000fw";
719 sc->txchainmask = IWN_ANT_B;
720 sc->rxchainmask = IWN_ANT_AB;
721 break;
722 case IWN_HW_REV_TYPE_5150:
723 sc->sc_hal = &iwn5000_hal;
724 sc->limits = &iwn5150_sensitivity_limits;
725 sc->fwname = "iwn5150fw";
726 sc->txchainmask = IWN_ANT_A;
727 sc->rxchainmask = IWN_ANT_AB;
728 break;
729 case IWN_HW_REV_TYPE_5300:
730 case IWN_HW_REV_TYPE_5350:
731 sc->sc_hal = &iwn5000_hal;
732 sc->limits = &iwn5000_sensitivity_limits;
733 sc->fwname = "iwn5000fw";
734 sc->txchainmask = IWN_ANT_ABC;
735 sc->rxchainmask = IWN_ANT_ABC;
736 break;
737 case IWN_HW_REV_TYPE_1000:
738 sc->sc_hal = &iwn5000_hal;
739 sc->limits = &iwn1000_sensitivity_limits;
740 sc->fwname = "iwn1000fw";
741 sc->txchainmask = IWN_ANT_A;
742 sc->rxchainmask = IWN_ANT_AB;
743 break;
744 case IWN_HW_REV_TYPE_6000:
745 sc->sc_hal = &iwn5000_hal;
746 sc->limits = &iwn6000_sensitivity_limits;
747 sc->fwname = "iwn6000fw";
748 switch (pci_get_device(sc->sc_dev)) {
749 case 0x422C:
750 case 0x4239:
751 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
752 sc->txchainmask = IWN_ANT_BC;
753 sc->rxchainmask = IWN_ANT_BC;
754 break;
755 default:
756 sc->txchainmask = IWN_ANT_ABC;
757 sc->rxchainmask = IWN_ANT_ABC;
758 break;
759 }
760 break;
761 case IWN_HW_REV_TYPE_6050:
762 sc->sc_hal = &iwn5000_hal;
763 sc->limits = &iwn6000_sensitivity_limits;
764 sc->fwname = "iwn6000fw";
765 sc->txchainmask = IWN_ANT_AB;
766 sc->rxchainmask = IWN_ANT_AB;
767 break;
768 default:
769 device_printf(sc->sc_dev, "adapter type %d not supported\n",
770 sc->hw_type);
771 return NULL;
772 }
773 return sc->sc_hal;
774}
775
776/*
777 * Attach the interface to 802.11 radiotap.
778 */
779static void
780iwn_radiotap_attach(struct iwn_softc *sc)
781{
782 struct ifnet *ifp = sc->sc_ifp;
783 struct ieee80211com *ic = ifp->if_l2com;
784
785 ieee80211_radiotap_attach(ic,
786 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
787 IWN_TX_RADIOTAP_PRESENT,
788 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
789 IWN_RX_RADIOTAP_PRESENT);
790}
791
792static struct ieee80211vap *
793iwn_vap_create(struct ieee80211com *ic,
794 const char name[IFNAMSIZ], int unit, int opmode, int flags,
795 const uint8_t bssid[IEEE80211_ADDR_LEN],
796 const uint8_t mac[IEEE80211_ADDR_LEN])
797{
798 struct iwn_vap *ivp;
799 struct ieee80211vap *vap;
800
801 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
802 return NULL;
3db796ac
JT		 803 ivp = (struct iwn_vap *) kmalloc(sizeof(struct iwn_vap),
804 M_80211_VAP, M_INTWAIT | M_ZERO);
ffd7c74a
JT		 805 if (ivp == NULL)
806 return NULL;
807 vap = &ivp->iv_vap;
808 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
809 vap->iv_bmissthreshold = 10; /* override default */
810 /* Override with driver methods. */
811 ivp->iv_newstate = vap->iv_newstate;
812 vap->iv_newstate = iwn_newstate;
813
814 ieee80211_ratectl_init(vap);
815 /* Complete setup. */
816 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
817 ic->ic_opmode = opmode;
818 return vap;
819}
820
821static void
822iwn_vap_delete(struct ieee80211vap *vap)
823{
824 struct iwn_vap *ivp = IWN_VAP(vap);
825
826 ieee80211_ratectl_deinit(vap);
827 ieee80211_vap_detach(vap);
3db796ac 828 kfree(ivp, M_80211_VAP);
ffd7c74a
JT		 829}
830
831static int
832iwn_cleanup(device_t dev)
833{
834 struct iwn_softc *sc = device_get_softc(dev);
835 struct ifnet *ifp = sc->sc_ifp;
836 struct ieee80211com *ic;
837 int i;
838
839 if (ifp != NULL) {
840 ic = ifp->if_l2com;
841
842 ieee80211_draintask(ic, &sc->sc_reinit_task);
843 ieee80211_draintask(ic, &sc->sc_radioon_task);
844 ieee80211_draintask(ic, &sc->sc_radiooff_task);
845
846 iwn_stop(sc);
3db796ac 847 callout_stop(&sc->sc_timer_to);
ffd7c74a
JT		 848 ieee80211_ifdetach(ic);
849 }
850
851 /* Free DMA resources. */
852 iwn_free_rx_ring(sc, &sc->rxq);
853 if (sc->sc_hal != NULL)
854 for (i = 0; i < sc->sc_hal->ntxqs; i++)
855 iwn_free_tx_ring(sc, &sc->txq[i]);
856 iwn_free_sched(sc);
857 iwn_free_kw(sc);
858 if (sc->ict != NULL)
859 iwn_free_ict(sc);
860 iwn_free_fwmem(sc);
861
862 if (sc->irq != NULL) {
863 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
864 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
865 if (sc->irq_rid == 1)
866 pci_release_msi(dev);
867 }
868
869 if (sc->mem != NULL)
870 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
871
872 if (ifp != NULL)
873 if_free(ifp);
874
875 IWN_LOCK_DESTROY(sc);
876 return 0;
877}
878
879static int
880iwn_detach(device_t dev)
881{
3db796ac
JT		 882 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
883
ffd7c74a 884 iwn_cleanup(dev);
3db796ac 885 bus_dma_tag_destroy(sc->sc_dmat);
ffd7c74a
JT		 886 return 0;
887}
888
889static int
890iwn_nic_lock(struct iwn_softc *sc)
891{
892 int ntries;
893
894 /* Request exclusive access to NIC. */
895 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
896
897 /* Spin until we actually get the lock. */
898 for (ntries = 0; ntries < 1000; ntries++) {
899 if ((IWN_READ(sc, IWN_GP_CNTRL) &
900 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
901 IWN_GP_CNTRL_MAC_ACCESS_ENA)
902 return 0;
903 DELAY(10);
904 }
905 return ETIMEDOUT;
906}
907
908static __inline void
909iwn_nic_unlock(struct iwn_softc *sc)
910{
911 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
912}
913
914static __inline uint32_t
915iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
916{
917 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
918 IWN_BARRIER_READ_WRITE(sc);
919 return IWN_READ(sc, IWN_PRPH_RDATA);
920}
921
922static __inline void
923iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
924{
925 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
926 IWN_BARRIER_WRITE(sc);
927 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
928}
929
930static __inline void
931iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
932{
933 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
934}
935
936static __inline void
937iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
938{
939 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
940}
941
942static __inline void
943iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
944 const uint32_t *data, int count)
945{
946 for (; count > 0; count--, data++, addr += 4)
947 iwn_prph_write(sc, addr, *data);
948}
949
950static __inline uint32_t
951iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
952{
953 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
954 IWN_BARRIER_READ_WRITE(sc);
955 return IWN_READ(sc, IWN_MEM_RDATA);
956}
957
958static __inline void
959iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
960{
961 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
962 IWN_BARRIER_WRITE(sc);
963 IWN_WRITE(sc, IWN_MEM_WDATA, data);
964}
965
966static __inline void
967iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
968{
969 uint32_t tmp;
970
971 tmp = iwn_mem_read(sc, addr & ~3);
972 if (addr & 3)
973 tmp = (tmp & 0x0000ffff) | data << 16;
974 else
975 tmp = (tmp & 0xffff0000) | data;
976 iwn_mem_write(sc, addr & ~3, tmp);
977}
978
979static __inline void
980iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
981 int count)
982{
983 for (; count > 0; count--, addr += 4)
984 *data++ = iwn_mem_read(sc, addr);
985}
986
987static __inline void
988iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
989 int count)
990{
991 for (; count > 0; count--, addr += 4)
992 iwn_mem_write(sc, addr, val);
993}
994
995static int
996iwn_eeprom_lock(struct iwn_softc *sc)
997{
998 int i, ntries;
999
1000 for (i = 0; i < 100; i++) {
1001 /* Request exclusive access to EEPROM. */
1002 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1003 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1004
1005 /* Spin until we actually get the lock. */
1006 for (ntries = 0; ntries < 100; ntries++) {
1007 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1008 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1009 return 0;
1010 DELAY(10);
1011 }
1012 }
1013 return ETIMEDOUT;
1014}
1015
1016static __inline void
1017iwn_eeprom_unlock(struct iwn_softc *sc)
1018{
1019 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1020}
1021
1022/*
1023 * Initialize access by host to One Time Programmable ROM.
1024 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1025 */
1026static int
1027iwn_init_otprom(struct iwn_softc *sc)
1028{
1029 uint16_t prev, base, next;
1030 int count, error;
1031
1032 /* Wait for clock stabilization before accessing prph. */
1033 error = iwn_clock_wait(sc);
1034 if (error != 0)
1035 return error;
1036
1037 error = iwn_nic_lock(sc);
1038 if (error != 0)
1039 return error;
1040 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1041 DELAY(5);
1042 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1043 iwn_nic_unlock(sc);
1044
1045 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1046 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1047 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1048 IWN_RESET_LINK_PWR_MGMT_DIS);
1049 }
1050 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1051 /* Clear ECC status. */
1052 IWN_SETBITS(sc, IWN_OTP_GP,
1053 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1054
1055 /*
1056 * Find the block before last block (contains the EEPROM image)
1057 * for HW without OTP shadow RAM.
1058 */
1059 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1060 /* Switch to absolute addressing mode. */
1061 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1062 base = prev = 0;
1063 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1064 error = iwn_read_prom_data(sc, base, &next, 2);
1065 if (error != 0)
1066 return error;
1067 if (next == 0) /* End of linked-list. */
1068 break;
1069 prev = base;
1070 base = le16toh(next);
1071 }
1072 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1073 return EIO;
1074 /* Skip "next" word. */
1075 sc->prom_base = prev + 1;
1076 }
1077 return 0;
1078}
1079
1080static int
1081iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1082{
1083 uint32_t val, tmp;
1084 int ntries;
1085 uint8_t *out = data;
1086
1087 addr += sc->prom_base;
1088 for (; count > 0; count -= 2, addr++) {
1089 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1090 for (ntries = 0; ntries < 10; ntries++) {
1091 val = IWN_READ(sc, IWN_EEPROM);
1092 if (val & IWN_EEPROM_READ_VALID)
1093 break;
1094 DELAY(5);
1095 }
1096 if (ntries == 10) {
1097 device_printf(sc->sc_dev,
1098 "timeout reading ROM at 0x%x\n", addr);
1099 return ETIMEDOUT;
1100 }
1101 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1102 /* OTPROM, check for ECC errors. */
1103 tmp = IWN_READ(sc, IWN_OTP_GP);
1104 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1105 device_printf(sc->sc_dev,
1106 "OTPROM ECC error at 0x%x\n", addr);
1107 return EIO;
1108 }
1109 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1110 /* Correctable ECC error, clear bit. */
1111 IWN_SETBITS(sc, IWN_OTP_GP,
1112 IWN_OTP_GP_ECC_CORR_STTS);
1113 }
1114 }
1115 *out++ = val >> 16;
1116 if (count > 1)
1117 *out++ = val >> 24;
1118 }
1119 return 0;
1120}
1121
1122static void
1123iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1124{
1125 if (error != 0)
1126 return;
1127 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1128 *(bus_addr_t *)arg = segs[0].ds_addr;
1129}
1130
1131static int
1132iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1133 void **kvap, bus_size_t size, bus_size_t alignment, int flags)
1134{
1135 int error;
1136
1137 dma->size = size;
1138 dma->tag = NULL;
1139
3db796ac 1140 error = bus_dma_tag_create(sc->sc_dmat, alignment,
ffd7c74a 1141 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
3db796ac 1142 1, size, flags, &dma->tag);
ffd7c74a
JT		 1143 if (error != 0) {
1144 device_printf(sc->sc_dev,
1145 "%s: bus_dma_tag_create failed, error %d\n",
1146 __func__, error);
1147 goto fail;
1148 }
1149 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1150 flags | BUS_DMA_ZERO, &dma->map);
1151 if (error != 0) {
1152 device_printf(sc->sc_dev,
1153 "%s: bus_dmamem_alloc failed, error %d\n", __func__, error);
1154 goto fail;
1155 }
1156 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr,
1157 size, iwn_dma_map_addr, &dma->paddr, flags);
1158 if (error != 0) {
1159 device_printf(sc->sc_dev,
1160 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
1161 goto fail;
1162 }
1163
1164 if (kvap != NULL)
1165 *kvap = dma->vaddr;
1166 return 0;
1167fail:
1168 iwn_dma_contig_free(dma);
1169 return error;
1170}
1171
1172static void
1173iwn_dma_contig_free(struct iwn_dma_info *dma)
1174{
1175 if (dma->tag != NULL) {
1176 if (dma->map != NULL) {
1177 if (dma->paddr == 0) {
1178 bus_dmamap_sync(dma->tag, dma->map,
1179 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1180 bus_dmamap_unload(dma->tag, dma->map);
1181 }
1182 bus_dmamem_free(dma->tag, &dma->vaddr, dma->map);
1183 }
1184 bus_dma_tag_destroy(dma->tag);
1185 }
1186}
1187
1188static int
1189iwn_alloc_sched(struct iwn_softc *sc)
1190{
1191 /* TX scheduler rings must be aligned on a 1KB boundary. */
1192 return iwn_dma_contig_alloc(sc, &sc->sched_dma,
1193 (void **)&sc->sched, sc->sc_hal->schedsz, 1024, BUS_DMA_NOWAIT);
1194}
1195
1196static void
1197iwn_free_sched(struct iwn_softc *sc)
1198{
1199 iwn_dma_contig_free(&sc->sched_dma);
1200}
1201
1202static int
1203iwn_alloc_kw(struct iwn_softc *sc)
1204{
1205 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1206 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096,
1207 BUS_DMA_NOWAIT);
1208}
1209
1210static void
1211iwn_free_kw(struct iwn_softc *sc)
1212{
1213 iwn_dma_contig_free(&sc->kw_dma);
1214}
1215
1216static int
1217iwn_alloc_ict(struct iwn_softc *sc)
1218{
1219 /* ICT table must be aligned on a 4KB boundary. */
1220 return iwn_dma_contig_alloc(sc, &sc->ict_dma,
1221 (void **)&sc->ict, IWN_ICT_SIZE, 4096, BUS_DMA_NOWAIT);
1222}
1223
1224static void
1225iwn_free_ict(struct iwn_softc *sc)
1226{
1227 iwn_dma_contig_free(&sc->ict_dma);
1228}
1229
1230static int
1231iwn_alloc_fwmem(struct iwn_softc *sc)
1232{
1233 /* Must be aligned on a 16-byte boundary. */
1234 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL,
1235 sc->sc_hal->fwsz, 16, BUS_DMA_NOWAIT);
1236}
1237
1238static void
1239iwn_free_fwmem(struct iwn_softc *sc)
1240{
1241 iwn_dma_contig_free(&sc->fw_dma);
1242}
1243
1244static int
1245iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1246{
1247 bus_size_t size;
1248 int i, error;
1249
1250 ring->cur = 0;
1251
1252 /* Allocate RX descriptors (256-byte aligned). */
1253 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1254 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1255 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1256 if (error != 0) {
1257 device_printf(sc->sc_dev,
1258 "%s: could not allocate Rx ring DMA memory, error %d\n",
1259 __func__, error);
1260 goto fail;
1261 }
1262
3db796ac 1263 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
ffd7c74a 1264 BUS_SPACE_MAXADDR_32BIT,
3db796ac
JT		 1265 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1266 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
ffd7c74a
JT		 1267 if (error != 0) {
1268 device_printf(sc->sc_dev,
1269 "%s: bus_dma_tag_create_failed, error %d\n",
1270 __func__, error);
1271 goto fail;
1272 }
1273
1274 /* Allocate RX status area (16-byte aligned). */
1275 error = iwn_dma_contig_alloc(sc, &ring->stat_dma,
1276 (void **)&ring->stat, sizeof (struct iwn_rx_status),
1277 16, BUS_DMA_NOWAIT);
1278 if (error != 0) {
1279 device_printf(sc->sc_dev,
1280 "%s: could not allocate Rx status DMA memory, error %d\n",
1281 __func__, error);
1282 goto fail;
1283 }
1284
1285 /*
1286 * Allocate and map RX buffers.
1287 */
1288 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1289 struct iwn_rx_data *data = &ring->data[i];
1290 bus_addr_t paddr;
1291
1292 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1293 if (error != 0) {
1294 device_printf(sc->sc_dev,
1295 "%s: bus_dmamap_create failed, error %d\n",
1296 __func__, error);
1297 goto fail;
1298 }
1299
3db796ac 1300 data->m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT		 1301 if (data->m == NULL) {
1302 device_printf(sc->sc_dev,
1303 "%s: could not allocate rx mbuf\n", __func__);
1304 error = ENOMEM;
1305 goto fail;
1306 }
1307
1308 /* Map page. */
1309 error = bus_dmamap_load(ring->data_dmat, data->map,
3db796ac 1310 mtod(data->m, caddr_t), MCLBYTES,
ffd7c74a
JT		 1311 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
1312 if (error != 0 && error != EFBIG) {
1313 device_printf(sc->sc_dev,
1314 "%s: bus_dmamap_load failed, error %d\n",
1315 __func__, error);
1316 m_freem(data->m);
1317 error = ENOMEM; /* XXX unique code */
1318 goto fail;
1319 }
1320 bus_dmamap_sync(ring->data_dmat, data->map,
1321 BUS_DMASYNC_PREWRITE);
1322
1323 /* Set physical address of RX buffer (256-byte aligned). */
1324 ring->desc[i] = htole32(paddr >> 8);
1325 }
1326 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1327 BUS_DMASYNC_PREWRITE);
1328 return 0;
1329fail:
1330 iwn_free_rx_ring(sc, ring);
1331 return error;
1332}
1333
1334static void
1335iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1336{
1337 int ntries;
1338
1339 if (iwn_nic_lock(sc) == 0) {
1340 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1341 for (ntries = 0; ntries < 1000; ntries++) {
1342 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1343 IWN_FH_RX_STATUS_IDLE)
1344 break;
1345 DELAY(10);
1346 }
1347 iwn_nic_unlock(sc);
1348#ifdef IWN_DEBUG
1349 if (ntries == 1000)
1350 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
1351 "timeout resetting Rx ring");
1352#endif
1353 }
1354 ring->cur = 0;
1355 sc->last_rx_valid = 0;
1356}
1357
1358static void
1359iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1360{
1361 int i;
1362
1363 iwn_dma_contig_free(&ring->desc_dma);
1364 iwn_dma_contig_free(&ring->stat_dma);
1365
1366 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1367 struct iwn_rx_data *data = &ring->data[i];
1368
1369 if (data->m != NULL) {
1370 bus_dmamap_sync(ring->data_dmat, data->map,
1371 BUS_DMASYNC_POSTREAD);
1372 bus_dmamap_unload(ring->data_dmat, data->map);
1373 m_freem(data->m);
1374 }
1375 if (data->map != NULL)
1376 bus_dmamap_destroy(ring->data_dmat, data->map);
1377 }
1378}
1379
1380static int
1381iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1382{
1383 bus_size_t size;
1384 bus_addr_t paddr;
1385 int i, error;
1386
1387 ring->qid = qid;
1388 ring->queued = 0;
1389 ring->cur = 0;
1390
1391 /* Allocate TX descriptors (256-byte aligned.) */
1392 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_desc);
1393 error = iwn_dma_contig_alloc(sc, &ring->desc_dma,
1394 (void **)&ring->desc, size, 256, BUS_DMA_NOWAIT);
1395 if (error != 0) {
1396 device_printf(sc->sc_dev,
1397 "%s: could not allocate TX ring DMA memory, error %d\n",
1398 __func__, error);
1399 goto fail;
1400 }
1401
1402 /*
1403 * We only use rings 0 through 4 (4 EDCA + cmd) so there is no need
1404 * to allocate commands space for other rings.
1405 */
1406 if (qid > 4)
1407 return 0;
1408
1409 size = IWN_TX_RING_COUNT * sizeof(struct iwn_tx_cmd);
1410 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma,
1411 (void **)&ring->cmd, size, 4, BUS_DMA_NOWAIT);
1412 if (error != 0) {
1413 device_printf(sc->sc_dev,
1414 "%s: could not allocate TX cmd DMA memory, error %d\n",
1415 __func__, error);
1416 goto fail;
1417 }
1418
3db796ac 1419 error = bus_dma_tag_create(sc->sc_dmat, 1, 0,
ffd7c74a
JT		 1420 BUS_SPACE_MAXADDR_32BIT,
1421 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
3db796ac 1422 MCLBYTES, BUS_DMA_NOWAIT, &ring->data_dmat);
ffd7c74a
JT		 1423 if (error != 0) {
1424 device_printf(sc->sc_dev,
1425 "%s: bus_dma_tag_create_failed, error %d\n",
1426 __func__, error);
1427 goto fail;
1428 }
1429
1430 paddr = ring->cmd_dma.paddr;
1431 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1432 struct iwn_tx_data *data = &ring->data[i];
1433
1434 data->cmd_paddr = paddr;
1435 data->scratch_paddr = paddr + 12;
1436 paddr += sizeof (struct iwn_tx_cmd);
1437
1438 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1439 if (error != 0) {
1440 device_printf(sc->sc_dev,
1441 "%s: bus_dmamap_create failed, error %d\n",
1442 __func__, error);
1443 goto fail;
1444 }
1445 bus_dmamap_sync(ring->data_dmat, data->map,
1446 BUS_DMASYNC_PREWRITE);
1447 }
1448 return 0;
1449fail:
1450 iwn_free_tx_ring(sc, ring);
1451 return error;
1452}
1453
1454static void
1455iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1456{
1457 int i;
1458
1459 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1460 struct iwn_tx_data *data = &ring->data[i];
1461
1462 if (data->m != NULL) {
1463 bus_dmamap_unload(ring->data_dmat, data->map);
1464 m_freem(data->m);
1465 data->m = NULL;
1466 }
1467 }
1468 /* Clear TX descriptors. */
1469 memset(ring->desc, 0, ring->desc_dma.size);
1470 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1471 BUS_DMASYNC_PREWRITE);
1472 sc->qfullmsk &= ~(1 << ring->qid);
1473 ring->queued = 0;
1474 ring->cur = 0;
1475}
1476
1477static void
1478iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1479{
1480 int i;
1481
1482 iwn_dma_contig_free(&ring->desc_dma);
1483 iwn_dma_contig_free(&ring->cmd_dma);
1484
1485 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1486 struct iwn_tx_data *data = &ring->data[i];
1487
1488 if (data->m != NULL) {
1489 bus_dmamap_sync(ring->data_dmat, data->map,
1490 BUS_DMASYNC_POSTWRITE);
1491 bus_dmamap_unload(ring->data_dmat, data->map);
1492 m_freem(data->m);
1493 }
1494 if (data->map != NULL)
1495 bus_dmamap_destroy(ring->data_dmat, data->map);
1496 }
1497}
1498
1499static void
1500iwn5000_ict_reset(struct iwn_softc *sc)
1501{
1502 /* Disable interrupts. */
1503 IWN_WRITE(sc, IWN_INT_MASK, 0);
1504
1505 /* Reset ICT table. */
1506 memset(sc->ict, 0, IWN_ICT_SIZE);
1507 sc->ict_cur = 0;
1508
1509 /* Set physical address of ICT table (4KB aligned.) */
1510 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1511 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1512 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1513
1514 /* Enable periodic RX interrupt. */
1515 sc->int_mask |= IWN_INT_RX_PERIODIC;
1516 /* Switch to ICT interrupt mode in driver. */
1517 sc->sc_flags |= IWN_FLAG_USE_ICT;
1518
1519 /* Re-enable interrupts. */
1520 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1521 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1522}
1523
1524static int
1525iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1526{
1527 const struct iwn_hal *hal = sc->sc_hal;
1528 int error;
1529 uint16_t val;
1530
1531 /* Check whether adapter has an EEPROM or an OTPROM. */
1532 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1533 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1534 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1535 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1536 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1537
1538 /* Adapter has to be powered on for EEPROM access to work. */
1539 error = iwn_apm_init(sc);
1540 if (error != 0) {
1541 device_printf(sc->sc_dev,
1542 "%s: could not power ON adapter, error %d\n",
1543 __func__, error);
1544 return error;
1545 }
1546
1547 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1548 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1549 return EIO;
1550 }
1551 error = iwn_eeprom_lock(sc);
1552 if (error != 0) {
1553 device_printf(sc->sc_dev,
1554 "%s: could not lock ROM, error %d\n",
1555 __func__, error);
1556 return error;
1557 }
1558
1559 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1560 error = iwn_init_otprom(sc);
1561 if (error != 0) {
1562 device_printf(sc->sc_dev,
1563 "%s: could not initialize OTPROM, error %d\n",
1564 __func__, error);
1565 return error;
1566 }
1567 }
1568
1569 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1570 sc->rfcfg = le16toh(val);
1571 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1572
1573 /* Read MAC address. */
1574 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1575
1576 /* Read adapter-specific information from EEPROM. */
1577 hal->read_eeprom(sc);
1578
1579 iwn_apm_stop(sc); /* Power OFF adapter. */
1580
1581 iwn_eeprom_unlock(sc);
1582 return 0;
1583}
1584
1585static void
1586iwn4965_read_eeprom(struct iwn_softc *sc)
1587{
1588 uint32_t addr;
1589 int i;
1590 uint16_t val;
1591
1592 /* Read regulatory domain (4 ASCII characters.) */
1593 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1594
1595 /* Read the list of authorized channels (20MHz ones only.) */
1596 for (i = 0; i < 5; i++) {
1597 addr = iwn4965_regulatory_bands[i];
1598 iwn_read_eeprom_channels(sc, i, addr);
1599 }
1600
1601 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1602 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1603 sc->maxpwr2GHz = val & 0xff;
1604 sc->maxpwr5GHz = val >> 8;
1605 /* Check that EEPROM values are within valid range. */
1606 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1607 sc->maxpwr5GHz = 38;
1608 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1609 sc->maxpwr2GHz = 38;
1610 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1611 sc->maxpwr2GHz, sc->maxpwr5GHz);
1612
1613 /* Read samples for each TX power group. */
1614 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1615 sizeof sc->bands);
1616
1617 /* Read voltage at which samples were taken. */
1618 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1619 sc->eeprom_voltage = (int16_t)le16toh(val);
1620 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1621 sc->eeprom_voltage);
1622
1623#ifdef IWN_DEBUG
1624 /* Print samples. */
1625 if (sc->sc_debug & IWN_DEBUG_ANY) {
1626 for (i = 0; i < IWN_NBANDS; i++)
1627 iwn4965_print_power_group(sc, i);
1628 }
1629#endif
1630}
1631
1632#ifdef IWN_DEBUG
1633static void
1634iwn4965_print_power_group(struct iwn_softc *sc, int i)
1635{
1636 struct iwn4965_eeprom_band *band = &sc->bands[i];
1637 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1638 int j, c;
1639
3db796ac
JT		 1640 kprintf("===band %d===\n", i);
1641 kprintf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1642 kprintf("chan1 num=%d\n", chans[0].num);
ffd7c74a
JT		 1643 for (c = 0; c < 2; c++) {
1644 for (j = 0; j < IWN_NSAMPLES; j++) {
3db796ac 1645 kprintf("chain %d, sample %d: temp=%d gain=%d "
ffd7c74a
JT		 1646 "power=%d pa_det=%d\n", c, j,
1647 chans[0].samples[c][j].temp,
1648 chans[0].samples[c][j].gain,
1649 chans[0].samples[c][j].power,
1650 chans[0].samples[c][j].pa_det);
1651 }
1652 }
3db796ac 1653 kprintf("chan2 num=%d\n", chans[1].num);
ffd7c74a
JT		 1654 for (c = 0; c < 2; c++) {
1655 for (j = 0; j < IWN_NSAMPLES; j++) {
3db796ac 1656 kprintf("chain %d, sample %d: temp=%d gain=%d "
ffd7c74a
JT		 1657 "power=%d pa_det=%d\n", c, j,
1658 chans[1].samples[c][j].temp,
1659 chans[1].samples[c][j].gain,
1660 chans[1].samples[c][j].power,
1661 chans[1].samples[c][j].pa_det);
1662 }
1663 }
1664}
1665#endif
1666
1667static void
1668iwn5000_read_eeprom(struct iwn_softc *sc)
1669{
1670 struct iwn5000_eeprom_calib_hdr hdr;
1671 int32_t temp, volt;
1672 uint32_t addr, base;
1673 int i;
1674 uint16_t val;
1675
1676 /* Read regulatory domain (4 ASCII characters.) */
1677 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1678 base = le16toh(val);
1679 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1680 sc->eeprom_domain, 4);
1681
1682 /* Read the list of authorized channels (20MHz ones only.) */
1683 for (i = 0; i < 5; i++) {
1684 addr = base + iwn5000_regulatory_bands[i];
1685 iwn_read_eeprom_channels(sc, i, addr);
1686 }
1687
1688 /* Read enhanced TX power information for 6000 Series. */
1689 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1690 iwn_read_eeprom_enhinfo(sc);
1691
1692 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1693 base = le16toh(val);
1694 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1695 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1696 "%s: calib version=%u pa type=%u voltage=%u\n",
1697 __func__, hdr.version, hdr.pa_type, le16toh(hdr.volt));
1698 sc->calib_ver = hdr.version;
1699
1700 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1701 /* Compute temperature offset. */
1702 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1703 temp = le16toh(val);
1704 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1705 volt = le16toh(val);
1706 sc->temp_off = temp - (volt / -5);
1707 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1708 temp, volt, sc->temp_off);
1709 } else {
1710 /* Read crystal calibration. */
1711 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1712 &sc->eeprom_crystal, sizeof (uint32_t));
1713 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1714 le32toh(sc->eeprom_crystal));
1715 }
1716}
1717
1718/*
1719 * Translate EEPROM flags to net80211.
1720 */
1721static uint32_t
1722iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1723{
1724 uint32_t nflags;
1725
1726 nflags = 0;
1727 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1728 nflags |= IEEE80211_CHAN_PASSIVE;
1729 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1730 nflags |= IEEE80211_CHAN_NOADHOC;
1731 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1732 nflags |= IEEE80211_CHAN_DFS;
1733 /* XXX apparently IBSS may still be marked */
1734 nflags |= IEEE80211_CHAN_NOADHOC;
1735 }
1736
1737 return nflags;
1738}
1739
1740static void
1741iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1742{
1743 struct ifnet *ifp = sc->sc_ifp;
1744 struct ieee80211com *ic = ifp->if_l2com;
1745 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1746 const struct iwn_chan_band *band = &iwn_bands[n];
1747 struct ieee80211_channel *c;
1748 int i, chan, nflags;
1749
1750 for (i = 0; i < band->nchan; i++) {
1751 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1752 DPRINTF(sc, IWN_DEBUG_RESET,
1753 "skip chan %d flags 0x%x maxpwr %d\n",
1754 band->chan[i], channels[i].flags,
1755 channels[i].maxpwr);
1756 continue;
1757 }
1758 chan = band->chan[i];
1759 nflags = iwn_eeprom_channel_flags(&channels[i]);
1760
1761 DPRINTF(sc, IWN_DEBUG_RESET,
1762 "add chan %d flags 0x%x maxpwr %d\n",
1763 chan, channels[i].flags, channels[i].maxpwr);
1764
1765 c = &ic->ic_channels[ic->ic_nchans++];
1766 c->ic_ieee = chan;
1767 c->ic_maxregpower = channels[i].maxpwr;
1768 c->ic_maxpower = 2*c->ic_maxregpower;
1769
1770 /* Save maximum allowed TX power for this channel. */
1771 sc->maxpwr[chan] = channels[i].maxpwr;
1772
1773 if (n == 0) { /* 2GHz band */
1774 c->ic_freq = ieee80211_ieee2mhz(chan,
1775 IEEE80211_CHAN_G);
1776
1777 /* G =>'s B is supported */
1778 c->ic_flags = IEEE80211_CHAN_B | nflags;
1779
1780 c = &ic->ic_channels[ic->ic_nchans++];
1781 c[0] = c[-1];
1782 c->ic_flags = IEEE80211_CHAN_G | nflags;
1783 } else { /* 5GHz band */
1784 c->ic_freq = ieee80211_ieee2mhz(chan,
1785 IEEE80211_CHAN_A);
1786 c->ic_flags = IEEE80211_CHAN_A | nflags;
1787 sc->sc_flags |= IWN_FLAG_HAS_5GHZ;
1788 }
1789#if 0 /* HT */
1790 /* XXX no constraints on using HT20 */
1791 /* add HT20, HT40 added separately */
1792 c = &ic->ic_channels[ic->ic_nchans++];
1793 c[0] = c[-1];
1794 c->ic_flags |= IEEE80211_CHAN_HT20;
1795 /* XXX NARROW =>'s 1/2 and 1/4 width? */
1796#endif
1797 }
1798}
1799
1800#if 0 /* HT */
1801static void
1802iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1803{
1804 struct ifnet *ifp = sc->sc_ifp;
1805 struct ieee80211com *ic = ifp->if_l2com;
1806 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1807 const struct iwn_chan_band *band = &iwn_bands[n];
1808 struct ieee80211_channel *c, *cent, *extc;
1809 int i;
1810
1811 for (i = 0; i < band->nchan; i++) {
1812 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID) ||
1813 !(channels[i].flags & IWN_EEPROM_CHAN_WIDE)) {
1814 DPRINTF(sc, IWN_DEBUG_RESET,
1815 "skip chan %d flags 0x%x maxpwr %d\n",
1816 band->chan[i], channels[i].flags,
1817 channels[i].maxpwr);
1818 continue;
1819 }
1820 /*
1821 * Each entry defines an HT40 channel pair; find the
1822 * center channel, then the extension channel above.
1823 */
1824 cent = ieee80211_find_channel_byieee(ic, band->chan[i],
1825 band->flags & ~IEEE80211_CHAN_HT);
1826 if (cent == NULL) { /* XXX shouldn't happen */
1827 device_printf(sc->sc_dev,
1828 "%s: no entry for channel %d\n",
1829 __func__, band->chan[i]);
1830 continue;
1831 }
1832 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1833 band->flags & ~IEEE80211_CHAN_HT);
1834 if (extc == NULL) {
1835 DPRINTF(sc, IWN_DEBUG_RESET,
1836 "skip chan %d, extension channel not found\n",
1837 band->chan[i]);
1838 continue;
1839 }
1840
1841 DPRINTF(sc, IWN_DEBUG_RESET,
1842 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1843 band->chan[i], channels[i].flags, channels[i].maxpwr);
1844
1845 c = &ic->ic_channels[ic->ic_nchans++];
1846 c[0] = cent[0];
1847 c->ic_extieee = extc->ic_ieee;
1848 c->ic_flags &= ~IEEE80211_CHAN_HT;
1849 c->ic_flags |= IEEE80211_CHAN_HT40U;
1850 c = &ic->ic_channels[ic->ic_nchans++];
1851 c[0] = extc[0];
1852 c->ic_extieee = cent->ic_ieee;
1853 c->ic_flags &= ~IEEE80211_CHAN_HT;
1854 c->ic_flags |= IEEE80211_CHAN_HT40D;
1855 }
1856}
1857#endif
1858
1859static void
1860iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1861{
1862 struct ifnet *ifp = sc->sc_ifp;
1863 struct ieee80211com *ic = ifp->if_l2com;
1864
1865 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1866 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1867
1868 if (n < 5)
1869 iwn_read_eeprom_band(sc, n);
1870#if 0 /* HT */
1871 else
1872 iwn_read_eeprom_ht40(sc, n);
1873#endif
1874 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1875}
1876
1877#define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
1878
1879static void
1880iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
1881{
1882 struct iwn_eeprom_enhinfo enhinfo[35];
1883 uint16_t val, base;
1884 int8_t maxpwr;
1885 int i;
1886
1887 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1888 base = le16toh(val);
1889 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
1890 enhinfo, sizeof enhinfo);
1891
1892 memset(sc->enh_maxpwr, 0, sizeof sc->enh_maxpwr);
1893 for (i = 0; i < nitems(enhinfo); i++) {
1894 if (enhinfo[i].chan == 0 || enhinfo[i].reserved != 0)
1895 continue; /* Skip invalid entries. */
1896
1897 maxpwr = 0;
1898 if (sc->txchainmask & IWN_ANT_A)
1899 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
1900 if (sc->txchainmask & IWN_ANT_B)
1901 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
1902 if (sc->txchainmask & IWN_ANT_C)
1903 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
1904 if (sc->ntxchains == 2)
1905 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
1906 else if (sc->ntxchains == 3)
1907 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
1908 maxpwr /= 2; /* Convert half-dBm to dBm. */
1909
1910 DPRINTF(sc, IWN_DEBUG_RESET, "enhinfo %d, maxpwr=%d\n", i,
1911 maxpwr);
1912 sc->enh_maxpwr[i] = maxpwr;
1913 }
1914}
1915
1916static struct ieee80211_node *
1917iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
1918{
3db796ac 1919 return kmalloc(sizeof (struct iwn_node), M_80211_NODE,M_INTWAIT | M_ZERO);
ffd7c74a
JT		 1920}
1921
1922static void
1923iwn_newassoc(struct ieee80211_node *ni, int isnew)
1924{
1925 /* XXX move */
3db796ac
JT		 1926 //if (!isnew) {
1927 ieee80211_ratectl_node_deinit(ni);
1928 //}
1929
ffd7c74a
JT		 1930 ieee80211_ratectl_node_init(ni);
1931}
1932
1933static int
1934iwn_media_change(struct ifnet *ifp)
1935{
1936 int error = ieee80211_media_change(ifp);
1937 /* NB: only the fixed rate can change and that doesn't need a reset */
1938 return (error == ENETRESET ? 0 : error);
1939}
1940
1941static int
1942iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1943{
1944 struct iwn_vap *ivp = IWN_VAP(vap);
1945 struct ieee80211com *ic = vap->iv_ic;
1946 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1947 int error;
1948
1949 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1950 ieee80211_state_name[vap->iv_state],
1951 ieee80211_state_name[nstate]);
1952
1953 IEEE80211_UNLOCK(ic);
1954 IWN_LOCK(sc);
1955 callout_stop(&sc->sc_timer_to);
1956
1957 if (nstate == IEEE80211_S_AUTH && vap->iv_state != IEEE80211_S_AUTH) {
1958 /* !AUTH -> AUTH requires adapter config */
1959 /* Reset state to handle reassociations correctly. */
1960 sc->rxon.associd = 0;
1961 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
1962 iwn_calib_reset(sc);
1963 error = iwn_auth(sc, vap);
1964 }
1965 if (nstate == IEEE80211_S_RUN && vap->iv_state != IEEE80211_S_RUN) {
1966 /*
1967 * !RUN -> RUN requires setting the association id
1968 * which is done with a firmware cmd. We also defer
1969 * starting the timers until that work is done.
1970 */
1971 error = iwn_run(sc, vap);
1972 }
1973 if (nstate == IEEE80211_S_RUN) {
1974 /*
1975 * RUN -> RUN transition; just restart the timers.
1976 */
1977 iwn_calib_reset(sc);
1978 }
1979 IWN_UNLOCK(sc);
1980 IEEE80211_LOCK(ic);
1981 return ivp->iv_newstate(vap, nstate, arg);
1982}
1983
1984/*
1985 * Process an RX_PHY firmware notification. This is usually immediately
1986 * followed by an MPDU_RX_DONE notification.
1987 */
1988static void
1989iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
1990 struct iwn_rx_data *data)
1991{
1992 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
1993
1994 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
1995 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
1996
1997 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
1998 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
1999 sc->last_rx_valid = 1;
2000}
2001
2002static void
2003iwn_timer_timeout(void *arg)
2004{
2005 struct iwn_softc *sc = arg;
2006 uint32_t flags = 0;
2007
2008 IWN_LOCK_ASSERT(sc);
2009
2010 if (sc->calib_cnt && --sc->calib_cnt == 0) {
2011 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2012 "send statistics request");
2013 (void) iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2014 sizeof flags, 1);
2015 sc->calib_cnt = 60; /* do calibration every 60s */
2016 }
2017 iwn_watchdog(sc); /* NB: piggyback tx watchdog */
2018 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
2019}
2020
2021static void
2022iwn_calib_reset(struct iwn_softc *sc)
2023{
2024 callout_reset(&sc->sc_timer_to, hz, iwn_timer_timeout, sc);
2025 sc->calib_cnt = 60; /* do calibration every 60s */
2026}
2027
2028/*
2029 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2030 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2031 */
2032static void
2033iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2034 struct iwn_rx_data *data)
2035{
2036 const struct iwn_hal *hal = sc->sc_hal;
2037 struct ifnet *ifp = sc->sc_ifp;
2038 struct ieee80211com *ic = ifp->if_l2com;
2039 struct iwn_rx_ring *ring = &sc->rxq;
2040 struct ieee80211_frame *wh;
2041 struct ieee80211_node *ni;
2042 struct mbuf *m, *m1;
2043 struct iwn_rx_stat *stat;
2044 caddr_t head;
2045 bus_addr_t paddr;
2046 uint32_t flags;
2047 int error, len, rssi, nf;
2048
2049 if (desc->type == IWN_MPDU_RX_DONE) {
2050 /* Check for prior RX_PHY notification. */
2051 if (!sc->last_rx_valid) {
2052 DPRINTF(sc, IWN_DEBUG_ANY,
2053 "%s: missing RX_PHY\n", __func__);
2054 ifp->if_ierrors++;
2055 return;
2056 }
2057 sc->last_rx_valid = 0;
2058 stat = &sc->last_rx_stat;
2059 } else
2060 stat = (struct iwn_rx_stat *)(desc + 1);
2061
2062 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2063
2064 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2065 device_printf(sc->sc_dev,
2066 "%s: invalid rx statistic header, len %d\n",
2067 __func__, stat->cfg_phy_len);
2068 ifp->if_ierrors++;
2069 return;
2070 }
2071 if (desc->type == IWN_MPDU_RX_DONE) {
2072 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2073 head = (caddr_t)(mpdu + 1);
2074 len = le16toh(mpdu->len);
2075 } else {
2076 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2077 len = le16toh(stat->len);
2078 }
2079
2080 flags = le32toh(*(uint32_t *)(head + len));
2081
2082 /* Discard frames with a bad FCS early. */
2083 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2084 DPRINTF(sc, IWN_DEBUG_RECV, "%s: rx flags error %x\n",
2085 __func__, flags);
2086 ifp->if_ierrors++;
2087 return;
2088 }
2089 /* Discard frames that are too short. */
2090 if (len < sizeof (*wh)) {
2091 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2092 __func__, len);
2093 ifp->if_ierrors++;
2094 return;
2095 }
2096
2097 /* XXX don't need mbuf, just dma buffer */
3db796ac 2098 m1 = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT		 2099 if (m1 == NULL) {
2100 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2101 __func__);
2102 ifp->if_ierrors++;
2103 return;
2104 }
2105 bus_dmamap_unload(ring->data_dmat, data->map);
2106
2107 error = bus_dmamap_load(ring->data_dmat, data->map,
3db796ac 2108 mtod(m1, caddr_t), MCLBYTES,
ffd7c74a
JT		 2109 iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2110 if (error != 0 && error != EFBIG) {
2111 device_printf(sc->sc_dev,
2112 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2113 m_freem(m1);
2114 ifp->if_ierrors++;
2115 return;
2116 }
2117
2118 m = data->m;
2119 data->m = m1;
2120 /* Update RX descriptor. */
2121 ring->desc[ring->cur] = htole32(paddr >> 8);
2122 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2123 BUS_DMASYNC_PREWRITE);
2124
2125 /* Finalize mbuf. */
2126 m->m_pkthdr.rcvif = ifp;
2127 m->m_data = head;
2128 m->m_pkthdr.len = m->m_len = len;
2129
2130 rssi = hal->get_rssi(sc, stat);
2131
2132 /* Grab a reference to the source node. */
2133 wh = mtod(m, struct ieee80211_frame *);
2134 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2135 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2136 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2137
2138 if (ieee80211_radiotap_active(ic)) {
2139 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2140
2141 tap->wr_tsft = htole64(stat->tstamp);
2142 tap->wr_flags = 0;
2143 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2144 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2145 switch (stat->rate) {
2146 /* CCK rates. */
2147 case 10: tap->wr_rate = 2; break;
2148 case 20: tap->wr_rate = 4; break;
2149 case 55: tap->wr_rate = 11; break;
2150 case 110: tap->wr_rate = 22; break;
2151 /* OFDM rates. */
2152 case 0xd: tap->wr_rate = 12; break;
2153 case 0xf: tap->wr_rate = 18; break;
2154 case 0x5: tap->wr_rate = 24; break;
2155 case 0x7: tap->wr_rate = 36; break;
2156 case 0x9: tap->wr_rate = 48; break;
2157 case 0xb: tap->wr_rate = 72; break;
2158 case 0x1: tap->wr_rate = 96; break;
2159 case 0x3: tap->wr_rate = 108; break;
2160 /* Unknown rate: should not happen. */
2161 default: tap->wr_rate = 0;
2162 }
2163 tap->wr_dbm_antsignal = rssi;
2164 tap->wr_dbm_antnoise = nf;
2165 }
2166
2167 IWN_UNLOCK(sc);
2168
2169 /* Send the frame to the 802.11 layer. */
2170 if (ni != NULL) {
2171 (void) ieee80211_input(ni, m, rssi - nf, nf);
2172 /* Node is no longer needed. */
2173 ieee80211_free_node(ni);
2174 } else
2175 (void) ieee80211_input_all(ic, m, rssi - nf, nf);
2176
2177 IWN_LOCK(sc);
2178}
2179
2180#if 0 /* HT */
2181/* Process an incoming Compressed BlockAck. */
2182static void
2183iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2184 struct iwn_rx_data *data)
2185{
2186 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2187 struct iwn_tx_ring *txq;
2188
2189 txq = &sc->txq[letoh16(ba->qid)];
2190 /* XXX TBD */
2191}
2192#endif
2193
2194/*
2195 * Process a CALIBRATION_RESULT notification sent by the initialization
2196 * firmware on response to a CMD_CALIB_CONFIG command (5000 only.)
2197 */
2198static void
2199iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2200 struct iwn_rx_data *data)
2201{
2202 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2203 int len, idx = -1;
2204
2205 /* Runtime firmware should not send such a notification. */
2206 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2207 return;
2208
2209 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2210 len = (le32toh(desc->len) & 0x3fff) - 4;
2211
2212 switch (calib->code) {
2213 case IWN5000_PHY_CALIB_DC:
2214 if (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2215 sc->hw_type == IWN_HW_REV_TYPE_6050)
2216 idx = 0;
2217 break;
2218 case IWN5000_PHY_CALIB_LO:
2219 idx = 1;
2220 break;
2221 case IWN5000_PHY_CALIB_TX_IQ:
2222 idx = 2;
2223 break;
2224 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2225 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2226 sc->hw_type != IWN_HW_REV_TYPE_5150)
2227 idx = 3;
2228 break;
2229 case IWN5000_PHY_CALIB_BASE_BAND:
2230 idx = 4;
2231 break;
2232 }
2233 if (idx == -1) /* Ignore other results. */
2234 return;
2235
2236 /* Save calibration result. */
2237 if (sc->calibcmd[idx].buf != NULL)
3db796ac
JT		 2238 kfree(sc->calibcmd[idx].buf, M_DEVBUF);
2239 sc->calibcmd[idx].buf = kmalloc(len, M_DEVBUF, M_INTWAIT);
ffd7c74a
JT		 2240 if (sc->calibcmd[idx].buf == NULL) {
2241 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2242 "not enough memory for calibration result %d\n",
2243 calib->code);
2244 return;
2245 }
2246 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2247 "saving calibration result code=%d len=%d\n", calib->code, len);
2248 sc->calibcmd[idx].len = len;
2249 memcpy(sc->calibcmd[idx].buf, calib, len);
2250}
2251
2252/*
2253 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2254 * The latter is sent by the firmware after each received beacon.
2255 */
2256static void
2257iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2258 struct iwn_rx_data *data)
2259{
2260 const struct iwn_hal *hal = sc->sc_hal;
2261 struct ifnet *ifp = sc->sc_ifp;
2262 struct ieee80211com *ic = ifp->if_l2com;
2263 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2264 struct iwn_calib_state *calib = &sc->calib;
2265 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2266 int temp;
2267
2268 /* Beacon stats are meaningful only when associated and not scanning. */
2269 if (vap->iv_state != IEEE80211_S_RUN ||
2270 (ic->ic_flags & IEEE80211_F_SCAN))
2271 return;
2272
2273 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2274 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: cmd %d\n", __func__, desc->type);
2275 iwn_calib_reset(sc); /* Reset TX power calibration timeout. */
2276
2277 /* Test if temperature has changed. */
2278 if (stats->general.temp != sc->rawtemp) {
2279 /* Convert "raw" temperature to degC. */
2280 sc->rawtemp = stats->general.temp;
2281 temp = hal->get_temperature(sc);
2282 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2283 __func__, temp);
2284
2285 /* Update TX power if need be (4965AGN only.) */
2286 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2287 iwn4965_power_calibration(sc, temp);
2288 }
2289
2290 if (desc->type != IWN_BEACON_STATISTICS)
2291 return; /* Reply to a statistics request. */
2292
2293 sc->noise = iwn_get_noise(&stats->rx.general);
2294 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2295
2296 /* Test that RSSI and noise are present in stats report. */
2297 if (le32toh(stats->rx.general.flags) != 1) {
2298 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2299 "received statistics without RSSI");
2300 return;
2301 }
2302
2303 if (calib->state == IWN_CALIB_STATE_ASSOC)
2304 iwn_collect_noise(sc, &stats->rx.general);
2305 else if (calib->state == IWN_CALIB_STATE_RUN)
2306 iwn_tune_sensitivity(sc, &stats->rx);
2307}
2308
2309/*
2310 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2311 * and 5000 adapters have different incompatible TX status formats.
2312 */
2313static void
2314iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2315 struct iwn_rx_data *data)
2316{
2317 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2318 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2319
2320 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2321 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2322 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2323 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2324 le32toh(stat->status));
2325
2326 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2327 iwn_tx_done(sc, desc, stat->ackfailcnt, le32toh(stat->status) & 0xff);
2328}
2329
2330static void
2331iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2332 struct iwn_rx_data *data)
2333{
2334 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2335 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2336
2337 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2338 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2339 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2340 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2341 le32toh(stat->status));
2342
2343#ifdef notyet
2344 /* Reset TX scheduler slot. */
2345 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2346#endif
2347
2348 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2349 iwn_tx_done(sc, desc, stat->ackfailcnt, le16toh(stat->status) & 0xff);
2350}
2351
2352/*
2353 * Adapter-independent backend for TX_DONE firmware notifications.
2354 */
2355static void
2356iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2357 uint8_t status)
2358{
2359 struct ifnet *ifp = sc->sc_ifp;
2360 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2361 struct iwn_tx_data *data = &ring->data[desc->idx];
2362 struct mbuf *m;
2363 struct ieee80211_node *ni;
2364 struct ieee80211vap *vap;
2365
2366 KASSERT(data->ni != NULL, ("no node"));
2367
2368 /* Unmap and free mbuf. */
2369 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2370 bus_dmamap_unload(ring->data_dmat, data->map);
2371 m = data->m, data->m = NULL;
2372 ni = data->ni, data->ni = NULL;
2373 vap = ni->ni_vap;
2374
2375 if (m->m_flags & M_TXCB) {
2376 /*
2377 * Channels marked for "radar" require traffic to be received
2378 * to unlock before we can transmit. Until traffic is seen
2379 * any attempt to transmit is returned immediately with status
2380 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2381 * happen on first authenticate after scanning. To workaround
2382 * this we ignore a failure of this sort in AUTH state so the
2383 * 802.11 layer will fall back to using a timeout to wait for
2384 * the AUTH reply. This allows the firmware time to see
2385 * traffic so a subsequent retry of AUTH succeeds. It's
2386 * unclear why the firmware does not maintain state for
2387 * channels recently visited as this would allow immediate
2388 * use of the channel after a scan (where we see traffic).
2389 */
2390 if (status == IWN_TX_FAIL_TX_LOCKED &&
2391 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2392 ieee80211_process_callback(ni, m, 0);
2393 else
2394 ieee80211_process_callback(ni, m,
2395 (status & IWN_TX_FAIL) != 0);
2396 }
2397
2398 /*
2399 * Update rate control statistics for the node.
2400 */
2401 if (status & 0x80) {
2402 ifp->if_oerrors++;
2403 ieee80211_ratectl_tx_complete(vap, ni,
2404 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2405 } else {
2406 ieee80211_ratectl_tx_complete(vap, ni,
2407 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2408 }
2409 m_freem(m);
2410 ieee80211_free_node(ni);
2411
2412 sc->sc_tx_timer = 0;
2413 if (--ring->queued < IWN_TX_RING_LOMARK) {
2414 sc->qfullmsk &= ~(1 << ring->qid);
2415 if (sc->qfullmsk == 0 &&
3db796ac
JT		 2416 (ifp->if_flags & IFF_OACTIVE)) {
2417 ifp->if_flags &= ~IFF_OACTIVE;
ffd7c74a
JT		 2418 iwn_start_locked(ifp);
2419 }
2420 }
2421}
2422
2423/*
2424 * Process a "command done" firmware notification. This is where we wakeup
2425 * processes waiting for a synchronous command completion.
2426 */
2427static void
2428iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2429{
2430 struct iwn_tx_ring *ring = &sc->txq[4];
2431 struct iwn_tx_data *data;
2432
2433 if ((desc->qid & 0xf) != 4)
2434 return; /* Not a command ack. */
2435
2436 data = &ring->data[desc->idx];
2437
2438 /* If the command was mapped in an mbuf, free it. */
2439 if (data->m != NULL) {
2440 bus_dmamap_unload(ring->data_dmat, data->map);
2441 m_freem(data->m);
2442 data->m = NULL;
2443 }
2444 wakeup(&ring->desc[desc->idx]);
2445}
2446
2447/*
2448 * Process an INT_FH_RX or INT_SW_RX interrupt.
2449 */
2450static void
2451iwn_notif_intr(struct iwn_softc *sc)
2452{
2453 struct ifnet *ifp = sc->sc_ifp;
2454 struct ieee80211com *ic = ifp->if_l2com;
2455 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2456 uint16_t hw;
2457
2458 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2459 BUS_DMASYNC_POSTREAD);
2460
2461 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2462 while (sc->rxq.cur != hw) {
2463 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2464 struct iwn_rx_desc *desc;
2465
2466 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2467 BUS_DMASYNC_POSTREAD);
2468 desc = mtod(data->m, struct iwn_rx_desc *);
2469
2470 DPRINTF(sc, IWN_DEBUG_RECV,
2471 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2472 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2473 desc->type, iwn_intr_str(desc->type),
2474 le16toh(desc->len));
2475
2476 if (!(desc->qid & 0x80)) /* Reply to a command. */
2477 iwn_cmd_done(sc, desc);
2478
2479 switch (desc->type) {
2480 case IWN_RX_PHY:
2481 iwn_rx_phy(sc, desc, data);
2482 break;
2483
2484 case IWN_RX_DONE: /* 4965AGN only. */
2485 case IWN_MPDU_RX_DONE:
2486 /* An 802.11 frame has been received. */
2487 iwn_rx_done(sc, desc, data);
2488 break;
2489
2490#if 0 /* HT */
2491 case IWN_RX_COMPRESSED_BA:
2492 /* A Compressed BlockAck has been received. */
2493 iwn_rx_compressed_ba(sc, desc, data);
2494 break;
2495#endif
2496
2497 case IWN_TX_DONE:
2498 /* An 802.11 frame has been transmitted. */
2499 sc->sc_hal->tx_done(sc, desc, data);
2500 break;
2501
2502 case IWN_RX_STATISTICS:
2503 case IWN_BEACON_STATISTICS:
2504 iwn_rx_statistics(sc, desc, data);
2505 break;
2506
2507 case IWN_BEACON_MISSED:
2508 {
2509 struct iwn_beacon_missed *miss =
2510 (struct iwn_beacon_missed *)(desc + 1);
2511 int misses;
2512
2513 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2514 BUS_DMASYNC_POSTREAD);
2515 misses = le32toh(miss->consecutive);
2516
2517 /* XXX not sure why we're notified w/ zero */
2518 if (misses == 0)
2519 break;
2520 DPRINTF(sc, IWN_DEBUG_STATE,
2521 "%s: beacons missed %d/%d\n", __func__,
2522 misses, le32toh(miss->total));
2523
2524 /*
2525 * If more than 5 consecutive beacons are missed,
2526 * reinitialize the sensitivity state machine.
2527 */
2528 if (vap->iv_state == IEEE80211_S_RUN && misses > 5)
2529 (void) iwn_init_sensitivity(sc);
2530 if (misses >= vap->iv_bmissthreshold) {
2531 IWN_UNLOCK(sc);
2532 ieee80211_beacon_miss(ic);
2533 IWN_LOCK(sc);
2534 }
2535 break;
2536 }
2537 case IWN_UC_READY:
2538 {
2539 struct iwn_ucode_info *uc =
2540 (struct iwn_ucode_info *)(desc + 1);
2541
2542 /* The microcontroller is ready. */
2543 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2544 BUS_DMASYNC_POSTREAD);
2545 DPRINTF(sc, IWN_DEBUG_RESET,
2546 "microcode alive notification version=%d.%d "
2547 "subtype=%x alive=%x\n", uc->major, uc->minor,
2548 uc->subtype, le32toh(uc->valid));
2549
2550 if (le32toh(uc->valid) != 1) {
2551 device_printf(sc->sc_dev,
2552 "microcontroller initialization failed");
2553 break;
2554 }
2555 if (uc->subtype == IWN_UCODE_INIT) {
2556 /* Save microcontroller report. */
2557 memcpy(&sc->ucode_info, uc, sizeof (*uc));
2558 }
2559 /* Save the address of the error log in SRAM. */
2560 sc->errptr = le32toh(uc->errptr);
2561 break;
2562 }
2563 case IWN_STATE_CHANGED:
2564 {
2565 uint32_t *status = (uint32_t *)(desc + 1);
2566
2567 /*
2568 * State change allows hardware switch change to be
2569 * noted. However, we handle this in iwn_intr as we
2570 * get both the enable/disble intr.
2571 */
2572 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2573 BUS_DMASYNC_POSTREAD);
2574 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
2575 le32toh(*status));
2576 break;
2577 }
2578 case IWN_START_SCAN:
2579 {
2580 struct iwn_start_scan *scan =
2581 (struct iwn_start_scan *)(desc + 1);
2582
2583 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2584 BUS_DMASYNC_POSTREAD);
2585 DPRINTF(sc, IWN_DEBUG_ANY,
2586 "%s: scanning channel %d status %x\n",
2587 __func__, scan->chan, le32toh(scan->status));
2588 break;
2589 }
2590 case IWN_STOP_SCAN:
2591 {
2592 struct iwn_stop_scan *scan =
2593 (struct iwn_stop_scan *)(desc + 1);
2594
2595 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2596 BUS_DMASYNC_POSTREAD);
2597 DPRINTF(sc, IWN_DEBUG_STATE,
2598 "scan finished nchan=%d status=%d chan=%d\n",
2599 scan->nchan, scan->status, scan->chan);
2600
2601 IWN_UNLOCK(sc);
2602 ieee80211_scan_next(vap);
2603 IWN_LOCK(sc);
2604 break;
2605 }
2606 case IWN5000_CALIBRATION_RESULT:
2607 iwn5000_rx_calib_results(sc, desc, data);
2608 break;
2609
2610 case IWN5000_CALIBRATION_DONE:
2611 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
2612 wakeup(sc);
2613 break;
2614 }
2615
2616 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
2617 }
2618
2619 /* Tell the firmware what we have processed. */
2620 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
2621 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
2622}
2623
2624/*
2625 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
2626 * from power-down sleep mode.
2627 */
2628static void
2629iwn_wakeup_intr(struct iwn_softc *sc)
2630{
2631 int qid;
2632
2633 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
2634 __func__);
2635
2636 /* Wakeup RX and TX rings. */
2637 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
2638 for (qid = 0; qid < sc->sc_hal->ntxqs; qid++) {
2639 struct iwn_tx_ring *ring = &sc->txq[qid];
2640 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
2641 }
2642}
2643
2644static void
2645iwn_rftoggle_intr(struct iwn_softc *sc)
2646{
2647 struct ifnet *ifp = sc->sc_ifp;
2648 struct ieee80211com *ic = ifp->if_l2com;
2649 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
2650
2651 IWN_LOCK_ASSERT(sc);
2652
2653 device_printf(sc->sc_dev, "RF switch: radio %s\n",
2654 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
2655 if (tmp & IWN_GP_CNTRL_RFKILL)
2656 ieee80211_runtask(ic, &sc->sc_radioon_task);
2657 else
2658 ieee80211_runtask(ic, &sc->sc_radiooff_task);
2659}
2660
2661/*
2662 * Dump the error log of the firmware when a firmware panic occurs. Although
2663 * we can't debug the firmware because it is neither open source nor free, it
2664 * can help us to identify certain classes of problems.
2665 */
2666static void
2667iwn_fatal_intr(struct iwn_softc *sc)
2668{
2669 const struct iwn_hal *hal = sc->sc_hal;
2670 struct iwn_fw_dump dump;
2671 int i;
2672
2673 IWN_LOCK_ASSERT(sc);
2674
2675 /* Force a complete recalibration on next init. */
2676 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
2677
2678 /* Check that the error log address is valid. */
2679 if (sc->errptr < IWN_FW_DATA_BASE ||
2680 sc->errptr + sizeof (dump) >
2681 IWN_FW_DATA_BASE + hal->fw_data_maxsz) {
3db796ac 2682 kprintf("%s: bad firmware error log address 0x%08x\n",
ffd7c74a
JT		 2683 __func__, sc->errptr);
2684 return;
2685 }
2686 if (iwn_nic_lock(sc) != 0) {
3db796ac 2687 kprintf("%s: could not read firmware error log\n",
ffd7c74a
JT		 2688 __func__);
2689 return;
2690 }
2691 /* Read firmware error log from SRAM. */
2692 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
2693 sizeof (dump) / sizeof (uint32_t));
2694 iwn_nic_unlock(sc);
2695
2696 if (dump.valid == 0) {
3db796ac 2697 kprintf("%s: firmware error log is empty\n",
ffd7c74a
JT		 2698 __func__);
2699 return;
2700 }
3db796ac
JT		 2701 kprintf("firmware error log:\n");
2702 kprintf(" error type = \"%s\" (0x%08X)\n",
ffd7c74a
JT		 2703 (dump.id < nitems(iwn_fw_errmsg)) ?
2704 iwn_fw_errmsg[dump.id] : "UNKNOWN",
2705 dump.id);
3db796ac
JT		 2706 kprintf(" program counter = 0x%08X\n", dump.pc);
2707 kprintf(" source line = 0x%08X\n", dump.src_line);
2708 kprintf(" error data = 0x%08X%08X\n",
ffd7c74a 2709 dump.error_data[0], dump.error_data[1]);
3db796ac 2710 kprintf(" branch link = 0x%08X%08X\n",
ffd7c74a 2711 dump.branch_link[0], dump.branch_link[1]);
3db796ac 2712 kprintf(" interrupt link = 0x%08X%08X\n",
ffd7c74a 2713 dump.interrupt_link[0], dump.interrupt_link[1]);
3db796ac 2714 kprintf(" time = %u\n", dump.time[0]);
ffd7c74a
JT		 2715
2716 /* Dump driver status (TX and RX rings) while we're here. */
3db796ac 2717 kprintf("driver status:\n");
ffd7c74a
JT		 2718 for (i = 0; i < hal->ntxqs; i++) {
2719 struct iwn_tx_ring *ring = &sc->txq[i];
3db796ac 2720 kprintf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
ffd7c74a
JT		 2721 i, ring->qid, ring->cur, ring->queued);
2722 }
3db796ac 2723 kprintf(" rx ring: cur=%d\n", sc->rxq.cur);
ffd7c74a
JT		 2724}
2725
2726static void
2727iwn_intr(void *arg)
2728{
2729 struct iwn_softc *sc = arg;
2730 struct ifnet *ifp = sc->sc_ifp;
2731 uint32_t r1, r2, tmp;
2732
ffd7c74a
JT		 2733 /* Disable interrupts. */
2734 IWN_WRITE(sc, IWN_INT_MASK, 0);
2735
2736 /* Read interrupts from ICT (fast) or from registers (slow). */
2737 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2738 tmp = 0;
2739 while (sc->ict[sc->ict_cur] != 0) {
2740 tmp |= sc->ict[sc->ict_cur];
2741 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
2742 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
2743 }
2744 tmp = le32toh(tmp);
2745 if (tmp == 0xffffffff) /* Shouldn't happen. */
2746 tmp = 0;
2747 else if (tmp & 0xc0000) /* Workaround a HW bug. */
2748 tmp |= 0x8000;
2749 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
2750 r2 = 0; /* Unused. */
2751 } else {
2752 r1 = IWN_READ(sc, IWN_INT);
2753 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
2754 return; /* Hardware gone! */
2755 r2 = IWN_READ(sc, IWN_FH_INT);
2756 }
2757
2758 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
2759
2760 if (r1 == 0 && r2 == 0)
2761 goto done; /* Interrupt not for us. */
2762
2763 /* Acknowledge interrupts. */
2764 IWN_WRITE(sc, IWN_INT, r1);
2765 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
2766 IWN_WRITE(sc, IWN_FH_INT, r2);
2767
2768 if (r1 & IWN_INT_RF_TOGGLED) {
2769 iwn_rftoggle_intr(sc);
2770 goto done;
2771 }
2772 if (r1 & IWN_INT_CT_REACHED) {
2773 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
2774 __func__);
2775 }
2776 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
2777 iwn_fatal_intr(sc);
2778 ifp->if_flags &= ~IFF_UP;
2779 iwn_stop_locked(sc);
2780 goto done;
2781 }
2782 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
2783 (r2 & IWN_FH_INT_RX)) {
2784 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
2785 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
2786 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
2787 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2788 IWN_INT_PERIODIC_DIS);
2789 iwn_notif_intr(sc);
2790 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
2791 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
2792 IWN_INT_PERIODIC_ENA);
2793 }
2794 } else
2795 iwn_notif_intr(sc);
2796 }
2797
2798 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
2799 if (sc->sc_flags & IWN_FLAG_USE_ICT)
2800 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
2801 wakeup(sc); /* FH DMA transfer completed. */
2802 }
2803
2804 if (r1 & IWN_INT_ALIVE)
2805 wakeup(sc); /* Firmware is alive. */
2806
2807 if (r1 & IWN_INT_WAKEUP)
2808 iwn_wakeup_intr(sc);
2809
2810done:
2811 /* Re-enable interrupts. */
2812 if (ifp->if_flags & IFF_UP)
2813 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
2814
ffd7c74a
JT		 2815}
2816
2817/*
2818 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
2819 * 5000 adapters use a slightly different format.)
2820 */
2821static void
2822iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2823 uint16_t len)
2824{
2825 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
2826
2827 *w = htole16(len + 8);
2828 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2829 BUS_DMASYNC_PREWRITE);
2830 if (idx < IWN_SCHED_WINSZ) {
2831 *(w + IWN_TX_RING_COUNT) = *w;
2832 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2833 BUS_DMASYNC_PREWRITE);
2834 }
2835}
2836
2837static void
2838iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
2839 uint16_t len)
2840{
2841 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2842
2843 *w = htole16(id << 12 | (len + 8));
2844
2845 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2846 BUS_DMASYNC_PREWRITE);
2847 if (idx < IWN_SCHED_WINSZ) {
2848 *(w + IWN_TX_RING_COUNT) = *w;
2849 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2850 BUS_DMASYNC_PREWRITE);
2851 }
2852}
2853
2854#ifdef notyet
2855static void
2856iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
2857{
2858 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
2859
2860 *w = (*w & htole16(0xf000)) | htole16(1);
2861 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2862 BUS_DMASYNC_PREWRITE);
2863 if (idx < IWN_SCHED_WINSZ) {
2864 *(w + IWN_TX_RING_COUNT) = *w;
2865 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
2866 BUS_DMASYNC_PREWRITE);
2867 }
2868}
2869#endif
2870
2871static uint8_t
2872iwn_plcp_signal(int rate) {
2873 int i;
2874
2875 for (i = 0; i < IWN_RIDX_MAX + 1; i++) {
2876 if (rate == iwn_rates[i].rate)
2877 return i;
2878 }
2879
2880 return 0;
2881}
2882
2883static int
2884iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
2885 struct iwn_tx_ring *ring)
2886{
2887 const struct iwn_hal *hal = sc->sc_hal;
2888 const struct ieee80211_txparam *tp;
2889 const struct iwn_rate *rinfo;
2890 struct ieee80211vap *vap = ni->ni_vap;
2891 struct ieee80211com *ic = ni->ni_ic;
2892 struct iwn_node *wn = (void *)ni;
2893 struct iwn_tx_desc *desc;
2894 struct iwn_tx_data *data;
2895 struct iwn_tx_cmd *cmd;
2896 struct iwn_cmd_data *tx;
2897 struct ieee80211_frame *wh;
2898 struct ieee80211_key *k = NULL;
2899 struct mbuf *mnew;
2900 bus_dma_segment_t segs[IWN_MAX_SCATTER];
2901 uint32_t flags;
2902 u_int hdrlen;
2903 int totlen, error, pad, nsegs = 0, i, rate;
2904 uint8_t ridx, type, txant;
2905
2906 IWN_LOCK_ASSERT(sc);
2907
2908 wh = mtod(m, struct ieee80211_frame *);
2909 hdrlen = ieee80211_anyhdrsize(wh);
2910 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2911
2912 desc = &ring->desc[ring->cur];
2913 data = &ring->data[ring->cur];
2914
2915 /* Choose a TX rate index. */
2916 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
2917 if (type == IEEE80211_FC0_TYPE_MGT)
2918 rate = tp->mgmtrate;
2919 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
2920 rate = tp->mcastrate;
2921 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
2922 rate = tp->ucastrate;
2923 else {
2924 /* XXX pass pktlen */
3db796ac
JT		 2925 ieee80211_ratectl_rate(ni, NULL, 0);
2926
ffd7c74a
JT		 2927 rate = ni->ni_txrate;
2928 }
2929 ridx = iwn_plcp_signal(rate);
2930 rinfo = &iwn_rates[ridx];
2931
2932 /* Encrypt the frame if need be. */
2933 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2934 k = ieee80211_crypto_encap(ni, m);
2935 if (k == NULL) {
2936 m_freem(m);
2937 return ENOBUFS;
2938 }
2939 /* Packet header may have moved, reset our local pointer. */
2940 wh = mtod(m, struct ieee80211_frame *);
2941 }
2942 totlen = m->m_pkthdr.len;
2943
2944 if (ieee80211_radiotap_active_vap(vap)) {
2945 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
2946
2947 tap->wt_flags = 0;
2948 tap->wt_rate = rinfo->rate;
2949 if (k != NULL)
2950 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
2951
2952 ieee80211_radiotap_tx(vap, m);
2953 }
2954
2955 /* Prepare TX firmware command. */
2956 cmd = &ring->cmd[ring->cur];
2957 cmd->code = IWN_CMD_TX_DATA;
2958 cmd->flags = 0;
2959 cmd->qid = ring->qid;
2960 cmd->idx = ring->cur;
2961
2962 tx = (struct iwn_cmd_data *)cmd->data;
2963 /* NB: No need to clear tx, all fields are reinitialized here. */
2964 tx->scratch = 0; /* clear "scratch" area */
2965
2966 flags = 0;
2967 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
2968 flags |= IWN_TX_NEED_ACK;
2969 if ((wh->i_fc[0] &
2970 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
2971 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
2972 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
2973
2974 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
2975 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
2976
2977 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
2978 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2979 /* NB: Group frames are sent using CCK in 802.11b/g. */
2980 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
2981 flags |= IWN_TX_NEED_RTS;
2982 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
2983 ridx >= IWN_RIDX_OFDM6) {
2984 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
2985 flags |= IWN_TX_NEED_CTS;
2986 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
2987 flags |= IWN_TX_NEED_RTS;
2988 }
2989 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
2990 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
2991 /* 5000 autoselects RTS/CTS or CTS-to-self. */
2992 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
2993 flags |= IWN_TX_NEED_PROTECTION;
2994 } else
2995 flags |= IWN_TX_FULL_TXOP;
2996 }
2997 }
2998
2999 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3000 type != IEEE80211_FC0_TYPE_DATA)
3001 tx->id = hal->broadcast_id;
3002 else
3003 tx->id = wn->id;
3004
3005 if (type == IEEE80211_FC0_TYPE_MGT) {
3006 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3007
3008 /* Tell HW to set timestamp in probe responses. */
3009 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3010 flags |= IWN_TX_INSERT_TSTAMP;
3011
3012 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3013 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3014 tx->timeout = htole16(3);
3015 else
3016 tx->timeout = htole16(2);
3017 } else
3018 tx->timeout = htole16(0);
3019
3020 if (hdrlen & 3) {
3021 /* First segment length must be a multiple of 4. */
3022 flags |= IWN_TX_NEED_PADDING;
3023 pad = 4 - (hdrlen & 3);
3024 } else
3025 pad = 0;
3026
3027 tx->len = htole16(totlen);
3028 tx->tid = 0;
3029 tx->rts_ntries = 60;
3030 tx->data_ntries = 15;
3031 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3032 tx->plcp = rinfo->plcp;
3033 tx->rflags = rinfo->flags;
3034 if (tx->id == hal->broadcast_id) {
3035 /* Group or management frame. */
3036 tx->linkq = 0;
3037 /* XXX Alternate between antenna A and B? */
3038 txant = IWN_LSB(sc->txchainmask);
3039 tx->rflags |= IWN_RFLAG_ANT(txant);
3040 } else {
3041 tx->linkq = 0;
3042 flags |= IWN_TX_LINKQ; /* enable MRR */
3043 }
3044
3045 /* Set physical address of "scratch area". */
3046 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3047 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3048
3049 /* Copy 802.11 header in TX command. */
3050 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3051
3052 /* Trim 802.11 header. */
3053 m_adj(m, hdrlen);
3054 tx->security = 0;
3055 tx->flags = htole32(flags);
3056
3057 if (m->m_len > 0) {
3db796ac
JT		 3058 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3059 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT		 3060 if (error == EFBIG) {
3061 /* too many fragments, linearize */
3db796ac 3062 mnew = m_defrag(m, MB_DONTWAIT);
ffd7c74a
JT		 3063 if (mnew == NULL) {
3064 device_printf(sc->sc_dev,
3065 "%s: could not defrag mbuf\n", __func__);
3066 m_freem(m);
3067 return ENOBUFS;
3068 }
3069 m = mnew;
3db796ac
JT		 3070 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3071 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT		 3072 }
3073 if (error != 0) {
3074 device_printf(sc->sc_dev,
3db796ac 3075 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
ffd7c74a
JT		 3076 __func__, error);
3077 m_freem(m);
3078 return error;
3079 }
3080 }
3081
3082 data->m = m;
3083 data->ni = ni;
3084
3085 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3086 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3087
3088 /* Fill TX descriptor. */
3089 desc->nsegs = 1 + nsegs;
3090 /* First DMA segment is used by the TX command. */
3091 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3092 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3093 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3094 /* Other DMA segments are for data payload. */
3095 for (i = 1; i <= nsegs; i++) {
3096 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3097 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3098 segs[i - 1].ds_len << 4);
3099 }
3100
3101 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3102 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3103 BUS_DMASYNC_PREWRITE);
3104 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3105 BUS_DMASYNC_PREWRITE);
3106
3107#ifdef notyet
3108 /* Update TX scheduler. */
3109 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3110#endif
3111
3112 /* Kick TX ring. */
3113 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3114 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3115
3116 /* Mark TX ring as full if we reach a certain threshold. */
3117 if (++ring->queued > IWN_TX_RING_HIMARK)
3118 sc->qfullmsk |= 1 << ring->qid;
3119
3120 return 0;
3121}
3122
3123static int
3124iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3125 struct ieee80211_node *ni, struct iwn_tx_ring *ring,
3126 const struct ieee80211_bpf_params *params)
3127{
3128 const struct iwn_hal *hal = sc->sc_hal;
3129 const struct iwn_rate *rinfo;
3130 struct ifnet *ifp = sc->sc_ifp;
3131 struct ieee80211vap *vap = ni->ni_vap;
3132 struct ieee80211com *ic = ifp->if_l2com;
3133 struct iwn_tx_cmd *cmd;
3134 struct iwn_cmd_data *tx;
3135 struct ieee80211_frame *wh;
3136 struct iwn_tx_desc *desc;
3137 struct iwn_tx_data *data;
3138 struct mbuf *mnew;
3139 bus_addr_t paddr;
3140 bus_dma_segment_t segs[IWN_MAX_SCATTER];
3141 uint32_t flags;
3142 u_int hdrlen;
3143 int totlen, error, pad, nsegs = 0, i, rate;
3144 uint8_t ridx, type, txant;
3145
3146 IWN_LOCK_ASSERT(sc);
3147
3148 wh = mtod(m, struct ieee80211_frame *);
3149 hdrlen = ieee80211_anyhdrsize(wh);
3150 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3151
3152 desc = &ring->desc[ring->cur];
3153 data = &ring->data[ring->cur];
3154
3155 /* Choose a TX rate index. */
3156 rate = params->ibp_rate0;
3157 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3158 /* XXX fall back to mcast/mgmt rate? */
3159 m_freem(m);
3160 return EINVAL;
3161 }
3162 ridx = iwn_plcp_signal(rate);
3163 rinfo = &iwn_rates[ridx];
3164
3165 totlen = m->m_pkthdr.len;
3166
3167 /* Prepare TX firmware command. */
3168 cmd = &ring->cmd[ring->cur];
3169 cmd->code = IWN_CMD_TX_DATA;
3170 cmd->flags = 0;
3171 cmd->qid = ring->qid;
3172 cmd->idx = ring->cur;
3173
3174 tx = (struct iwn_cmd_data *)cmd->data;
3175 /* NB: No need to clear tx, all fields are reinitialized here. */
3176 tx->scratch = 0; /* clear "scratch" area */
3177
3178 flags = 0;
3179 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3180 flags |= IWN_TX_NEED_ACK;
3181 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3182 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3183 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3184 flags &= ~IWN_TX_NEED_RTS;
3185 flags |= IWN_TX_NEED_PROTECTION;
3186 } else
3187 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3188 }
3189 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3190 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3191 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3192 flags &= ~IWN_TX_NEED_CTS;
3193 flags |= IWN_TX_NEED_PROTECTION;
3194 } else
3195 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3196 }
3197 if (type == IEEE80211_FC0_TYPE_MGT) {
3198 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3199
3200 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3201 flags |= IWN_TX_INSERT_TSTAMP;
3202
3203 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3204 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3205 tx->timeout = htole16(3);
3206 else
3207 tx->timeout = htole16(2);
3208 } else
3209 tx->timeout = htole16(0);
3210
3211 if (hdrlen & 3) {
3212 /* First segment length must be a multiple of 4. */
3213 flags |= IWN_TX_NEED_PADDING;
3214 pad = 4 - (hdrlen & 3);
3215 } else
3216 pad = 0;
3217
3218 if (ieee80211_radiotap_active_vap(vap)) {
3219 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3220
3221 tap->wt_flags = 0;
3222 tap->wt_rate = rate;
3223
3224 ieee80211_radiotap_tx(vap, m);
3225 }
3226
3227 tx->len = htole16(totlen);
3228 tx->tid = 0;
3229 tx->id = hal->broadcast_id;
3230 tx->rts_ntries = params->ibp_try1;
3231 tx->data_ntries = params->ibp_try0;
3232 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3233 tx->plcp = rinfo->plcp;
3234 tx->rflags = rinfo->flags;
3235 /* Group or management frame. */
3236 tx->linkq = 0;
3237 txant = IWN_LSB(sc->txchainmask);
3238 tx->rflags |= IWN_RFLAG_ANT(txant);
3239 /* Set physical address of "scratch area". */
3240 paddr = ring->cmd_dma.paddr + ring->cur * sizeof (struct iwn_tx_cmd);
3241 tx->loaddr = htole32(IWN_LOADDR(paddr));
3242 tx->hiaddr = IWN_HIADDR(paddr);
3243
3244 /* Copy 802.11 header in TX command. */
3245 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3246
3247 /* Trim 802.11 header. */
3248 m_adj(m, hdrlen);
3249 tx->security = 0;
3250 tx->flags = htole32(flags);
3251
3252 if (m->m_len > 0) {
3db796ac
JT		 3253 error = bus_dmamap_load_mbuf_segment(ring->data_dmat, data->map,
3254 m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT		 3255 if (error == EFBIG) {
3256 /* Too many fragments, linearize. */
3db796ac 3257 mnew = m_defrag(m, MB_DONTWAIT);
ffd7c74a
JT		 3258 if (mnew == NULL) {
3259 device_printf(sc->sc_dev,
3260 "%s: could not defrag mbuf\n", __func__);
3261 m_freem(m);
3262 return ENOBUFS;
3263 }
3264 m = mnew;
3db796ac
JT		 3265 error = bus_dmamap_load_mbuf_segment(ring->data_dmat,
3266 data->map, m, segs, IWN_MAX_SCATTER - 1, &nsegs, BUS_DMA_NOWAIT);
ffd7c74a
JT		 3267 }
3268 if (error != 0) {
3269 device_printf(sc->sc_dev,
3db796ac 3270 "%s: bus_dmamap_load_mbuf_segment failed, error %d\n",
ffd7c74a
JT		 3271 __func__, error);
3272 m_freem(m);
3273 return error;
3274 }
3275 }
3276
3277 data->m = m;
3278 data->ni = ni;
3279
3280 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3281 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3282
3283 /* Fill TX descriptor. */
3284 desc->nsegs = 1 + nsegs;
3285 /* First DMA segment is used by the TX command. */
3286 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3287 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3288 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3289 /* Other DMA segments are for data payload. */
3290 for (i = 1; i <= nsegs; i++) {
3291 desc->segs[i].addr = htole32(IWN_LOADDR(segs[i - 1].ds_addr));
3292 desc->segs[i].len = htole16(IWN_HIADDR(segs[i - 1].ds_addr) |
3293 segs[i - 1].ds_len << 4);
3294 }
3295
3296 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3297 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3298 BUS_DMASYNC_PREWRITE);
3299 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3300 BUS_DMASYNC_PREWRITE);
3301
3302#ifdef notyet
3303 /* Update TX scheduler. */
3304 hal->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3305#endif
3306
3307 /* Kick TX ring. */
3308 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3309 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3310
3311 /* Mark TX ring as full if we reach a certain threshold. */
3312 if (++ring->queued > IWN_TX_RING_HIMARK)
3313 sc->qfullmsk |= 1 << ring->qid;
3314
3315 return 0;
3316}
3317
3318static int
3319iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3320 const struct ieee80211_bpf_params *params)
3321{
3322 struct ieee80211com *ic = ni->ni_ic;
3323 struct ifnet *ifp = ic->ic_ifp;
3324 struct iwn_softc *sc = ifp->if_softc;
3325 struct iwn_tx_ring *txq;
3326 int error = 0;
3327
3db796ac 3328 if ((ifp->if_flags & IFF_RUNNING) == 0) {
ffd7c74a
JT		 3329 ieee80211_free_node(ni);
3330 m_freem(m);
3331 return ENETDOWN;
3332 }
3333
3334 IWN_LOCK(sc);
3335 if (params == NULL)
3336 txq = &sc->txq[M_WME_GETAC(m)];
3337 else
3338 txq = &sc->txq[params->ibp_pri & 3];
3339
3340 if (params == NULL) {
3341 /*
3342 * Legacy path; interpret frame contents to decide
3343 * precisely how to send the frame.
3344 */
3345 error = iwn_tx_data(sc, m, ni, txq);
3346 } else {
3347 /*
3348 * Caller supplied explicit parameters to use in
3349 * sending the frame.
3350 */
3351 error = iwn_tx_data_raw(sc, m, ni, txq, params);
3352 }
3353 if (error != 0) {
3354 /* NB: m is reclaimed on tx failure */
3355 ieee80211_free_node(ni);
3356 ifp->if_oerrors++;
3357 }
3358 IWN_UNLOCK(sc);
3359 return error;
3360}
3361
3362static void
3363iwn_start(struct ifnet *ifp)
3364{
3365 struct iwn_softc *sc = ifp->if_softc;
3366
3db796ac
JT		 3367 IWN_LOCK_ASSERT(sc);
3368
ffd7c74a 3369 iwn_start_locked(ifp);
ffd7c74a
JT		 3370}
3371
3372static void
3373iwn_start_locked(struct ifnet *ifp)
3374{
3375 struct iwn_softc *sc = ifp->if_softc;
3376 struct ieee80211_node *ni;
3377 struct iwn_tx_ring *txq;
3378 struct mbuf *m;
3379 int pri;
3380
3381 IWN_LOCK_ASSERT(sc);
3382
3383 for (;;) {
3384 if (sc->qfullmsk != 0) {
3db796ac 3385 ifp->if_flags |= IFF_OACTIVE;
ffd7c74a
JT		 3386 break;
3387 }
3db796ac 3388 m = ifq_dequeue(&ifp->if_snd, NULL);
ffd7c74a
JT		 3389 if (m == NULL)
3390 break;
3391 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3392 pri = M_WME_GETAC(m);
3393 txq = &sc->txq[pri];
3394 if (iwn_tx_data(sc, m, ni, txq) != 0) {
3395 ifp->if_oerrors++;
3396 ieee80211_free_node(ni);
3397 break;
3398 }
3399 sc->sc_tx_timer = 5;
3400 }
3401}
3402
3403static void
3404iwn_watchdog(struct iwn_softc *sc)
3405{
3406 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
3407 struct ifnet *ifp = sc->sc_ifp;
3408 struct ieee80211com *ic = ifp->if_l2com;
3409
3410 if_printf(ifp, "device timeout\n");
3411 ieee80211_runtask(ic, &sc->sc_reinit_task);
3412 }
3413}
3414
3415static int
3db796ac 3416iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *ucred)
ffd7c74a
JT		 3417{
3418 struct iwn_softc *sc = ifp->if_softc;
3419 struct ieee80211com *ic = ifp->if_l2com;
3420 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3421 struct ifreq *ifr = (struct ifreq *) data;
3422 int error = 0, startall = 0, stop = 0;
3423
3424 switch (cmd) {
3425 case SIOCSIFFLAGS:
3426 IWN_LOCK(sc);
3427 if (ifp->if_flags & IFF_UP) {
3db796ac 3428 if (!(ifp->if_flags & IFF_RUNNING)) {
ffd7c74a
JT		 3429 iwn_init_locked(sc);
3430 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3431 startall = 1;
3432 else
3433 stop = 1;
3434 }
3435 } else {
3db796ac 3436 if (ifp->if_flags & IFF_RUNNING)
ffd7c74a
JT		 3437 iwn_stop_locked(sc);
3438 }
3439 IWN_UNLOCK(sc);
3440 if (startall)
3441 ieee80211_start_all(ic);
3442 else if (vap != NULL && stop)
3443 ieee80211_stop(vap);
3444 break;
3445 case SIOCGIFMEDIA:
3446 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3447 break;
3448 case SIOCGIFADDR:
3449 error = ether_ioctl(ifp, cmd, data);
3450 break;
3451 default:
3452 error = EINVAL;
3453 break;
3454 }
3455 return error;
3456}
3457
3458/*
3459 * Send a command to the firmware.
3460 */
3461static int
3462iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3463{
3464 struct iwn_tx_ring *ring = &sc->txq[4];
3465 struct iwn_tx_desc *desc;
3466 struct iwn_tx_data *data;
3467 struct iwn_tx_cmd *cmd;
3468 struct mbuf *m;
3469 bus_addr_t paddr;
3470 int totlen, error;
3471
3472 IWN_LOCK_ASSERT(sc);
3473
3474 desc = &ring->desc[ring->cur];
3475 data = &ring->data[ring->cur];
3476 totlen = 4 + size;
3477
3478 if (size > sizeof cmd->data) {
3479 /* Command is too large to fit in a descriptor. */
3480 if (totlen > MCLBYTES)
3481 return EINVAL;
3db796ac 3482 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
ffd7c74a
JT		 3483 if (m == NULL)
3484 return ENOMEM;
3485 cmd = mtod(m, struct iwn_tx_cmd *);
3486 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3487 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3488 if (error != 0) {
3489 m_freem(m);
3490 return error;
3491 }
3492 data->m = m;
3493 } else {
3494 cmd = &ring->cmd[ring->cur];
3495 paddr = data->cmd_paddr;
3496 }
3497
3498 cmd->code = code;
3499 cmd->flags = 0;
3500 cmd->qid = ring->qid;
3501 cmd->idx = ring->cur;
3502 memcpy(cmd->data, buf, size);
3503
3504 desc->nsegs = 1;
3505 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
3506 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
3507
3508 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
3509 __func__, iwn_intr_str(cmd->code), cmd->code,
3510 cmd->flags, cmd->qid, cmd->idx);
3511
3512 if (size > sizeof cmd->data) {
3513 bus_dmamap_sync(ring->data_dmat, data->map,
3514 BUS_DMASYNC_PREWRITE);
3515 } else {
3516 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3517 BUS_DMASYNC_PREWRITE);
3518 }
3519 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3520 BUS_DMASYNC_PREWRITE);
3521
3522#ifdef notyet
3523 /* Update TX scheduler. */
3524 sc->sc_hal->update_sched(sc, ring->qid, ring->cur, 0, 0);
3525#endif
3526
3527 /* Kick command ring. */
3528 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3529 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3530
3db796ac 3531 return async ? 0 : zsleep(desc, sc->sc_ifp->if_serializer, 0, "iwncmd", hz);
ffd7c74a
JT		 3532}
3533
3534static int
3535iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3536{
3537 struct iwn4965_node_info hnode;
3538 caddr_t src, dst;
3539
3540 /*
3541 * We use the node structure for 5000 Series internally (it is
3542 * a superset of the one for 4965AGN). We thus copy the common
3543 * fields before sending the command.
3544 */
3545 src = (caddr_t)node;
3546 dst = (caddr_t)&hnode;
3547 memcpy(dst, src, 48);
3548 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
3549 memcpy(dst + 48, src + 72, 20);
3550 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
3551}
3552
3553static int
3554iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
3555{
3556 /* Direct mapping. */
3557 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
3558}
3559
3560#if 0 /* HT */
3561static const uint8_t iwn_ridx_to_plcp[] = {
3562 10, 20, 55, 110, /* CCK */
3563 0xd, 0xf, 0x5, 0x7, 0x9, 0xb, 0x1, 0x3, 0x3 /* OFDM R1-R4 */
3564};
3565static const uint8_t iwn_siso_mcs_to_plcp[] = {
3566 0, 0, 0, 0, /* CCK */
3567 0, 0, 1, 2, 3, 4, 5, 6, 7 /* HT */
3568};
3569static const uint8_t iwn_mimo_mcs_to_plcp[] = {
3570 0, 0, 0, 0, /* CCK */
3571 8, 8, 9, 10, 11, 12, 13, 14, 15 /* HT */
3572};
3573#endif
3574static const uint8_t iwn_prev_ridx[] = {
3575 /* NB: allow fallback from CCK11 to OFDM9 and from OFDM6 to CCK5 */
3576 0, 0, 1, 5, /* CCK */
3577 2, 4, 3, 6, 7, 8, 9, 10, 10 /* OFDM */
3578};
3579
3580/*
3581 * Configure hardware link parameters for the specified
3582 * node operating on the specified channel.
3583 */
3584static int
3585iwn_set_link_quality(struct iwn_softc *sc, uint8_t id, int async)
3586{
3587 struct ifnet *ifp = sc->sc_ifp;
3588 struct ieee80211com *ic = ifp->if_l2com;
3589 struct iwn_cmd_link_quality linkq;
3590 const struct iwn_rate *rinfo;
3591 int i;
3592 uint8_t txant, ridx;
3593
3594 /* Use the first valid TX antenna. */
3595 txant = IWN_LSB(sc->txchainmask);
3596
3597 memset(&linkq, 0, sizeof linkq);
3598 linkq.id = id;
3599 linkq.antmsk_1stream = txant;
3600 linkq.antmsk_2stream = IWN_ANT_AB;
3601 linkq.ampdu_max = 31;
3602 linkq.ampdu_threshold = 3;
3603 linkq.ampdu_limit = htole16(4000); /* 4ms */
3604
3605#if 0 /* HT */
3606 if (IEEE80211_IS_CHAN_HT(c))
3607 linkq.mimo = 1;
3608#endif
3609
3610 if (id == IWN_ID_BSS)
3611 ridx = IWN_RIDX_OFDM54;
3612 else if (IEEE80211_IS_CHAN_A(ic->ic_curchan))
3613 ridx = IWN_RIDX_OFDM6;
3614 else
3615 ridx = IWN_RIDX_CCK1;
3616
3617 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
3618 rinfo = &iwn_rates[ridx];
3619#if 0 /* HT */
3620 if (IEEE80211_IS_CHAN_HT40(c)) {
3621 linkq.retry[i].plcp = iwn_mimo_mcs_to_plcp[ridx]
3622 | IWN_RIDX_MCS;
3623 linkq.retry[i].rflags = IWN_RFLAG_HT
3624 | IWN_RFLAG_HT40;
3625 /* XXX shortGI */
3626 } else if (IEEE80211_IS_CHAN_HT(c)) {
3627 linkq.retry[i].plcp = iwn_siso_mcs_to_plcp[ridx]
3628 | IWN_RIDX_MCS;
3629 linkq.retry[i].rflags = IWN_RFLAG_HT;
3630 /* XXX shortGI */
3631 } else
3632#endif
3633 {
3634 linkq.retry[i].plcp = rinfo->plcp;
3635 linkq.retry[i].rflags = rinfo->flags;
3636 }
3637 linkq.retry[i].rflags |= IWN_RFLAG_ANT(txant);
3638 ridx = iwn_prev_ridx[ridx];
3639 }
3640#ifdef IWN_DEBUG
3641 if (sc->sc_debug & IWN_DEBUG_STATE) {
3db796ac 3642 kprintf("%s: set link quality for node %d, mimo %d ssmask %d\n",
ffd7c74a 3643 __func__, id, linkq.mimo, linkq.antmsk_1stream);
3db796ac 3644 kprintf("%s:", __func__);
ffd7c74a 3645 for (i = 0; i < IWN_MAX_TX_RETRIES; i++)
3db796ac 3646 kprintf(" %d:%x", linkq.retry[i].plcp,
ffd7c74a 3647 linkq.retry[i].rflags);
3db796ac 3648 kprintf("\n");
ffd7c74a
JT		 3649 }
3650#endif
3651 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
3652}
3653
3654/*
3655 * Broadcast node is used to send group-addressed and management frames.
3656 */
3657static int
3658iwn_add_broadcast_node(struct iwn_softc *sc, int async)
3659{
3660 const struct iwn_hal *hal = sc->sc_hal;
3661 struct ifnet *ifp = sc->sc_ifp;
3662 struct iwn_node_info node;
3663 int error;
3664
3665 memset(&node, 0, sizeof node);
3666 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
3667 node.id = hal->broadcast_id;
3668 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
3669 error = hal->add_node(sc, &node, async);
3670 if (error != 0)
3671 return error;
3672
3673 error = iwn_set_link_quality(sc, hal->broadcast_id, async);
3674 return error;
3675}
3676
3677static int
3678iwn_wme_update(struct ieee80211com *ic)
3679{
3680#define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
3681#define IWN_TXOP_TO_US(v) (v<<5)
3682 struct iwn_softc *sc = ic->ic_ifp->if_softc;
3683 struct iwn_edca_params cmd;
3684 int i;
3685
3686 memset(&cmd, 0, sizeof cmd);
3687 cmd.flags = htole32(IWN_EDCA_UPDATE);
3688 for (i = 0; i < WME_NUM_AC; i++) {
3689 const struct wmeParams *wmep =
3690 &ic->ic_wme.wme_chanParams.cap_wmeParams[i];
3691 cmd.ac[i].aifsn = wmep->wmep_aifsn;
3692 cmd.ac[i].cwmin = htole16(IWN_EXP2(wmep->wmep_logcwmin));
3693 cmd.ac[i].cwmax = htole16(IWN_EXP2(wmep->wmep_logcwmax));
3694 cmd.ac[i].txoplimit =
3695 htole16(IWN_TXOP_TO_US(wmep->wmep_txopLimit));
3696 }
3697 IEEE80211_UNLOCK(ic);
3698 IWN_LOCK(sc);
3699 (void) iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1 /*async*/);
3700 IWN_UNLOCK(sc);
3701 IEEE80211_LOCK(ic);
3702 return 0;
3703#undef IWN_TXOP_TO_US
3704#undef IWN_EXP2
3705}
3706
3707static void
3708iwn_update_mcast(struct ifnet *ifp)
3709{
3710 /* Ignore */
3711}
3712
3713static void
3714iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
3715{
3716 struct iwn_cmd_led led;
3717
3718 /* Clear microcode LED ownership. */
3719 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
3720
3721 led.which = which;
3722 led.unit = htole32(10000); /* on/off in unit of 100ms */
3723 led.off = off;
3724 led.on = on;
3725 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
3726}
3727
3728/*
3729 * Set the critical temperature at which the firmware will stop the radio
3730 * and notify us.
3731 */
3732static int
3733iwn_set_critical_temp(struct iwn_softc *sc)
3734{
3735 struct iwn_critical_temp crit;
3736 int32_t temp;
3737
3738 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
3739
3740 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
3741 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
3742 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
3743 temp = IWN_CTOK(110);
3744 else
3745 temp = 110;
3746 memset(&crit, 0, sizeof crit);
3747 crit.tempR = htole32(temp);
3748 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n",
3749 temp);
3750 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
3751}
3752
3753static int
3754iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
3755{
3756 struct iwn_cmd_timing cmd;
3757 uint64_t val, mod;
3758
3759 memset(&cmd, 0, sizeof cmd);
3760 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
3761 cmd.bintval = htole16(ni->ni_intval);
3762 cmd.lintval = htole16(10);
3763
3764 /* Compute remaining time until next beacon. */
3765 val = (uint64_t)ni->ni_intval * 1024; /* msecs -> usecs */
3766 mod = le64toh(cmd.tstamp) % val;
3767 cmd.binitval = htole32((uint32_t)(val - mod));
3768
3769 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
3770 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
3771
3772 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
3773}
3774
3775static void
3776iwn4965_power_calibration(struct iwn_softc *sc, int temp)
3777{
3778 struct ifnet *ifp = sc->sc_ifp;
3779 struct ieee80211com *ic = ifp->if_l2com;
3780
3781 /* Adjust TX power if need be (delta >= 3 degC.) */
3782 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
3783 __func__, sc->temp, temp);
3784 if (abs(temp - sc->temp) >= 3) {
3785 /* Record temperature of last calibration. */
3786 sc->temp = temp;
3787 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
3788 }
3789}
3790
3791/*
3792 * Set TX power for current channel (each rate has its own power settings).
3793 * This function takes into account the regulatory information from EEPROM,
3794 * the current temperature and the current voltage.
3795 */
3796static int
3797iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3798 int async)
3799{
3800/* Fixed-point arithmetic division using a n-bit fractional part. */
3801#define fdivround(a, b, n) \
3802 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
3803/* Linear interpolation. */
3804#define interpolate(x, x1, y1, x2, y2, n) \
3805 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
3806
3807 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
3808 struct ifnet *ifp = sc->sc_ifp;
3809 struct ieee80211com *ic = ifp->if_l2com;
3810 struct iwn_ucode_info *uc = &sc->ucode_info;
3811 struct iwn4965_cmd_txpower cmd;
3812 struct iwn4965_eeprom_chan_samples *chans;
3813 int32_t vdiff, tdiff;
3814 int i, c, grp, maxpwr;
3815 const uint8_t *rf_gain, *dsp_gain;
3816 uint8_t chan;
3817
3818 /* Retrieve channel number. */
3819 chan = ieee80211_chan2ieee(ic, ch);
3820 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
3821 chan);
3822
3823 memset(&cmd, 0, sizeof cmd);
3824 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
3825 cmd.chan = chan;
3826
3827 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
3828 maxpwr = sc->maxpwr5GHz;
3829 rf_gain = iwn4965_rf_gain_5ghz;
3830 dsp_gain = iwn4965_dsp_gain_5ghz;
3831 } else {
3832 maxpwr = sc->maxpwr2GHz;
3833 rf_gain = iwn4965_rf_gain_2ghz;
3834 dsp_gain = iwn4965_dsp_gain_2ghz;
3835 }
3836
3837 /* Compute voltage compensation. */
3838 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
3839 if (vdiff > 0)
3840 vdiff *= 2;
3841 if (abs(vdiff) > 2)
3842 vdiff = 0;
3843 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3844 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
3845 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
3846
3847 /* Get channel attenuation group. */
3848 if (chan <= 20) /* 1-20 */
3849 grp = 4;
3850 else if (chan <= 43) /* 34-43 */
3851 grp = 0;
3852 else if (chan <= 70) /* 44-70 */
3853 grp = 1;
3854 else if (chan <= 124) /* 71-124 */
3855 grp = 2;
3856 else /* 125-200 */
3857 grp = 3;
3858 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3859 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
3860
3861 /* Get channel sub-band. */
3862 for (i = 0; i < IWN_NBANDS; i++)
3863 if (sc->bands[i].lo != 0 &&
3864 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
3865 break;
3866 if (i == IWN_NBANDS) /* Can't happen in real-life. */
3867 return EINVAL;
3868 chans = sc->bands[i].chans;
3869 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3870 "%s: chan %d sub-band=%d\n", __func__, chan, i);
3871
3872 for (c = 0; c < 2; c++) {
3873 uint8_t power, gain, temp;
3874 int maxchpwr, pwr, ridx, idx;
3875
3876 power = interpolate(chan,
3877 chans[0].num, chans[0].samples[c][1].power,
3878 chans[1].num, chans[1].samples[c][1].power, 1);
3879 gain = interpolate(chan,
3880 chans[0].num, chans[0].samples[c][1].gain,
3881 chans[1].num, chans[1].samples[c][1].gain, 1);
3882 temp = interpolate(chan,
3883 chans[0].num, chans[0].samples[c][1].temp,
3884 chans[1].num, chans[1].samples[c][1].temp, 1);
3885 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3886 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
3887 __func__, c, power, gain, temp);
3888
3889 /* Compute temperature compensation. */
3890 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
3891 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3892 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
3893 __func__, tdiff, sc->temp, temp);
3894
3895 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
3896 /* Convert dBm to half-dBm. */
3897 maxchpwr = sc->maxpwr[chan] * 2;
3898 if ((ridx / 8) & 1)
3899 maxchpwr -= 6; /* MIMO 2T: -3dB */
3900
3901 pwr = maxpwr;
3902
3903 /* Adjust TX power based on rate. */
3904 if ((ridx % 8) == 5)
3905 pwr -= 15; /* OFDM48: -7.5dB */
3906 else if ((ridx % 8) == 6)
3907 pwr -= 17; /* OFDM54: -8.5dB */
3908 else if ((ridx % 8) == 7)
3909 pwr -= 20; /* OFDM60: -10dB */
3910 else
3911 pwr -= 10; /* Others: -5dB */
3912
3913 /* Do not exceed channel max TX power. */
3914 if (pwr > maxchpwr)
3915 pwr = maxchpwr;
3916
3917 idx = gain - (pwr - power) - tdiff - vdiff;
3918 if ((ridx / 8) & 1) /* MIMO */
3919 idx += (int32_t)le32toh(uc->atten[grp][c]);
3920
3921 if (cmd.band == 0)
3922 idx += 9; /* 5GHz */
3923 if (ridx == IWN_RIDX_MAX)
3924 idx += 5; /* CCK */
3925
3926 /* Make sure idx stays in a valid range. */
3927 if (idx < 0)
3928 idx = 0;
3929 else if (idx > IWN4965_MAX_PWR_INDEX)
3930 idx = IWN4965_MAX_PWR_INDEX;
3931
3932 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3933 "%s: Tx chain %d, rate idx %d: power=%d\n",
3934 __func__, c, ridx, idx);
3935 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
3936 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
3937 }
3938 }
3939
3940 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
3941 "%s: set tx power for chan %d\n", __func__, chan);
3942 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
3943
3944#undef interpolate
3945#undef fdivround
3946}
3947
3948static int
3949iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
3950 int async)
3951{
3952 struct iwn5000_cmd_txpower cmd;
3953
3954 /*
3955 * TX power calibration is handled automatically by the firmware
3956 * for 5000 Series.
3957 */
3958 memset(&cmd, 0, sizeof cmd);
3959 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
3960 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
3961 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
3962 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
3963 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
3964}
3965
3966/*
3967 * Retrieve the maximum RSSI (in dBm) among receivers.
3968 */
3969static int
3970iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
3971{
3972 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
3973 uint8_t mask, agc;
3974 int rssi;
3975
3976 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
3977 agc = (le16toh(phy->agc) >> 7) & 0x7f;
3978
3979 rssi = 0;
3980#if 0
3981 if (mask & IWN_ANT_A) /* Ant A */
3982 rssi = max(rssi, phy->rssi[0]);
3983 if (mask & IWN_ATH_B) /* Ant B */
3984 rssi = max(rssi, phy->rssi[2]);
3985 if (mask & IWN_ANT_C) /* Ant C */
3986 rssi = max(rssi, phy->rssi[4]);
3987#else
3988 rssi = max(rssi, phy->rssi[0]);
3989 rssi = max(rssi, phy->rssi[2]);
3990 rssi = max(rssi, phy->rssi[4]);
3991#endif
3992
3993 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d mask 0x%x rssi %d %d %d "
3994 "result %d\n", __func__, agc, mask,
3995 phy->rssi[0], phy->rssi[2], phy->rssi[4],
3996 rssi - agc - IWN_RSSI_TO_DBM);
3997 return rssi - agc - IWN_RSSI_TO_DBM;
3998}
3999
4000static int
4001iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4002{
4003 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4004 int rssi;
4005 uint8_t agc;
4006
4007 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4008
4009 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4010 le16toh(phy->rssi[1]) & 0xff);
4011 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4012
4013 DPRINTF(sc, IWN_DEBUG_RECV, "%s: agc %d rssi %d %d %d "
4014 "result %d\n", __func__, agc,
4015 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4016 rssi - agc - IWN_RSSI_TO_DBM);
4017 return rssi - agc - IWN_RSSI_TO_DBM;
4018}
4019
4020/*
4021 * Retrieve the average noise (in dBm) among receivers.
4022 */
4023static int
4024iwn_get_noise(const struct iwn_rx_general_stats *stats)
4025{
4026 int i, total, nbant, noise;
4027
4028 total = nbant = 0;
4029 for (i = 0; i < 3; i++) {
4030 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4031 continue;
4032 total += noise;
4033 nbant++;
4034 }
4035 /* There should be at least one antenna but check anyway. */
4036 return (nbant == 0) ? -127 : (total / nbant) - 107;
4037}
4038
4039/*
4040 * Compute temperature (in degC) from last received statistics.
4041 */
4042static int
4043iwn4965_get_temperature(struct iwn_softc *sc)
4044{
4045 struct iwn_ucode_info *uc = &sc->ucode_info;
4046 int32_t r1, r2, r3, r4, temp;
4047
4048 r1 = le32toh(uc->temp[0].chan20MHz);
4049 r2 = le32toh(uc->temp[1].chan20MHz);
4050 r3 = le32toh(uc->temp[2].chan20MHz);
4051 r4 = le32toh(sc->rawtemp);
4052
4053 if (r1 == r3) /* Prevents division by 0 (should not happen.) */
4054 return 0;
4055
4056 /* Sign-extend 23-bit R4 value to 32-bit. */
4057 r4 = (r4 << 8) >> 8;
4058 /* Compute temperature in Kelvin. */
4059 temp = (259 * (r4 - r2)) / (r3 - r1);
4060 temp = (temp * 97) / 100 + 8;
4061
4062 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
4063 IWN_KTOC(temp));
4064 return IWN_KTOC(temp);
4065}
4066
4067static int
4068iwn5000_get_temperature(struct iwn_softc *sc)
4069{
4070 int32_t temp;
4071
4072 /*
4073 * Temperature is not used by the driver for 5000 Series because
4074 * TX power calibration is handled by firmware. We export it to
4075 * users through the sensor framework though.
4076 */
4077 temp = le32toh(sc->rawtemp);
4078 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
4079 temp = (temp / -5) + sc->temp_off;
4080 temp = IWN_KTOC(temp);
4081 }
4082 return temp;
4083}
4084
4085/*
4086 * Initialize sensitivity calibration state machine.
4087 */
4088static int
4089iwn_init_sensitivity(struct iwn_softc *sc)
4090{
4091 const struct iwn_hal *hal = sc->sc_hal;
4092 struct iwn_calib_state *calib = &sc->calib;
4093 uint32_t flags;
4094 int error;
4095
4096 /* Reset calibration state machine. */
4097 memset(calib, 0, sizeof (*calib));
4098 calib->state = IWN_CALIB_STATE_INIT;
4099 calib->cck_state = IWN_CCK_STATE_HIFA;
4100 /* Set initial correlation values. */
4101 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
4102 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
4103 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
4104 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
4105 calib->cck_x4 = 125;
4106 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
4107 calib->energy_cck = sc->limits->energy_cck;
4108
4109 /* Write initial sensitivity. */
4110 error = iwn_send_sensitivity(sc);
4111 if (error != 0)
4112 return error;
4113
4114 /* Write initial gains. */
4115 error = hal->init_gains(sc);
4116 if (error != 0)
4117 return error;
4118
4119 /* Request statistics at each beacon interval. */
4120 flags = 0;
4121 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: calibrate phy\n", __func__);
4122 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
4123}
4124
4125/*
4126 * Collect noise and RSSI statistics for the first 20 beacons received
4127 * after association and use them to determine connected antennas and
4128 * to set differential gains.
4129 */
4130static void
4131iwn_collect_noise(struct iwn_softc *sc,
4132 const struct iwn_rx_general_stats *stats)
4133{
4134 const struct iwn_hal *hal = sc->sc_hal;
4135 struct iwn_calib_state *calib = &sc->calib;
4136 uint32_t val;
4137 int i;
4138
4139 /* Accumulate RSSI and noise for all 3 antennas. */
4140 for (i = 0; i < 3; i++) {
4141 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
4142 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
4143 }
4144 /* NB: We update differential gains only once after 20 beacons. */
4145 if (++calib->nbeacons < 20)
4146 return;
4147
4148 /* Determine highest average RSSI. */
4149 val = MAX(calib->rssi[0], calib->rssi[1]);
4150 val = MAX(calib->rssi[2], val);
4151
4152 /* Determine which antennas are connected. */
4153 sc->chainmask = 0;
4154 for (i = 0; i < 3; i++)
4155 if (val - calib->rssi[i] <= 15 * 20)
4156 sc->chainmask |= 1 << i;
4157 /* If none of the TX antennas are connected, keep at least one. */
4158 if ((sc->chainmask & sc->txchainmask) == 0)
4159 sc->chainmask |= IWN_LSB(sc->txchainmask);
4160
4161 (void)hal->set_gains(sc);
4162 calib->state = IWN_CALIB_STATE_RUN;
4163
4164#ifdef notyet
4165 /* XXX Disable RX chains with no antennas connected. */
4166 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
4167 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4168#endif
4169
4170#if 0
4171 /* XXX: not yet */
4172 /* Enable power-saving mode if requested by user. */
4173 if (sc->sc_ic.ic_flags & IEEE80211_F_PMGTON)
4174 (void)iwn_set_pslevel(sc, 0, 3, 1);
4175#endif
4176}
4177
4178static int
4179iwn4965_init_gains(struct iwn_softc *sc)
4180{
4181 struct iwn_phy_calib_gain cmd;
4182
4183 memset(&cmd, 0, sizeof cmd);
4184 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4185 /* Differential gains initially set to 0 for all 3 antennas. */
4186 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4187 "%s: setting initial differential gains\n", __func__);
4188 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4189}
4190
4191static int
4192iwn5000_init_gains(struct iwn_softc *sc)
4193{
4194 struct iwn_phy_calib cmd;
4195
4196 memset(&cmd, 0, sizeof cmd);
4197 cmd.code = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
4198 cmd.ngroups = 1;
4199 cmd.isvalid = 1;
4200 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4201 "%s: setting initial differential gains\n", __func__);
4202 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4203}
4204
4205static int
4206iwn4965_set_gains(struct iwn_softc *sc)
4207{
4208 struct iwn_calib_state *calib = &sc->calib;
4209 struct iwn_phy_calib_gain cmd;
4210 int i, delta, noise;
4211
4212 /* Get minimal noise among connected antennas. */
4213 noise = INT_MAX; /* NB: There's at least one antenna. */
4214 for (i = 0; i < 3; i++)
4215 if (sc->chainmask & (1 << i))
4216 noise = MIN(calib->noise[i], noise);
4217
4218 memset(&cmd, 0, sizeof cmd);
4219 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4220 /* Set differential gains for connected antennas. */
4221 for (i = 0; i < 3; i++) {
4222 if (sc->chainmask & (1 << i)) {
4223 /* Compute attenuation (in unit of 1.5dB). */
4224 delta = (noise - (int32_t)calib->noise[i]) / 30;
4225 /* NB: delta <= 0 */
4226 /* Limit to [-4.5dB,0]. */
4227 cmd.gain[i] = MIN(abs(delta), 3);
4228 if (delta < 0)
4229 cmd.gain[i] |= 1 << 2; /* sign bit */
4230 }
4231 }
4232 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4233 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
4234 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
4235 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4236}
4237
4238static int
4239iwn5000_set_gains(struct iwn_softc *sc)
4240{
4241 struct iwn_calib_state *calib = &sc->calib;
4242 struct iwn_phy_calib_gain cmd;
4243 int i, ant, delta, div;
4244
4245 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
4246 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
4247
4248 memset(&cmd, 0, sizeof cmd);
4249 cmd.code = IWN5000_PHY_CALIB_NOISE_GAIN;
4250 cmd.ngroups = 1;
4251 cmd.isvalid = 1;
4252 /* Get first available RX antenna as referential. */
4253 ant = IWN_LSB(sc->rxchainmask);
4254 /* Set differential gains for other antennas. */
4255 for (i = ant + 1; i < 3; i++) {
4256 if (sc->chainmask & (1 << i)) {
4257 /* The delta is relative to antenna "ant". */
4258 delta = ((int32_t)calib->noise[ant] -
4259 (int32_t)calib->noise[i]) / div;
4260 /* Limit to [-4.5dB,+4.5dB]. */
4261 cmd.gain[i - 1] = MIN(abs(delta), 3);
4262 if (delta < 0)
4263 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
4264 }
4265 }
4266 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4267 "setting differential gains Ant B/C: %x/%x (%x)\n",
4268 cmd.gain[0], cmd.gain[1], sc->chainmask);
4269 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4270}
4271
4272/*
4273 * Tune RF RX sensitivity based on the number of false alarms detected
4274 * during the last beacon period.
4275 */
4276static void
4277iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
4278{
4279#define inc(val, inc, max) \
4280 if ((val) < (max)) { \
4281 if ((val) < (max) - (inc)) \
4282 (val) += (inc); \
4283 else \
4284 (val) = (max); \
4285 needs_update = 1; \
4286 }
4287#define dec(val, dec, min) \
4288 if ((val) > (min)) { \
4289 if ((val) > (min) + (dec)) \
4290 (val) -= (dec); \
4291 else \
4292 (val) = (min); \
4293 needs_update = 1; \
4294 }
4295
4296 const struct iwn_sensitivity_limits *limits = sc->limits;
4297 struct iwn_calib_state *calib = &sc->calib;
4298 uint32_t val, rxena, fa;
4299 uint32_t energy[3], energy_min;
4300 uint8_t noise[3], noise_ref;
4301 int i, needs_update = 0;
4302
4303 /* Check that we've been enabled long enough. */
4304 rxena = le32toh(stats->general.load);
4305 if (rxena == 0)
4306 return;
4307
4308 /* Compute number of false alarms since last call for OFDM. */
4309 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
4310 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
4311 fa *= 200 * 1024; /* 200TU */
4312
4313 /* Save counters values for next call. */
4314 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
4315 calib->fa_ofdm = le32toh(stats->ofdm.fa);
4316
4317 if (fa > 50 * rxena) {
4318 /* High false alarm count, decrease sensitivity. */
4319 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4320 "%s: OFDM high false alarm count: %u\n", __func__, fa);
4321 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
4322 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
4323 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
4324 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
4325
4326 } else if (fa < 5 * rxena) {
4327 /* Low false alarm count, increase sensitivity. */
4328 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4329 "%s: OFDM low false alarm count: %u\n", __func__, fa);
4330 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4331 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4332 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4333 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4334 }
4335
4336 /* Compute maximum noise among 3 receivers. */
4337 for (i = 0; i < 3; i++)
4338 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4339 val = MAX(noise[0], noise[1]);
4340 val = MAX(noise[2], val);
4341 /* Insert it into our samples table. */
4342 calib->noise_samples[calib->cur_noise_sample] = val;
4343 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4344
4345 /* Compute maximum noise among last 20 samples. */
4346 noise_ref = calib->noise_samples[0];
4347 for (i = 1; i < 20; i++)
4348 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4349
4350 /* Compute maximum energy among 3 receivers. */
4351 for (i = 0; i < 3; i++)
4352 energy[i] = le32toh(stats->general.energy[i]);
4353 val = MIN(energy[0], energy[1]);
4354 val = MIN(energy[2], val);
4355 /* Insert it into our samples table. */
4356 calib->energy_samples[calib->cur_energy_sample] = val;
4357 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4358
4359 /* Compute minimum energy among last 10 samples. */
4360 energy_min = calib->energy_samples[0];
4361 for (i = 1; i < 10; i++)
4362 energy_min = MAX(energy_min, calib->energy_samples[i]);
4363 energy_min += 6;
4364
4365 /* Compute number of false alarms since last call for CCK. */
4366 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4367 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4368 fa *= 200 * 1024; /* 200TU */
4369
4370 /* Save counters values for next call. */
4371 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4372 calib->fa_cck = le32toh(stats->cck.fa);
4373
4374 if (fa > 50 * rxena) {
4375 /* High false alarm count, decrease sensitivity. */
4376 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4377 "%s: CCK high false alarm count: %u\n", __func__, fa);
4378 calib->cck_state = IWN_CCK_STATE_HIFA;
4379 calib->low_fa = 0;
4380
4381 if (calib->cck_x4 > 160) {
4382 calib->noise_ref = noise_ref;
4383 if (calib->energy_cck > 2)
4384 dec(calib->energy_cck, 2, energy_min);
4385 }
4386 if (calib->cck_x4 < 160) {
4387 calib->cck_x4 = 161;
4388 needs_update = 1;
4389 } else
4390 inc(calib->cck_x4, 3, limits->max_cck_x4);
4391
4392 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4393
4394 } else if (fa < 5 * rxena) {
4395 /* Low false alarm count, increase sensitivity. */
4396 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4397 "%s: CCK low false alarm count: %u\n", __func__, fa);
4398 calib->cck_state = IWN_CCK_STATE_LOFA;
4399 calib->low_fa++;
4400
4401 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4402 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4403 calib->low_fa > 100)) {
4404 inc(calib->energy_cck, 2, limits->min_energy_cck);
4405 dec(calib->cck_x4, 3, limits->min_cck_x4);
4406 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4407 }
4408 } else {
4409 /* Not worth to increase or decrease sensitivity. */
4410 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4411 "%s: CCK normal false alarm count: %u\n", __func__, fa);
4412 calib->low_fa = 0;
4413 calib->noise_ref = noise_ref;
4414
4415 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4416 /* Previous interval had many false alarms. */
4417 dec(calib->energy_cck, 8, energy_min);
4418 }
4419 calib->cck_state = IWN_CCK_STATE_INIT;
4420 }
4421
4422 if (needs_update)
4423 (void)iwn_send_sensitivity(sc);
4424#undef dec
4425#undef inc
4426}
4427
4428static int
4429iwn_send_sensitivity(struct iwn_softc *sc)
4430{
4431 struct iwn_calib_state *calib = &sc->calib;
4432 struct iwn_sensitivity_cmd cmd;
4433
4434 memset(&cmd, 0, sizeof cmd);
4435 cmd.which = IWN_SENSITIVITY_WORKTBL;
4436 /* OFDM modulation. */
4437 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4438 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4439 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4440 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4441 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4442 cmd.energy_ofdm_th = htole16(62);
4443 /* CCK modulation. */
4444 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4445 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4446 cmd.energy_cck = htole16(calib->energy_cck);
4447 /* Barker modulation: use default values. */
4448 cmd.corr_barker = htole16(190);
4449 cmd.corr_barker_mrc = htole16(390);
4450
4451 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4452 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
4453 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4454 calib->ofdm_mrc_x4, calib->cck_x4,
4455 calib->cck_mrc_x4, calib->energy_cck);
4456 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, sizeof cmd, 1);
4457}
4458
4459/*
4460 * Set STA mode power saving level (between 0 and 5).
4461 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4462 */
4463static int
4464iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4465{
4466 const struct iwn_pmgt *pmgt;
4467 struct iwn_pmgt_cmd cmd;
4468 uint32_t max, skip_dtim;
4469 uint32_t tmp;
4470 int i;
4471
4472 /* Select which PS parameters to use. */
4473 if (dtim <= 2)
4474 pmgt = &iwn_pmgt[0][level];
4475 else if (dtim <= 10)
4476 pmgt = &iwn_pmgt[1][level];
4477 else
4478 pmgt = &iwn_pmgt[2][level];
4479
4480 memset(&cmd, 0, sizeof cmd);
4481 if (level != 0) /* not CAM */
4482 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4483 if (level == 5)
4484 cmd.flags |= htole16(IWN_PS_FAST_PD);
4485 /* Retrieve PCIe Active State Power Management (ASPM). */
4486 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
4487 if (!(tmp & 0x1)) /* L0s Entry disabled. */
4488 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4489 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4490 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4491
4492 if (dtim == 0) {
4493 dtim = 1;
4494 skip_dtim = 0;
4495 } else
4496 skip_dtim = pmgt->skip_dtim;
4497 if (skip_dtim != 0) {
4498 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4499 max = pmgt->intval[4];
4500 if (max == (uint32_t)-1)
4501 max = dtim * (skip_dtim + 1);
4502 else if (max > dtim)
4503 max = (max / dtim) * dtim;
4504 } else
4505 max = dtim;
4506 for (i = 0; i < 5; i++)
4507 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
4508
4509 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
4510 level);
4511 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4512}
4513
4514static int
4515iwn_config(struct iwn_softc *sc)
4516{
4517 const struct iwn_hal *hal = sc->sc_hal;
4518 struct ifnet *ifp = sc->sc_ifp;
4519 struct ieee80211com *ic = ifp->if_l2com;
4520 struct iwn_bluetooth bluetooth;
4521 uint32_t txmask;
4522 int error;
4523 uint16_t rxchain;
4524
4525 /* Configure valid TX chains for 5000 Series. */
4526 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
4527 txmask = htole32(sc->txchainmask);
4528 DPRINTF(sc, IWN_DEBUG_RESET,
4529 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
4530 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
4531 sizeof txmask, 0);
4532 if (error != 0) {
4533 device_printf(sc->sc_dev,
4534 "%s: could not configure valid TX chains, "
4535 "error %d\n", __func__, error);
4536 return error;
4537 }
4538 }
4539
4540 /* Configure bluetooth coexistence. */
4541 memset(&bluetooth, 0, sizeof bluetooth);
4542 bluetooth.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
4543 bluetooth.lead_time = IWN_BT_LEAD_TIME_DEF;
4544 bluetooth.max_kill = IWN_BT_MAX_KILL_DEF;
4545 DPRINTF(sc, IWN_DEBUG_RESET, "%s: config bluetooth coexistence\n",
4546 __func__);
4547 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &bluetooth, sizeof bluetooth, 0);
4548 if (error != 0) {
4549 device_printf(sc->sc_dev,
4550 "%s: could not configure bluetooth coexistence, error %d\n",
4551 __func__, error);
4552 return error;
4553 }
4554
4555 /* Set mode, channel, RX filter and enable RX. */
4556 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
4557 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp));
4558 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp));
4559 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
4560 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4561 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
4562 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4563 switch (ic->ic_opmode) {
4564 case IEEE80211_M_STA:
4565 sc->rxon.mode = IWN_MODE_STA;
4566 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
4567 break;
4568 case IEEE80211_M_MONITOR:
4569 sc->rxon.mode = IWN_MODE_MONITOR;
4570 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
4571 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
4572 break;
4573 default:
4574 /* Should not get there. */
4575 break;
4576 }
4577 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
4578 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
4579 sc->rxon.ht_single_mask = 0xff;
4580 sc->rxon.ht_dual_mask = 0xff;
4581 sc->rxon.ht_triple_mask = 0xff;
4582 rxchain =
4583 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4584 IWN_RXCHAIN_MIMO_COUNT(2) |
4585 IWN_RXCHAIN_IDLE_COUNT(2);
4586 sc->rxon.rxchain = htole16(rxchain);
4587 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
4588 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 0);
4589 if (error != 0) {
4590 device_printf(sc->sc_dev,
4591 "%s: RXON command failed\n", __func__);
4592 return error;
4593 }
4594
4595 error = iwn_add_broadcast_node(sc, 0);
4596 if (error != 0) {
4597 device_printf(sc->sc_dev,
4598 "%s: could not add broadcast node\n", __func__);
4599 return error;
4600 }
4601
4602 /* Configuration has changed, set TX power accordingly. */
4603 error = hal->set_txpower(sc, ic->ic_curchan, 0);
4604 if (error != 0) {
4605 device_printf(sc->sc_dev,
4606 "%s: could not set TX power\n", __func__);
4607 return error;
4608 }
4609
4610 error = iwn_set_critical_temp(sc);
4611 if (error != 0) {
4612 device_printf(sc->sc_dev,
4613 "%s: ccould not set critical temperature\n", __func__);
4614 return error;
4615 }
4616
4617 /* Set power saving level to CAM during initialization. */
4618 error = iwn_set_pslevel(sc, 0, 0, 0);
4619 if (error != 0) {
4620 device_printf(sc->sc_dev,
4621 "%s: could not set power saving level\n", __func__);
4622 return error;
4623 }
4624 return 0;
4625}
4626
4627static int
4628iwn_scan(struct iwn_softc *sc)
4629{
4630 struct ifnet *ifp = sc->sc_ifp;
4631 struct ieee80211com *ic = ifp->if_l2com;
4632 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/
4633 struct iwn_scan_hdr *hdr;
4634 struct iwn_cmd_data *tx;
4635 struct iwn_scan_essid *essid;
4636 struct iwn_scan_chan *chan;
4637 struct ieee80211_frame *wh;
4638 struct ieee80211_rateset *rs;
4639 struct ieee80211_channel *c;
4640 int buflen, error, nrates;
4641 uint16_t rxchain;
4642 uint8_t *buf, *frm, txant;
4643
3db796ac 4644 buf = kmalloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_INTWAIT | M_ZERO);
ffd7c74a
JT		 4645 if (buf == NULL) {
4646 device_printf(sc->sc_dev,
4647 "%s: could not allocate buffer for scan command\n",
4648 __func__);
4649 return ENOMEM;
4650 }
4651 hdr = (struct iwn_scan_hdr *)buf;
4652
4653 /*
4654 * Move to the next channel if no frames are received within 10ms
4655 * after sending the probe request.
4656 */
4657 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
4658 hdr->quiet_threshold = htole16(1); /* min # of packets */
4659
4660 /* Select antennas for scanning. */
4661 rxchain =
4662 IWN_RXCHAIN_VALID(sc->rxchainmask) |
4663 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
4664 IWN_RXCHAIN_DRIVER_FORCE;
4665 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) &&
4666 sc->hw_type == IWN_HW_REV_TYPE_4965) {
4667 /* Ant A must be avoided in 5GHz because of an HW bug. */
4668 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_BC);
4669 } else /* Use all available RX antennas. */
4670 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
4671 hdr->rxchain = htole16(rxchain);
4672 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
4673
4674 tx = (struct iwn_cmd_data *)(hdr + 1);
4675 tx->flags = htole32(IWN_TX_AUTO_SEQ);
4676 tx->id = sc->sc_hal->broadcast_id;
4677 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
4678
4679 if (IEEE80211_IS_CHAN_A(ic->ic_curchan)) {
4680 /* Send probe requests at 6Mbps. */
4681 tx->plcp = iwn_rates[IWN_RIDX_OFDM6].plcp;
4682 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
4683 } else {
4684 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
4685 /* Send probe requests at 1Mbps. */
4686 tx->plcp = iwn_rates[IWN_RIDX_CCK1].plcp;
4687 tx->rflags = IWN_RFLAG_CCK;
4688 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
4689 }
4690 /* Use the first valid TX antenna. */
4691 txant = IWN_LSB(sc->txchainmask);
4692 tx->rflags |= IWN_RFLAG_ANT(txant);
4693
4694 essid = (struct iwn_scan_essid *)(tx + 1);
4695 if (ss->ss_ssid[0].len != 0) {
4696 essid[0].id = IEEE80211_ELEMID_SSID;
4697 essid[0].len = ss->ss_ssid[0].len;
4698 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
4699 }
4700
4701 /*
4702 * Build a probe request frame. Most of the following code is a
4703 * copy & paste of what is done in net80211.
4704 */
4705 wh = (struct ieee80211_frame *)(essid + 20);
4706 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
4707 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
4708 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
4709 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
4710 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
4711 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
4712 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
4713 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
4714
4715 frm = (uint8_t *)(wh + 1);
4716
4717 /* Add SSID IE. */
4718 *frm++ = IEEE80211_ELEMID_SSID;
4719 *frm++ = ss->ss_ssid[0].len;
4720 memcpy(frm, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
4721 frm += ss->ss_ssid[0].len;
4722
4723 /* Add supported rates IE. */
4724 *frm++ = IEEE80211_ELEMID_RATES;
4725 nrates = rs->rs_nrates;
4726 if (nrates > IEEE80211_RATE_SIZE)
4727 nrates = IEEE80211_RATE_SIZE;
4728 *frm++ = nrates;
4729 memcpy(frm, rs->rs_rates, nrates);
4730 frm += nrates;
4731
4732 /* Add supported xrates IE. */
4733 if (rs->rs_nrates > IEEE80211_RATE_SIZE) {
4734 nrates = rs->rs_nrates - IEEE80211_RATE_SIZE;
4735 *frm++ = IEEE80211_ELEMID_XRATES;
4736 *frm++ = (uint8_t)nrates;
4737 memcpy(frm, rs->rs_rates + IEEE80211_RATE_SIZE, nrates);
4738 frm += nrates;
4739 }
4740
4741 /* Set length of probe request. */
4742 tx->len = htole16(frm - (uint8_t *)wh);
4743
4744 c = ic->ic_curchan;
4745 chan = (struct iwn_scan_chan *)frm;
4746 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
4747 chan->flags = 0;
4748 if (ss->ss_nssid > 0)
4749 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
4750 chan->dsp_gain = 0x6e;
4751 if (IEEE80211_IS_CHAN_5GHZ(c) &&
4752 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
4753 chan->rf_gain = 0x3b;
4754 chan->active = htole16(24);
4755 chan->passive = htole16(110);
4756 chan->flags |= htole32(IWN_CHAN_ACTIVE);
4757 } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
4758 chan->rf_gain = 0x3b;
4759 chan->active = htole16(24);
4760 if (sc->rxon.associd)
4761 chan->passive = htole16(78);
4762 else
4763 chan->passive = htole16(110);
4764 hdr->crc_threshold = 0xffff;
4765 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
4766 chan->rf_gain = 0x28;
4767 chan->active = htole16(36);
4768 chan->passive = htole16(120);
4769 chan->flags |= htole32(IWN_CHAN_ACTIVE);
4770 } else {
4771 chan->rf_gain = 0x28;
4772 chan->active = htole16(36);
4773 if (sc->rxon.associd)
4774 chan->passive = htole16(88);
4775 else
4776 chan->passive = htole16(120);
4777 hdr->crc_threshold = 0xffff;
4778 }
4779
4780 DPRINTF(sc, IWN_DEBUG_STATE,
4781 "%s: chan %u flags 0x%x rf_gain 0x%x "
4782 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__,
4783 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
4784 chan->active, chan->passive);
4785
4786 hdr->nchan++;
4787 chan++;
4788 buflen = (uint8_t *)chan - buf;
4789 hdr->len = htole16(buflen);
4790
4791 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
4792 hdr->nchan);
4793 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
3db796ac 4794 kfree(buf, M_DEVBUF);
ffd7c74a
JT		 4795 return error;
4796}
4797
4798static int
4799iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
4800{
4801 const struct iwn_hal *hal = sc->sc_hal;
4802 struct ifnet *ifp = sc->sc_ifp;
4803 struct ieee80211com *ic = ifp->if_l2com;
4804 struct ieee80211_node *ni = vap->iv_bss;
4805 int error;
4806
4807 sc->calib.state = IWN_CALIB_STATE_INIT;
4808
4809 /* Update adapter configuration. */
4810 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4811 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan));
4812 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4813 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4814 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4815 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4816 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4817 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4818 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4819 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4820 sc->rxon.cck_mask = 0;
4821 sc->rxon.ofdm_mask = 0x15;
4822 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4823 sc->rxon.cck_mask = 0x03;
4824 sc->rxon.ofdm_mask = 0;
4825 } else {
4826 /* XXX assume 802.11b/g */
4827 sc->rxon.cck_mask = 0x0f;
4828 sc->rxon.ofdm_mask = 0x15;
4829 }
4830 DPRINTF(sc, IWN_DEBUG_STATE,
4831 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x "
4832 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x "
4833 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n",
4834 __func__,
4835 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags),
4836 sc->rxon.cck_mask, sc->rxon.ofdm_mask,
4837 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask,
4838 le16toh(sc->rxon.rxchain),
4839 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":",
4840 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter));
4841 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4842 if (error != 0) {
4843 device_printf(sc->sc_dev,
4844 "%s: RXON command failed, error %d\n", __func__, error);
4845 return error;
4846 }
4847
4848 /* Configuration has changed, set TX power accordingly. */
4849 error = hal->set_txpower(sc, ni->ni_chan, 1);
4850 if (error != 0) {
4851 device_printf(sc->sc_dev,
4852 "%s: could not set Tx power, error %d\n", __func__, error);
4853 return error;
4854 }
4855 /*
4856 * Reconfiguring RXON clears the firmware nodes table so we must
4857 * add the broadcast node again.
4858 */
4859 error = iwn_add_broadcast_node(sc, 1);
4860 if (error != 0) {
4861 device_printf(sc->sc_dev,
4862 "%s: could not add broadcast node, error %d\n",
4863 __func__, error);
4864 return error;
4865 }
4866 return 0;
4867}
4868
4869/*
4870 * Configure the adapter for associated state.
4871 */
4872static int
4873iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
4874{
4875#define MS(v,x) (((v) & x) >> x##_S)
4876 const struct iwn_hal *hal = sc->sc_hal;
4877 struct ifnet *ifp = sc->sc_ifp;
4878 struct ieee80211com *ic = ifp->if_l2com;
4879 struct ieee80211_node *ni = vap->iv_bss;
4880 struct iwn_node_info node;
4881 int error;
4882
4883 sc->calib.state = IWN_CALIB_STATE_INIT;
4884
4885 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4886 /* Link LED blinks while monitoring. */
4887 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
4888 return 0;
4889 }
4890 error = iwn_set_timing(sc, ni);
4891 if (error != 0) {
4892 device_printf(sc->sc_dev,
4893 "%s: could not set timing, error %d\n", __func__, error);
4894 return error;
4895 }
4896
4897 /* Update adapter configuration. */
4898 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4899 sc->rxon.chan = htole16(ieee80211_chan2ieee(ic, ni->ni_chan));
4900 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
4901 /* Short preamble and slot time are negotiated when associating. */
4902 sc->rxon.flags &= ~htole32(IWN_RXON_SHPREAMBLE | IWN_RXON_SHSLOT);
4903 sc->rxon.flags |= htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
4904 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4905 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4906 else
4907 sc->rxon.flags &= ~htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
4908 if (ic->ic_flags & IEEE80211_F_SHSLOT)
4909 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
4910 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4911 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
4912 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4913 sc->rxon.cck_mask = 0;
4914 sc->rxon.ofdm_mask = 0x15;
4915 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4916 sc->rxon.cck_mask = 0x03;
4917 sc->rxon.ofdm_mask = 0;
4918 } else {
4919 /* XXX assume 802.11b/g */
4920 sc->rxon.cck_mask = 0x0f;
4921 sc->rxon.ofdm_mask = 0x15;
4922 }
4923#if 0 /* HT */
4924 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
4925 sc->rxon.flags &= ~htole32(IWN_RXON_HT);
4926 if (IEEE80211_IS_CHAN_HT40U(ni->ni_chan))
4927 sc->rxon.flags |= htole32(IWN_RXON_HT40U);
4928 else if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
4929 sc->rxon.flags |= htole32(IWN_RXON_HT40D);
4930 else
4931 sc->rxon.flags |= htole32(IWN_RXON_HT20);
4932 sc->rxon.rxchain = htole16(
4933 IWN_RXCHAIN_VALID(3)
4934 | IWN_RXCHAIN_MIMO_COUNT(3)
4935 | IWN_RXCHAIN_IDLE_COUNT(1)
4936 | IWN_RXCHAIN_MIMO_FORCE);
4937
4938 maxrxampdu = MS(ni->ni_htparam, IEEE80211_HTCAP_MAXRXAMPDU);
4939 ampdudensity = MS(ni->ni_htparam, IEEE80211_HTCAP_MPDUDENSITY);
4940 } else
4941 maxrxampdu = ampdudensity = 0;
4942#endif
4943 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
4944
4945 DPRINTF(sc, IWN_DEBUG_STATE,
4946 "%s: config chan %d mode %d flags 0x%x cck 0x%x ofdm 0x%x "
4947 "ht_single 0x%x ht_dual 0x%x rxchain 0x%x "
4948 "myaddr %6D wlap %6D bssid %6D associd %d filter 0x%x\n",
4949 __func__,
4950 le16toh(sc->rxon.chan), sc->rxon.mode, le32toh(sc->rxon.flags),
4951 sc->rxon.cck_mask, sc->rxon.ofdm_mask,
4952 sc->rxon.ht_single_mask, sc->rxon.ht_dual_mask,
4953 le16toh(sc->rxon.rxchain),
4954 sc->rxon.myaddr, ":", sc->rxon.wlap, ":", sc->rxon.bssid, ":",
4955 le16toh(sc->rxon.associd), le32toh(sc->rxon.filter));
4956 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, hal->rxonsz, 1);
4957 if (error != 0) {
4958 device_printf(sc->sc_dev,
4959 "%s: could not update configuration, error %d\n",
4960 __func__, error);
4961 return error;
4962 }
4963
4964 /* Configuration has changed, set TX power accordingly. */
4965 error = hal->set_txpower(sc, ni->ni_chan, 1);
4966 if (error != 0) {
4967 device_printf(sc->sc_dev,
4968 "%s: could not set Tx power, error %d\n", __func__, error);
4969 return error;
4970 }
4971
4972 /* Add BSS node. */
4973 memset(&node, 0, sizeof node);
4974 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
4975 node.id = IWN_ID_BSS;
4976#ifdef notyet
4977 node.htflags = htole32(IWN_AMDPU_SIZE_FACTOR(3) |
4978 IWN_AMDPU_DENSITY(5)); /* 2us */
4979#endif
4980 DPRINTF(sc, IWN_DEBUG_STATE, "%s: add BSS node, id %d htflags 0x%x\n",
4981 __func__, node.id, le32toh(node.htflags));
4982 error = hal->add_node(sc, &node, 1);
4983 if (error != 0) {
4984 device_printf(sc->sc_dev, "could not add BSS node\n");
4985 return error;
4986 }
4987 DPRINTF(sc, IWN_DEBUG_STATE, "setting link quality for node %d\n",
4988 node.id);
4989 error = iwn_set_link_quality(sc, node.id, 1);
4990 if (error != 0) {
4991 device_printf(sc->sc_dev,
4992 "%s: could not setup MRR for node %d, error %d\n",
4993 __func__, node.id, error);
4994 return error;
4995 }
4996
4997 error = iwn_init_sensitivity(sc);
4998 if (error != 0) {
4999 device_printf(sc->sc_dev,
5000 "%s: could not set sensitivity, error %d\n",
5001 __func__, error);
5002 return error;
5003 }
5004
5005 /* Start periodic calibration timer. */
5006 sc->calib.state = IWN_CALIB_STATE_ASSOC;
5007 iwn_calib_reset(sc);
5008
5009 /* Link LED always on while associated. */
5010 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
5011
5012 return 0;
5013#undef MS
5014}
5015
5016#if 0 /* HT */
5017/*
5018 * This function is called by upper layer when an ADDBA request is received
5019 * from another STA and before the ADDBA response is sent.
5020 */
5021static int
5022iwn_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5023 uint8_t tid)
5024{
5025 struct ieee80211_rx_ba *ba = &ni->ni_rx_ba[tid];
5026 struct iwn_softc *sc = ic->ic_softc;
5027 struct iwn_node *wn = (void *)ni;
5028 struct iwn_node_info node;
5029
5030 memset(&node, 0, sizeof node);
5031 node.id = wn->id;
5032 node.control = IWN_NODE_UPDATE;
5033 node.flags = IWN_FLAG_SET_ADDBA;
5034 node.addba_tid = tid;
5035 node.addba_ssn = htole16(ba->ba_winstart);
5036 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
5037 wn->id, tid, ba->ba_winstart));
5038 return sc->sc_hal->add_node(sc, &node, 1);
5039}
5040
5041/*
5042 * This function is called by upper layer on teardown of an HT-immediate
5043 * Block Ack agreement (eg. uppon receipt of a DELBA frame.)
5044 */
5045static void
5046iwn_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
5047 uint8_t tid)
5048{
5049 struct iwn_softc *sc = ic->ic_softc;
5050 struct iwn_node *wn = (void *)ni;
5051 struct iwn_node_info node;
5052
5053 memset(&node, 0, sizeof node);
5054 node.id = wn->id;
5055 node.control = IWN_NODE_UPDATE;
5056 node.flags = IWN_FLAG_SET_DELBA;
5057 node.delba_tid = tid;
5058 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
5059 (void)sc->sc_hal->add_node(sc, &node, 1);
5060}
5061
5062/*
5063 * This function is called by upper layer when an ADDBA response is received
5064 * from another STA.
5065 */
5066static int
5067iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5068 uint8_t tid)
5069{
5070 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5071 struct iwn_softc *sc = ic->ic_softc;
5072 const struct iwn_hal *hal = sc->sc_hal;
5073 struct iwn_node *wn = (void *)ni;
5074 struct iwn_node_info node;
5075 int error;
5076
5077 /* Enable TX for the specified RA/TID. */
5078 wn->disable_tid &= ~(1 << tid);
5079 memset(&node, 0, sizeof node);
5080 node.id = wn->id;
5081 node.control = IWN_NODE_UPDATE;
5082 node.flags = IWN_FLAG_SET_DISABLE_TID;
5083 node.disable_tid = htole16(wn->disable_tid);
5084 error = hal->add_node(sc, &node, 1);
5085 if (error != 0)
5086 return error;
5087
5088 if ((error = iwn_nic_lock(sc)) != 0)
5089 return error;
5090 hal->ampdu_tx_start(sc, ni, tid, ba->ba_winstart);
5091 iwn_nic_unlock(sc);
5092 return 0;
5093}
5094
5095static void
5096iwn_ampdu_tx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
5097 uint8_t tid)
5098{
5099 struct ieee80211_tx_ba *ba = &ni->ni_tx_ba[tid];
5100 struct iwn_softc *sc = ic->ic_softc;
5101 int error;
5102
5103 error = iwn_nic_lock(sc);
5104 if (error != 0)
5105 return;
5106 sc->sc_hal->ampdu_tx_stop(sc, tid, ba->ba_winstart);
5107 iwn_nic_unlock(sc);
5108}
5109
5110static void
5111iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5112 uint8_t tid, uint16_t ssn)
5113{
5114 struct iwn_node *wn = (void *)ni;
5115 int qid = 7 + tid;
5116
5117 /* Stop TX scheduler while we're changing its configuration. */
5118 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5119 IWN4965_TXQ_STATUS_CHGACT);
5120
5121 /* Assign RA/TID translation to the queue. */
5122 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5123 wn->id << 4 | tid);
5124
5125 /* Enable chain-building mode for the queue. */
5126 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5127
5128 /* Set starting sequence number from the ADDBA request. */
5129 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5130 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5131
5132 /* Set scheduler window size. */
5133 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5134 IWN_SCHED_WINSZ);
5135 /* Set scheduler frame limit. */
5136 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5137 IWN_SCHED_LIMIT << 16);
5138
5139 /* Enable interrupts for the queue. */
5140 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5141
5142 /* Mark the queue as active. */
5143 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5144 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5145 iwn_tid2fifo[tid] << 1);
5146}
5147
5148static void
5149iwn4965_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5150{
5151 int qid = 7 + tid;
5152
5153 /* Stop TX scheduler while we're changing its configuration. */
5154 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5155 IWN4965_TXQ_STATUS_CHGACT);
5156
5157 /* Set starting sequence number from the ADDBA request. */
5158 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5159 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5160
5161 /* Disable interrupts for the queue. */
5162 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5163
5164 /* Mark the queue as inactive. */
5165 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5166 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5167}
5168
5169static void
5170iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5171 uint8_t tid, uint16_t ssn)
5172{
5173 struct iwn_node *wn = (void *)ni;
5174 int qid = 10 + tid;
5175
5176 /* Stop TX scheduler while we're changing its configuration. */
5177 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5178 IWN5000_TXQ_STATUS_CHGACT);
5179
5180 /* Assign RA/TID translation to the queue. */
5181 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5182 wn->id << 4 | tid);
5183
5184 /* Enable chain-building mode for the queue. */
5185 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5186
5187 /* Enable aggregation for the queue. */
5188 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5189
5190 /* Set starting sequence number from the ADDBA request. */
5191 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5192 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5193
5194 /* Set scheduler window size and frame limit. */
5195 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5196 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5197
5198 /* Enable interrupts for the queue. */
5199 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5200
5201 /* Mark the queue as active. */
5202 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5203 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5204}
5205
5206static void
5207iwn5000_ampdu_tx_stop(struct iwn_softc *sc, uint8_t tid, uint16_t ssn)
5208{
5209 int qid = 10 + tid;
5210
5211 /* Stop TX scheduler while we're changing its configuration. */
5212 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5213 IWN5000_TXQ_STATUS_CHGACT);
5214
5215 /* Disable aggregation for the queue. */
5216 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5217
5218 /* Set starting sequence number from the ADDBA request. */
5219 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5220 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5221
5222 /* Disable interrupts for the queue. */
5223 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5224
5225 /* Mark the queue as inactive. */
5226 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5227 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5228}
5229#endif
5230
5231/*
5232 * Query calibration tables from the initialization firmware. We do this
5233 * only once at first boot. Called from a process context.
5234 */
5235static int
5236iwn5000_query_calibration(struct iwn_softc *sc)
5237{
5238 struct iwn5000_calib_config cmd;
5239 int error;
5240
5241 memset(&cmd, 0, sizeof cmd);
5242 cmd.ucode.once.enable = 0xffffffff;
5243 cmd.ucode.once.start = 0xffffffff;
5244 cmd.ucode.once.send = 0xffffffff;
5245 cmd.ucode.flags = 0xffffffff;
5246 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
5247 __func__);
5248 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5249 if (error != 0)
5250 return error;
5251
5252 /* Wait at most two seconds for calibration to complete. */
5253 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
3db796ac 5254 error = zsleep(sc, sc->sc_ifp->if_serializer, 0, "iwninit", 2 * hz);
ffd7c74a
JT		 5255 return error;
5256}
5257
5258/*
5259 * Send calibration results to the runtime firmware. These results were
5260 * obtained on first boot from the initialization firmware.
5261 */
5262static int
5263iwn5000_send_calibration(struct iwn_softc *sc)
5264{
5265 int idx, error;
5266
5267 for (idx = 0; idx < 5; idx++) {
5268 if (sc->calibcmd[idx].buf == NULL)
5269 continue; /* No results available. */
5270 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5271 "send calibration result idx=%d len=%d\n",
5272 idx, sc->calibcmd[idx].len);
5273 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5274 sc->calibcmd[idx].len, 0);
5275 if (error != 0) {
5276 device_printf(sc->sc_dev,
5277 "%s: could not send calibration result, error %d\n",
5278 __func__, error);
5279 return error;
5280 }
5281 }
5282 return 0;
5283}
5284
5285static int
5286iwn5000_send_wimax_coex(struct iwn_softc *sc)
5287{
5288 struct iwn5000_wimax_coex wimax;
5289
5290#ifdef notyet
5291 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5292 /* Enable WiMAX coexistence for combo adapters. */
5293 wimax.flags =
5294 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5295 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5296 IWN_WIMAX_COEX_STA_TABLE_VALID |
5297 IWN_WIMAX_COEX_ENABLE;
5298 memcpy(wimax.events, iwn6050_wimax_events,
5299 sizeof iwn6050_wimax_events);
5300 } else
5301#endif
5302 {
5303 /* Disable WiMAX coexistence. */
5304 wimax.flags = 0;
5305 memset(wimax.events, 0, sizeof wimax.events);
5306 }
5307 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
5308 __func__);
5309 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5310}
5311
5312/*
5313 * This function is called after the runtime firmware notifies us of its
5314 * readiness (called in a process context.)
5315 */
5316static int
5317iwn4965_post_alive(struct iwn_softc *sc)
5318{
5319 int error, qid;
5320
5321 if ((error = iwn_nic_lock(sc)) != 0)
5322 return error;
5323
5324 /* Clear TX scheduler state in SRAM. */
5325 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5326 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5327 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5328
5329 /* Set physical address of TX scheduler rings (1KB aligned.) */
5330 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5331
5332 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5333
5334 /* Disable chain mode for all our 16 queues. */
5335 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5336
5337 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5338 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5339 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5340
5341 /* Set scheduler window size. */
5342 iwn_mem_write(sc, sc->sched_base +
5343 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5344 /* Set scheduler frame limit. */
5345 iwn_mem_write(sc, sc->sched_base +
5346 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5347 IWN_SCHED_LIMIT << 16);
5348 }
5349
5350 /* Enable interrupts for all our 16 queues. */
5351 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
5352 /* Identify TX FIFO rings (0-7). */
5353 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
5354
5355 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5356 for (qid = 0; qid < 7; qid++) {
5357 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
5358 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5359 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
5360 }
5361 iwn_nic_unlock(sc);
5362 return 0;
5363}
5364
5365/*
5366 * This function is called after the initialization or runtime firmware
5367 * notifies us of its readiness (called in a process context.)
5368 */
5369static int
5370iwn5000_post_alive(struct iwn_softc *sc)
5371{
5372 int error, qid;
5373
5374 /* Switch to using ICT interrupt mode. */
5375 iwn5000_ict_reset(sc);
5376
5377 error = iwn_nic_lock(sc);
5378 if (error != 0)
5379 return error;
5380
5381 /* Clear TX scheduler state in SRAM. */
5382 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5383 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
5384 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
5385
5386 /* Set physical address of TX scheduler rings (1KB aligned.) */
5387 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5388
5389 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5390
5391 /* Enable chain mode for all queues, except command queue. */
5392 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
5393 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
5394
5395 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
5396 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
5397 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5398
5399 iwn_mem_write(sc, sc->sched_base +
5400 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
5401 /* Set scheduler window size and frame limit. */
5402 iwn_mem_write(sc, sc->sched_base +
5403 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5404 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5405 }
5406
5407 /* Enable interrupts for all our 20 queues. */
5408 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
5409 /* Identify TX FIFO rings (0-7). */
5410 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
5411
5412 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
5413 for (qid = 0; qid < 7; qid++) {
5414 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
5415 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5416 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
5417 }
5418 iwn_nic_unlock(sc);
5419
5420 /* Configure WiMAX coexistence for combo adapters. */
5421 error = iwn5000_send_wimax_coex(sc);
5422 if (error != 0) {
5423 device_printf(sc->sc_dev,
5424 "%s: could not configure WiMAX coexistence, error %d\n",
5425 __func__, error);
5426 return error;
5427 }
5428 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
5429 struct iwn5000_phy_calib_crystal cmd;
5430
5431 /* Perform crystal calibration. */
5432 memset(&cmd, 0, sizeof cmd);
5433 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5434 cmd.ngroups = 1;
5435 cmd.isvalid = 1;
5436 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5437 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5438 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5439 "sending crystal calibration %d, %d\n",
5440 cmd.cap_pin[0], cmd.cap_pin[1]);
5441 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5442 if (error != 0) {
5443 device_printf(sc->sc_dev,
5444 "%s: crystal calibration failed, error %d\n",
5445 __func__, error);
5446 return error;
5447 }
5448 }
5449 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
5450 /* Query calibration from the initialization firmware. */
5451 error = iwn5000_query_calibration(sc);
5452 if (error != 0) {
5453 device_printf(sc->sc_dev,
5454 "%s: could not query calibration, error %d\n",
5455 __func__, error);
5456 return error;
5457 }
5458 /*
5459 * We have the calibration results now, reboot with the
5460 * runtime firmware (call ourselves recursively!)
5461 */
5462 iwn_hw_stop(sc);
5463 error = iwn_hw_init(sc);
5464 } else {
5465 /* Send calibration results to runtime firmware. */
5466 error = iwn5000_send_calibration(sc);
5467 }
5468 return error;
5469}
5470
5471/*
5472 * The firmware boot code is small and is intended to be copied directly into
5473 * the NIC internal memory (no DMA transfer.)
5474 */
5475static int
5476iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
5477{
5478 int error, ntries;
5479
5480 size /= sizeof (uint32_t);
5481
5482 error = iwn_nic_lock(sc);
5483 if (error != 0)
5484 return error;
5485
5486 /* Copy microcode image into NIC memory. */
5487 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
5488 (const uint32_t *)ucode, size);
5489
5490 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
5491 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
5492 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
5493
5494 /* Start boot load now. */
5495 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
5496
5497 /* Wait for transfer to complete. */
5498 for (ntries = 0; ntries < 1000; ntries++) {
5499 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
5500 IWN_BSM_WR_CTRL_START))
5501 break;
5502 DELAY(10);
5503 }
5504 if (ntries == 1000) {
5505 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
5506 __func__);
5507 iwn_nic_unlock(sc);
5508 return ETIMEDOUT;
5509 }
5510
5511 /* Enable boot after power up. */
5512 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
5513
5514 iwn_nic_unlock(sc);
5515 return 0;
5516}
5517
5518static int
5519iwn4965_load_firmware(struct iwn_softc *sc)
5520{
5521 struct iwn_fw_info *fw = &sc->fw;
5522 struct iwn_dma_info *dma = &sc->fw_dma;
5523 int error;
5524
5525 /* Copy initialization sections into pre-allocated DMA-safe memory. */
5526 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
5527 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5528 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5529 fw->init.text, fw->init.textsz);
5530 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5531
5532 /* Tell adapter where to find initialization sections. */
5533 error = iwn_nic_lock(sc);
5534 if (error != 0)
5535 return error;
5536 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5537 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
5538 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5539 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5540 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
5541 iwn_nic_unlock(sc);
5542
5543 /* Load firmware boot code. */
5544 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
5545 if (error != 0) {
5546 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
5547 __func__);
5548 return error;
5549 }
5550 /* Now press "execute". */
5551 IWN_WRITE(sc, IWN_RESET, 0);
5552
5553 /* Wait at most one second for first alive notification. */
3db796ac 5554 error = zsleep(sc, sc->sc_ifp->if_serializer, 0, "iwninit", hz);
ffd7c74a
JT		 5555 if (error) {
5556 device_printf(sc->sc_dev,
5557 "%s: timeout waiting for adapter to initialize, error %d\n",
5558 __func__, error);
5559 return error;
5560 }
5561
5562 /* Retrieve current temperature for initial TX power calibration. */
5563 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
5564 sc->temp = iwn4965_get_temperature(sc);
5565
5566 /* Copy runtime sections into pre-allocated DMA-safe memory. */
5567 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
5568 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5569 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
5570 fw->main.text, fw->main.textsz);
5571 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5572
5573 /* Tell adapter where to find runtime sections. */
5574 error = iwn_nic_lock(sc);
5575 if (error != 0)
5576 return error;
5577
5578 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
5579 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
5580 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
5581 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
5582 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
5583 IWN_FW_UPDATED | fw->main.textsz);
5584 iwn_nic_unlock(sc);
5585
5586 return 0;
5587}
5588
5589static int
5590iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
5591 const uint8_t *section, int size)
5592{
5593 struct iwn_dma_info *dma = &sc->fw_dma;
5594 int error;
5595
5596 /* Copy firmware section into pre-allocated DMA-safe memory. */
5597 memcpy(dma->vaddr, section, size);
5598 bus_dmamap_sync(sc->fw_dma.tag, dma->map, BUS_DMASYNC_PREWRITE);
5599
5600 error = iwn_nic_lock(sc);
5601 if (error != 0)
5602 return error;
5603
5604 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5605 IWN_FH_TX_CONFIG_DMA_PAUSE);
5606
5607 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
5608 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
5609 IWN_LOADDR(dma->paddr));
5610 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
5611 IWN_HIADDR(dma->paddr) << 28 | size);
5612 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
5613 IWN_FH_TXBUF_STATUS_TBNUM(1) |
5614 IWN_FH_TXBUF_STATUS_TBIDX(1) |
5615 IWN_FH_TXBUF_STATUS_TFBD_VALID);
5616
5617 /* Kick Flow Handler to start DMA transfer. */
5618 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
5619 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
5620
5621 iwn_nic_unlock(sc);
5622
5623 /* Wait at most five seconds for FH DMA transfer to complete. */
3db796ac 5624 return zsleep(sc, sc->sc_ifp->if_serializer, 0, "iwninit", hz);
ffd7c74a
JT		 5625}
5626
5627static int
5628iwn5000_load_firmware(struct iwn_softc *sc)
5629{
5630 struct iwn_fw_part *fw;
5631 int error;
5632
5633 /* Load the initialization firmware on first boot only. */
5634 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
5635 &sc->fw.main : &sc->fw.init;
5636
5637 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
5638 fw->text, fw->textsz);
5639 if (error != 0) {
5640 device_printf(sc->sc_dev,
5641 "%s: could not load firmware %s section, error %d\n",
5642 __func__, ".text", error);
5643 return error;
5644 }
5645 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
5646 fw->data, fw->datasz);
5647 if (error != 0) {
5648 device_printf(sc->sc_dev,
5649 "%s: could not load firmware %s section, error %d\n",
5650 __func__, ".data", error);
5651 return error;
5652 }
5653
5654 /* Now press "execute". */
5655 IWN_WRITE(sc, IWN_RESET, 0);
5656 return 0;
5657}
5658
5659static int
5660iwn_read_firmware(struct iwn_softc *sc)
5661{
5662 const struct iwn_hal *hal = sc->sc_hal;
5663 struct iwn_fw_info *fw = &sc->fw;
5664 const uint32_t *ptr;
5665 uint32_t rev;
5666 size_t size;
5667
5668 IWN_UNLOCK(sc);
5669
5670 /* Read firmware image from filesystem. */
5671 sc->fw_fp = firmware_get(sc->fwname);
5672 if (sc->fw_fp == NULL) {
5673 device_printf(sc->sc_dev,
5674 "%s: could not load firmare image \"%s\"\n", __func__,
5675 sc->fwname);
5676 IWN_LOCK(sc);
5677 return EINVAL;
5678 }
5679 IWN_LOCK(sc);
5680
5681 size = sc->fw_fp->datasize;
5682 if (size < 28) {
5683 device_printf(sc->sc_dev,
5684 "%s: truncated firmware header: %zu bytes\n",
5685 __func__, size);
5686 return EINVAL;
5687 }
5688
5689 /* Process firmware header. */
5690 ptr = (const uint32_t *)sc->fw_fp->data;
5691 rev = le32toh(*ptr++);
5692 /* Check firmware API version. */
5693 if (IWN_FW_API(rev) <= 1) {
5694 device_printf(sc->sc_dev,
5695 "%s: bad firmware, need API version >=2\n", __func__);
5696 return EINVAL;
5697 }
5698 if (IWN_FW_API(rev) >= 3) {
5699 /* Skip build number (version 2 header). */
5700 size -= 4;
5701 ptr++;
5702 }
5703 fw->main.textsz = le32toh(*ptr++);
5704 fw->main.datasz = le32toh(*ptr++);
5705 fw->init.textsz = le32toh(*ptr++);
5706 fw->init.datasz = le32toh(*ptr++);
5707 fw->boot.textsz = le32toh(*ptr++);
5708 size -= 24;
5709
5710 /* Sanity-check firmware header. */
5711 if (fw->main.textsz > hal->fw_text_maxsz ||
5712 fw->main.datasz > hal->fw_data_maxsz ||
5713 fw->init.textsz > hal->fw_text_maxsz ||
5714 fw->init.datasz > hal->fw_data_maxsz ||
5715 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
5716 (fw->boot.textsz & 3) != 0) {
5717 device_printf(sc->sc_dev, "%s: invalid firmware header\n",
5718 __func__);
5719 return EINVAL;
5720 }
5721
5722 /* Check that all firmware sections fit. */
5723 if (fw->main.textsz + fw->main.datasz + fw->init.textsz +
5724 fw->init.datasz + fw->boot.textsz > size) {
5725 device_printf(sc->sc_dev,
5726 "%s: firmware file too short: %zu bytes\n",
5727 __func__, size);
5728 return EINVAL;
5729 }
5730
5731 /* Get pointers to firmware sections. */
5732 fw->main.text = (const uint8_t *)ptr;
5733 fw->main.data = fw->main.text + fw->main.textsz;
5734 fw->init.text = fw->main.data + fw->main.datasz;
5735 fw->init.data = fw->init.text + fw->init.textsz;
5736 fw->boot.text = fw->init.data + fw->init.datasz;
5737
5738 return 0;
5739}
5740
5741static int
5742iwn_clock_wait(struct iwn_softc *sc)
5743{
5744 int ntries;
5745
5746 /* Set "initialization complete" bit. */
5747 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5748
5749 /* Wait for clock stabilization. */
5750 for (ntries = 0; ntries < 2500; ntries++) {
5751 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
5752 return 0;
5753 DELAY(10);
5754 }
5755 device_printf(sc->sc_dev,
5756 "%s: timeout waiting for clock stabilization\n", __func__);
5757 return ETIMEDOUT;
5758}
5759
5760static int
5761iwn_apm_init(struct iwn_softc *sc)
5762{
5763 uint32_t tmp;
5764 int error;
5765
5766 /* Disable L0s exit timer (NMI bug workaround.) */
5767 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
5768 /* Don't wait for ICH L0s (ICH bug workaround.) */
5769 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
5770
5771 /* Set FH wait threshold to max (HW bug under stress workaround.) */
5772 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
5773
5774 /* Enable HAP INTA to move adapter from L1a to L0s. */
5775 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
5776
5777 /* Retrieve PCIe Active State Power Management (ASPM). */
5778 tmp = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
5779 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
5780 if (tmp & 0x02) /* L1 Entry enabled. */
5781 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5782 else
5783 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
5784
5785 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
5786 sc->hw_type != IWN_HW_REV_TYPE_6000 &&
5787 sc->hw_type != IWN_HW_REV_TYPE_6050)
5788 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
5789
5790 /* Wait for clock stabilization before accessing prph. */
5791 error = iwn_clock_wait(sc);
5792 if (error != 0)
5793 return error;
5794
5795 error = iwn_nic_lock(sc);
5796 if (error != 0)
5797 return error;
5798
5799 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
5800 /* Enable DMA and BSM (Bootstrap State Machine.) */
5801 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5802 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
5803 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
5804 } else {
5805 /* Enable DMA. */
5806 iwn_prph_write(sc, IWN_APMG_CLK_EN,
5807 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
5808 }
5809 DELAY(20);
5810
5811 /* Disable L1-Active. */
5812 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
5813 iwn_nic_unlock(sc);
5814
5815 return 0;
5816}
5817
5818static void
5819iwn_apm_stop_master(struct iwn_softc *sc)
5820{
5821 int ntries;
5822
5823 /* Stop busmaster DMA activity. */
5824 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
5825 for (ntries = 0; ntries < 100; ntries++) {
5826 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
5827 return;
5828 DELAY(10);
5829 }
5830 device_printf(sc->sc_dev, "%s: timeout waiting for master\n",
5831 __func__);
5832}
5833
5834static void
5835iwn_apm_stop(struct iwn_softc *sc)
5836{
5837 iwn_apm_stop_master(sc);
5838
5839 /* Reset the entire device. */
5840 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
5841 DELAY(10);
5842 /* Clear "initialization complete" bit. */
5843 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
5844}
5845
5846static int
5847iwn4965_nic_config(struct iwn_softc *sc)
5848{
5849 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
5850 /*
5851 * I don't believe this to be correct but this is what the
5852 * vendor driver is doing. Probably the bits should not be
5853 * shifted in IWN_RFCFG_*.
5854 */
5855 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5856 IWN_RFCFG_TYPE(sc->rfcfg) |
5857 IWN_RFCFG_STEP(sc->rfcfg) |
5858 IWN_RFCFG_DASH(sc->rfcfg));
5859 }
5860 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5861 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
5862 return 0;
5863}
5864
5865static int
5866iwn5000_nic_config(struct iwn_softc *sc)
5867{
5868 uint32_t tmp;
5869 int error;
5870
5871 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
5872 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5873 IWN_RFCFG_TYPE(sc->rfcfg) |
5874 IWN_RFCFG_STEP(sc->rfcfg) |
5875 IWN_RFCFG_DASH(sc->rfcfg));
5876 }
5877 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
5878 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
5879
5880 error = iwn_nic_lock(sc);
5881 if (error != 0)
5882 return error;
5883 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
5884
5885 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
5886 /*
5887 * Select first Switching Voltage Regulator (1.32V) to
5888 * solve a stability issue related to noisy DC2DC line
5889 * in the silicon of 1000 Series.
5890 */
5891 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
5892 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
5893 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
5894 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
5895 }
5896 iwn_nic_unlock(sc);
5897
5898 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
5899 /* Use internal power amplifier only. */
5900 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
5901 }
5902 if (sc->hw_type == IWN_HW_REV_TYPE_6050 && sc->calib_ver >= 6) {
5903 /* Indicate that ROM calibration version is >=6. */
5904 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
5905 }
5906 return 0;
5907}
5908
5909/*
5910 * Take NIC ownership over Intel Active Management Technology (AMT).
5911 */
5912static int
5913iwn_hw_prepare(struct iwn_softc *sc)
5914{
5915 int ntries;
5916
5917 /* Check if hardware is ready. */
5918 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
5919 for (ntries = 0; ntries < 5; ntries++) {
5920 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
5921 IWN_HW_IF_CONFIG_NIC_READY)
5922 return 0;
5923 DELAY(10);
5924 }
5925
5926 /* Hardware not ready, force into ready state. */
5927 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
5928 for (ntries = 0; ntries < 15000; ntries++) {
5929 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
5930 IWN_HW_IF_CONFIG_PREPARE_DONE))
5931 break;
5932 DELAY(10);
5933 }
5934 if (ntries == 15000)
5935 return ETIMEDOUT;
5936
5937 /* Hardware should be ready now. */
5938 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
5939 for (ntries = 0; ntries < 5; ntries++) {
5940 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
5941 IWN_HW_IF_CONFIG_NIC_READY)
5942 return 0;
5943 DELAY(10);
5944 }
5945 return ETIMEDOUT;
5946}
5947
5948static int
5949iwn_hw_init(struct iwn_softc *sc)
5950{
5951 const struct iwn_hal *hal = sc->sc_hal;
5952 int error, chnl, qid;
5953
5954 /* Clear pending interrupts. */
5955 IWN_WRITE(sc, IWN_INT, 0xffffffff);
5956
5957 error = iwn_apm_init(sc);
5958 if (error != 0) {
5959 device_printf(sc->sc_dev,
5960 "%s: could not power ON adapter, error %d\n",
5961 __func__, error);
5962 return error;
5963 }
5964
5965 /* Select VMAIN power source. */
5966 error = iwn_nic_lock(sc);
5967 if (error != 0)
5968 return error;
5969 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
5970 iwn_nic_unlock(sc);
5971
5972 /* Perform adapter-specific initialization. */
5973 error = hal->nic_config(sc);
5974 if (error != 0)
5975 return error;
5976
5977 /* Initialize RX ring. */
5978 error = iwn_nic_lock(sc);
5979 if (error != 0)
5980 return error;
5981 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
5982 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
5983 /* Set physical address of RX ring (256-byte aligned.) */
5984 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
5985 /* Set physical address of RX status (16-byte aligned.) */
5986 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
5987 /* Enable RX. */
5988 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
5989 IWN_FH_RX_CONFIG_ENA |
5990 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
5991 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
5992 IWN_FH_RX_CONFIG_SINGLE_FRAME |
5993 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
5994 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
5995 iwn_nic_unlock(sc);
5996 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
5997
5998 error = iwn_nic_lock(sc);
5999 if (error != 0)
6000 return error;
6001
6002 /* Initialize TX scheduler. */
6003 iwn_prph_write(sc, hal->sched_txfact_addr, 0);
6004
6005 /* Set physical address of "keep warm" page (16-byte aligned.) */
6006 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6007
6008 /* Initialize TX rings. */
6009 for (qid = 0; qid < hal->ntxqs; qid++) {
6010 struct iwn_tx_ring *txq = &sc->txq[qid];
6011
6012 /* Set physical address of TX ring (256-byte aligned.) */
6013 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6014 txq->desc_dma.paddr >> 8);
6015 }
6016 iwn_nic_unlock(sc);
6017
6018 /* Enable DMA channels. */
6019 for (chnl = 0; chnl < hal->ndmachnls; chnl++) {
6020 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6021 IWN_FH_TX_CONFIG_DMA_ENA |
6022 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6023 }
6024
6025 /* Clear "radio off" and "commands blocked" bits. */
6026 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6027 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6028
6029 /* Clear pending interrupts. */
6030 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6031 /* Enable interrupt coalescing. */
6032 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6033 /* Enable interrupts. */
6034 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6035
6036 /* _Really_ make sure "radio off" bit is cleared! */
6037 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6038 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6039
6040 error = hal->load_firmware(sc);
6041 if (error != 0) {
6042 device_printf(sc->sc_dev,
6043 "%s: could not load firmware, error %d\n",
6044 __func__, error);
6045 return error;
6046 }
6047 /* Wait at most one second for firmware alive notification. */
3db796ac 6048 error = zsleep(sc, sc->sc_ifp->if_serializer, 0, "iwninit", hz);
ffd7c74a
JT		 6049 if (error != 0) {
6050 device_printf(sc->sc_dev,
6051 "%s: timeout waiting for adapter to initialize, error %d\n",
6052 __func__, error);
6053 return error;
6054 }
6055 /* Do post-firmware initialization. */
6056 return hal->post_alive(sc);
6057}
6058
6059static void
6060iwn_hw_stop(struct iwn_softc *sc)
6061{
6062 const struct iwn_hal *hal = sc->sc_hal;
6063 uint32_t tmp;
6064 int chnl, qid, ntries;
6065
6066 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6067
6068 /* Disable interrupts. */
6069 IWN_WRITE(sc, IWN_INT_MASK, 0);
6070 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6071 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6072 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6073
6074 /* Make sure we no longer hold the NIC lock. */
6075 iwn_nic_unlock(sc);
6076
6077 /* Stop TX scheduler. */
6078 iwn_prph_write(sc, hal->sched_txfact_addr, 0);
6079
6080 /* Stop all DMA channels. */
6081 if (iwn_nic_lock(sc) == 0) {
6082 for (chnl = 0; chnl < hal->ndmachnls; chnl++) {
6083 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6084 for (ntries = 0; ntries < 200; ntries++) {
6085 tmp = IWN_READ(sc, IWN_FH_TX_STATUS);
6086 if ((tmp & IWN_FH_TX_STATUS_IDLE(chnl)) ==
6087 IWN_FH_TX_STATUS_IDLE(chnl))
6088 break;
6089 DELAY(10);
6090 }
6091 }
6092 iwn_nic_unlock(sc);
6093 }
6094
6095 /* Stop RX ring. */
6096 iwn_reset_rx_ring(sc, &sc->rxq);
6097
6098 /* Reset all TX rings. */
6099 for (qid = 0; qid < hal->ntxqs; qid++)
6100 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6101
6102 if (iwn_nic_lock(sc) == 0) {
6103 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6104 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6105 iwn_nic_unlock(sc);
6106 }
6107 DELAY(5);
6108
6109 /* Power OFF adapter. */
6110 iwn_apm_stop(sc);
6111}
6112
6113static void
6114iwn_init_locked(struct iwn_softc *sc)
6115{
6116 struct ifnet *ifp = sc->sc_ifp;
6117 int error;
6118
6119 IWN_LOCK_ASSERT(sc);
6120
6121 error = iwn_hw_prepare(sc);
6122 if (error != 0) {
6123 device_printf(sc->sc_dev, "%s: hardware not ready, eror %d\n",
6124 __func__, error);
6125 goto fail;
6126 }
6127
6128 /* Initialize interrupt mask to default value. */
6129 sc->int_mask = IWN_INT_MASK_DEF;
6130 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6131
6132 /* Check that the radio is not disabled by hardware switch. */
6133 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6134 device_printf(sc->sc_dev,
6135 "radio is disabled by hardware switch\n");
6136
6137 /* Enable interrupts to get RF toggle notifications. */
6138 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6139 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6140 return;
6141 }
6142
6143 /* Read firmware images from the filesystem. */
6144 error = iwn_read_firmware(sc);
6145 if (error != 0) {
6146 device_printf(sc->sc_dev,
6147 "%s: could not read firmware, error %d\n",
6148 __func__, error);
6149 goto fail;
6150 }
6151
6152 /* Initialize hardware and upload firmware. */
6153 error = iwn_hw_init(sc);
6154 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6155 sc->fw_fp = NULL;
6156 if (error != 0) {
6157 device_printf(sc->sc_dev,
6158 "%s: could not initialize hardware, error %d\n",
6159 __func__, error);
6160 goto fail;
6161 }
6162
6163 /* Configure adapter now that it is ready. */
6164 error = iwn_config(sc);
6165 if (error != 0) {
6166 device_printf(sc->sc_dev,
6167 "%s: could not configure device, error %d\n",
6168 __func__, error);
6169 goto fail;
6170 }
6171
3db796ac
JT		 6172 ifp->if_flags &= ~IFF_OACTIVE;
6173 ifp->if_flags |= IFF_RUNNING;
ffd7c74a
JT		 6174
6175 return;
6176
6177fail:
6178 iwn_stop_locked(sc);
6179}
6180
6181static void
6182iwn_init(void *arg)
6183{
6184 struct iwn_softc *sc = arg;
6185 struct ifnet *ifp = sc->sc_ifp;
6186 struct ieee80211com *ic = ifp->if_l2com;
6187
6188 IWN_LOCK(sc);
6189 iwn_init_locked(sc);
6190 IWN_UNLOCK(sc);
6191
3db796ac 6192 if (ifp->if_flags & IFF_RUNNING)
ffd7c74a
JT		 6193 ieee80211_start_all(ic);
6194}
6195
6196static void
6197iwn_stop_locked(struct iwn_softc *sc)
6198{
6199 struct ifnet *ifp = sc->sc_ifp;
6200
6201 IWN_LOCK_ASSERT(sc);
6202
6203 sc->sc_tx_timer = 0;
6204 callout_stop(&sc->sc_timer_to);
3db796ac 6205 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ffd7c74a
JT		 6206
6207 /* Power OFF hardware. */
6208 iwn_hw_stop(sc);
6209}
6210
6211static void
6212iwn_stop(struct iwn_softc *sc)
6213{
6214 IWN_LOCK(sc);
6215 iwn_stop_locked(sc);
6216 IWN_UNLOCK(sc);
6217}
6218
6219/*
6220 * Callback from net80211 to start a scan.
6221 */
6222static void
6223iwn_scan_start(struct ieee80211com *ic)
6224{
6225 struct ifnet *ifp = ic->ic_ifp;
6226 struct iwn_softc *sc = ifp->if_softc;
6227
6228 IWN_LOCK(sc);
6229 /* make the link LED blink while we're scanning */
6230 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
6231 IWN_UNLOCK(sc);
6232}
6233
6234/*
6235 * Callback from net80211 to terminate a scan.
6236 */
6237static void
6238iwn_scan_end(struct ieee80211com *ic)
6239{
6240 struct ifnet *ifp = ic->ic_ifp;
6241 struct iwn_softc *sc = ifp->if_softc;
6242 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6243
6244 IWN_LOCK(sc);
6245 if (vap->iv_state == IEEE80211_S_RUN) {
6246 /* Set link LED to ON status if we are associated */
6247 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
6248 }
6249 IWN_UNLOCK(sc);
6250}
6251
6252/*
6253 * Callback from net80211 to force a channel change.
6254 */
6255static void
6256iwn_set_channel(struct ieee80211com *ic)
6257{
6258 const struct ieee80211_channel *c = ic->ic_curchan;
6259 struct ifnet *ifp = ic->ic_ifp;
6260 struct iwn_softc *sc = ifp->if_softc;
6261
6262 IWN_LOCK(sc);
6263 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
6264 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
6265 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
6266 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
6267 IWN_UNLOCK(sc);
6268}
6269
6270/*
6271 * Callback from net80211 to start scanning of the current channel.
6272 */
6273static void
6274iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
6275{
6276 struct ieee80211vap *vap = ss->ss_vap;
6277 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6278 int error;
6279
6280 IWN_LOCK(sc);
6281 error = iwn_scan(sc);
6282 IWN_UNLOCK(sc);
6283 if (error != 0)
6284 ieee80211_cancel_scan(vap);
6285}
6286
6287/*
6288 * Callback from net80211 to handle the minimum dwell time being met.
6289 * The intent is to terminate the scan but we just let the firmware
6290 * notify us when it's finished as we have no safe way to abort it.
6291 */
6292static void
6293iwn_scan_mindwell(struct ieee80211_scan_state *ss)
6294{
6295 /* NB: don't try to abort scan; wait for firmware to finish */
6296}
6297
6298static struct iwn_eeprom_chan *
6299iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
6300{
6301 int i, j;
6302
6303 for (j = 0; j < 7; j++) {
6304 for (i = 0; i < iwn_bands[j].nchan; i++) {
6305 if (iwn_bands[j].chan[i] == c->ic_ieee)
6306 return &sc->eeprom_channels[j][i];
6307 }
6308 }
6309
6310 return NULL;
6311}
6312
6313/*
6314 * Enforce flags read from EEPROM.
6315 */
6316static int
6317iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
6318 int nchan, struct ieee80211_channel chans[])
6319{
6320 struct iwn_softc *sc = ic->ic_ifp->if_softc;
6321 int i;
6322
6323 for (i = 0; i < nchan; i++) {
6324 struct ieee80211_channel *c = &chans[i];
6325 struct iwn_eeprom_chan *channel;
6326
6327 channel = iwn_find_eeprom_channel(sc, c);
6328 if (channel == NULL) {
6329 if_printf(ic->ic_ifp,
6330 "%s: invalid channel %u freq %u/0x%x\n",
6331 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
6332 return EINVAL;
6333 }
6334 c->ic_flags |= iwn_eeprom_channel_flags(channel);
6335 }
6336
6337 return 0;
6338}
6339
6340static void
6341iwn_hw_reset(void *arg0, int pending)
6342{
6343 struct iwn_softc *sc = arg0;
6344 struct ifnet *ifp = sc->sc_ifp;
6345 struct ieee80211com *ic = ifp->if_l2com;
6346
6347 iwn_stop(sc);
6348 iwn_init(sc);
6349 ieee80211_notify_radio(ic, 1);
6350}
6351
6352static void
6353iwn_radio_on(void *arg0, int pending)
6354{
6355 struct iwn_softc *sc = arg0;
6356 struct ifnet *ifp = sc->sc_ifp;
6357 struct ieee80211com *ic = ifp->if_l2com;
6358 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6359
6360 if (vap != NULL) {
6361 iwn_init(sc);
6362 ieee80211_init(vap);
6363 }
6364}
6365
6366static void
6367iwn_radio_off(void *arg0, int pending)
6368{
6369 struct iwn_softc *sc = arg0;
6370 struct ifnet *ifp = sc->sc_ifp;
6371 struct ieee80211com *ic = ifp->if_l2com;
6372 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6373
6374 iwn_stop(sc);
6375 if (vap != NULL)
6376 ieee80211_stop(vap);
6377
6378 /* Enable interrupts to get RF toggle notification. */
6379 IWN_LOCK(sc);
6380 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6381 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6382 IWN_UNLOCK(sc);
6383}
6384
6385static void
6386iwn_sysctlattach(struct iwn_softc *sc)
6387{
3db796ac
JT		 6388 struct sysctl_ctx_list *ctx;
6389 struct sysctl_oid *tree;
6390
6391 ctx = &sc->sc_sysctl_ctx;
6392 tree = sc->sc_sysctl_tree;
6393 if (tree == NULL) {
6394 device_printf(sc->sc_dev, "can't add sysctl node\n");
6395 return;
6396 }
ffd7c74a
JT		 6397
6398#ifdef IWN_DEBUG
6399 sc->sc_debug = 0;
6400 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6401 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
6402#endif
6403}
6404
6405static int
6406iwn_shutdown(device_t dev)
6407{
6408 struct iwn_softc *sc = device_get_softc(dev);
6409
6410 iwn_stop(sc);
6411 return 0;
6412}
6413
6414static int
6415iwn_suspend(device_t dev)
6416{
6417 struct iwn_softc *sc = device_get_softc(dev);
6418 struct ifnet *ifp = sc->sc_ifp;
6419 struct ieee80211com *ic = ifp->if_l2com;
6420 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6421
6422 iwn_stop(sc);
6423 if (vap != NULL)
6424 ieee80211_stop(vap);
6425 return 0;
6426}
6427
6428static int
6429iwn_resume(device_t dev)
6430{
6431 struct iwn_softc *sc = device_get_softc(dev);
6432 struct ifnet *ifp = sc->sc_ifp;
6433 struct ieee80211com *ic = ifp->if_l2com;
6434 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6435
6436 /* Clear device-specific "PCI retry timeout" register (41h). */
6437 pci_write_config(dev, 0x41, 0, 1);
6438
6439 if (ifp->if_flags & IFF_UP) {
6440 iwn_init(sc);
6441 if (vap != NULL)
6442 ieee80211_init(vap);
3db796ac 6443 if (ifp->if_flags & IFF_RUNNING)
ffd7c74a
JT		 6444 iwn_start(ifp);
6445 }
6446 return 0;
6447}
6448
6449#ifdef IWN_DEBUG
6450static const char *
6451iwn_intr_str(uint8_t cmd)
6452{
6453 switch (cmd) {
6454 /* Notifications */
6455 case IWN_UC_READY: return "UC_READY";
6456 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE";
6457 case IWN_TX_DONE: return "TX_DONE";
6458 case IWN_START_SCAN: return "START_SCAN";
6459 case IWN_STOP_SCAN: return "STOP_SCAN";
6460 case IWN_RX_STATISTICS: return "RX_STATS";
6461 case IWN_BEACON_STATISTICS: return "BEACON_STATS";
6462 case IWN_STATE_CHANGED: return "STATE_CHANGED";
6463 case IWN_BEACON_MISSED: return "BEACON_MISSED";
6464 case IWN_RX_PHY: return "RX_PHY";
6465 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE";
6466 case IWN_RX_DONE: return "RX_DONE";
6467
6468 /* Command Notifications */
6469 case IWN_CMD_RXON: return "IWN_CMD_RXON";
6470 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC";
6471 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS";
6472 case IWN_CMD_TIMING: return "IWN_CMD_TIMING";
6473 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY";
6474 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED";
6475 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX";
6476 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG";
6477 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT";
6478 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE";
6479 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE";
6480 case IWN_CMD_SCAN: return "IWN_CMD_SCAN";
6481 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS";
6482 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER";
6483 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM";
6484 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG";
6485 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX";
6486 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP";
6487 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY";
6488 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB";
6489 }
6490 return "UNKNOWN INTR NOTIF/CMD";
6491}
6492#endif /* IWN_DEBUG */
6493
6494static device_method_t iwn_methods[] = {
6495 /* Device interface */
6496 DEVMETHOD(device_probe, iwn_probe),
6497 DEVMETHOD(device_attach, iwn_attach),
6498 DEVMETHOD(device_detach, iwn_detach),
6499 DEVMETHOD(device_shutdown, iwn_shutdown),
6500 DEVMETHOD(device_suspend, iwn_suspend),
6501 DEVMETHOD(device_resume, iwn_resume),
6502 { 0, 0 }
6503};
6504
6505static driver_t iwn_driver = {
6506 "iwn",
6507 iwn_methods,
6508 sizeof (struct iwn_softc)
6509};
6510static devclass_t iwn_devclass;
6511
6512DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0);
6513MODULE_DEPEND(iwn, pci, 1, 1, 1);
6514MODULE_DEPEND(iwn, firmware, 1, 1, 1);
6515MODULE_DEPEND(iwn, wlan, 1, 1, 1);
3db796ac 6516MODULE_DEPEND(iwn, wlan_amrr, 1, 1, 1);
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