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emx: Add TSO support
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
5330213c
SZ		 1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
8434a83b 68#include "opt_rss.h"
e6cde6e6 69#include "opt_emx.h"
5330213c
SZ		 70
71#include <sys/param.h>
72#include <sys/bus.h>
73#include <sys/endian.h>
74#include <sys/interrupt.h>
75#include <sys/kernel.h>
76#include <sys/ktr.h>
77#include <sys/malloc.h>
78#include <sys/mbuf.h>
79#include <sys/proc.h>
80#include <sys/rman.h>
81#include <sys/serialize.h>
bc197380 82#include <sys/serialize2.h>
5330213c
SZ		 83#include <sys/socket.h>
84#include <sys/sockio.h>
85#include <sys/sysctl.h>
86#include <sys/systm.h>
87
88#include <net/bpf.h>
89#include <net/ethernet.h>
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/if_dl.h>
93#include <net/if_media.h>
94#include <net/ifq_var.h>
89d8e73d 95#include <net/toeplitz.h>
9cc86e17 96#include <net/toeplitz2.h>
5330213c
SZ		 97#include <net/vlan/if_vlan_var.h>
98#include <net/vlan/if_vlan_ether.h>
b3a7093f 99#include <net/if_poll.h>
5330213c
SZ		 100
101#include <netinet/in_systm.h>
102#include <netinet/in.h>
103#include <netinet/ip.h>
104#include <netinet/tcp.h>
105#include <netinet/udp.h>
106
107#include <bus/pci/pcivar.h>
108#include <bus/pci/pcireg.h>
109
110#include <dev/netif/ig_hal/e1000_api.h>
111#include <dev/netif/ig_hal/e1000_82571.h>
112#include <dev/netif/emx/if_emx.h>
113
3f939c23
SZ		 114#ifdef EMX_RSS_DEBUG
115#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116do { \
89d8e73d 117 if (sc->rss_debug >= lvl) \
3f939c23
SZ		 118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119} while (0)
120#else /* !EMX_RSS_DEBUG */
121#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122#endif /* EMX_RSS_DEBUG */
123
8f594b38
SZ		 124#define EMX_TX_SERIALIZE 1
125#define EMX_RX_SERIALIZE 2
126
5330213c
SZ		 127#define EMX_NAME "Intel(R) PRO/1000 "
128
129#define EMX_DEVICE(id) \
130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
131#define EMX_DEVICE_NULL { 0, 0, NULL }
132
133static const struct emx_device {
134 uint16_t vid;
135 uint16_t did;
136 const char *desc;
137} emx_devices[] = {
138 EMX_DEVICE(82571EB_COPPER),
139 EMX_DEVICE(82571EB_FIBER),
140 EMX_DEVICE(82571EB_SERDES),
141 EMX_DEVICE(82571EB_SERDES_DUAL),
142 EMX_DEVICE(82571EB_SERDES_QUAD),
143 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 144 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
5330213c
SZ		 145 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
146 EMX_DEVICE(82571EB_QUAD_FIBER),
147 EMX_DEVICE(82571PT_QUAD_COPPER),
148
149 EMX_DEVICE(82572EI_COPPER),
150 EMX_DEVICE(82572EI_FIBER),
151 EMX_DEVICE(82572EI_SERDES),
152 EMX_DEVICE(82572EI),
153
154 EMX_DEVICE(82573E),
155 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(82573L),
157
158 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
160 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
161 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
162
163 EMX_DEVICE(82574L),
2d0e5700 164 EMX_DEVICE(82574LA),
5330213c
SZ		 165
166 /* required last entry */
167 EMX_DEVICE_NULL
168};
169
170static int emx_probe(device_t);
171static int emx_attach(device_t);
172static int emx_detach(device_t);
173static int emx_shutdown(device_t);
174static int emx_suspend(device_t);
175static int emx_resume(device_t);
176
177static void emx_init(void *);
178static void emx_stop(struct emx_softc *);
179static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
180static void emx_start(struct ifnet *);
b3a7093f
SZ		 181#ifdef IFPOLL_ENABLE
182static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
5330213c
SZ		 183#endif
184static void emx_watchdog(struct ifnet *);
185static void emx_media_status(struct ifnet *, struct ifmediareq *);
186static int emx_media_change(struct ifnet *);
187static void emx_timer(void *);
6d435846
SZ		 188static void emx_serialize(struct ifnet *, enum ifnet_serialize);
189static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
190static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
2c9effcf
SZ		 191#ifdef INVARIANTS
192static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
193 boolean_t);
194#endif
5330213c
SZ		 195
196static void emx_intr(void *);
4cb541ae
SZ		 197static void emx_intr_mask(void *);
198static void emx_intr_body(struct emx_softc *, boolean_t);
c39e3a1f 199static void emx_rxeof(struct emx_softc *, int, int);
5330213c
SZ		 200static void emx_txeof(struct emx_softc *);
201static void emx_tx_collect(struct emx_softc *);
202static void emx_tx_purge(struct emx_softc *);
203static void emx_enable_intr(struct emx_softc *);
204static void emx_disable_intr(struct emx_softc *);
205
071699f8
SZ		 206static int emx_dma_alloc(struct emx_softc *);
207static void emx_dma_free(struct emx_softc *);
5330213c 208static void emx_init_tx_ring(struct emx_softc *);
c39e3a1f
SZ		 209static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
210static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 211static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 212static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 213static void emx_destroy_tx_ring(struct emx_softc *, int);
c39e3a1f
SZ		 214static void emx_destroy_rx_ring(struct emx_softc *,
215 struct emx_rxdata *, int);
216static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 217static int emx_encap(struct emx_softc *, struct mbuf **);
5330213c
SZ		 218static int emx_txcsum(struct emx_softc *, struct mbuf *,
219 uint32_t *, uint32_t *);
3eb0ea09
SZ		 220static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
221static int emx_tso_setup(struct emx_softc *, struct mbuf *,
222 uint32_t *, uint32_t *);
5330213c
SZ		 223
224static int emx_is_valid_eaddr(const uint8_t *);
2d0e5700 225static int emx_reset(struct emx_softc *);
5330213c
SZ		 226static void emx_setup_ifp(struct emx_softc *);
227static void emx_init_tx_unit(struct emx_softc *);
228static void emx_init_rx_unit(struct emx_softc *);
229static void emx_update_stats(struct emx_softc *);
230static void emx_set_promisc(struct emx_softc *);
231static void emx_disable_promisc(struct emx_softc *);
232static void emx_set_multi(struct emx_softc *);
233static void emx_update_link_status(struct emx_softc *);
234static void emx_smartspeed(struct emx_softc *);
2d0e5700 235static void emx_set_itr(struct emx_softc *, uint32_t);
6d5e2922 236static void emx_disable_aspm(struct emx_softc *);
5330213c
SZ		 237
238static void emx_print_debug_info(struct emx_softc *);
239static void emx_print_nvm_info(struct emx_softc *);
240static void emx_print_hw_stats(struct emx_softc *);
241
242static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
243static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
244static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
245static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
246static void emx_add_sysctl(struct emx_softc *);
247
bca7c435
SZ		 248static void emx_serialize_skipmain(struct emx_softc *);
249static void emx_deserialize_skipmain(struct emx_softc *);
250
5330213c
SZ		 251/* Management and WOL Support */
252static void emx_get_mgmt(struct emx_softc *);
253static void emx_rel_mgmt(struct emx_softc *);
254static void emx_get_hw_control(struct emx_softc *);
255static void emx_rel_hw_control(struct emx_softc *);
256static void emx_enable_wol(device_t);
257
258static device_method_t emx_methods[] = {
259 /* Device interface */
260 DEVMETHOD(device_probe, emx_probe),
261 DEVMETHOD(device_attach, emx_attach),
262 DEVMETHOD(device_detach, emx_detach),
263 DEVMETHOD(device_shutdown, emx_shutdown),
264 DEVMETHOD(device_suspend, emx_suspend),
265 DEVMETHOD(device_resume, emx_resume),
266 { 0, 0 }
267};
268
269static driver_t emx_driver = {
270 "emx",
271 emx_methods,
272 sizeof(struct emx_softc),
273};
274
275static devclass_t emx_devclass;
276
277DECLARE_DUMMY_MODULE(if_emx);
278MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
aa2b9d05 279DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
5330213c
SZ		 280
281/*
282 * Tunables
283 */
284static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
285static int emx_rxd = EMX_DEFAULT_RXD;
286static int emx_txd = EMX_DEFAULT_TXD;
704b6287 287static int emx_smart_pwr_down = 0;
724cbff8 288static int emx_rxr = 0;
5330213c
SZ		 289
290/* Controls whether promiscuous also shows bad packets */
b4d8c36b 291static int emx_debug_sbp = 0;
5330213c 292
704b6287
SZ		 293static int emx_82573_workaround = 1;
294static int emx_msi_enable = 1;
5330213c
SZ		 295
296TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
297TUNABLE_INT("hw.emx.rxd", &emx_rxd);
724cbff8 298TUNABLE_INT("hw.emx.rxr", &emx_rxr);
5330213c
SZ		 299TUNABLE_INT("hw.emx.txd", &emx_txd);
300TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
301TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
302TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
704b6287 303TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
5330213c
SZ		 304
305/* Global used in WOL setup with multiport cards */
306static int emx_global_quad_port_a = 0;
307
308/* Set this to one to display debug statistics */
309static int emx_display_debug_stats = 0;
310
311#if !defined(KTR_IF_EMX)
312#define KTR_IF_EMX KTR_ALL
313#endif
314KTR_INFO_MASTER(if_emx);
5bf48697
AE		 315KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
316KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
317KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
318KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
319KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
5330213c
SZ		 320#define logif(name) KTR_LOG(if_emx_ ## name)
321
235b9d30
SZ		 322static __inline void
323emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
324{
325 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 326 /* DD bit must be cleared */
235b9d30
SZ		 327 rxd->rxd_staterr = 0;
328}
329
330static __inline void
331emx_rxcsum(uint32_t staterr, struct mbuf *mp)
332{
333 /* Ignore Checksum bit is set */
334 if (staterr & E1000_RXD_STAT_IXSM)
335 return;
336
337 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
338 E1000_RXD_STAT_IPCS)
339 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
340
341 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
342 E1000_RXD_STAT_TCPCS) {
343 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
344 CSUM_PSEUDO_HDR |
345 CSUM_FRAG_NOT_CHECKED;
346 mp->m_pkthdr.csum_data = htons(0xffff);
347 }
348}
349
9cc86e17
SZ		 350static __inline struct pktinfo *
351emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
352 uint32_t mrq, uint32_t hash, uint32_t staterr)
353{
354 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
355 case EMX_RXDMRQ_IPV4_TCP:
356 pi->pi_netisr = NETISR_IP;
357 pi->pi_flags = 0;
358 pi->pi_l3proto = IPPROTO_TCP;
359 break;
360
361 case EMX_RXDMRQ_IPV6_TCP:
362 pi->pi_netisr = NETISR_IPV6;
363 pi->pi_flags = 0;
364 pi->pi_l3proto = IPPROTO_TCP;
365 break;
366
367 case EMX_RXDMRQ_IPV4:
368 if (staterr & E1000_RXD_STAT_IXSM)
369 return NULL;
370
371 if ((staterr &
372 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
373 E1000_RXD_STAT_TCPCS) {
374 pi->pi_netisr = NETISR_IP;
375 pi->pi_flags = 0;
376 pi->pi_l3proto = IPPROTO_UDP;
377 break;
378 }
379 /* FALL THROUGH */
380 default:
381 return NULL;
382 }
383
384 m->m_flags |= M_HASH;
385 m->m_pkthdr.hash = toeplitz_hash(hash);
386 return pi;
387}
388
5330213c
SZ		 389static int
390emx_probe(device_t dev)
391{
392 const struct emx_device *d;
393 uint16_t vid, did;
394
395 vid = pci_get_vendor(dev);
396 did = pci_get_device(dev);
397
398 for (d = emx_devices; d->desc != NULL; ++d) {
399 if (vid == d->vid && did == d->did) {
400 device_set_desc(dev, d->desc);
401 device_set_async_attach(dev, TRUE);
402 return 0;
403 }
404 }
405 return ENXIO;
406}
407
408static int
409emx_attach(device_t dev)
410{
411 struct emx_softc *sc = device_get_softc(dev);
412 struct ifnet *ifp = &sc->arpcom.ac_if;
d01335e8 413 int error = 0, i, throttle, msi_enable;
704b6287 414 u_int intr_flags;
2d0e5700 415 uint16_t eeprom_data, device_id, apme_mask;
4cb541ae 416 driver_intr_t *intr_func;
5330213c 417
6d435846
SZ		 418 lwkt_serialize_init(&sc->main_serialize);
419 lwkt_serialize_init(&sc->tx_serialize);
420 for (i = 0; i < EMX_NRX_RING; ++i)
421 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
422
6d435846
SZ		 423 i = 0;
424 sc->serializes[i++] = &sc->main_serialize;
425 sc->serializes[i++] = &sc->tx_serialize;
426 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
427 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
428 KKASSERT(i == EMX_NSERIALIZE);
429
c2022416 430 callout_init_mp(&sc->timer);
5330213c
SZ		 431
432 sc->dev = sc->osdep.dev = dev;
433
434 /*
435 * Determine hardware and mac type
436 */
437 sc->hw.vendor_id = pci_get_vendor(dev);
438 sc->hw.device_id = pci_get_device(dev);
439 sc->hw.revision_id = pci_get_revid(dev);
440 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
441 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
442
443 if (e1000_set_mac_type(&sc->hw))
444 return ENXIO;
445
3eb0ea09
SZ		 446 /*
447 * Pullup extra 4bytes into the first data segment, see:
448 * 82571/82572 specification update errata #7
449 *
450 * NOTE:
451 * 4bytes instead of 2bytes, which are mentioned in the errata,
452 * are pulled; mainly to keep rest of the data properly aligned.
453 */
454 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
455 sc->flags |= EMX_FLAG_TSO_PULLEX;
456
5330213c
SZ		 457 /* Enable bus mastering */
458 pci_enable_busmaster(dev);
459
460 /*
461 * Allocate IO memory
462 */
463 sc->memory_rid = EMX_BAR_MEM;
464 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
465 &sc->memory_rid, RF_ACTIVE);
466 if (sc->memory == NULL) {
467 device_printf(dev, "Unable to allocate bus resource: memory\n");
468 error = ENXIO;
469 goto fail;
470 }
471 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
472 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
473
474 /* XXX This is quite goofy, it is not actually used */
475 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
476
477 /*
a835687d
SZ		 478 * Don't enable MSI-X on 82574, see:
479 * 82574 specification update errata #15
480 *
d01335e8 481 * Don't enable MSI on 82571/82572, see:
a835687d 482 * 82571/82572 specification update errata #63
d01335e8
SZ		 483 */
484 msi_enable = emx_msi_enable;
485 if (msi_enable &&
486 (sc->hw.mac.type == e1000_82571 ||
487 sc->hw.mac.type == e1000_82572))
488 msi_enable = 0;
489
490 /*
5330213c
SZ		 491 * Allocate interrupt
492 */
d01335e8 493 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
7fb43956 494 &sc->intr_rid, &intr_flags);
704b6287 495
4cb541ae
SZ		 496 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
497 int unshared;
498
499 unshared = device_getenv_int(dev, "irq.unshared", 0);
500 if (!unshared) {
501 sc->flags |= EMX_FLAG_SHARED_INTR;
502 if (bootverbose)
503 device_printf(dev, "IRQ shared\n");
504 } else {
505 intr_flags &= ~RF_SHAREABLE;
506 if (bootverbose)
507 device_printf(dev, "IRQ unshared\n");
508 }
509 }
510
5330213c 511 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
704b6287 512 intr_flags);
5330213c
SZ		 513 if (sc->intr_res == NULL) {
514 device_printf(dev, "Unable to allocate bus resource: "
515 "interrupt\n");
516 error = ENXIO;
517 goto fail;
518 }
519
520 /* Save PCI command register for Shared Code */
521 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
522 sc->hw.back = &sc->osdep;
523
524 /* Do Shared Code initialization */
525 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
526 device_printf(dev, "Setup of Shared code failed\n");
527 error = ENXIO;
528 goto fail;
529 }
530 e1000_get_bus_info(&sc->hw);
531
5330213c
SZ		 532 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
533 sc->hw.phy.autoneg_wait_to_complete = FALSE;
534 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
5330213c
SZ		 535
536 /*
537 * Interrupt throttle rate
538 */
b4d8c36b
SZ		 539 throttle = device_getenv_int(dev, "int_throttle_ceil",
540 emx_int_throttle_ceil);
541 if (throttle == 0) {
5330213c
SZ		 542 sc->int_throttle_ceil = 0;
543 } else {
5330213c
SZ		 544 if (throttle < 0)
545 throttle = EMX_DEFAULT_ITR;
546
547 /* Recalculate the tunable value to get the exact frequency. */
548 throttle = 1000000000 / 256 / throttle;
549
550 /* Upper 16bits of ITR is reserved and should be zero */
551 if (throttle & 0xffff0000)
552 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
553
554 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
555 }
556
557 e1000_init_script_state_82541(&sc->hw, TRUE);
558 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
559
560 /* Copper options */
561 if (sc->hw.phy.media_type == e1000_media_type_copper) {
562 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
563 sc->hw.phy.disable_polarity_correction = FALSE;
564 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
565 }
566
567 /* Set the frame limits assuming standard ethernet sized frames. */
568 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
569 sc->min_frame_size = ETHER_MIN_LEN;
570
571 /* This controls when hardware reports transmit completion status. */
572 sc->hw.mac.report_tx_early = 1;
573
65c7a6af 574 /* Calculate # of RX rings */
724cbff8 575 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
a317449e 576 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
65c7a6af 577
071699f8
SZ		 578 /* Allocate RX/TX rings' busdma(9) stuffs */
579 error = emx_dma_alloc(sc);
580 if (error)
e5b3bcc4 581 goto fail;
e5b3bcc4 582
2d0e5700
SZ		 583 /* Allocate multicast array memory. */
584 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
585 M_DEVBUF, M_WAITOK);
586
587 /* Indicate SOL/IDER usage */
588 if (e1000_check_reset_block(&sc->hw)) {
589 device_printf(dev,
590 "PHY reset is blocked due to SOL/IDER session.\n");
591 }
592
593 /*
594 * Start from a known state, this is important in reading the
595 * nvm and mac from that.
596 */
597 e1000_reset_hw(&sc->hw);
598
5330213c
SZ		 599 /* Make sure we have a good EEPROM before we read from it */
600 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
601 /*
602 * Some PCI-E parts fail the first check due to
603 * the link being in sleep state, call it again,
604 * if it fails a second time its a real issue.
605 */
606 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
607 device_printf(dev,
608 "The EEPROM Checksum Is Not Valid\n");
609 error = EIO;
610 goto fail;
611 }
612 }
613
5330213c
SZ		 614 /* Copy the permanent MAC address out of the EEPROM */
615 if (e1000_read_mac_addr(&sc->hw) < 0) {
616 device_printf(dev, "EEPROM read error while reading MAC"
617 " address\n");
618 error = EIO;
619 goto fail;
620 }
621 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
622 device_printf(dev, "Invalid MAC address\n");
623 error = EIO;
624 goto fail;
625 }
626
5330213c
SZ		 627 /* Determine if we have to control management hardware */
628 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
629
630 /*
631 * Setup Wake-on-Lan
632 */
2d0e5700
SZ		 633 apme_mask = EMX_EEPROM_APME;
634 eeprom_data = 0;
5330213c 635 switch (sc->hw.mac.type) {
2d0e5700
SZ		 636 case e1000_82573:
637 sc->has_amt = 1;
638 /* FALL THROUGH */
639
5330213c 640 case e1000_82571:
2d0e5700 641 case e1000_82572:
5330213c
SZ		 642 case e1000_80003es2lan:
643 if (sc->hw.bus.func == 1) {
644 e1000_read_nvm(&sc->hw,
645 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
646 } else {
647 e1000_read_nvm(&sc->hw,
648 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
649 }
5330213c
SZ		 650 break;
651
652 default:
2d0e5700
SZ		 653 e1000_read_nvm(&sc->hw,
654 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
5330213c
SZ		 655 break;
656 }
2d0e5700
SZ		 657 if (eeprom_data & apme_mask)
658 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
659
5330213c
SZ		 660 /*
661 * We have the eeprom settings, now apply the special cases
662 * where the eeprom may be wrong or the board won't support
663 * wake on lan on a particular port
664 */
665 device_id = pci_get_device(dev);
666 switch (device_id) {
667 case E1000_DEV_ID_82571EB_FIBER:
668 /*
669 * Wake events only supported on port A for dual fiber
670 * regardless of eeprom setting
671 */
672 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
673 E1000_STATUS_FUNC_1)
674 sc->wol = 0;
675 break;
676
677 case E1000_DEV_ID_82571EB_QUAD_COPPER:
678 case E1000_DEV_ID_82571EB_QUAD_FIBER:
679 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
680 /* if quad port sc, disable WoL on all but port A */
681 if (emx_global_quad_port_a != 0)
682 sc->wol = 0;
683 /* Reset for multiple quad port adapters */
684 if (++emx_global_quad_port_a == 4)
685 emx_global_quad_port_a = 0;
686 break;
687 }
688
689 /* XXX disable wol */
690 sc->wol = 0;
691
2d0e5700
SZ		 692 /* Setup OS specific network interface */
693 emx_setup_ifp(sc);
694
695 /* Add sysctl tree, must after em_setup_ifp() */
696 emx_add_sysctl(sc);
697
698 /* Reset the hardware */
699 error = emx_reset(sc);
700 if (error) {
701 device_printf(dev, "Unable to reset the hardware\n");
702 goto fail;
703 }
704
705 /* Initialize statistics */
706 emx_update_stats(sc);
707
708 sc->hw.mac.get_link_status = 1;
709 emx_update_link_status(sc);
710
5330213c
SZ		 711 sc->spare_tx_desc = EMX_TX_SPARE;
712
713 /*
714 * Keep following relationship between spare_tx_desc, oact_tx_desc
715 * and tx_int_nsegs:
716 * (spare_tx_desc + EMX_TX_RESERVED) <=
717 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
718 */
719 sc->oact_tx_desc = sc->num_tx_desc / 8;
720 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
721 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
722 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
723 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
724
725 sc->tx_int_nsegs = sc->num_tx_desc / 16;
726 if (sc->tx_int_nsegs < sc->oact_tx_desc)
727 sc->tx_int_nsegs = sc->oact_tx_desc;
728
2d0e5700
SZ		 729 /* Non-AMT based hardware can now take control from firmware */
730 if (sc->has_manage && !sc->has_amt)
731 emx_get_hw_control(sc);
732
4cb541ae
SZ		 733 /*
734 * Missing Interrupt Following ICR read:
735 *
a835687d
SZ		 736 * 82571/82572 specification update errata #76
737 * 82573 specification update errata #31
738 * 82574 specification update errata #12
4cb541ae
SZ		 739 */
740 intr_func = emx_intr;
741 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
742 (sc->hw.mac.type == e1000_82571 ||
743 sc->hw.mac.type == e1000_82572 ||
744 sc->hw.mac.type == e1000_82573 ||
745 sc->hw.mac.type == e1000_82574))
746 intr_func = emx_intr_mask;
747
748 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
6d435846 749 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ		 750 if (error) {
751 device_printf(dev, "Failed to register interrupt handler");
752 ether_ifdetach(&sc->arpcom.ac_if);
753 goto fail;
754 }
755
704b6287 756 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
5330213c
SZ		 757 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
758 return (0);
759fail:
760 emx_detach(dev);
761 return (error);
762}
763
764static int
765emx_detach(device_t dev)
766{
767 struct emx_softc *sc = device_get_softc(dev);
768
769 if (device_is_attached(dev)) {
770 struct ifnet *ifp = &sc->arpcom.ac_if;
771
6d435846 772 ifnet_serialize_all(ifp);
5330213c
SZ		 773
774 emx_stop(sc);
775
776 e1000_phy_hw_reset(&sc->hw);
777
778 emx_rel_mgmt(sc);
2d0e5700 779 emx_rel_hw_control(sc);
5330213c
SZ		 780
781 if (sc->wol) {
782 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
783 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
784 emx_enable_wol(dev);
785 }
786
787 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
788
6d435846 789 ifnet_deserialize_all(ifp);
5330213c
SZ		 790
791 ether_ifdetach(ifp);
2d0e5700
SZ		 792 } else {
793 emx_rel_hw_control(sc);
5330213c
SZ		 794 }
795 bus_generic_detach(dev);
796
797 if (sc->intr_res != NULL) {
798 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
799 sc->intr_res);
800 }
801
7fb43956 802 if (sc->intr_type == PCI_INTR_TYPE_MSI)
704b6287
SZ		 803 pci_release_msi(dev);
804
5330213c
SZ		 805 if (sc->memory != NULL) {
806 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
807 sc->memory);
808 }
809
071699f8 810 emx_dma_free(sc);
5330213c
SZ		 811
812 /* Free sysctl tree */
813 if (sc->sysctl_tree != NULL)
814 sysctl_ctx_free(&sc->sysctl_ctx);
815
816 return (0);
817}
818
819static int
820emx_shutdown(device_t dev)
821{
822 return emx_suspend(dev);
823}
824
825static int
826emx_suspend(device_t dev)
827{
828 struct emx_softc *sc = device_get_softc(dev);
829 struct ifnet *ifp = &sc->arpcom.ac_if;
830
6d435846 831 ifnet_serialize_all(ifp);
5330213c
SZ		 832
833 emx_stop(sc);
834
835 emx_rel_mgmt(sc);
2d0e5700 836 emx_rel_hw_control(sc);
5330213c 837
2d0e5700 838 if (sc->wol) {
5330213c
SZ		 839 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
840 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
841 emx_enable_wol(dev);
2d0e5700 842 }
5330213c 843
6d435846 844 ifnet_deserialize_all(ifp);
5330213c
SZ		 845
846 return bus_generic_suspend(dev);
847}
848
849static int
850emx_resume(device_t dev)
851{
852 struct emx_softc *sc = device_get_softc(dev);
853 struct ifnet *ifp = &sc->arpcom.ac_if;
854
6d435846 855 ifnet_serialize_all(ifp);
5330213c
SZ		 856
857 emx_init(sc);
858 emx_get_mgmt(sc);
859 if_devstart(ifp);
860
6d435846 861 ifnet_deserialize_all(ifp);
5330213c
SZ		 862
863 return bus_generic_resume(dev);
864}
865
866static void
867emx_start(struct ifnet *ifp)
868{
869 struct emx_softc *sc = ifp->if_softc;
870 struct mbuf *m_head;
871
6d435846 872 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ		 873
874 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
875 return;
876
877 if (!sc->link_active) {
878 ifq_purge(&ifp->if_snd);
879 return;
880 }
881
882 while (!ifq_is_empty(&ifp->if_snd)) {
883 /* Now do we at least have a minimal? */
884 if (EMX_IS_OACTIVE(sc)) {
885 emx_tx_collect(sc);
886 if (EMX_IS_OACTIVE(sc)) {
887 ifp->if_flags |= IFF_OACTIVE;
888 sc->no_tx_desc_avail1++;
889 break;
890 }
891 }
892
893 logif(pkt_txqueue);
894 m_head = ifq_dequeue(&ifp->if_snd, NULL);
895 if (m_head == NULL)
896 break;
897
898 if (emx_encap(sc, &m_head)) {
899 ifp->if_oerrors++;
900 emx_tx_collect(sc);
901 continue;
902 }
903
904 /* Send a copy of the frame to the BPF listener */
905 ETHER_BPF_MTAP(ifp, m_head);
906
907 /* Set timeout in case hardware has problems transmitting. */
908 ifp->if_timer = EMX_TX_TIMEOUT;
909 }
910}
911
912static int
913emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
914{
915 struct emx_softc *sc = ifp->if_softc;
916 struct ifreq *ifr = (struct ifreq *)data;
917 uint16_t eeprom_data = 0;
918 int max_frame_size, mask, reinit;
919 int error = 0;
920
2c9effcf 921 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 922
923 switch (command) {
924 case SIOCSIFMTU:
925 switch (sc->hw.mac.type) {
926 case e1000_82573:
927 /*
928 * 82573 only supports jumbo frames
929 * if ASPM is disabled.
930 */
931 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
932 &eeprom_data);
933 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
934 max_frame_size = ETHER_MAX_LEN;
935 break;
936 }
937 /* FALL THROUGH */
938
939 /* Limit Jumbo Frame size */
940 case e1000_82571:
941 case e1000_82572:
942 case e1000_82574:
943 case e1000_80003es2lan:
944 max_frame_size = 9234;
945 break;
946
947 default:
948 max_frame_size = MAX_JUMBO_FRAME_SIZE;
949 break;
950 }
951 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
952 ETHER_CRC_LEN) {
953 error = EINVAL;
954 break;
955 }
956
957 ifp->if_mtu = ifr->ifr_mtu;
958 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
959 ETHER_CRC_LEN;
960
961 if (ifp->if_flags & IFF_RUNNING)
962 emx_init(sc);
963 break;
964
965 case SIOCSIFFLAGS:
966 if (ifp->if_flags & IFF_UP) {
967 if ((ifp->if_flags & IFF_RUNNING)) {
968 if ((ifp->if_flags ^ sc->if_flags) &
969 (IFF_PROMISC | IFF_ALLMULTI)) {
970 emx_disable_promisc(sc);
971 emx_set_promisc(sc);
972 }
973 } else {
974 emx_init(sc);
975 }
976 } else if (ifp->if_flags & IFF_RUNNING) {
977 emx_stop(sc);
978 }
979 sc->if_flags = ifp->if_flags;
980 break;
981
982 case SIOCADDMULTI:
983 case SIOCDELMULTI:
984 if (ifp->if_flags & IFF_RUNNING) {
985 emx_disable_intr(sc);
986 emx_set_multi(sc);
b3a7093f
SZ		 987#ifdef IFPOLL_ENABLE
988 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ		 989#endif
990 emx_enable_intr(sc);
991 }
992 break;
993
994 case SIOCSIFMEDIA:
995 /* Check SOL/IDER usage */
996 if (e1000_check_reset_block(&sc->hw)) {
997 device_printf(sc->dev, "Media change is"
998 " blocked due to SOL/IDER session.\n");
999 break;
1000 }
1001 /* FALL THROUGH */
1002
1003 case SIOCGIFMEDIA:
1004 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1005 break;
1006
1007 case SIOCSIFCAP:
1008 reinit = 0;
1009 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3eb0ea09
SZ		 1010 if (mask & IFCAP_RXCSUM) {
1011 ifp->if_capenable ^= IFCAP_RXCSUM;
5330213c
SZ		 1012 reinit = 1;
1013 }
1014 if (mask & IFCAP_VLAN_HWTAGGING) {
1015 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1016 reinit = 1;
1017 }
3eb0ea09
SZ		 1018 if (mask & IFCAP_TXCSUM) {
1019 ifp->if_capenable ^= IFCAP_TXCSUM;
1020 if (ifp->if_capenable & IFCAP_TXCSUM)
1021 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1022 else
1023 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1024 }
1025 if (mask & IFCAP_TSO) {
1026 ifp->if_capenable ^= IFCAP_TSO;
1027 if (ifp->if_capenable & IFCAP_TSO)
1028 ifp->if_hwassist |= CSUM_TSO;
1029 else
1030 ifp->if_hwassist &= ~CSUM_TSO;
1031 }
13890b61 1032 if (mask & IFCAP_RSS)
8434a83b 1033 ifp->if_capenable ^= IFCAP_RSS;
5330213c
SZ		 1034 if (reinit && (ifp->if_flags & IFF_RUNNING))
1035 emx_init(sc);
1036 break;
1037
1038 default:
1039 error = ether_ioctl(ifp, command, data);
1040 break;
1041 }
1042 return (error);
1043}
1044
1045static void
1046emx_watchdog(struct ifnet *ifp)
1047{
1048 struct emx_softc *sc = ifp->if_softc;
1049
2c9effcf 1050 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1051
1052 /*
1053 * The timer is set to 5 every time start queues a packet.
1054 * Then txeof keeps resetting it as long as it cleans at
1055 * least one descriptor.
1056 * Finally, anytime all descriptors are clean the timer is
1057 * set to 0.
1058 */
1059
1060 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1061 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1062 /*
1063 * If we reach here, all TX jobs are completed and
1064 * the TX engine should have been idled for some time.
1065 * We don't need to call if_devstart() here.
1066 */
1067 ifp->if_flags &= ~IFF_OACTIVE;
1068 ifp->if_timer = 0;
1069 return;
1070 }
1071
1072 /*
1073 * If we are in this routine because of pause frames, then
1074 * don't reset the hardware.
1075 */
1076 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1077 ifp->if_timer = EMX_TX_TIMEOUT;
1078 return;
1079 }
1080
1081 if (e1000_check_for_link(&sc->hw) == 0)
1082 if_printf(ifp, "watchdog timeout -- resetting\n");
1083
1084 ifp->if_oerrors++;
1085 sc->watchdog_events++;
1086
1087 emx_init(sc);
1088
1089 if (!ifq_is_empty(&ifp->if_snd))
1090 if_devstart(ifp);
1091}
1092
1093static void
1094emx_init(void *xsc)
1095{
1096 struct emx_softc *sc = xsc;
1097 struct ifnet *ifp = &sc->arpcom.ac_if;
1098 device_t dev = sc->dev;
1099 uint32_t pba;
3f939c23 1100 int i;
5330213c 1101
2c9effcf 1102 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1103
1104 emx_stop(sc);
1105
1106 /*
1107 * Packet Buffer Allocation (PBA)
1108 * Writing PBA sets the receive portion of the buffer
1109 * the remainder is used for the transmit buffer.
1110 */
1111 switch (sc->hw.mac.type) {
1112 /* Total Packet Buffer on these is 48K */
1113 case e1000_82571:
1114 case e1000_82572:
1115 case e1000_80003es2lan:
1116 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1117 break;
1118
1119 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1120 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1121 break;
1122
1123 case e1000_82574:
1124 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1125 break;
1126
1127 default:
1128 /* Devices before 82547 had a Packet Buffer of 64K. */
1129 if (sc->max_frame_size > 8192)
1130 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1131 else
1132 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1133 }
1134 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1135
1136 /* Get the latest mac address, User can use a LAA */
1137 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1138
1139 /* Put the address into the Receive Address Array */
1140 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1141
1142 /*
1143 * With the 82571 sc, RAR[0] may be overwritten
1144 * when the other port is reset, we make a duplicate
1145 * in RAR[14] for that eventuality, this assures
1146 * the interface continues to function.
1147 */
1148 if (sc->hw.mac.type == e1000_82571) {
1149 e1000_set_laa_state_82571(&sc->hw, TRUE);
1150 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1151 E1000_RAR_ENTRIES - 1);
1152 }
1153
1154 /* Initialize the hardware */
2d0e5700
SZ		 1155 if (emx_reset(sc)) {
1156 device_printf(dev, "Unable to reset the hardware\n");
5330213c
SZ		 1157 /* XXX emx_stop()? */
1158 return;
1159 }
1160 emx_update_link_status(sc);
1161
1162 /* Setup VLAN support, basic and offload if available */
1163 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1164
1165 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1166 uint32_t ctrl;
1167
1168 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1169 ctrl |= E1000_CTRL_VME;
1170 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1171 }
1172
5330213c
SZ		 1173 /* Configure for OS presence */
1174 emx_get_mgmt(sc);
1175
1176 /* Prepare transmit descriptors and buffers */
1177 emx_init_tx_ring(sc);
1178 emx_init_tx_unit(sc);
1179
1180 /* Setup Multicast table */
1181 emx_set_multi(sc);
1182
1183 /* Prepare receive descriptors and buffers */
13890b61 1184 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 1185 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1186 device_printf(dev,
1187 "Could not setup receive structures\n");
1188 emx_stop(sc);
1189 return;
1190 }
5330213c
SZ		 1191 }
1192 emx_init_rx_unit(sc);
1193
1194 /* Don't lose promiscuous settings */
1195 emx_set_promisc(sc);
1196
1197 ifp->if_flags |= IFF_RUNNING;
1198 ifp->if_flags &= ~IFF_OACTIVE;
1199
1200 callout_reset(&sc->timer, hz, emx_timer, sc);
1201 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1202
1203 /* MSI/X configuration for 82574 */
1204 if (sc->hw.mac.type == e1000_82574) {
1205 int tmp;
1206
1207 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1208 tmp |= E1000_CTRL_EXT_PBA_CLR;
1209 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1210 /*
2d0e5700 1211 * XXX MSIX
5330213c
SZ		 1212 * Set the IVAR - interrupt vector routing.
1213 * Each nibble represents a vector, high bit
1214 * is enable, other 3 bits are the MSIX table
1215 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1216 * Link (other) to 2, hence the magic number.
1217 */
1218 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1219 }
1220
b3a7093f 1221#ifdef IFPOLL_ENABLE
5330213c
SZ		 1222 /*
1223 * Only enable interrupts if we are not polling, make sure
1224 * they are off otherwise.
1225 */
b3a7093f 1226 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ		 1227 emx_disable_intr(sc);
1228 else
b3a7093f 1229#endif /* IFPOLL_ENABLE */
5330213c
SZ		 1230 emx_enable_intr(sc);
1231
2d0e5700
SZ		 1232 /* AMT based hardware can now take control from firmware */
1233 if (sc->has_manage && sc->has_amt)
1234 emx_get_hw_control(sc);
1235
5330213c
SZ		 1236 /* Don't reset the phy next time init gets called */
1237 sc->hw.phy.reset_disable = TRUE;
1238}
1239
5330213c
SZ		 1240static void
1241emx_intr(void *xsc)
1242{
4cb541ae
SZ		 1243 emx_intr_body(xsc, TRUE);
1244}
1245
1246static void
1247emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1248{
5330213c
SZ		 1249 struct ifnet *ifp = &sc->arpcom.ac_if;
1250 uint32_t reg_icr;
1251
1252 logif(intr_beg);
6d435846 1253 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ		 1254
1255 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1256
4cb541ae 1257 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
5330213c
SZ		 1258 logif(intr_end);
1259 return;
1260 }
1261
1262 /*
1263 * XXX: some laptops trigger several spurious interrupts
df50f778 1264 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ		 1265 * reports all-ones value in this case. Processing such
1266 * interrupts would lead to a freeze. I don't know why.
1267 */
1268 if (reg_icr == 0xffffffff) {
1269 logif(intr_end);
1270 return;
1271 }
1272
1273 if (ifp->if_flags & IFF_RUNNING) {
1274 if (reg_icr &
3f939c23
SZ		 1275 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1276 int i;
1277
13890b61 1278 for (i = 0; i < sc->rx_ring_cnt; ++i) {
6d435846
SZ		 1279 lwkt_serialize_enter(
1280 &sc->rx_data[i].rx_serialize);
3f939c23 1281 emx_rxeof(sc, i, -1);
6d435846
SZ		 1282 lwkt_serialize_exit(
1283 &sc->rx_data[i].rx_serialize);
1284 }
3f939c23 1285 }
6446af7b 1286 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1287 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ		 1288 emx_txeof(sc);
1289 if (!ifq_is_empty(&ifp->if_snd))
1290 if_devstart(ifp);
6d435846 1291 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ		 1292 }
1293 }
1294
1295 /* Link status change */
1296 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1297 emx_serialize_skipmain(sc);
6d435846 1298
5330213c
SZ		 1299 callout_stop(&sc->timer);
1300 sc->hw.mac.get_link_status = 1;
1301 emx_update_link_status(sc);
1302
1303 /* Deal with TX cruft when link lost */
1304 emx_tx_purge(sc);
1305
1306 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1307
bca7c435 1308 emx_deserialize_skipmain(sc);
5330213c
SZ		 1309 }
1310
1311 if (reg_icr & E1000_ICR_RXO)
1312 sc->rx_overruns++;
1313
1314 logif(intr_end);
1315}
1316
1317static void
4cb541ae
SZ		 1318emx_intr_mask(void *xsc)
1319{
1320 struct emx_softc *sc = xsc;
1321
1322 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1323 /*
1324 * NOTE:
1325 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1326 * so don't check it.
1327 */
1328 emx_intr_body(sc, FALSE);
1329 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1330}
1331
1332static void
5330213c
SZ		 1333emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1334{
1335 struct emx_softc *sc = ifp->if_softc;
1336
2c9effcf 1337 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1338
1339 emx_update_link_status(sc);
1340
1341 ifmr->ifm_status = IFM_AVALID;
1342 ifmr->ifm_active = IFM_ETHER;
1343
1344 if (!sc->link_active)
1345 return;
1346
1347 ifmr->ifm_status |= IFM_ACTIVE;
1348
1349 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1350 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1351 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1352 } else {
1353 switch (sc->link_speed) {
1354 case 10:
1355 ifmr->ifm_active |= IFM_10_T;
1356 break;
1357 case 100:
1358 ifmr->ifm_active |= IFM_100_TX;
1359 break;
1360
1361 case 1000:
1362 ifmr->ifm_active |= IFM_1000_T;
1363 break;
1364 }
1365 if (sc->link_duplex == FULL_DUPLEX)
1366 ifmr->ifm_active |= IFM_FDX;
1367 else
1368 ifmr->ifm_active |= IFM_HDX;
1369 }
1370}
1371
1372static int
1373emx_media_change(struct ifnet *ifp)
1374{
1375 struct emx_softc *sc = ifp->if_softc;
1376 struct ifmedia *ifm = &sc->media;
1377
2c9effcf 1378 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1379
1380 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1381 return (EINVAL);
1382
1383 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1384 case IFM_AUTO:
1385 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1386 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1387 break;
1388
1389 case IFM_1000_LX:
1390 case IFM_1000_SX:
1391 case IFM_1000_T:
1392 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1393 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1394 break;
1395
1396 case IFM_100_TX:
1397 sc->hw.mac.autoneg = FALSE;
1398 sc->hw.phy.autoneg_advertised = 0;
1399 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1400 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1401 else
1402 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1403 break;
1404
1405 case IFM_10_T:
1406 sc->hw.mac.autoneg = FALSE;
1407 sc->hw.phy.autoneg_advertised = 0;
1408 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1409 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1410 else
1411 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1412 break;
1413
1414 default:
1415 if_printf(ifp, "Unsupported media type\n");
1416 break;
1417 }
1418
1419 /*
1420 * As the speed/duplex settings my have changed we need to
1421 * reset the PHY.
1422 */
1423 sc->hw.phy.reset_disable = FALSE;
1424
1425 emx_init(sc);
1426
1427 return (0);
1428}
1429
1430static int
1431emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1432{
1433 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1434 bus_dmamap_t map;
323e5ecd 1435 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
5330213c
SZ		 1436 struct e1000_tx_desc *ctxd = NULL;
1437 struct mbuf *m_head = *m_headp;
1438 uint32_t txd_upper, txd_lower, cmd = 0;
1439 int maxsegs, nsegs, i, j, first, last = 0, error;
1440
3eb0ea09
SZ		 1441 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1442 error = emx_tso_pullup(sc, m_headp);
1443 if (error)
1444 return error;
1445 m_head = *m_headp;
1446 }
1447
5330213c
SZ		 1448 txd_upper = txd_lower = 0;
1449
1450 /*
1451 * Capture the first descriptor index, this descriptor
1452 * will have the index of the EOP which is the only one
1453 * that now gets a DONE bit writeback.
1454 */
1455 first = sc->next_avail_tx_desc;
323e5ecd 1456 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 1457 tx_buffer_mapped = tx_buffer;
1458 map = tx_buffer->map;
1459
1460 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
ed20d0e3 1461 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
5330213c
SZ		 1462 if (maxsegs > EMX_MAX_SCATTER)
1463 maxsegs = EMX_MAX_SCATTER;
1464
1465 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1466 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1467 if (error) {
1468 if (error == ENOBUFS)
1469 sc->mbuf_alloc_failed++;
1470 else
1471 sc->no_tx_dma_setup++;
1472
1473 m_freem(*m_headp);
1474 *m_headp = NULL;
1475 return error;
1476 }
1477 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1478
1479 m_head = *m_headp;
1480 sc->tx_nsegs += nsegs;
1481
3eb0ea09
SZ		 1482 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1483 /* TSO will consume one TX desc */
1484 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1485 &txd_upper, &txd_lower);
1486 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
5330213c
SZ		 1487 /* TX csum offloading will consume one TX desc */
1488 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1489 }
1490 i = sc->next_avail_tx_desc;
1491
1492 /* Set up our transmit descriptors */
1493 for (j = 0; j < nsegs; j++) {
323e5ecd 1494 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 1495 ctxd = &sc->tx_desc_base[i];
1496
1497 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1498 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1499 txd_lower | segs[j].ds_len);
1500 ctxd->upper.data = htole32(txd_upper);
1501
1502 last = i;
1503 if (++i == sc->num_tx_desc)
1504 i = 0;
5330213c
SZ		 1505 }
1506
1507 sc->next_avail_tx_desc = i;
1508
1509 KKASSERT(sc->num_tx_desc_avail > nsegs);
1510 sc->num_tx_desc_avail -= nsegs;
1511
1512 /* Handle VLAN tag */
1513 if (m_head->m_flags & M_VLANTAG) {
1514 /* Set the vlan id. */
1515 ctxd->upper.fields.special =
1516 htole16(m_head->m_pkthdr.ether_vlantag);
1517
1518 /* Tell hardware to add tag */
1519 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1520 }
1521
1522 tx_buffer->m_head = m_head;
1523 tx_buffer_mapped->map = tx_buffer->map;
1524 tx_buffer->map = map;
1525
1526 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1527 sc->tx_nsegs = 0;
4e4e8481
SZ		 1528
1529 /*
1530 * Report Status (RS) is turned on
1531 * every tx_int_nsegs descriptors.
1532 */
5330213c
SZ		 1533 cmd = E1000_TXD_CMD_RS;
1534
b4b0a2b4
SZ		 1535 /*
1536 * Keep track of the descriptor, which will
1537 * be written back by hardware.
1538 */
5330213c
SZ		 1539 sc->tx_dd[sc->tx_dd_tail] = last;
1540 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1541 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1542 }
1543
1544 /*
1545 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ		 1546 */
1547 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1548
1549 /*
5330213c
SZ		 1550 * Advance the Transmit Descriptor Tail (TDT), this tells
1551 * the E1000 that this frame is available to transmit.
1552 */
1553 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1554
1555 return (0);
1556}
1557
1558static void
1559emx_set_promisc(struct emx_softc *sc)
1560{
1561 struct ifnet *ifp = &sc->arpcom.ac_if;
1562 uint32_t reg_rctl;
1563
1564 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1565
1566 if (ifp->if_flags & IFF_PROMISC) {
1567 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1568 /* Turn this on if you want to see bad packets */
1569 if (emx_debug_sbp)
1570 reg_rctl |= E1000_RCTL_SBP;
1571 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1572 } else if (ifp->if_flags & IFF_ALLMULTI) {
1573 reg_rctl |= E1000_RCTL_MPE;
1574 reg_rctl &= ~E1000_RCTL_UPE;
1575 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1576 }
1577}
1578
1579static void
1580emx_disable_promisc(struct emx_softc *sc)
1581{
1582 uint32_t reg_rctl;
1583
1584 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1585
1586 reg_rctl &= ~E1000_RCTL_UPE;
1587 reg_rctl &= ~E1000_RCTL_MPE;
1588 reg_rctl &= ~E1000_RCTL_SBP;
1589 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1590}
1591
1592static void
1593emx_set_multi(struct emx_softc *sc)
1594{
1595 struct ifnet *ifp = &sc->arpcom.ac_if;
1596 struct ifmultiaddr *ifma;
1597 uint32_t reg_rctl = 0;
2d0e5700 1598 uint8_t *mta;
5330213c
SZ		 1599 int mcnt = 0;
1600
2d0e5700
SZ		 1601 mta = sc->mta;
1602 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1603
441d34b2 1604 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ		 1605 if (ifma->ifma_addr->sa_family != AF_LINK)
1606 continue;
1607
1608 if (mcnt == EMX_MCAST_ADDR_MAX)
1609 break;
1610
1611 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1612 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1613 mcnt++;
1614 }
1615
1616 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1617 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1618 reg_rctl |= E1000_RCTL_MPE;
1619 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1620 } else {
6a5a645e 1621 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
5330213c
SZ		 1622 }
1623}
1624
1625/*
1626 * This routine checks for link status and updates statistics.
1627 */
1628static void
1629emx_timer(void *xsc)
1630{
1631 struct emx_softc *sc = xsc;
1632 struct ifnet *ifp = &sc->arpcom.ac_if;
1633
6d435846 1634 ifnet_serialize_all(ifp);
5330213c
SZ		 1635
1636 emx_update_link_status(sc);
1637 emx_update_stats(sc);
1638
1639 /* Reset LAA into RAR[0] on 82571 */
1640 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1641 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1642
1643 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1644 emx_print_hw_stats(sc);
1645
1646 emx_smartspeed(sc);
1647
1648 callout_reset(&sc->timer, hz, emx_timer, sc);
1649
6d435846 1650 ifnet_deserialize_all(ifp);
5330213c
SZ		 1651}
1652
1653static void
1654emx_update_link_status(struct emx_softc *sc)
1655{
1656 struct e1000_hw *hw = &sc->hw;
1657 struct ifnet *ifp = &sc->arpcom.ac_if;
1658 device_t dev = sc->dev;
1659 uint32_t link_check = 0;
1660
1661 /* Get the cached link value or read phy for real */
1662 switch (hw->phy.media_type) {
1663 case e1000_media_type_copper:
1664 if (hw->mac.get_link_status) {
1665 /* Do the work to read phy */
1666 e1000_check_for_link(hw);
1667 link_check = !hw->mac.get_link_status;
1668 if (link_check) /* ESB2 fix */
1669 e1000_cfg_on_link_up(hw);
1670 } else {
1671 link_check = TRUE;
1672 }
1673 break;
1674
1675 case e1000_media_type_fiber:
1676 e1000_check_for_link(hw);
1677 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1678 break;
1679
1680 case e1000_media_type_internal_serdes:
1681 e1000_check_for_link(hw);
1682 link_check = sc->hw.mac.serdes_has_link;
1683 break;
1684
1685 case e1000_media_type_unknown:
1686 default:
1687 break;
1688 }
1689
1690 /* Now check for a transition */
1691 if (link_check && sc->link_active == 0) {
1692 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1693 &sc->link_duplex);
1694
1695 /*
1696 * Check if we should enable/disable SPEED_MODE bit on
1697 * 82571EB/82572EI
1698 */
2d0e5700
SZ		 1699 if (sc->link_speed != SPEED_1000 &&
1700 (hw->mac.type == e1000_82571 ||
1701 hw->mac.type == e1000_82572)) {
5330213c
SZ		 1702 int tarc0;
1703
1704 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2d0e5700 1705 tarc0 &= ~EMX_TARC_SPEED_MODE;
5330213c
SZ		 1706 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1707 }
1708 if (bootverbose) {
1709 device_printf(dev, "Link is up %d Mbps %s\n",
1710 sc->link_speed,
1711 ((sc->link_duplex == FULL_DUPLEX) ?
1712 "Full Duplex" : "Half Duplex"));
1713 }
1714 sc->link_active = 1;
1715 sc->smartspeed = 0;
1716 ifp->if_baudrate = sc->link_speed * 1000000;
1717 ifp->if_link_state = LINK_STATE_UP;
1718 if_link_state_change(ifp);
1719 } else if (!link_check && sc->link_active == 1) {
1720 ifp->if_baudrate = sc->link_speed = 0;
1721 sc->link_duplex = 0;
1722 if (bootverbose)
1723 device_printf(dev, "Link is Down\n");
1724 sc->link_active = 0;
1725#if 0
1726 /* Link down, disable watchdog */
1727 if->if_timer = 0;
1728#endif
1729 ifp->if_link_state = LINK_STATE_DOWN;
1730 if_link_state_change(ifp);
1731 }
1732}
1733
1734static void
1735emx_stop(struct emx_softc *sc)
1736{
1737 struct ifnet *ifp = &sc->arpcom.ac_if;
1738 int i;
1739
2c9effcf 1740 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ		 1741
1742 emx_disable_intr(sc);
1743
1744 callout_stop(&sc->timer);
1745
1746 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1747 ifp->if_timer = 0;
1748
3f939c23
SZ		 1749 /*
1750 * Disable multiple receive queues.
1751 *
1752 * NOTE:
1753 * We should disable multiple receive queues before
1754 * resetting the hardware.
1755 */
1756 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1757
5330213c
SZ		 1758 e1000_reset_hw(&sc->hw);
1759 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1760
1761 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1762 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 1763
1764 if (tx_buffer->m_head != NULL) {
1765 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1766 m_freem(tx_buffer->m_head);
1767 tx_buffer->m_head = NULL;
1768 }
1769 }
1770
13890b61 1771 for (i = 0; i < sc->rx_ring_cnt; ++i)
3f939c23 1772 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ		 1773
1774 sc->csum_flags = 0;
3eb0ea09 1775 sc->csum_lhlen = 0;
5330213c 1776 sc->csum_iphlen = 0;
3eb0ea09
SZ		 1777 sc->csum_thlen = 0;
1778 sc->csum_mss = 0;
1779 sc->csum_pktlen = 0;
5330213c
SZ		 1780
1781 sc->tx_dd_head = 0;
1782 sc->tx_dd_tail = 0;
1783 sc->tx_nsegs = 0;
1784}
1785
1786static int
2d0e5700 1787emx_reset(struct emx_softc *sc)
5330213c
SZ		 1788{
1789 device_t dev = sc->dev;
1790 uint16_t rx_buffer_size;
1791
5330213c
SZ		 1792 /* Set up smart power down as default off on newer adapters. */
1793 if (!emx_smart_pwr_down &&
1794 (sc->hw.mac.type == e1000_82571 ||
1795 sc->hw.mac.type == e1000_82572)) {
1796 uint16_t phy_tmp = 0;
1797
1798 /* Speed up time to link by disabling smart power down. */
1799 e1000_read_phy_reg(&sc->hw,
1800 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1801 phy_tmp &= ~IGP02E1000_PM_SPD;
1802 e1000_write_phy_reg(&sc->hw,
1803 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1804 }
1805
1806 /*
1807 * These parameters control the automatic generation (Tx) and
1808 * response (Rx) to Ethernet PAUSE frames.
1809 * - High water mark should allow for at least two frames to be
1810 * received after sending an XOFF.
1811 * - Low water mark works best when it is very near the high water mark.
1812 * This allows the receiver to restart by sending XON when it has
1813 * drained a bit. Here we use an arbitary value of 1500 which will
1814 * restart after one full frame is pulled from the buffer. There
1815 * could be several smaller frames in the buffer and if so they will
1816 * not trigger the XON until their total number reduces the buffer
1817 * by 1500.
1818 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1819 */
1820 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1821
1822 sc->hw.fc.high_water = rx_buffer_size -
1823 roundup2(sc->max_frame_size, 1024);
1824 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1825
1826 if (sc->hw.mac.type == e1000_80003es2lan)
1827 sc->hw.fc.pause_time = 0xFFFF;
1828 else
1829 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1830 sc->hw.fc.send_xon = TRUE;
1831 sc->hw.fc.requested_mode = e1000_fc_full;
1832
2d0e5700
SZ		 1833 /* Issue a global reset */
1834 e1000_reset_hw(&sc->hw);
1835 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
6d5e2922 1836 emx_disable_aspm(sc);
2d0e5700 1837
5330213c
SZ		 1838 if (e1000_init_hw(&sc->hw) < 0) {
1839 device_printf(dev, "Hardware Initialization Failed\n");
1840 return (EIO);
1841 }
1842
2d0e5700
SZ		 1843 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1844 e1000_get_phy_info(&sc->hw);
5330213c
SZ		 1845 e1000_check_for_link(&sc->hw);
1846
1847 return (0);
1848}
1849
1850static void
1851emx_setup_ifp(struct emx_softc *sc)
1852{
1853 struct ifnet *ifp = &sc->arpcom.ac_if;
1854
1855 if_initname(ifp, device_get_name(sc->dev),
1856 device_get_unit(sc->dev));
1857 ifp->if_softc = sc;
1858 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1859 ifp->if_init = emx_init;
1860 ifp->if_ioctl = emx_ioctl;
1861 ifp->if_start = emx_start;
b3a7093f
SZ		 1862#ifdef IFPOLL_ENABLE
1863 ifp->if_qpoll = emx_qpoll;
5330213c
SZ		 1864#endif
1865 ifp->if_watchdog = emx_watchdog;
6d435846
SZ		 1866 ifp->if_serialize = emx_serialize;
1867 ifp->if_deserialize = emx_deserialize;
1868 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ		 1869#ifdef INVARIANTS
1870 ifp->if_serialize_assert = emx_serialize_assert;
1871#endif
5330213c
SZ		 1872 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1873 ifq_set_ready(&ifp->if_snd);
1874
ae474cfa 1875 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
5330213c
SZ		 1876
1877 ifp->if_capabilities = IFCAP_HWCSUM |
1878 IFCAP_VLAN_HWTAGGING |
3eb0ea09
SZ		 1879 IFCAP_VLAN_MTU |
1880 IFCAP_TSO;
8434a83b
SZ		 1881 if (sc->rx_ring_cnt > 1)
1882 ifp->if_capabilities |= IFCAP_RSS;
5330213c 1883 ifp->if_capenable = ifp->if_capabilities;
3eb0ea09 1884 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
5330213c
SZ		 1885
1886 /*
1887 * Tell the upper layer(s) we support long frames.
1888 */
1889 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1890
1891 /*
1892 * Specify the media types supported by this sc and register
1893 * callbacks to update media and link information
1894 */
1895 ifmedia_init(&sc->media, IFM_IMASK,
1896 emx_media_change, emx_media_status);
1897 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1898 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1899 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1900 0, NULL);
1901 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1902 } else {
1903 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1904 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1905 0, NULL);
1906 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1907 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1908 0, NULL);
1909 if (sc->hw.phy.type != e1000_phy_ife) {
1910 ifmedia_add(&sc->media,
1911 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1912 ifmedia_add(&sc->media,
1913 IFM_ETHER | IFM_1000_T, 0, NULL);
1914 }
1915 }
1916 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1917 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1918}
1919
1920/*
1921 * Workaround for SmartSpeed on 82541 and 82547 controllers
1922 */
1923static void
1924emx_smartspeed(struct emx_softc *sc)
1925{
1926 uint16_t phy_tmp;
1927
1928 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1929 sc->hw.mac.autoneg == 0 ||
1930 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1931 return;
1932
1933 if (sc->smartspeed == 0) {
1934 /*
1935 * If Master/Slave config fault is asserted twice,
1936 * we assume back-to-back
1937 */
1938 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1939 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1940 return;
1941 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1942 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1943 e1000_read_phy_reg(&sc->hw,
1944 PHY_1000T_CTRL, &phy_tmp);
1945 if (phy_tmp & CR_1000T_MS_ENABLE) {
1946 phy_tmp &= ~CR_1000T_MS_ENABLE;
1947 e1000_write_phy_reg(&sc->hw,
1948 PHY_1000T_CTRL, phy_tmp);
1949 sc->smartspeed++;
1950 if (sc->hw.mac.autoneg &&
1951 !e1000_phy_setup_autoneg(&sc->hw) &&
1952 !e1000_read_phy_reg(&sc->hw,
1953 PHY_CONTROL, &phy_tmp)) {
1954 phy_tmp |= MII_CR_AUTO_NEG_EN |
1955 MII_CR_RESTART_AUTO_NEG;
1956 e1000_write_phy_reg(&sc->hw,
1957 PHY_CONTROL, phy_tmp);
1958 }
1959 }
1960 }
1961 return;
1962 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1963 /* If still no link, perhaps using 2/3 pair cable */
1964 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1965 phy_tmp |= CR_1000T_MS_ENABLE;
1966 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1967 if (sc->hw.mac.autoneg &&
1968 !e1000_phy_setup_autoneg(&sc->hw) &&
1969 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1970 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1971 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1972 }
1973 }
1974
1975 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1976 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1977 sc->smartspeed = 0;
1978}
1979
1980static int
5330213c
SZ		 1981emx_create_tx_ring(struct emx_softc *sc)
1982{
1983 device_t dev = sc->dev;
323e5ecd 1984 struct emx_txbuf *tx_buffer;
b4d8c36b 1985 int error, i, tsize, ntxd;
bdca134f
SZ		 1986
1987 /*
1988 * Validate number of transmit descriptors. It must not exceed
1989 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1990 */
b4d8c36b
SZ		 1991 ntxd = device_getenv_int(dev, "txd", emx_txd);
1992 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1993 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
bdca134f 1994 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
b4d8c36b 1995 EMX_DEFAULT_TXD, ntxd);
bdca134f
SZ		 1996 sc->num_tx_desc = EMX_DEFAULT_TXD;
1997 } else {
b4d8c36b 1998 sc->num_tx_desc = ntxd;
bdca134f
SZ		 1999 }
2000
2001 /*
2002 * Allocate Transmit Descriptor ring
2003 */
2004 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2005 EMX_DBA_ALIGN);
a596084c
SZ		 2006 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2007 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2008 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2009 &sc->tx_desc_paddr);
2010 if (sc->tx_desc_base == NULL) {
bdca134f 2011 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 2012 return ENOMEM;
bdca134f 2013 }
5330213c 2014
323e5ecd
SZ		 2015 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2016 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ		 2017
2018 /*
2019 * Create DMA tags for tx buffers
2020 */
2021 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2022 1, 0, /* alignment, bounds */
2023 BUS_SPACE_MAXADDR, /* lowaddr */
2024 BUS_SPACE_MAXADDR, /* highaddr */
2025 NULL, NULL, /* filter, filterarg */
2026 EMX_TSO_SIZE, /* maxsize */
2027 EMX_MAX_SCATTER, /* nsegments */
2028 EMX_MAX_SEGSIZE, /* maxsegsize */
2029 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2030 BUS_DMA_ONEBPAGE, /* flags */
2031 &sc->txtag);
2032 if (error) {
2033 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ		 2034 kfree(sc->tx_buf, M_DEVBUF);
2035 sc->tx_buf = NULL;
5330213c
SZ		 2036 return error;
2037 }
2038
2039 /*
2040 * Create DMA maps for tx buffers
2041 */
2042 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 2043 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 2044
2045 error = bus_dmamap_create(sc->txtag,
2046 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2047 &tx_buffer->map);
2048 if (error) {
2049 device_printf(dev, "Unable to create TX DMA map\n");
2050 emx_destroy_tx_ring(sc, i);
2051 return error;
2052 }
2053 }
2054 return (0);
2055}
2056
2057static void
2058emx_init_tx_ring(struct emx_softc *sc)
2059{
2060 /* Clear the old ring contents */
2061 bzero(sc->tx_desc_base,
2062 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2063
2064 /* Reset state */
2065 sc->next_avail_tx_desc = 0;
2066 sc->next_tx_to_clean = 0;
2067 sc->num_tx_desc_avail = sc->num_tx_desc;
2068}
2069
2070static void
2071emx_init_tx_unit(struct emx_softc *sc)
2072{
2073 uint32_t tctl, tarc, tipg = 0;
2074 uint64_t bus_addr;
2075
2076 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 2077 bus_addr = sc->tx_desc_paddr;
5330213c
SZ		 2078 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2079 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2080 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2081 (uint32_t)(bus_addr >> 32));
2082 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2083 (uint32_t)bus_addr);
2084 /* Setup the HW Tx Head and Tail descriptor pointers */
2085 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2086 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2087
2088 /* Set the default values for the Tx Inter Packet Gap timer */
2089 switch (sc->hw.mac.type) {
2090 case e1000_80003es2lan:
2091 tipg = DEFAULT_82543_TIPG_IPGR1;
2092 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2093 E1000_TIPG_IPGR2_SHIFT;
2094 break;
2095
2096 default:
2097 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2098 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2099 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2100 else
2101 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2102 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2103 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2104 break;
2105 }
2106
2107 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2108
2109 /* NOTE: 0 is not allowed for TIDV */
2110 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2111 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2112
2113 if (sc->hw.mac.type == e1000_82571 ||
2114 sc->hw.mac.type == e1000_82572) {
2115 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2116 tarc |= EMX_TARC_SPEED_MODE;
2117 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2118 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2119 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2120 tarc |= 1;
2121 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2122 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2123 tarc |= 1;
2124 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2125 }
2126
2127 /* Program the Transmit Control Register */
2128 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2129 tctl &= ~E1000_TCTL_CT;
2130 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2131 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2132 tctl |= E1000_TCTL_MULR;
2133
2134 /* This write will effectively turn on the transmit unit. */
2135 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2136}
2137
2138static void
2139emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2140{
323e5ecd 2141 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2142 int i;
2143
bdca134f 2144 /* Free Transmit Descriptor ring */
a596084c
SZ		 2145 if (sc->tx_desc_base) {
2146 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2147 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2148 sc->tx_desc_dmap);
2149 bus_dma_tag_destroy(sc->tx_desc_dtag);
2150
2151 sc->tx_desc_base = NULL;
2152 }
bdca134f 2153
323e5ecd 2154 if (sc->tx_buf == NULL)
5330213c
SZ		 2155 return;
2156
2157 for (i = 0; i < ndesc; i++) {
323e5ecd 2158 tx_buffer = &sc->tx_buf[i];
5330213c
SZ		 2159
2160 KKASSERT(tx_buffer->m_head == NULL);
2161 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2162 }
2163 bus_dma_tag_destroy(sc->txtag);
2164
323e5ecd
SZ		 2165 kfree(sc->tx_buf, M_DEVBUF);
2166 sc->tx_buf = NULL;
5330213c
SZ		 2167}
2168
2169/*
2170 * The offload context needs to be set when we transfer the first
2171 * packet of a particular protocol (TCP/UDP). This routine has been
2172 * enhanced to deal with inserted VLAN headers.
2173 *
2174 * If the new packet's ether header length, ip header length and
2175 * csum offloading type are same as the previous packet, we should
2176 * avoid allocating a new csum context descriptor; mainly to take
2177 * advantage of the pipeline effect of the TX data read request.
2178 *
2179 * This function returns number of TX descrptors allocated for
2180 * csum context.
2181 */
2182static int
2183emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2184 uint32_t *txd_upper, uint32_t *txd_lower)
2185{
2186 struct e1000_context_desc *TXD;
5330213c
SZ		 2187 int curr_txd, ehdrlen, csum_flags;
2188 uint32_t cmd, hdr_len, ip_hlen;
5330213c
SZ		 2189
2190 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
68447568
SZ		 2191 ip_hlen = mp->m_pkthdr.csum_iphlen;
2192 ehdrlen = mp->m_pkthdr.csum_lhlen;
5330213c 2193
3eb0ea09 2194 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
5330213c
SZ		 2195 sc->csum_flags == csum_flags) {
2196 /*
2197 * Same csum offload context as the previous packets;
2198 * just return.
2199 */
2200 *txd_upper = sc->csum_txd_upper;
2201 *txd_lower = sc->csum_txd_lower;
2202 return 0;
2203 }
2204
2205 /*
2206 * Setup a new csum offload context.
2207 */
2208
2209 curr_txd = sc->next_avail_tx_desc;
5330213c
SZ		 2210 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2211
2212 cmd = 0;
2213
2214 /* Setup of IP header checksum. */
2215 if (csum_flags & CSUM_IP) {
2216 /*
2217 * Start offset for header checksum calculation.
2218 * End offset for header checksum calculation.
2219 * Offset of place to put the checksum.
2220 */
2221 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2222 TXD->lower_setup.ip_fields.ipcse =
2223 htole16(ehdrlen + ip_hlen - 1);
2224 TXD->lower_setup.ip_fields.ipcso =
2225 ehdrlen + offsetof(struct ip, ip_sum);
2226 cmd |= E1000_TXD_CMD_IP;
2227 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2228 }
2229 hdr_len = ehdrlen + ip_hlen;
2230
2231 if (csum_flags & CSUM_TCP) {
2232 /*
2233 * Start offset for payload checksum calculation.
2234 * End offset for payload checksum calculation.
2235 * Offset of place to put the checksum.
2236 */
2237 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2238 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2239 TXD->upper_setup.tcp_fields.tucso =
2240 hdr_len + offsetof(struct tcphdr, th_sum);
2241 cmd |= E1000_TXD_CMD_TCP;
2242 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2243 } else if (csum_flags & CSUM_UDP) {
2244 /*
2245 * Start offset for header checksum calculation.
2246 * End offset for header checksum calculation.
2247 * Offset of place to put the checksum.
2248 */
2249 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2250 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2251 TXD->upper_setup.tcp_fields.tucso =
2252 hdr_len + offsetof(struct udphdr, uh_sum);
2253 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2254 }
2255
2256 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2257 E1000_TXD_DTYP_D; /* Data descr */
2258
2259 /* Save the information for this csum offloading context */
3eb0ea09 2260 sc->csum_lhlen = ehdrlen;
5330213c
SZ		 2261 sc->csum_iphlen = ip_hlen;
2262 sc->csum_flags = csum_flags;
2263 sc->csum_txd_upper = *txd_upper;
2264 sc->csum_txd_lower = *txd_lower;
2265
2266 TXD->tcp_seg_setup.data = htole32(0);
2267 TXD->cmd_and_length =
2268 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ		 2269
2270 if (++curr_txd == sc->num_tx_desc)
2271 curr_txd = 0;
2272
2273 KKASSERT(sc->num_tx_desc_avail > 0);
2274 sc->num_tx_desc_avail--;
2275
2276 sc->next_avail_tx_desc = curr_txd;
2277 return 1;
2278}
2279
5330213c
SZ		 2280static void
2281emx_txeof(struct emx_softc *sc)
2282{
2283 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2284 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2285 int first, num_avail;
2286
2287 if (sc->tx_dd_head == sc->tx_dd_tail)
2288 return;
2289
2290 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2291 return;
2292
2293 num_avail = sc->num_tx_desc_avail;
2294 first = sc->next_tx_to_clean;
2295
2296 while (sc->tx_dd_head != sc->tx_dd_tail) {
2297 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2298 struct e1000_tx_desc *tx_desc;
5330213c
SZ		 2299
2300 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ		 2301 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2302 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2303
2304 if (++dd_idx == sc->num_tx_desc)
2305 dd_idx = 0;
2306
2307 while (first != dd_idx) {
2308 logif(pkt_txclean);
2309
5330213c
SZ		 2310 num_avail++;
2311
323e5ecd 2312 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 2313 if (tx_buffer->m_head) {
2314 ifp->if_opackets++;
2315 bus_dmamap_unload(sc->txtag,
2316 tx_buffer->map);
2317 m_freem(tx_buffer->m_head);
2318 tx_buffer->m_head = NULL;
2319 }
2320
2321 if (++first == sc->num_tx_desc)
2322 first = 0;
2323 }
2324 } else {
2325 break;
2326 }
2327 }
2328 sc->next_tx_to_clean = first;
2329 sc->num_tx_desc_avail = num_avail;
2330
2331 if (sc->tx_dd_head == sc->tx_dd_tail) {
2332 sc->tx_dd_head = 0;
2333 sc->tx_dd_tail = 0;
2334 }
2335
2336 if (!EMX_IS_OACTIVE(sc)) {
2337 ifp->if_flags &= ~IFF_OACTIVE;
2338
2339 /* All clean, turn off the timer */
2340 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2341 ifp->if_timer = 0;
2342 }
2343}
2344
2345static void
2346emx_tx_collect(struct emx_softc *sc)
2347{
2348 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2349 struct emx_txbuf *tx_buffer;
5330213c
SZ		 2350 int tdh, first, num_avail, dd_idx = -1;
2351
2352 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2353 return;
2354
2355 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2356 if (tdh == sc->next_tx_to_clean)
2357 return;
2358
2359 if (sc->tx_dd_head != sc->tx_dd_tail)
2360 dd_idx = sc->tx_dd[sc->tx_dd_head];
2361
2362 num_avail = sc->num_tx_desc_avail;
2363 first = sc->next_tx_to_clean;
2364
2365 while (first != tdh) {
2366 logif(pkt_txclean);
2367
5330213c
SZ		 2368 num_avail++;
2369
323e5ecd 2370 tx_buffer = &sc->tx_buf[first];
5330213c
SZ		 2371 if (tx_buffer->m_head) {
2372 ifp->if_opackets++;
2373 bus_dmamap_unload(sc->txtag,
2374 tx_buffer->map);
2375 m_freem(tx_buffer->m_head);
2376 tx_buffer->m_head = NULL;
2377 }
2378
2379 if (first == dd_idx) {
2380 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2381 if (sc->tx_dd_head == sc->tx_dd_tail) {
2382 sc->tx_dd_head = 0;
2383 sc->tx_dd_tail = 0;
2384 dd_idx = -1;
2385 } else {
2386 dd_idx = sc->tx_dd[sc->tx_dd_head];
2387 }
2388 }
2389
2390 if (++first == sc->num_tx_desc)
2391 first = 0;
2392 }
2393 sc->next_tx_to_clean = first;
2394 sc->num_tx_desc_avail = num_avail;
2395
2396 if (!EMX_IS_OACTIVE(sc)) {
2397 ifp->if_flags &= ~IFF_OACTIVE;
2398
2399 /* All clean, turn off the timer */
2400 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2401 ifp->if_timer = 0;
2402 }
2403}
2404
2405/*
2406 * When Link is lost sometimes there is work still in the TX ring
2407 * which will result in a watchdog, rather than allow that do an
2408 * attempted cleanup and then reinit here. Note that this has been
2409 * seens mostly with fiber adapters.
2410 */
2411static void
2412emx_tx_purge(struct emx_softc *sc)
2413{
2414 struct ifnet *ifp = &sc->arpcom.ac_if;
2415
2416 if (!sc->link_active && ifp->if_timer) {
2417 emx_tx_collect(sc);
2418 if (ifp->if_timer) {
2419 if_printf(ifp, "Link lost, TX pending, reinit\n");
2420 ifp->if_timer = 0;
2421 emx_init(sc);
2422 }
2423 }
2424}
2425
2426static int
c39e3a1f 2427emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ		 2428{
2429 struct mbuf *m;
2430 bus_dma_segment_t seg;
2431 bus_dmamap_t map;
323e5ecd 2432 struct emx_rxbuf *rx_buffer;
5330213c
SZ		 2433 int error, nseg;
2434
2435 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2436 if (m == NULL) {
c39e3a1f 2437 rdata->mbuf_cluster_failed++;
5330213c
SZ		 2438 if (init) {
2439 if_printf(&sc->arpcom.ac_if,
2440 "Unable to allocate RX mbuf\n");
2441 }
2442 return (ENOBUFS);
2443 }
2444 m->m_len = m->m_pkthdr.len = MCLBYTES;
2445
2446 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2447 m_adj(m, ETHER_ALIGN);
2448
c39e3a1f
SZ		 2449 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2450 rdata->rx_sparemap, m,
5330213c
SZ		 2451 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2452 if (error) {
2453 m_freem(m);
2454 if (init) {
2455 if_printf(&sc->arpcom.ac_if,
2456 "Unable to load RX mbuf\n");
2457 }
2458 return (error);
2459 }
2460
323e5ecd 2461 rx_buffer = &rdata->rx_buf[i];
5330213c 2462 if (rx_buffer->m_head != NULL)
c39e3a1f 2463 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ		 2464
2465 map = rx_buffer->map;
c39e3a1f
SZ		 2466 rx_buffer->map = rdata->rx_sparemap;
2467 rdata->rx_sparemap = map;
5330213c
SZ		 2468
2469 rx_buffer->m_head = m;
235b9d30 2470 rx_buffer->paddr = seg.ds_addr;
5330213c 2471
235b9d30 2472 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ		 2473 return (0);
2474}
2475
2476static int
c39e3a1f 2477emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ		 2478{
2479 device_t dev = sc->dev;
323e5ecd 2480 struct emx_rxbuf *rx_buffer;
b4d8c36b 2481 int i, error, rsize, nrxd;
bdca134f
SZ		 2482
2483 /*
2484 * Validate number of receive descriptors. It must not exceed
2485 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2486 */
b4d8c36b
SZ		 2487 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2488 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2489 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
bdca134f 2490 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
b4d8c36b 2491 EMX_DEFAULT_RXD, nrxd);
c39e3a1f 2492 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2493 } else {
b4d8c36b 2494 rdata->num_rx_desc = nrxd;
bdca134f
SZ		 2495 }
2496
2497 /*
2498 * Allocate Receive Descriptor ring
2499 */
235b9d30 2500 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2501 EMX_DBA_ALIGN);
235b9d30 2502 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2503 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ		 2504 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2505 &rdata->rx_desc_paddr);
235b9d30 2506 if (rdata->rx_desc == NULL) {
bdca134f 2507 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2508 return ENOMEM;
bdca134f 2509 }
5330213c 2510
323e5ecd
SZ		 2511 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2512 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ		 2513
2514 /*
2515 * Create DMA tag for rx buffers
2516 */
2517 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2518 1, 0, /* alignment, bounds */
2519 BUS_SPACE_MAXADDR, /* lowaddr */
2520 BUS_SPACE_MAXADDR, /* highaddr */
2521 NULL, NULL, /* filter, filterarg */
2522 MCLBYTES, /* maxsize */
2523 1, /* nsegments */
2524 MCLBYTES, /* maxsegsize */
2525 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2526 &rdata->rxtag);
5330213c
SZ		 2527 if (error) {
2528 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ		 2529 kfree(rdata->rx_buf, M_DEVBUF);
2530 rdata->rx_buf = NULL;
5330213c
SZ		 2531 return error;
2532 }
2533
2534 /*
2535 * Create spare DMA map for rx buffers
2536 */
c39e3a1f
SZ		 2537 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2538 &rdata->rx_sparemap);
5330213c
SZ		 2539 if (error) {
2540 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2541 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ		 2542 kfree(rdata->rx_buf, M_DEVBUF);
2543 rdata->rx_buf = NULL;
5330213c
SZ		 2544 return error;
2545 }
2546
2547 /*
2548 * Create DMA maps for rx buffers
2549 */
c39e3a1f 2550 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2551 rx_buffer = &rdata->rx_buf[i];
5330213c 2552
c39e3a1f 2553 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ		 2554 &rx_buffer->map);
2555 if (error) {
2556 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2557 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ		 2558 return error;
2559 }
2560 }
2561 return (0);
2562}
2563
c39e3a1f
SZ		 2564static void
2565emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2566{
2567 int i;
2568
2569 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2570 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ		 2571
2572 if (rx_buffer->m_head != NULL) {
2573 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2574 m_freem(rx_buffer->m_head);
2575 rx_buffer->m_head = NULL;
2576 }
2577 }
2578
2579 if (rdata->fmp != NULL)
2580 m_freem(rdata->fmp);
2581 rdata->fmp = NULL;
2582 rdata->lmp = NULL;
2583}
2584
5330213c 2585static int
c39e3a1f 2586emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ		 2587{
2588 int i, error;
2589
2590 /* Reset descriptor ring */
235b9d30 2591 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ		 2592
2593 /* Allocate new ones. */
c39e3a1f
SZ		 2594 for (i = 0; i < rdata->num_rx_desc; i++) {
2595 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ		 2596 if (error)
2597 return (error);
2598 }
2599
2600 /* Setup our descriptor pointers */
c39e3a1f 2601 rdata->next_rx_desc_to_check = 0;
5330213c
SZ		 2602
2603 return (0);
2604}
2605
2606static void
2607emx_init_rx_unit(struct emx_softc *sc)
2608{
2609 struct ifnet *ifp = &sc->arpcom.ac_if;
2610 uint64_t bus_addr;
2d0e5700 2611 uint32_t rctl, itr, rfctl;
3f939c23 2612 int i;
5330213c
SZ		 2613
2614 /*
2615 * Make sure receives are disabled while setting
2616 * up the descriptor ring
2617 */
2618 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2619 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2620
2621 /*
2622 * Set the interrupt throttling rate. Value is calculated
2623 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2624 */
2d0e5700
SZ		 2625 if (sc->int_throttle_ceil)
2626 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2627 else
2628 itr = 0;
2629 emx_set_itr(sc, itr);
5330213c 2630
235b9d30
SZ		 2631 /* Use extended RX descriptor */
2632 rfctl = E1000_RFCTL_EXTEN;
2633
5330213c 2634 /* Disable accelerated ackknowledge */
235b9d30
SZ		 2635 if (sc->hw.mac.type == e1000_82574)
2636 rfctl |= E1000_RFCTL_ACK_DIS;
2637
2638 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c 2639
65c7a6af
SZ		 2640 /*
2641 * Receive Checksum Offload for TCP and UDP
2642 *
2643 * Checksum offloading is also enabled if multiple receive
2644 * queue is to be supported, since we need it to figure out
2645 * packet type.
2646 */
13890b61
SZ		 2647 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2648 sc->rx_ring_cnt > 1) {
2d0e5700
SZ		 2649 uint32_t rxcsum;
2650
5330213c 2651 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ		 2652
2653 /*
2654 * NOTE:
2655 * PCSD must be enabled to enable multiple
2656 * receive queues.
2657 */
2658 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2659 E1000_RXCSUM_PCSD;
5330213c
SZ		 2660 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2661 }
2662
2663 /*
65c7a6af 2664 * Configure multiple receive queue (RSS)
3f939c23 2665 */
13890b61 2666 if (sc->rx_ring_cnt > 1) {
89d8e73d
SZ		 2667 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2668 uint32_t reta;
2669
13890b61
SZ		 2670 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2671 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
89d8e73d 2672
65c7a6af
SZ		 2673 /*
2674 * NOTE:
2675 * When we reach here, RSS has already been disabled
2676 * in emx_stop(), so we could safely configure RSS key
2677 * and redirect table.
2678 */
3f939c23 2679
65c7a6af
SZ		 2680 /*
2681 * Configure RSS key
2682 */
89d8e73d
SZ		 2683 toeplitz_get_key(key, sizeof(key));
2684 for (i = 0; i < EMX_NRSSRK; ++i) {
2685 uint32_t rssrk;
2686
2687 rssrk = EMX_RSSRK_VAL(key, i);
2688 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2689
2690 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2691 }
3f939c23 2692
65c7a6af 2693 /*
89d8e73d
SZ		 2694 * Configure RSS redirect table in following fashion:
2695 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2696 */
89d8e73d
SZ		 2697 reta = 0;
2698 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2699 uint32_t q;
2700
13890b61 2701 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
89d8e73d
SZ		 2702 reta |= q << (8 * i);
2703 }
2704 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2705
65c7a6af
SZ		 2706 for (i = 0; i < EMX_NRETA; ++i)
2707 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2708
65c7a6af
SZ		 2709 /*
2710 * Enable multiple receive queues.
2711 * Enable IPv4 RSS standard hash functions.
2712 * Disable RSS interrupt.
2713 */
2714 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2715 E1000_MRQC_ENABLE_RSS_2Q |
2716 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2717 E1000_MRQC_RSS_FIELD_IPV4);
2718 }
3f939c23
SZ		 2719
2720 /*
5330213c
SZ		 2721 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2722 * long latencies are observed, like Lenovo X60. This
2723 * change eliminates the problem, but since having positive
2724 * values in RDTR is a known source of problems on other
2725 * platforms another solution is being sought.
2726 */
2727 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2728 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2729 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2730 }
2731
13890b61 2732 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2d0e5700
SZ		 2733 struct emx_rxdata *rdata = &sc->rx_data[i];
2734
2735 /*
2736 * Setup the Base and Length of the Rx Descriptor Ring
2737 */
2738 bus_addr = rdata->rx_desc_paddr;
2739 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2740 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2741 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2742 (uint32_t)(bus_addr >> 32));
2743 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2744 (uint32_t)bus_addr);
2745
2746 /*
2747 * Setup the HW Rx Head and Tail Descriptor Pointers
2748 */
3f939c23
SZ		 2749 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2750 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2751 sc->rx_data[i].num_rx_desc - 1);
2752 }
2753
2d0e5700
SZ		 2754 /* Setup the Receive Control Register */
2755 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2756 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2757 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2758 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2759
2760 /* Make sure VLAN Filters are off */
2761 rctl &= ~E1000_RCTL_VFE;
2762
2763 /* Don't store bad paket */
2764 rctl &= ~E1000_RCTL_SBP;
2765
2766 /* MCLBYTES */
2767 rctl |= E1000_RCTL_SZ_2048;
2768
2769 if (ifp->if_mtu > ETHERMTU)
2770 rctl |= E1000_RCTL_LPE;
2771 else
2772 rctl &= ~E1000_RCTL_LPE;
2773
3f939c23
SZ		 2774 /* Enable Receives */
2775 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ		 2776}
2777
2778static void
c39e3a1f 2779emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2780{
323e5ecd 2781 struct emx_rxbuf *rx_buffer;
5330213c
SZ		 2782 int i;
2783
bdca134f 2784 /* Free Receive Descriptor ring */
235b9d30 2785 if (rdata->rx_desc) {
c39e3a1f 2786 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2787 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ		 2788 rdata->rx_desc_dmap);
2789 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2790
235b9d30 2791 rdata->rx_desc = NULL;
a596084c 2792 }
bdca134f 2793
323e5ecd 2794 if (rdata->rx_buf == NULL)
5330213c
SZ		 2795 return;
2796
2797 for (i = 0; i < ndesc; i++) {
323e5ecd 2798 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ		 2799
2800 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2801 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2802 }
c39e3a1f
SZ		 2803 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2804 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2805
323e5ecd
SZ		 2806 kfree(rdata->rx_buf, M_DEVBUF);
2807 rdata->rx_buf = NULL;
5330213c
SZ		 2808}
2809
2810static void
c39e3a1f 2811emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2812{
c39e3a1f 2813 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2814 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2815 uint32_t staterr;
235b9d30 2816 emx_rxdesc_t *current_desc;
5330213c
SZ		 2817 struct mbuf *mp;
2818 int i;
5330213c 2819
c39e3a1f 2820 i = rdata->next_rx_desc_to_check;
235b9d30
SZ		 2821 current_desc = &rdata->rx_desc[i];
2822 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2823
235b9d30 2824 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ		 2825 return;
2826
235b9d30 2827 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2828 struct pktinfo *pi = NULL, pi0;
235b9d30 2829 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2830 struct mbuf *m = NULL;
0acc29d6 2831 int eop, len;
5330213c
SZ		 2832
2833 logif(pkt_receive);
2834
235b9d30 2835 mp = rx_buf->m_head;
5330213c
SZ		 2836
2837 /*
2838 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2839 * needs to access the last received byte in the mbuf.
2840 */
235b9d30 2841 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ		 2842 BUS_DMASYNC_POSTREAD);
2843
0acc29d6 2844 len = le16toh(current_desc->rxd_length);
235b9d30 2845 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ		 2846 count--;
2847 eop = 1;
5330213c
SZ		 2848 } else {
2849 eop = 0;
5330213c
SZ		 2850 }
2851
235b9d30
SZ		 2852 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2853 uint16_t vlan = 0;
3f939c23 2854 uint32_t mrq, rss_hash;
235b9d30
SZ		 2855
2856 /*
2857 * Save several necessary information,
2858 * before emx_newbuf() destroy it.
2859 */
2860 if ((staterr & E1000_RXD_STAT_VP) && eop)
2861 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2862
3f939c23
SZ		 2863 mrq = le32toh(current_desc->rxd_mrq);
2864 rss_hash = le32toh(current_desc->rxd_rss);
2865
2866 EMX_RSS_DPRINTF(sc, 10,
2867 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2868 ring_idx, mrq, rss_hash);
2869
c39e3a1f 2870 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ		 2871 ifp->if_iqdrops++;
2872 goto discard;
2873 }
2874
2875 /* Assign correct length to the current fragment */
2876 mp->m_len = len;
2877
c39e3a1f 2878 if (rdata->fmp == NULL) {
5330213c 2879 mp->m_pkthdr.len = len;
c39e3a1f
SZ		 2880 rdata->fmp = mp; /* Store the first mbuf */
2881 rdata->lmp = mp;
5330213c
SZ		 2882 } else {
2883 /*
2884 * Chain mbuf's together
2885 */
c39e3a1f
SZ		 2886 rdata->lmp->m_next = mp;
2887 rdata->lmp = rdata->lmp->m_next;
2888 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ		 2889 }
2890
2891 if (eop) {
c39e3a1f 2892 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ		 2893 ifp->if_ipackets++;
2894
235b9d30
SZ		 2895 if (ifp->if_capenable & IFCAP_RXCSUM)
2896 emx_rxcsum(staterr, rdata->fmp);
5330213c 2897
235b9d30 2898 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2899 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2900 vlan;
c39e3a1f 2901 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2902 }
c39e3a1f
SZ		 2903 m = rdata->fmp;
2904 rdata->fmp = NULL;
2905 rdata->lmp = NULL;
3f939c23 2906
9cc86e17
SZ		 2907 if (ifp->if_capenable & IFCAP_RSS) {
2908 pi = emx_rssinfo(m, &pi0, mrq,
2909 rss_hash, staterr);
2910 }
3f939c23
SZ		 2911#ifdef EMX_RSS_DEBUG
2912 rdata->rx_pkts++;
2913#endif
5330213c
SZ		 2914 }
2915 } else {
2916 ifp->if_ierrors++;
2917discard:
235b9d30 2918 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ		 2919 if (rdata->fmp != NULL) {
2920 m_freem(rdata->fmp);
2921 rdata->fmp = NULL;
2922 rdata->lmp = NULL;
5330213c
SZ		 2923 }
2924 m = NULL;
2925 }
2926
5330213c 2927 if (m != NULL)
eda7db08 2928 ether_input_pkt(ifp, m, pi);
5330213c
SZ		 2929
2930 /* Advance our pointers to the next descriptor. */
c39e3a1f 2931 if (++i == rdata->num_rx_desc)
5330213c 2932 i = 0;
235b9d30
SZ		 2933
2934 current_desc = &rdata->rx_desc[i];
2935 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2936 }
c39e3a1f 2937 rdata->next_rx_desc_to_check = i;
5330213c 2938
3f939c23 2939 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2940 if (--i < 0)
c39e3a1f 2941 i = rdata->num_rx_desc - 1;
3f939c23 2942 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ		 2943}
2944
2945static void
5330213c
SZ		 2946emx_enable_intr(struct emx_softc *sc)
2947{
2d0e5700
SZ		 2948 uint32_t ims_mask = IMS_ENABLE_MASK;
2949
6d435846 2950 lwkt_serialize_handler_enable(&sc->main_serialize);
2d0e5700
SZ		 2951
2952#if 0
2953 if (sc->hw.mac.type == e1000_82574) {
2954 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2955 ims_mask |= EM_MSIX_MASK;
2956 }
2957#endif
2958 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
5330213c
SZ		 2959}
2960
2961static void
2962emx_disable_intr(struct emx_softc *sc)
2963{
2d0e5700
SZ		 2964 if (sc->hw.mac.type == e1000_82574)
2965 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
5330213c 2966 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2d0e5700 2967
6d435846 2968 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ		 2969}
2970
2971/*
2972 * Bit of a misnomer, what this really means is
2973 * to enable OS management of the system... aka
2974 * to disable special hardware management features
2975 */
2976static void
2977emx_get_mgmt(struct emx_softc *sc)
2978{
2979 /* A shared code workaround */
2980 if (sc->has_manage) {
2981 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2982 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2983
2984 /* disable hardware interception of ARP */
2985 manc &= ~(E1000_MANC_ARP_EN);
2986
2987 /* enable receiving management packets to the host */
2988 manc |= E1000_MANC_EN_MNG2HOST;
2989#define E1000_MNG2HOST_PORT_623 (1 << 5)
2990#define E1000_MNG2HOST_PORT_664 (1 << 6)
2991 manc2h |= E1000_MNG2HOST_PORT_623;
2992 manc2h |= E1000_MNG2HOST_PORT_664;
2993 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2994
2995 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2996 }
2997}
2998
2999/*
3000 * Give control back to hardware management
3001 * controller if there is one.
3002 */
3003static void
3004emx_rel_mgmt(struct emx_softc *sc)
3005{
3006 if (sc->has_manage) {
3007 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3008
3009 /* re-enable hardware interception of ARP */
3010 manc |= E1000_MANC_ARP_EN;
3011 manc &= ~E1000_MANC_EN_MNG2HOST;
3012
3013 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3014 }
3015}
3016
3017/*
3018 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3019 * For ASF and Pass Through versions of f/w this means that
3020 * the driver is loaded. For AMT version (only with 82573)
3021 * of the f/w this means that the network i/f is open.
3022 */
3023static void
3024emx_get_hw_control(struct emx_softc *sc)
3025{
5330213c 3026 /* Let firmware know the driver has taken over */
2d0e5700
SZ		 3027 if (sc->hw.mac.type == e1000_82573) {
3028 uint32_t swsm;
3029
5330213c
SZ		 3030 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3031 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3032 swsm | E1000_SWSM_DRV_LOAD);
2d0e5700
SZ		 3033 } else {
3034 uint32_t ctrl_ext;
5330213c 3035
5330213c
SZ		 3036 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3037 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3038 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
5330213c 3039 }
2d0e5700 3040 sc->control_hw = 1;
5330213c
SZ		 3041}
3042
3043/*
3044 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3045 * For ASF and Pass Through versions of f/w this means that the
3046 * driver is no longer loaded. For AMT version (only with 82573)
3047 * of the f/w this means that the network i/f is closed.
3048 */
3049static void
3050emx_rel_hw_control(struct emx_softc *sc)
3051{
2d0e5700
SZ		 3052 if (!sc->control_hw)
3053 return;
3054 sc->control_hw = 0;
5330213c
SZ		 3055
3056 /* Let firmware taken over control of h/w */
2d0e5700
SZ		 3057 if (sc->hw.mac.type == e1000_82573) {
3058 uint32_t swsm;
3059
5330213c
SZ		 3060 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3061 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3062 swsm & ~E1000_SWSM_DRV_LOAD);
2d0e5700
SZ		 3063 } else {
3064 uint32_t ctrl_ext;
5330213c 3065
5330213c
SZ		 3066 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3067 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3068 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
5330213c
SZ		 3069 }
3070}
3071
3072static int
3073emx_is_valid_eaddr(const uint8_t *addr)
3074{
3075 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3076
3077 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3078 return (FALSE);
3079
3080 return (TRUE);
3081}
3082
3083/*
3084 * Enable PCI Wake On Lan capability
3085 */
3086void
3087emx_enable_wol(device_t dev)
3088{
3089 uint16_t cap, status;
3090 uint8_t id;
3091
3092 /* First find the capabilities pointer*/
3093 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3094
3095 /* Read the PM Capabilities */
3096 id = pci_read_config(dev, cap, 1);
3097 if (id != PCIY_PMG) /* Something wrong */
3098 return;
3099
3100 /*
3101 * OK, we have the power capabilities,
3102 * so now get the status register
3103 */
3104 cap += PCIR_POWER_STATUS;
3105 status = pci_read_config(dev, cap, 2);
3106 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3107 pci_write_config(dev, cap, status, 2);
3108}
3109
3110static void
3111emx_update_stats(struct emx_softc *sc)
3112{
3113 struct ifnet *ifp = &sc->arpcom.ac_if;
3114
3115 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3116 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3117 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3118 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3119 }
3120 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3121 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3122 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3123 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3124
3125 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3126 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3127 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3128 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3129 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3130 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3131 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3132 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3133 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3134 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3135 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3136 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3137 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3138 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3139 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3140 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3141 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3142 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3143 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3144 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3145
3146 /* For the 64-bit byte counters the low dword must be read first. */
3147 /* Both registers clear on the read of the high dword */
3148
3149 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3150 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3151
3152 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3153 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3154 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3155 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3156 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3157
3158 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3159 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3160
3161 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3162 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3163 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3164 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3165 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3166 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3167 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3168 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3169 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3170 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3171
3172 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3173 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3174 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3175 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3176 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3177 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3178
3179 ifp->if_collisions = sc->stats.colc;
3180
3181 /* Rx Errors */
3182 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3183 sc->stats.crcerrs + sc->stats.algnerrc +
3184 sc->stats.ruc + sc->stats.roc +
3185 sc->stats.mpc + sc->stats.cexterr;
3186
3187 /* Tx Errors */
3188 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3189 sc->watchdog_events;
3190}
3191
3192static void
3193emx_print_debug_info(struct emx_softc *sc)
3194{
3195 device_t dev = sc->dev;
3196 uint8_t *hw_addr = sc->hw.hw_addr;
3197
3198 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3199 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3200 E1000_READ_REG(&sc->hw, E1000_CTRL),
3201 E1000_READ_REG(&sc->hw, E1000_RCTL));
3202 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3203 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3204 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3205 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3206 sc->hw.fc.high_water, sc->hw.fc.low_water);
3207 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3208 E1000_READ_REG(&sc->hw, E1000_TIDV),
3209 E1000_READ_REG(&sc->hw, E1000_TADV));
3210 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3211 E1000_READ_REG(&sc->hw, E1000_RDTR),
3212 E1000_READ_REG(&sc->hw, E1000_RADV));
3213 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3214 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3215 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3216 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3217 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3218 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3219 device_printf(dev, "Num Tx descriptors avail = %d\n",
3220 sc->num_tx_desc_avail);
3221 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3222 sc->no_tx_desc_avail1);
3223 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3224 sc->no_tx_desc_avail2);
3225 device_printf(dev, "Std mbuf failed = %ld\n",
3226 sc->mbuf_alloc_failed);
3227 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3228 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ		 3229 device_printf(dev, "Driver dropped packets = %ld\n",
3230 sc->dropped_pkts);
3231 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3232 sc->no_tx_dma_setup);
5330213c
SZ		 3233}
3234
3235static void
3236emx_print_hw_stats(struct emx_softc *sc)
3237{
3238 device_t dev = sc->dev;
3239
3240 device_printf(dev, "Excessive collisions = %lld\n",
3241 (long long)sc->stats.ecol);
3242#if (DEBUG_HW > 0) /* Dont output these errors normally */
3243 device_printf(dev, "Symbol errors = %lld\n",
3244 (long long)sc->stats.symerrs);
3245#endif
3246 device_printf(dev, "Sequence errors = %lld\n",
3247 (long long)sc->stats.sec);
3248 device_printf(dev, "Defer count = %lld\n",
3249 (long long)sc->stats.dc);
3250 device_printf(dev, "Missed Packets = %lld\n",
3251 (long long)sc->stats.mpc);
3252 device_printf(dev, "Receive No Buffers = %lld\n",
3253 (long long)sc->stats.rnbc);
3254 /* RLEC is inaccurate on some hardware, calculate our own. */
3255 device_printf(dev, "Receive Length Errors = %lld\n",
3256 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3257 device_printf(dev, "Receive errors = %lld\n",
3258 (long long)sc->stats.rxerrc);
3259 device_printf(dev, "Crc errors = %lld\n",
3260 (long long)sc->stats.crcerrs);
3261 device_printf(dev, "Alignment errors = %lld\n",
3262 (long long)sc->stats.algnerrc);
3263 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3264 (long long)sc->stats.cexterr);
3265 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3266 device_printf(dev, "watchdog timeouts = %ld\n",
3267 sc->watchdog_events);
3268 device_printf(dev, "XON Rcvd = %lld\n",
3269 (long long)sc->stats.xonrxc);
3270 device_printf(dev, "XON Xmtd = %lld\n",
3271 (long long)sc->stats.xontxc);
3272 device_printf(dev, "XOFF Rcvd = %lld\n",
3273 (long long)sc->stats.xoffrxc);
3274 device_printf(dev, "XOFF Xmtd = %lld\n",
3275 (long long)sc->stats.xofftxc);
3276 device_printf(dev, "Good Packets Rcvd = %lld\n",
3277 (long long)sc->stats.gprc);
3278 device_printf(dev, "Good Packets Xmtd = %lld\n",
3279 (long long)sc->stats.gptc);
3280}
3281
3282static void
3283emx_print_nvm_info(struct emx_softc *sc)
3284{
3285 uint16_t eeprom_data;
3286 int i, j, row = 0;
3287
3288 /* Its a bit crude, but it gets the job done */
3289 kprintf("\nInterface EEPROM Dump:\n");
3290 kprintf("Offset\n0x0000 ");
3291 for (i = 0, j = 0; i < 32; i++, j++) {
3292 if (j == 8) { /* Make the offset block */
3293 j = 0; ++row;
3294 kprintf("\n0x00%x0 ",row);
3295 }
3296 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3297 kprintf("%04x ", eeprom_data);
3298 }
3299 kprintf("\n");
3300}
3301
3302static int
3303emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3304{
3305 struct emx_softc *sc;
3306 struct ifnet *ifp;
3307 int error, result;
3308
3309 result = -1;
3310 error = sysctl_handle_int(oidp, &result, 0, req);
3311 if (error || !req->newptr)
3312 return (error);
3313
3314 sc = (struct emx_softc *)arg1;
3315 ifp = &sc->arpcom.ac_if;
3316
6d435846 3317 ifnet_serialize_all(ifp);
5330213c
SZ		 3318
3319 if (result == 1)
3320 emx_print_debug_info(sc);
3321
3322 /*
3323 * This value will cause a hex dump of the
3324 * first 32 16-bit words of the EEPROM to
3325 * the screen.
3326 */
3327 if (result == 2)
3328 emx_print_nvm_info(sc);
3329
6d435846 3330 ifnet_deserialize_all(ifp);
5330213c
SZ		 3331
3332 return (error);
3333}
3334
3335static int
3336emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3337{
3338 int error, result;
3339
3340 result = -1;
3341 error = sysctl_handle_int(oidp, &result, 0, req);
3342 if (error || !req->newptr)
3343 return (error);
3344
3345 if (result == 1) {
3346 struct emx_softc *sc = (struct emx_softc *)arg1;
3347 struct ifnet *ifp = &sc->arpcom.ac_if;
3348
6d435846 3349 ifnet_serialize_all(ifp);
5330213c 3350 emx_print_hw_stats(sc);
6d435846 3351 ifnet_deserialize_all(ifp);
5330213c
SZ		 3352 }
3353 return (error);
3354}
3355
3356static void
3357emx_add_sysctl(struct emx_softc *sc)
3358{
3f939c23
SZ		 3359#ifdef EMX_RSS_DEBUG
3360 char rx_pkt[32];
3361 int i;
3362#endif
5330213c
SZ		 3363
3364 sysctl_ctx_init(&sc->sysctl_ctx);
3365 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3366 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3367 device_get_nameunit(sc->dev),
3368 CTLFLAG_RD, 0, "");
3369 if (sc->sysctl_tree == NULL) {
3370 device_printf(sc->dev, "can't add sysctl node\n");
3371 return;
3372 }
3373
3374 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3375 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3376 emx_sysctl_debug_info, "I", "Debug Information");
3377
3378 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3379 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3380 emx_sysctl_stats, "I", "Statistics");
3381
3382 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ		 3383 OID_AUTO, "rxd", CTLFLAG_RD,
3384 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3385 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3386 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3387
5330213c
SZ		 3388 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3389 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3390 sc, 0, emx_sysctl_int_throttle, "I",
3391 "interrupt throttling rate");
3392 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3393 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3394 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3395 "# segments per TX interrupt");
3f939c23 3396
8434a83b 3397 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
13890b61
SZ		 3398 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3399 &sc->rx_ring_cnt, 0, "RX ring count");
8434a83b 3400
3f939c23
SZ		 3401#ifdef EMX_RSS_DEBUG
3402 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3403 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3404 0, "RSS debug level");
65c7a6af 3405 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3406 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3407 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3408 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3409 rx_pkt, CTLFLAG_RW,
3f939c23
SZ		 3410 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3411 }
3412#endif
5330213c
SZ		 3413}
3414
3415static int
3416emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3417{
3418 struct emx_softc *sc = (void *)arg1;
3419 struct ifnet *ifp = &sc->arpcom.ac_if;
3420 int error, throttle;
3421
3422 throttle = sc->int_throttle_ceil;
3423 error = sysctl_handle_int(oidp, &throttle, 0, req);
3424 if (error || req->newptr == NULL)
3425 return error;
3426 if (throttle < 0 || throttle > 1000000000 / 256)
3427 return EINVAL;
3428
3429 if (throttle) {
3430 /*
3431 * Set the interrupt throttling rate in 256ns increments,
3432 * recalculate sysctl value assignment to get exact frequency.
3433 */
3434 throttle = 1000000000 / 256 / throttle;
3435
3436 /* Upper 16bits of ITR is reserved and should be zero */
3437 if (throttle & 0xffff0000)
3438 return EINVAL;
3439 }
3440
6d435846 3441 ifnet_serialize_all(ifp);
5330213c
SZ		 3442
3443 if (throttle)
3444 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3445 else
3446 sc->int_throttle_ceil = 0;
3447
3448 if (ifp->if_flags & IFF_RUNNING)
2d0e5700 3449 emx_set_itr(sc, throttle);
5330213c 3450
6d435846 3451 ifnet_deserialize_all(ifp);
5330213c
SZ		 3452
3453 if (bootverbose) {
3454 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3455 sc->int_throttle_ceil);
3456 }
3457 return 0;
3458}
3459
3460static int
3461emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3462{
3463 struct emx_softc *sc = (void *)arg1;
3464 struct ifnet *ifp = &sc->arpcom.ac_if;
3465 int error, segs;
3466
3467 segs = sc->tx_int_nsegs;
3468 error = sysctl_handle_int(oidp, &segs, 0, req);
3469 if (error || req->newptr == NULL)
3470 return error;
3471 if (segs <= 0)
3472 return EINVAL;
3473
6d435846 3474 ifnet_serialize_all(ifp);
5330213c
SZ		 3475
3476 /*
3477 * Don't allow int_tx_nsegs to become:
3478 * o Less the oact_tx_desc
3479 * o Too large that no TX desc will cause TX interrupt to
3480 * be generated (OACTIVE will never recover)
3481 * o Too small that will cause tx_dd[] overflow
3482 */
3483 if (segs < sc->oact_tx_desc ||
3484 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3485 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3486 error = EINVAL;
3487 } else {
3488 error = 0;
3489 sc->tx_int_nsegs = segs;
3490 }
3491
6d435846 3492 ifnet_deserialize_all(ifp);
5330213c
SZ		 3493
3494 return error;
3495}
071699f8
SZ		 3496
3497static int
3498emx_dma_alloc(struct emx_softc *sc)
3499{
3f939c23 3500 int error, i;
071699f8
SZ		 3501
3502 /*
3503 * Create top level busdma tag
3504 */
3505 error = bus_dma_tag_create(NULL, 1, 0,
3506 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3507 NULL, NULL,
3508 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3509 0, &sc->parent_dtag);
3510 if (error) {
3511 device_printf(sc->dev, "could not create top level DMA tag\n");
3512 return error;
3513 }
3514
3515 /*
3516 * Allocate transmit descriptors ring and buffers
3517 */
3518 error = emx_create_tx_ring(sc);
3519 if (error) {
3520 device_printf(sc->dev, "Could not setup transmit structures\n");
3521 return error;
3522 }
3523
3524 /*
3525 * Allocate receive descriptors ring and buffers
3526 */
65c7a6af 3527 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3528 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3529 if (error) {
3530 device_printf(sc->dev,
3531 "Could not setup receive structures\n");
3532 return error;
3533 }
071699f8
SZ		 3534 }
3535 return 0;
3536}
3537
3538static void
3539emx_dma_free(struct emx_softc *sc)
3540{
3f939c23
SZ		 3541 int i;
3542
071699f8 3543 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3544
65c7a6af 3545 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ		 3546 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3547 sc->rx_data[i].num_rx_desc);
3548 }
071699f8
SZ		 3549
3550 /* Free top level busdma tag */
3551 if (sc->parent_dtag != NULL)
3552 bus_dma_tag_destroy(sc->parent_dtag);
3553}
6d435846
SZ		 3554
3555static void
3556emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3557{
3558 struct emx_softc *sc = ifp->if_softc;
6d435846 3559
8f594b38
SZ		 3560 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3561 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ		 3562}
3563
3564static void
3565emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3566{
3567 struct emx_softc *sc = ifp->if_softc;
6d435846 3568
8f594b38
SZ		 3569 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3570 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846
SZ		 3571}
3572
3573static int
3574emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3575{
3576 struct emx_softc *sc = ifp->if_softc;
6d435846 3577
8f594b38
SZ		 3578 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3579 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
6d435846 3580}
bca7c435
SZ		 3581
3582static void
3583emx_serialize_skipmain(struct emx_softc *sc)
3584{
3585 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3586}
3587
3588static void
3589emx_deserialize_skipmain(struct emx_softc *sc)
3590{
3591 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3592}
2c9effcf
SZ		 3593
3594#ifdef INVARIANTS
3595
3596static void
3597emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
8f594b38 3598 boolean_t serialized)
2c9effcf
SZ		 3599{
3600 struct emx_softc *sc = ifp->if_softc;
2c9effcf 3601
8f594b38
SZ		 3602 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3603 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
2c9effcf
SZ		 3604}
3605
3606#endif /* INVARIANTS */
b3a7093f
SZ		 3607
3608#ifdef IFPOLL_ENABLE
3609
3610static void
3611emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3612{
3613 struct emx_softc *sc = ifp->if_softc;
3614 uint32_t reg_icr;
3615
3616 ASSERT_SERIALIZED(&sc->main_serialize);
3617
3618 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3619 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3cbe4103
SZ		 3620 emx_serialize_skipmain(sc);
3621
3622 callout_stop(&sc->timer);
3623 sc->hw.mac.get_link_status = 1;
3624 emx_update_link_status(sc);
3625 callout_reset(&sc->timer, hz, emx_timer, sc);
3626
3627 emx_deserialize_skipmain(sc);
b3a7093f
SZ		 3628 }
3629}
3630
3631static void
3632emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3633{
3634 struct emx_softc *sc = ifp->if_softc;
3635
3636 ASSERT_SERIALIZED(&sc->tx_serialize);
3637
3638 emx_txeof(sc);
3639 if (!ifq_is_empty(&ifp->if_snd))
3640 if_devstart(ifp);
3641}
3642
3643static void
3644emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3645{
3646 struct emx_softc *sc = ifp->if_softc;
3647 struct emx_rxdata *rdata = arg;
3648
3649 ASSERT_SERIALIZED(&rdata->rx_serialize);
3650
3651 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3652}
3653
3654static void
3655emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3656{
3657 struct emx_softc *sc = ifp->if_softc;
3658
3659 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3660
3661 if (info) {
3662 int i;
3663
3664 info->ifpi_status.status_func = emx_qpoll_status;
3665 info->ifpi_status.serializer = &sc->main_serialize;
3666
3667 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3668 info->ifpi_tx[0].arg = NULL;
3669 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3670
3671 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3672 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3673 info->ifpi_rx[i].arg = &sc->rx_data[i];
3674 info->ifpi_rx[i].serializer =
3675 &sc->rx_data[i].rx_serialize;
3676 }
3677
3678 if (ifp->if_flags & IFF_RUNNING)
3679 emx_disable_intr(sc);
3680 } else if (ifp->if_flags & IFF_RUNNING) {
3681 emx_enable_intr(sc);
3682 }
3683}
3684
3685#endif /* IFPOLL_ENABLE */
2d0e5700
SZ		 3686
3687static void
3688emx_set_itr(struct emx_softc *sc, uint32_t itr)
3689{
3690 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3691 if (sc->hw.mac.type == e1000_82574) {
3692 int i;
3693
3694 /*
3695 * When using MSIX interrupts we need to
3696 * throttle using the EITR register
3697 */
3698 for (i = 0; i < 4; ++i)
3699 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3700 }
3701}
6d5e2922
SZ		 3702
3703/*
3704 * Disable the L0s, 82574L Errata #20
3705 */
3706static void
3707emx_disable_aspm(struct emx_softc *sc)
3708{
04eb0cef 3709 uint16_t link_cap, link_ctrl, disable;
6d5e2922
SZ		 3710 uint8_t pcie_ptr, reg;
3711 device_t dev = sc->dev;
3712
3713 switch (sc->hw.mac.type) {
04eb0cef
SZ		 3714 case e1000_82571:
3715 case e1000_82572:
6d5e2922 3716 case e1000_82573:
04eb0cef
SZ		 3717 /*
3718 * 82573 specification update
a835687d
SZ		 3719 * errata #8 disable L0s