Use pcidevs.h.
[dragonfly.git] / sys / dev / netif / rl / if_rl.c
CommitLineData
984263bc
MD
1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
cdf89432 33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.30 2005/12/31 14:08:00 sephe Exp $
984263bc
MD
34 */
35
36/*
37 * RealTek 8129/8139 PCI NIC driver
38 *
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
41 * www.realtek.com.tw.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48/*
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
54 *
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
63 *
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
69 * levels.
70 *
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
74 *
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
79 * filter.
80 *
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
85 */
86
2b71c8f1
SZ
87#include "opt_polling.h"
88
984263bc 89#include <sys/param.h>
ca59556a 90#include <sys/endian.h>
984263bc
MD
91#include <sys/systm.h>
92#include <sys/sockio.h>
93#include <sys/mbuf.h>
94#include <sys/malloc.h>
95#include <sys/kernel.h>
ca59556a 96#include <sys/module.h>
984263bc 97#include <sys/socket.h>
78195a76 98#include <sys/serialize.h>
a3fbe745 99#include <sys/thread2.h>
984263bc
MD
100
101#include <net/if.h>
c2ffa639 102#include <net/ifq_var.h>
984263bc
MD
103#include <net/if_arp.h>
104#include <net/ethernet.h>
105#include <net/if_dl.h>
106#include <net/if_media.h>
107
108#include <net/bpf.h>
109
984263bc
MD
110#include <machine/bus_pio.h>
111#include <machine/bus_memio.h>
112#include <machine/bus.h>
113#include <machine/resource.h>
114#include <sys/bus.h>
115#include <sys/rman.h>
116
ca59556a
JS
117#include <dev/netif/mii_layer/mii.h>
118#include <dev/netif/mii_layer/miivar.h>
984263bc 119
1f2de5d4
MD
120#include <bus/pci/pcireg.h>
121#include <bus/pci/pcivar.h>
984263bc
MD
122
123/* "controller miibus0" required. See GENERIC if you get errors here. */
124#include "miibus_if.h"
125
126/*
127 * Default to using PIO access for this driver. On SMP systems,
128 * there appear to be problems with memory mapped mode: it looks like
129 * doing too many memory mapped access back to back in rapid succession
130 * can hang the bus. I'm inclined to blame this on crummy design/construction
131 * on the part of RealTek. Memory mapped mode does appear to work on
132 * uniprocessor systems though.
133 */
134#define RL_USEIOSPACE
135
ca59556a 136#include <dev/netif/rl/if_rlreg.h>
984263bc 137
984263bc
MD
138/*
139 * Various supported device vendors/types and their names.
140 */
ca59556a
JS
141static struct rl_type {
142 uint16_t rl_vid;
143 uint16_t rl_did;
144 const char *rl_name;
145} rl_devs[] = {
984263bc
MD
146 { RT_VENDORID, RT_DEVICEID_8129,
147 "RealTek 8129 10/100BaseTX" },
148 { RT_VENDORID, RT_DEVICEID_8139,
149 "RealTek 8139 10/100BaseTX" },
ca59556a
JS
150 { RT_VENDORID, RT_DEVICEID_8138,
151 "RealTek 8139 10/100BaseTX CardBus" },
984263bc
MD
152 { ACCTON_VENDORID, ACCTON_DEVICEID_5030,
153 "Accton MPX 5030/5038 10/100BaseTX" },
154 { DELTA_VENDORID, DELTA_DEVICEID_8139,
155 "Delta Electronics 8139 10/100BaseTX" },
156 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139,
157 "Addtron Technolgy 8139 10/100BaseTX" },
158 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS,
159 "D-Link DFE-530TX+ 10/100BaseTX" },
ca59556a
JS
160 { DLINK_VENDORID, DLINK_DEVICEID_690TXD,
161 "D-Link DFE-690TX 10/100BaseTX" },
984263bc
MD
162 { NORTEL_VENDORID, ACCTON_DEVICEID_5030,
163 "Nortel Networks 10/100BaseTX" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF,
165 "Peppercon AG ROL/F" },
ca59556a
JS
166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD,
167 "Corega FEther CB-TXD" },
168 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD,
169 "Corega FEtherII CB-TXD" },
170 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX,
171 "Planex FNW-3800-TX" },
984263bc
MD
172 { 0, 0, NULL }
173};
174
ca59556a
JS
175static int rl_probe(device_t);
176static int rl_attach(device_t);
177static int rl_detach(device_t);
178
179static int rl_encap(struct rl_softc *, struct mbuf * );
180
181static void rl_rxeof(struct rl_softc *);
182static void rl_txeof(struct rl_softc *);
183static void rl_intr(void *);
184static void rl_tick(void *);
185static void rl_start(struct ifnet *);
186static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
187static void rl_init(void *);
188static void rl_stop (struct rl_softc *);
189static void rl_watchdog(struct ifnet *);
190static int rl_suspend(device_t);
191static int rl_resume(device_t);
192static void rl_shutdown(device_t);
193static int rl_ifmedia_upd(struct ifnet *);
194static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
195
196static void rl_eeprom_putbyte(struct rl_softc *, int);
197static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
198static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
199static void rl_mii_sync(struct rl_softc *);
200static void rl_mii_send(struct rl_softc *, uint32_t, int);
201static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
202static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
203
204static int rl_miibus_readreg(device_t, int, int);
205static int rl_miibus_writereg(device_t, int, int, int);
206static void rl_miibus_statchg(device_t);
207
208static void rl_setmulti(struct rl_softc *);
209static void rl_reset(struct rl_softc *);
210static void rl_list_tx_init(struct rl_softc *);
211
212static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
213static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
9c095379
MD
214#ifdef DEVICE_POLLING
215static poll_handler_t rl_poll;
216#endif
984263bc
MD
217
218#ifdef RL_USEIOSPACE
ca59556a
JS
219#define RL_RES SYS_RES_IOPORT
220#define RL_RID RL_PCI_LOIO
984263bc 221#else
ca59556a
JS
222#define RL_RES SYS_RES_MEMORY
223#define RL_RID RL_PCI_LOMEM
984263bc
MD
224#endif
225
226static device_method_t rl_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, rl_probe),
229 DEVMETHOD(device_attach, rl_attach),
230 DEVMETHOD(device_detach, rl_detach),
231 DEVMETHOD(device_suspend, rl_suspend),
232 DEVMETHOD(device_resume, rl_resume),
233 DEVMETHOD(device_shutdown, rl_shutdown),
234
235 /* bus interface */
236 DEVMETHOD(bus_print_child, bus_generic_print_child),
237 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
238
239 /* MII interface */
240 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
241 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
242 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
243
244 { 0, 0 }
245};
246
ca59556a 247static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
984263bc
MD
248static devclass_t rl_devclass;
249
32832096 250DECLARE_DUMMY_MODULE(if_rl);
984263bc 251DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
ca59556a 252DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
984263bc 253DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
ca59556a 254MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
984263bc
MD
255
256#define EE_SET(x) \
ca59556a 257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
984263bc
MD
258
259#define EE_CLR(x) \
ca59556a
JS
260 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
261
262static void
263rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
264{
265 struct rl_softc *sc = arg;
266
267 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
268}
269
270static void
271rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
272{
273 struct rl_softc *sc = arg;
274
275 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
276}
984263bc
MD
277
278/*
279 * Send a read command and address to the EEPROM, check for ACK.
280 */
ca59556a
JS
281static void
282rl_eeprom_putbyte(struct rl_softc *sc, int addr)
984263bc 283{
ca59556a 284 int d, i;
984263bc 285
ca59556a 286 d = addr | sc->rl_eecmd_read;
984263bc
MD
287
288 /*
289 * Feed in each bit and strobe the clock.
290 */
291 for (i = 0x400; i; i >>= 1) {
ca59556a 292 if (d & i)
984263bc 293 EE_SET(RL_EE_DATAIN);
ca59556a 294 else
984263bc 295 EE_CLR(RL_EE_DATAIN);
984263bc
MD
296 DELAY(100);
297 EE_SET(RL_EE_CLK);
298 DELAY(150);
299 EE_CLR(RL_EE_CLK);
300 DELAY(100);
301 }
984263bc
MD
302}
303
304/*
305 * Read a word of data stored in the EEPROM at address 'addr.'
306 */
ca59556a
JS
307static void
308rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
984263bc 309{
ca59556a
JS
310 int i;
311 uint16_t word = 0;
984263bc
MD
312
313 /* Enter EEPROM access mode. */
314 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
315
316 /*
317 * Send address of word we want to read.
318 */
319 rl_eeprom_putbyte(sc, addr);
320
321 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
322
323 /*
324 * Start reading bits from EEPROM.
325 */
326 for (i = 0x8000; i; i >>= 1) {
327 EE_SET(RL_EE_CLK);
328 DELAY(100);
329 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
330 word |= i;
331 EE_CLR(RL_EE_CLK);
332 DELAY(100);
333 }
334
335 /* Turn off EEPROM access mode. */
336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
337
338 *dest = word;
984263bc
MD
339}
340
341/*
342 * Read a sequence of words from the EEPROM.
343 */
ca59556a
JS
344static void
345rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
984263bc 346{
ca59556a
JS
347 int i;
348 u_int16_t word = 0, *ptr;
984263bc
MD
349
350 for (i = 0; i < cnt; i++) {
351 rl_eeprom_getword(sc, off + i, &word);
352 ptr = (u_int16_t *)(dest + (i * 2));
353 if (swap)
354 *ptr = ntohs(word);
355 else
356 *ptr = word;
357 }
984263bc
MD
358}
359
360
361/*
362 * MII access routines are provided for the 8129, which
363 * doesn't have a built-in PHY. For the 8139, we fake things
364 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
365 * direct access PHY registers.
366 */
ca59556a
JS
367#define MII_SET(x) \
368 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
984263bc 369
ca59556a
JS
370#define MII_CLR(x) \
371 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
984263bc
MD
372
373/*
374 * Sync the PHYs by setting data bit and strobing the clock 32 times.
375 */
ca59556a
JS
376static void
377rl_mii_sync(struct rl_softc *sc)
984263bc 378{
ca59556a 379 int i;
984263bc
MD
380
381 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
382
383 for (i = 0; i < 32; i++) {
384 MII_SET(RL_MII_CLK);
385 DELAY(1);
386 MII_CLR(RL_MII_CLK);
387 DELAY(1);
388 }
984263bc
MD
389}
390
391/*
392 * Clock a series of bits through the MII.
393 */
ca59556a
JS
394static void
395rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
984263bc 396{
ca59556a 397 int i;
984263bc
MD
398
399 MII_CLR(RL_MII_CLK);
400
401 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
ca59556a 402 if (bits & i)
984263bc 403 MII_SET(RL_MII_DATAOUT);
ca59556a 404 else
984263bc 405 MII_CLR(RL_MII_DATAOUT);
984263bc
MD
406 DELAY(1);
407 MII_CLR(RL_MII_CLK);
408 DELAY(1);
409 MII_SET(RL_MII_CLK);
410 }
411}
412
413/*
414 * Read an PHY register through the MII.
415 */
ca59556a
JS
416static int
417rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 418{
a3fbe745 419 int ack, i;
984263bc 420
984263bc
MD
421 /*
422 * Set up frame for RX.
423 */
424 frame->mii_stdelim = RL_MII_STARTDELIM;
425 frame->mii_opcode = RL_MII_READOP;
426 frame->mii_turnaround = 0;
427 frame->mii_data = 0;
428
429 CSR_WRITE_2(sc, RL_MII, 0);
430
431 /*
432 * Turn on data xmit.
433 */
434 MII_SET(RL_MII_DIR);
435
436 rl_mii_sync(sc);
437
438 /*
439 * Send command/address info.
440 */
441 rl_mii_send(sc, frame->mii_stdelim, 2);
442 rl_mii_send(sc, frame->mii_opcode, 2);
443 rl_mii_send(sc, frame->mii_phyaddr, 5);
444 rl_mii_send(sc, frame->mii_regaddr, 5);
445
446 /* Idle bit */
447 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
448 DELAY(1);
449 MII_SET(RL_MII_CLK);
450 DELAY(1);
451
452 /* Turn off xmit. */
453 MII_CLR(RL_MII_DIR);
454
455 /* Check for ack */
456 MII_CLR(RL_MII_CLK);
457 DELAY(1);
458 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
459 MII_SET(RL_MII_CLK);
460 DELAY(1);
461
462 /*
463 * Now try reading data bits. If the ack failed, we still
464 * need to clock through 16 cycles to keep the PHY(s) in sync.
465 */
466 if (ack) {
467 for(i = 0; i < 16; i++) {
468 MII_CLR(RL_MII_CLK);
469 DELAY(1);
470 MII_SET(RL_MII_CLK);
471 DELAY(1);
472 }
ca59556a
JS
473 } else {
474 for (i = 0x8000; i; i >>= 1) {
475 MII_CLR(RL_MII_CLK);
476 DELAY(1);
477 if (!ack) {
478 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
479 frame->mii_data |= i;
480 DELAY(1);
481 }
482 MII_SET(RL_MII_CLK);
984263bc
MD
483 DELAY(1);
484 }
984263bc
MD
485 }
486
984263bc
MD
487 MII_CLR(RL_MII_CLK);
488 DELAY(1);
489 MII_SET(RL_MII_CLK);
490 DELAY(1);
491
ca59556a 492 return(ack ? 1 : 0);
984263bc
MD
493}
494
495/*
496 * Write to a PHY register through the MII.
497 */
ca59556a
JS
498static int
499rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
984263bc 500{
984263bc
MD
501 /*
502 * Set up frame for TX.
503 */
984263bc
MD
504 frame->mii_stdelim = RL_MII_STARTDELIM;
505 frame->mii_opcode = RL_MII_WRITEOP;
506 frame->mii_turnaround = RL_MII_TURNAROUND;
507
508 /*
509 * Turn on data output.
510 */
511 MII_SET(RL_MII_DIR);
512
513 rl_mii_sync(sc);
514
515 rl_mii_send(sc, frame->mii_stdelim, 2);
516 rl_mii_send(sc, frame->mii_opcode, 2);
517 rl_mii_send(sc, frame->mii_phyaddr, 5);
518 rl_mii_send(sc, frame->mii_regaddr, 5);
519 rl_mii_send(sc, frame->mii_turnaround, 2);
520 rl_mii_send(sc, frame->mii_data, 16);
521
522 /* Idle bit. */
523 MII_SET(RL_MII_CLK);
524 DELAY(1);
525 MII_CLR(RL_MII_CLK);
526 DELAY(1);
527
528 /*
529 * Turn off xmit.
530 */
531 MII_CLR(RL_MII_DIR);
532
984263bc
MD
533 return(0);
534}
535
ca59556a
JS
536static int
537rl_miibus_readreg(device_t dev, int phy, int reg)
984263bc 538{
ca59556a
JS
539 struct rl_softc *sc;
540 struct rl_mii_frame frame;
541 uint16_t rval = 0;
542 uint16_t rl8139_reg = 0;
984263bc
MD
543
544 sc = device_get_softc(dev);
545
546 if (sc->rl_type == RL_8139) {
547 /* Pretend the internal PHY is only at address 0 */
548 if (phy)
549 return(0);
ca59556a 550 switch (reg) {
984263bc
MD
551 case MII_BMCR:
552 rl8139_reg = RL_BMCR;
553 break;
554 case MII_BMSR:
555 rl8139_reg = RL_BMSR;
556 break;
557 case MII_ANAR:
558 rl8139_reg = RL_ANAR;
559 break;
560 case MII_ANER:
561 rl8139_reg = RL_ANER;
562 break;
563 case MII_ANLPAR:
564 rl8139_reg = RL_LPAR;
565 break;
566 case MII_PHYIDR1:
567 case MII_PHYIDR2:
568 return(0);
569 break;
570 /*
571 * Allow the rlphy driver to read the media status
572 * register. If we have a link partner which does not
573 * support NWAY, this is the register which will tell
574 * us the results of parallel detection.
575 */
576 case RL_MEDIASTAT:
577 rval = CSR_READ_1(sc, RL_MEDIASTAT);
578 return(rval);
984263bc 579 default:
ca59556a 580 device_printf(dev, "bad phy register\n");
984263bc
MD
581 return(0);
582 }
583 rval = CSR_READ_2(sc, rl8139_reg);
584 return(rval);
585 }
586
ca59556a 587 bzero(&frame, sizeof(frame));
984263bc
MD
588
589 frame.mii_phyaddr = phy;
590 frame.mii_regaddr = reg;
591 rl_mii_readreg(sc, &frame);
592
593 return(frame.mii_data);
594}
595
ca59556a
JS
596static int
597rl_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 598{
ca59556a
JS
599 struct rl_softc *sc;
600 struct rl_mii_frame frame;
601 u_int16_t rl8139_reg = 0;
984263bc
MD
602
603 sc = device_get_softc(dev);
604
605 if (sc->rl_type == RL_8139) {
606 /* Pretend the internal PHY is only at address 0 */
607 if (phy)
608 return(0);
ca59556a 609 switch (reg) {
984263bc
MD
610 case MII_BMCR:
611 rl8139_reg = RL_BMCR;
612 break;
613 case MII_BMSR:
614 rl8139_reg = RL_BMSR;
615 break;
616 case MII_ANAR:
617 rl8139_reg = RL_ANAR;
618 break;
619 case MII_ANER:
620 rl8139_reg = RL_ANER;
621 break;
622 case MII_ANLPAR:
623 rl8139_reg = RL_LPAR;
624 break;
625 case MII_PHYIDR1:
626 case MII_PHYIDR2:
627 return(0);
984263bc 628 default:
ca59556a 629 device_printf(dev, "bad phy register\n");
984263bc
MD
630 return(0);
631 }
632 CSR_WRITE_2(sc, rl8139_reg, data);
633 return(0);
634 }
635
ca59556a 636 bzero(&frame, sizeof(frame));
984263bc
MD
637
638 frame.mii_phyaddr = phy;
639 frame.mii_regaddr = reg;
640 frame.mii_data = data;
641
642 rl_mii_writereg(sc, &frame);
643
644 return(0);
645}
646
ca59556a
JS
647static void
648rl_miibus_statchg(device_t dev)
984263bc 649{
984263bc
MD
650}
651
652/*
653 * Program the 64-bit multicast hash filter.
654 */
ca59556a
JS
655static void
656rl_setmulti(struct rl_softc *sc)
984263bc 657{
ca59556a
JS
658 struct ifnet *ifp;
659 int h = 0;
660 uint32_t hashes[2] = { 0, 0 };
661 struct ifmultiaddr *ifma;
662 uint32_t rxfilt;
663 int mcnt = 0;
984263bc
MD
664
665 ifp = &sc->arpcom.ac_if;
666
667 rxfilt = CSR_READ_4(sc, RL_RXCFG);
668
669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
670 rxfilt |= RL_RXCFG_RX_MULTI;
671 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
672 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
673 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
674 return;
675 }
676
677 /* first, zot all the existing hash bits */
678 CSR_WRITE_4(sc, RL_MAR0, 0);
679 CSR_WRITE_4(sc, RL_MAR4, 0);
680
681 /* now program new ones */
ca59556a 682 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
683 if (ifma->ifma_addr->sa_family != AF_LINK)
684 continue;
ca59556a
JS
685 h = ether_crc32_be(
686 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
527b7d96 687 ETHER_ADDR_LEN) >> 26;
984263bc
MD
688 if (h < 32)
689 hashes[0] |= (1 << h);
690 else
691 hashes[1] |= (1 << (h - 32));
692 mcnt++;
693 }
694
695 if (mcnt)
696 rxfilt |= RL_RXCFG_RX_MULTI;
697 else
698 rxfilt &= ~RL_RXCFG_RX_MULTI;
699
700 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
701 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
702 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
984263bc
MD
703}
704
ca59556a
JS
705static void
706rl_reset(struct rl_softc *sc)
984263bc 707{
ca59556a 708 int i;
984263bc
MD
709
710 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
711
712 for (i = 0; i < RL_TIMEOUT; i++) {
713 DELAY(10);
714 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
715 break;
716 }
717 if (i == RL_TIMEOUT)
ca59556a 718 device_printf(sc->rl_dev, "reset never completed!\n");
984263bc
MD
719}
720
721/*
722 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
723 * IDs against our list and return a device name if we find a match.
49c37738
JS
724 *
725 * Return with a value < 0 to give re(4) a change to attach.
984263bc 726 */
ca59556a
JS
727static int
728rl_probe(device_t dev)
984263bc 729{
ca59556a
JS
730 struct rl_type *t;
731 uint16_t product = pci_get_device(dev);
732 uint16_t vendor = pci_get_vendor(dev);
984263bc 733
49c37738 734 for (t = rl_devs; t->rl_name != NULL; t++) {
ca59556a
JS
735 if (vendor == t->rl_vid && product == t->rl_did) {
736 device_set_desc(dev, t->rl_name);
49c37738 737 return(-100);
ca59556a 738 }
984263bc
MD
739 }
740
741 return(ENXIO);
742}
743
744/*
745 * Attach the interface. Allocate softc structures, do ifmedia
746 * setup and ethernet/BPF attach.
747 */
ca59556a
JS
748static int
749rl_attach(device_t dev)
984263bc 750{
ca59556a
JS
751 uint8_t eaddr[ETHER_ADDR_LEN];
752 uint16_t as[3];
753 struct rl_softc *sc;
754 struct ifnet *ifp;
755 uint16_t rl_did = 0;
756 int error = 0, rid, i;
984263bc
MD
757
758 sc = device_get_softc(dev);
ca59556a 759 sc->rl_dev = dev;
984263bc
MD
760
761 /*
762 * Handle power management nonsense.
763 */
764
ca59556a
JS
765 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
766 uint32_t iobase, membase, irq;
984263bc 767
ca59556a
JS
768 /* Save important PCI config data. */
769 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
770 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
771 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
984263bc 772
ca59556a
JS
773 /* Reset the power state. */
774 device_printf(dev, "chip is is in D%d power mode "
775 "-- setting to D0\n", pci_get_powerstate(dev));
776 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
984263bc 777
ca59556a
JS
778 /* Restore PCI config data. */
779 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
780 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
781 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
984263bc
MD
782 }
783
ca59556a 784 pci_enable_busmaster(dev);
984263bc
MD
785
786 rid = RL_RID;
4e6d744d 787 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
984263bc
MD
788
789 if (sc->rl_res == NULL) {
ca59556a 790 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
791 error = ENXIO;
792 goto fail;
793 }
794
795 sc->rl_btag = rman_get_bustag(sc->rl_res);
796 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
797
798 rid = 0;
ca59556a
JS
799 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
800 RF_SHAREABLE | RF_ACTIVE);
984263bc
MD
801
802 if (sc->rl_irq == NULL) {
ca59556a 803 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
804 error = ENXIO;
805 goto fail;
806 }
807
b3a81bea 808 callout_init(&sc->rl_stat_timer);
984263bc
MD
809
810 /* Reset the adapter. */
811 rl_reset(sc);
812
ca59556a
JS
813 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
814 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
815 if (rl_did != 0x8129)
816 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
817
984263bc
MD
818 /*
819 * Get station address from the EEPROM.
820 */
ca59556a
JS
821 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
822 for (i = 0; i < 3; i++) {
823 eaddr[(i * 2) + 0] = as[i] & 0xff;
824 eaddr[(i * 2) + 1] = as[i] >> 8;
825 }
984263bc
MD
826
827 /*
828 * Now read the exact device type from the EEPROM to find
829 * out if it's an 8129 or 8139.
830 */
831 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
832
833 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 ||
834 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 ||
ca59556a
JS
835 rl_did == DLINK_DEVICEID_530TXPLUS || rl_did == RT_DEVICEID_8138 ||
836 rl_did == DLINK_DEVICEID_690TXD ||
837 rl_did == COREGA_DEVICEID_FETHERCBTXD ||
838 rl_did == COREGA_DEVICEID_FETHERIICBTXD ||
839 rl_did == PLANEX_DEVICEID_FNW3800TX)
984263bc
MD
840 sc->rl_type = RL_8139;
841 else if (rl_did == RT_DEVICEID_8129)
842 sc->rl_type = RL_8129;
843 else {
ca59556a 844 device_printf(dev, "unknown device ID: %x\n", rl_did);
984263bc
MD
845 error = ENXIO;
846 goto fail;
847 }
848
ca59556a
JS
849#define RL_NSEG_NEW 32
850 error = bus_dma_tag_create(NULL, /* parent */
851 1, 0, /* alignment, boundary */
852 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
853 BUS_SPACE_MAXADDR, /* highaddr */
854 NULL, NULL, /* filter, filterarg */
855 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
856 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
857 BUS_DMA_ALLOCNOW, /* flags */
858 &sc->rl_parent_tag);
984263bc 859
ca59556a
JS
860 if (error) {
861 device_printf(dev, "can't create parent tag\n");
862 goto fail;
863 }
864
865 /*
866 * Now allocate a tag for the DMA descriptor lists.
867 * All of our lists are allocated as a contiguous block
868 * of memory.
869 */
870 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
871 1, 0, /* alignment, boundary */
872 BUS_SPACE_MAXADDR, /* lowaddr */
873 BUS_SPACE_MAXADDR, /* highaddr */
874 NULL, NULL, /* filter, filterarg */
875 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
877 0, /* flags */
878 &sc->rl_tag);
879
880 if (error) {
881 device_printf(dev, "can't create RX tag\n");
882 goto fail;
883 }
884
885 /*
886 * Now allocate a chunk of DMA-able memory based on the tag
887 * we just created.
888 */
889 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
890 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
891
892 if (error) {
893 device_printf(dev, "can't allocate RX memory!\n");
984263bc
MD
894 error = ENXIO;
895 goto fail;
896 }
897
898 /* Leave a few bytes before the start of the RX ring buffer. */
899 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
900 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
901
902 /* Do MII setup */
ca59556a
JS
903 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
904 rl_ifmedia_sts)) {
905 device_printf(dev, "MII without any phy!\n");
984263bc
MD
906 error = ENXIO;
907 goto fail;
908 }
909
910 ifp = &sc->arpcom.ac_if;
911 ifp->if_softc = sc;
ca59556a 912 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
913 ifp->if_mtu = ETHERMTU;
914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
915 ifp->if_ioctl = rl_ioctl;
984263bc
MD
916 ifp->if_start = rl_start;
917 ifp->if_watchdog = rl_watchdog;
918 ifp->if_init = rl_init;
919 ifp->if_baudrate = 10000000;
ca59556a
JS
920 ifp->if_capabilities = IFCAP_VLAN_MTU;
921#ifdef DEVICE_POLLING
9c095379 922 ifp->if_poll = rl_poll;
ca59556a 923#endif
c2ffa639
JS
924 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
925 ifq_set_ready(&ifp->if_snd);
984263bc
MD
926
927 /*
928 * Call MI attach routine.
929 */
78195a76 930 ether_ifattach(ifp, eaddr, NULL);
984263bc 931
78195a76
MD
932 error = bus_setup_intr(dev, sc->rl_irq, INTR_NETSAFE, rl_intr,
933 sc, &sc->rl_intrhand, ifp->if_serializer);
ca59556a
JS
934
935 if (error) {
936 device_printf(dev, "couldn't set up irq\n");
937 ether_ifdetach(ifp);
938 goto fail;
939 }
940
941 return(0);
942
984263bc 943fail:
ca59556a 944 rl_detach(dev);
984263bc
MD
945 return(error);
946}
947
ca59556a
JS
948static int
949rl_detach(device_t dev)
984263bc 950{
ca59556a
JS
951 struct rl_softc *sc;
952 struct ifnet *ifp;
984263bc
MD
953
954 sc = device_get_softc(dev);
955 ifp = &sc->arpcom.ac_if;
956
ca59556a 957 if (device_is_attached(dev)) {
cdf89432 958 lwkt_serialize_enter(ifp->if_serializer);
ca59556a 959 rl_stop(sc);
cdf89432
SZ
960 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
961 lwkt_serialize_exit(ifp->if_serializer);
962
ca59556a
JS
963 ether_ifdetach(ifp);
964 }
984263bc 965
ca59556a
JS
966 if (sc->rl_miibus)
967 device_delete_child(dev, sc->rl_miibus);
984263bc 968 bus_generic_detach(dev);
984263bc 969
ca59556a
JS
970 if (sc->rl_irq)
971 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
972 if (sc->rl_res)
973 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
984263bc 974
ca59556a
JS
975 if (sc->rl_cdata.rl_rx_buf) {
976 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
977 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
978 sc->rl_cdata.rl_rx_dmamap);
979 }
980 if (sc->rl_tag)
981 bus_dma_tag_destroy(sc->rl_tag);
982 if (sc->rl_parent_tag)
983 bus_dma_tag_destroy(sc->rl_parent_tag);
984263bc
MD
984
985 return(0);
986}
987
988/*
989 * Initialize the transmit descriptors.
990 */
ca59556a
JS
991static void
992rl_list_tx_init(struct rl_softc *sc)
984263bc 993{
ca59556a
JS
994 struct rl_chain_data *cd;
995 int i;
984263bc
MD
996
997 cd = &sc->rl_cdata;
998 for (i = 0; i < RL_TX_LIST_CNT; i++) {
999 cd->rl_tx_chain[i] = NULL;
1000 CSR_WRITE_4(sc,
ca59556a 1001 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
984263bc
MD
1002 }
1003
1004 sc->rl_cdata.cur_tx = 0;
1005 sc->rl_cdata.last_tx = 0;
984263bc
MD
1006}
1007
1008/*
1009 * A frame has been uploaded: pass the resulting mbuf chain up to
1010 * the higher level protocols.
1011 *
1012 * You know there's something wrong with a PCI bus-master chip design
1013 * when you have to use m_devget().
1014 *
1015 * The receive operation is badly documented in the datasheet, so I'll
1016 * attempt to document it here. The driver provides a buffer area and
1017 * places its base address in the RX buffer start address register.
1018 * The chip then begins copying frames into the RX buffer. Each frame
ca59556a 1019 * is preceded by a 32-bit RX status word which specifies the length
984263bc
MD
1020 * of the frame and certain other status bits. Each frame (starting with
1021 * the status word) is also 32-bit aligned. The frame length is in the
1022 * first 16 bits of the status word; the lower 15 bits correspond with
1023 * the 'rx status register' mentioned in the datasheet.
1024 *
1025 * Note: to make the Alpha happy, the frame payload needs to be aligned
1026 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1027 * the ring buffer starting at an address two bytes before the actual
1028 * data location. We can then shave off the first two bytes using m_adj().
1029 * The reason we do this is because m_devget() doesn't let us specify an
1030 * offset into the mbuf storage space, so we have to artificially create
1031 * one. The ring is allocated in such a way that there are a few unused
1032 * bytes of space preceecing it so that it will be safe for us to do the
1033 * 2-byte backstep even if reading from the ring at offset 0.
1034 */
ca59556a
JS
1035static void
1036rl_rxeof(struct rl_softc *sc)
984263bc 1037{
ca59556a
JS
1038 struct mbuf *m;
1039 struct ifnet *ifp;
1040 int total_len = 0;
1041 uint32_t rxstat;
1042 caddr_t rxbufpos;
1043 int wrap = 0;
1044 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
984263bc
MD
1045
1046 ifp = &sc->arpcom.ac_if;
1047
ca59556a
JS
1048 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1049 BUS_DMASYNC_POSTREAD);
1050
984263bc
MD
1051 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1052
1053 /* Do not try to read past this point. */
1054 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1055
1056 if (limit < cur_rx)
1057 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1058 else
1059 max_bytes = limit - cur_rx;
1060
1061 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1062#ifdef DEVICE_POLLING
46f25451 1063 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1064 if (sc->rxcycles <= 0)
1065 break;
1066 sc->rxcycles--;
1067 }
1068#endif /* DEVICE_POLLING */
1069 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
ca59556a 1070 rxstat = le32toh(*(uint32_t *)rxbufpos);
984263bc
MD
1071
1072 /*
1073 * Here's a totally undocumented fact for you. When the
1074 * RealTek chip is in the process of copying a packet into
1075 * RAM for you, the length will be 0xfff0. If you spot a
1076 * packet header with this value, you need to stop. The
1077 * datasheet makes absolutely no mention of this and
1078 * RealTek should be shot for this.
1079 */
ca59556a 1080 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
984263bc
MD
1081 break;
1082
ca59556a 1083 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
984263bc
MD
1084 ifp->if_ierrors++;
1085 rl_init(sc);
1086 return;
1087 }
1088
1089 /* No errors; receive the packet. */
1090 total_len = rxstat >> 16;
1091 rx_bytes += total_len + 4;
1092
1093 /*
1094 * XXX The RealTek chip includes the CRC with every
1095 * received frame, and there's no way to turn this
1096 * behavior off (at least, I can't find anything in
1097 * the manual that explains how to do it) so we have
1098 * to trim off the CRC manually.
1099 */
1100 total_len -= ETHER_CRC_LEN;
1101
1102 /*
1103 * Avoid trying to read more bytes than we know
1104 * the chip has prepared for us.
1105 */
1106 if (rx_bytes > max_bytes)
1107 break;
1108
1109 rxbufpos = sc->rl_cdata.rl_rx_buf +
ca59556a 1110 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
984263bc
MD
1111
1112 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1113 rxbufpos = sc->rl_cdata.rl_rx_buf;
1114
1115 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1116
1117 if (total_len > wrap) {
1118 /*
1119 * Fool m_devget() into thinking we want to copy
1120 * the whole buffer so we don't end up fragmenting
1121 * the data.
1122 */
1123 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1124 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1125 if (m == NULL) {
1126 ifp->if_ierrors++;
1127 } else {
1128 m_adj(m, RL_ETHER_ALIGN);
1129 m_copyback(m, wrap, total_len - wrap,
1130 sc->rl_cdata.rl_rx_buf);
1131 }
1132 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1133 } else {
1134 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1135 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1136 if (m == NULL) {
1137 ifp->if_ierrors++;
1138 } else
1139 m_adj(m, RL_ETHER_ALIGN);
1140 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1141 }
1142
1143 /*
1144 * Round up to 32-bit boundary.
1145 */
1146 cur_rx = (cur_rx + 3) & ~3;
1147 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1148
1149 if (m == NULL)
1150 continue;
1151
984263bc
MD
1152 ifp->if_ipackets++;
1153
78195a76 1154 ifp->if_input(ifp, m);
984263bc 1155 }
984263bc
MD
1156}
1157
1158/*
1159 * A frame was downloaded to the chip. It's safe for us to clean up
1160 * the list buffers.
1161 */
ca59556a
JS
1162static void
1163rl_txeof(struct rl_softc *sc)
984263bc 1164{
ca59556a
JS
1165 struct ifnet *ifp;
1166 uint32_t txstat;
984263bc
MD
1167
1168 ifp = &sc->arpcom.ac_if;
1169
1170 /*
1171 * Go through our tx list and free mbufs for those
1172 * frames that have been uploaded.
1173 */
1174 do {
ca59556a
JS
1175 if (RL_LAST_TXMBUF(sc) == NULL)
1176 break;
984263bc 1177 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
ca59556a
JS
1178 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1179 RL_TXSTAT_TXABRT)) == 0)
984263bc
MD
1180 break;
1181
1182 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1183
ca59556a
JS
1184 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1185 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1186 m_freem(RL_LAST_TXMBUF(sc));
1187 RL_LAST_TXMBUF(sc) = NULL;
ef042148 1188 RL_INC(sc->rl_cdata.last_tx);
ca59556a 1189
ef042148
JS
1190 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1191 sc->rl_txthresh += 32;
1192 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1193 sc->rl_txthresh = RL_TX_THRESH_MAX;
1194 }
ca59556a 1195
ef042148
JS
1196 if (txstat & RL_TXSTAT_TX_OK) {
1197 ifp->if_opackets++;
1198 } else {
984263bc 1199 ifp->if_oerrors++;
ef042148 1200 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
984263bc 1201 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
984263bc 1202 }
984263bc
MD
1203 ifp->if_flags &= ~IFF_OACTIVE;
1204 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1205
ca59556a
JS
1206 if (RL_LAST_TXMBUF(sc) == NULL)
1207 ifp->if_timer = 0;
1208 else if (ifp->if_timer == 0)
1209 ifp->if_timer = 5;
984263bc
MD
1210}
1211
ca59556a
JS
1212static void
1213rl_tick(void *xsc)
984263bc 1214{
ca59556a
JS
1215 struct rl_softc *sc = xsc;
1216 struct mii_data *mii;
984263bc 1217
78195a76 1218 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc 1219
984263bc 1220 mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1221 mii_tick(mii);
1222
b3a81bea 1223 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
a3fbe745 1224
78195a76 1225 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1226}
1227
1228#ifdef DEVICE_POLLING
984263bc
MD
1229
1230static void
ca59556a 1231rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
984263bc
MD
1232{
1233 struct rl_softc *sc = ifp->if_softc;
1234
9c095379
MD
1235 switch(cmd) {
1236 case POLL_REGISTER:
1237 /* disable interrupts */
1238 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1239 break;
1240 case POLL_DEREGISTER:
1241 /* enable interrupts */
ca59556a 1242 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
9c095379
MD
1243 break;
1244 default:
1245 sc->rxcycles = count;
1246 rl_rxeof(sc);
1247 rl_txeof(sc);
1248 if (!ifq_is_empty(&ifp->if_snd))
1249 rl_start(ifp);
1250
1251 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1252 uint16_t status;
1253
1254 status = CSR_READ_2(sc, RL_ISR);
1255 if (status == 0xffff)
1256 return;
1257 if (status)
1258 CSR_WRITE_2(sc, RL_ISR, status);
1259
1260 /*
1261 * XXX check behaviour on receiver stalls.
1262 */
984263bc 1263
9c095379
MD
1264 if (status & RL_ISR_SYSTEM_ERR) {
1265 rl_reset(sc);
1266 rl_init(sc);
1267 }
984263bc 1268 }
9c095379 1269 break;
984263bc
MD
1270 }
1271}
1272#endif /* DEVICE_POLLING */
1273
ca59556a
JS
1274static void
1275rl_intr(void *arg)
984263bc 1276{
ca59556a
JS
1277 struct rl_softc *sc;
1278 struct ifnet *ifp;
1279 uint16_t status;
984263bc
MD
1280
1281 sc = arg;
1282
ca59556a 1283 if (sc->suspended)
984263bc 1284 return;
984263bc
MD
1285
1286 ifp = &sc->arpcom.ac_if;
984263bc
MD
1287
1288 for (;;) {
984263bc 1289 status = CSR_READ_2(sc, RL_ISR);
ca59556a
JS
1290 /* If the card has gone away, the read returns 0xffff. */
1291 if (status == 0xffff)
1292 break;
1293
1294 if (status != 0)
984263bc
MD
1295 CSR_WRITE_2(sc, RL_ISR, status);
1296
1297 if ((status & RL_INTRS) == 0)
1298 break;
1299
1300 if (status & RL_ISR_RX_OK)
1301 rl_rxeof(sc);
1302
1303 if (status & RL_ISR_RX_ERR)
1304 rl_rxeof(sc);
1305
1306 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1307 rl_txeof(sc);
1308
1309 if (status & RL_ISR_SYSTEM_ERR) {
1310 rl_reset(sc);
1311 rl_init(sc);
1312 }
1313
1314 }
ca59556a 1315
c2ffa639 1316 if (!ifq_is_empty(&ifp->if_snd))
984263bc 1317 rl_start(ifp);
984263bc
MD
1318}
1319
1320/*
1321 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1322 * pointers to the fragment pointers.
1323 */
ca59556a
JS
1324static int
1325rl_encap(struct rl_softc *sc, struct mbuf *m_head)
984263bc 1326{
ca59556a 1327 struct mbuf *m_new = NULL;
984263bc
MD
1328
1329 /*
1330 * The RealTek is brain damaged and wants longword-aligned
1331 * TX buffers, plus we can only have one fragment buffer
1332 * per packet. We have to copy pretty much all the time.
1333 */
ca59556a 1334 m_new = m_defrag(m_head, MB_DONTWAIT);
984263bc 1335
ca59556a
JS
1336 if (m_new == NULL) {
1337 m_freem(m_head);
984263bc 1338 return(1);
984263bc 1339 }
984263bc
MD
1340 m_head = m_new;
1341
1342 /* Pad frames to at least 60 bytes. */
1343 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1344 /*
1345 * Make security concious people happy: zero out the
1346 * bytes in the pad area, since we don't know what
1347 * this mbuf cluster buffer's previous user might
1348 * have left in it.
1349 */
1350 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1351 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1352 m_head->m_pkthdr.len +=
1353 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1354 m_head->m_len = m_head->m_pkthdr.len;
1355 }
1356
1357 RL_CUR_TXMBUF(sc) = m_head;
1358
1359 return(0);
1360}
1361
1362/*
1363 * Main transmit routine.
1364 */
1365
ca59556a
JS
1366static void
1367rl_start(struct ifnet *ifp)
984263bc 1368{
ca59556a
JS
1369 struct rl_softc *sc;
1370 struct mbuf *m_head = NULL;
984263bc
MD
1371
1372 sc = ifp->if_softc;
1373
1374 while(RL_CUR_TXMBUF(sc) == NULL) {
d2c71fa0 1375 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1376 if (m_head == NULL)
1377 break;
1378
ca59556a 1379 if (rl_encap(sc, m_head))
984263bc 1380 break;
984263bc
MD
1381
1382 /*
1383 * If there's a BPF listener, bounce a copy of this frame
1384 * to him.
1385 */
ca59556a 1386 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
984263bc
MD
1387
1388 /*
1389 * Transmit the frame.
1390 */
ca59556a
JS
1391 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1392 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1393 mtod(RL_CUR_TXMBUF(sc), void *),
1394 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1395 rl_dma_map_txbuf, sc, 0);
1396 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1397 BUS_DMASYNC_PREREAD);
984263bc
MD
1398 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1399 RL_TXTHRESH(sc->rl_txthresh) |
1400 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1401
1402 RL_INC(sc->rl_cdata.cur_tx);
ca59556a
JS
1403
1404 /*
1405 * Set a timeout in case the chip goes out to lunch.
1406 */
1407 ifp->if_timer = 5;
984263bc
MD
1408 }
1409
1410 /*
1411 * We broke out of the loop because all our TX slots are
1412 * full. Mark the NIC as busy until it drains some of the
1413 * packets from the queue.
1414 */
1415 if (RL_CUR_TXMBUF(sc) != NULL)
1416 ifp->if_flags |= IFF_OACTIVE;
984263bc
MD
1417}
1418
ca59556a
JS
1419static void
1420rl_init(void *xsc)
984263bc 1421{
ca59556a
JS
1422 struct rl_softc *sc = xsc;
1423 struct ifnet *ifp = &sc->arpcom.ac_if;
1424 struct mii_data *mii;
ca59556a 1425 uint32_t rxcfg = 0;
984263bc 1426
984263bc
MD
1427 mii = device_get_softc(sc->rl_miibus);
1428
1429 /*
1430 * Cancel pending I/O and free all RX/TX buffers.
1431 */
1432 rl_stop(sc);
1433
ca59556a
JS
1434 /*
1435 * Init our MAC address. Even though the chipset documentation
1436 * doesn't mention it, we need to enter "Config register write enable"
1437 * mode to modify the ID registers.
1438 */
1439 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1440 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1441 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1442 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1443 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1444 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
984263bc
MD
1445
1446 /* Init the RX buffer pointer register. */
ca59556a
JS
1447 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1448 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1449 sc, 0);
1450 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1451 BUS_DMASYNC_PREWRITE);
984263bc
MD
1452
1453 /* Init TX descriptors. */
1454 rl_list_tx_init(sc);
1455
1456 /*
1457 * Enable transmit and receive.
1458 */
1459 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1460
1461 /*
1462 * Set the initial TX and RX configuration.
1463 */
1464 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1465 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1466
1467 /* Set the individual bit to receive frames for this host only. */
1468 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1469 rxcfg |= RL_RXCFG_RX_INDIV;
1470
1471 /* If we want promiscuous mode, set the allframes bit. */
1472 if (ifp->if_flags & IFF_PROMISC) {
1473 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1474 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1475 } else {
1476 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1477 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1478 }
1479
1480 /*
1481 * Set capture broadcast bit to capture broadcast frames.
1482 */
1483 if (ifp->if_flags & IFF_BROADCAST) {
1484 rxcfg |= RL_RXCFG_RX_BROAD;
1485 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1486 } else {
1487 rxcfg &= ~RL_RXCFG_RX_BROAD;
1488 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1489 }
1490
1491 /*
1492 * Program the multicast filter, if necessary.
1493 */
1494 rl_setmulti(sc);
1495
1496#ifdef DEVICE_POLLING
1497 /*
1498 * Only enable interrupts if we are polling, keep them off otherwise.
1499 */
46f25451 1500 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1501 CSR_WRITE_2(sc, RL_IMR, 0);
1502 else
1503#endif /* DEVICE_POLLING */
1504 /*
1505 * Enable interrupts.
1506 */
1507 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1508
1509 /* Set initial TX threshold */
1510 sc->rl_txthresh = RL_TX_THRESH_INIT;
1511
1512 /* Start RX/TX process. */
1513 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1514
1515 /* Enable receiver and transmitter. */
1516 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1517
1518 mii_mediachg(mii);
1519
1520 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1521
1522 ifp->if_flags |= IFF_RUNNING;
1523 ifp->if_flags &= ~IFF_OACTIVE;
1524
b3a81bea 1525 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
984263bc
MD
1526}
1527
1528/*
1529 * Set media options.
1530 */
ca59556a
JS
1531static int
1532rl_ifmedia_upd(struct ifnet *ifp)
984263bc 1533{
ca59556a
JS
1534 struct rl_softc *sc;
1535 struct mii_data *mii;
984263bc
MD
1536
1537 sc = ifp->if_softc;
1538 mii = device_get_softc(sc->rl_miibus);
1539 mii_mediachg(mii);
1540
1541 return(0);
1542}
1543
1544/*
1545 * Report current media status.
1546 */
ca59556a
JS
1547static void
1548rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1549{
ca59556a
JS
1550 struct rl_softc *sc = ifp->if_softc;
1551 struct mii_data *mii = device_get_softc(sc->rl_miibus);
984263bc
MD
1552
1553 mii_pollstat(mii);
1554 ifmr->ifm_active = mii->mii_media_active;
1555 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1556}
1557
ca59556a
JS
1558static int
1559rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1560{
ca59556a
JS
1561 struct rl_softc *sc = ifp->if_softc;
1562 struct ifreq *ifr = (struct ifreq *) data;
1563 struct mii_data *mii;
a3fbe745 1564 int error = 0;
984263bc 1565
ca59556a 1566 switch (command) {
984263bc
MD
1567 case SIOCSIFFLAGS:
1568 if (ifp->if_flags & IFF_UP) {
1569 rl_init(sc);
1570 } else {
1571 if (ifp->if_flags & IFF_RUNNING)
1572 rl_stop(sc);
1573 }
1574 error = 0;
1575 break;
1576 case SIOCADDMULTI:
1577 case SIOCDELMULTI:
1578 rl_setmulti(sc);
1579 error = 0;
1580 break;
1581 case SIOCGIFMEDIA:
1582 case SIOCSIFMEDIA:
1583 mii = device_get_softc(sc->rl_miibus);
1584 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1585 break;
ca59556a 1586 case SIOCSIFCAP:
ca59556a 1587 break;
984263bc 1588 default:
ca59556a 1589 error = ether_ioctl(ifp, command, data);
984263bc
MD
1590 break;
1591 }
1592
984263bc
MD
1593 return(error);
1594}
1595
ca59556a
JS
1596static void
1597rl_watchdog(struct ifnet *ifp)
984263bc 1598{
ca59556a 1599 struct rl_softc *sc = ifp->if_softc;
984263bc 1600
ca59556a 1601 device_printf(sc->rl_dev, "watchdog timeout\n");
a3fbe745 1602
78195a76 1603 lwkt_serialize_enter(ifp->if_serializer);
a3fbe745 1604
984263bc
MD
1605 ifp->if_oerrors++;
1606
1607 rl_txeof(sc);
1608 rl_rxeof(sc);
1609 rl_init(sc);
1610
78195a76 1611 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1612}
1613
1614/*
1615 * Stop the adapter and free any mbufs allocated to the
1616 * RX and TX lists.
1617 */
ca59556a
JS
1618static void
1619rl_stop(struct rl_softc *sc)
984263bc 1620{
ca59556a
JS
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
1622 int i;
984263bc 1623
984263bc
MD
1624 ifp->if_timer = 0;
1625
b3a81bea 1626 callout_stop(&sc->rl_stat_timer);
984263bc 1627 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1628
1629 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1630 CSR_WRITE_2(sc, RL_IMR, 0x0000);
ca59556a 1631 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
984263bc
MD
1632
1633 /*
1634 * Free the TX list buffers.
1635 */
1636 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1637 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
ca59556a
JS
1638 bus_dmamap_unload(sc->rl_tag,
1639 sc->rl_cdata.rl_tx_dmamap[i]);
1640 bus_dmamap_destroy(sc->rl_tag,
1641 sc->rl_cdata.rl_tx_dmamap[i]);
984263bc
MD
1642 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1643 sc->rl_cdata.rl_tx_chain[i] = NULL;
ca59556a
JS
1644 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1645 0x0000000);
984263bc
MD
1646 }
1647 }
984263bc
MD
1648}
1649
1650/*
1651 * Stop all chip I/O so that the kernel's probe routines don't
1652 * get confused by errant DMAs when rebooting.
1653 */
ca59556a
JS
1654static void
1655rl_shutdown(device_t dev)
984263bc 1656{
ca59556a 1657 struct rl_softc *sc;
984263bc
MD
1658
1659 sc = device_get_softc(dev);
78195a76 1660 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc 1661 rl_stop(sc);
78195a76 1662 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1663}
1664
1665/*
1666 * Device suspend routine. Stop the interface and save some PCI
1667 * settings in case the BIOS doesn't restore them properly on
1668 * resume.
1669 */
ca59556a
JS
1670static int
1671rl_suspend(device_t dev)
984263bc 1672{
ca59556a
JS
1673 struct rl_softc *sc = device_get_softc(dev);
1674 int i;
984263bc 1675
78195a76 1676 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1677 rl_stop(sc);
1678
1679 for (i = 0; i < 5; i++)
ca59556a 1680 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
984263bc
MD
1681 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1682 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1683 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1684 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1685
1686 sc->suspended = 1;
1687
78195a76 1688 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
984263bc
MD
1689 return (0);
1690}
1691
1692/*
1693 * Device resume routine. Restore some PCI settings in case the BIOS
1694 * doesn't, re-enable busmastering, and restart the interface if
1695 * appropriate.
1696 */
ca59556a 1697static int rl_resume(device_t dev)
984263bc 1698{
ca59556a
JS
1699 struct rl_softc *sc = device_get_softc(dev);
1700 struct ifnet *ifp = &sc->arpcom.ac_if;
3d0f5f54 1701 int i;
984263bc 1702
78195a76
MD
1703 lwkt_serialize_enter(ifp->if_serializer);
1704
984263bc
MD
1705 /* better way to do this? */
1706 for (i = 0; i < 5; i++)
ca59556a 1707 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
984263bc
MD
1708 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1709 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1710 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1711 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1712
1713 /* reenable busmastering */
1714 pci_enable_busmaster(dev);
1715 pci_enable_io(dev, RL_RES);
1716
1717 /* reinitialize interface if necessary */
1718 if (ifp->if_flags & IFF_UP)
1719 rl_init(sc);
1720
1721 sc->suspended = 0;
78195a76 1722 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1723 return (0);
1724}