Remove unused bfe_softc fields
[dragonfly.git] / sys / dev / netif / bfe / if_bfe.c
CommitLineData
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1/*
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
7 */
8
9/*
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
2ba09803 31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
a75a1559 32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
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33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/sockio.h>
38#include <sys/mbuf.h>
39#include <sys/malloc.h>
9db4b353 40#include <sys/interrupt.h>
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41#include <sys/kernel.h>
42#include <sys/socket.h>
43#include <sys/queue.h>
1f7ab7c9
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44#include <sys/bus.h>
45#include <sys/rman.h>
0f20326f 46#include <sys/thread2.h>
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47
48#include <net/if.h>
0bf9a476 49#include <net/ifq_var.h>
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50#include <net/if_arp.h>
51#include <net/ethernet.h>
52#include <net/if_dl.h>
53#include <net/if_media.h>
54
55#include <net/bpf.h>
56
57#include <net/if_types.h>
58#include <net/vlan/if_vlan_var.h>
59
60#include <netinet/in_systm.h>
61#include <netinet/in.h>
62#include <netinet/ip.h>
63
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64#include <bus/pci/pcireg.h>
65#include <bus/pci/pcivar.h>
66#include <bus/pci/pcidevs.h>
67
68#include <dev/netif/mii_layer/mii.h>
69#include <dev/netif/mii_layer/miivar.h>
70
bd1a73d5 71#include <dev/netif/bfe/if_bfereg.h>
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72
73MODULE_DEPEND(bfe, pci, 1, 1, 1);
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74MODULE_DEPEND(bfe, miibus, 1, 1, 1);
75
76/* "controller miibus0" required. See GENERIC if you get errors here. */
77#include "miibus_if.h"
78
79#define BFE_DEVDESC_MAX 64 /* Maximum device description length */
80
81static struct bfe_type bfe_devs[] = {
82 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
83 "Broadcom BCM4401 Fast Ethernet" },
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84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
85 "Broadcom BCM4401-B0 Fast Ethernet" },
bd1a73d5
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86 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
87 "Broadcom BCM4402 Fast Ethernet" },
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88 { 0, 0, NULL }
89};
90
91static int bfe_probe(device_t);
92static int bfe_attach(device_t);
93static int bfe_detach(device_t);
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94static void bfe_intr(void *);
95static void bfe_start(struct ifnet *);
bd4539cc 96static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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97static void bfe_init(void *);
98static void bfe_stop(struct bfe_softc *);
99static void bfe_watchdog(struct ifnet *);
100static void bfe_shutdown(device_t);
101static void bfe_tick(void *);
102static void bfe_txeof(struct bfe_softc *);
103static void bfe_rxeof(struct bfe_softc *);
104static void bfe_set_rx_mode(struct bfe_softc *);
105static int bfe_list_rx_init(struct bfe_softc *);
106static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
107static void bfe_rx_ring_free(struct bfe_softc *);
108
109static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110static int bfe_ifmedia_upd(struct ifnet *);
111static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112static int bfe_miibus_readreg(device_t, int, int);
113static int bfe_miibus_writereg(device_t, int, int, int);
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114static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
115 u_long, const int);
116static void bfe_get_config(struct bfe_softc *sc);
117static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118static void bfe_stats_update(struct bfe_softc *);
119static void bfe_clear_stats (struct bfe_softc *);
120static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122static int bfe_resetphy(struct bfe_softc *);
123static int bfe_setupphy(struct bfe_softc *);
124static void bfe_chip_reset(struct bfe_softc *);
125static void bfe_chip_halt(struct bfe_softc *);
126static void bfe_core_reset(struct bfe_softc *);
127static void bfe_core_disable(struct bfe_softc *);
128static int bfe_dma_alloc(device_t);
250ace3d 129static void bfe_dma_free(struct bfe_softc *);
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130static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
131static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
132static void bfe_cam_write(struct bfe_softc *, u_char *, int);
133
134static device_method_t bfe_methods[] = {
135 /* Device interface */
136 DEVMETHOD(device_probe, bfe_probe),
137 DEVMETHOD(device_attach, bfe_attach),
138 DEVMETHOD(device_detach, bfe_detach),
139 DEVMETHOD(device_shutdown, bfe_shutdown),
140
141 /* bus interface */
142 DEVMETHOD(bus_print_child, bus_generic_print_child),
143 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
144
145 /* MII interface */
146 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
147 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
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148
149 { 0, 0 }
150};
151
152static driver_t bfe_driver = {
153 "bfe",
154 bfe_methods,
155 sizeof(struct bfe_softc)
156};
157
158static devclass_t bfe_devclass;
159
160DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
162
163/*
164 * Probe for a Broadcom 4401 chip.
165 */
166static int
167bfe_probe(device_t dev)
168{
169 struct bfe_type *t;
97293ee3 170 uint16_t vendor, product;
7f186839 171
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172 vendor = pci_get_vendor(dev);
173 product = pci_get_device(dev);
7f186839 174
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175 for (t = bfe_devs; t->bfe_name != NULL; t++) {
176 if (vendor == t->bfe_vid && product == t->bfe_did) {
250ace3d 177 device_set_desc(dev, t->bfe_name);
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178 return(0);
179 }
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180 }
181
182 return(ENXIO);
183}
184
185static int
186bfe_dma_alloc(device_t dev)
187{
28488fd3 188 struct bfe_softc *sc = device_get_softc(dev);
96f2b7e7 189 int error, i, tx_pos = 0, rx_pos = 0;
7f186839 190
28488fd3 191 /*
884508cf
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192 * Parent tag. Apparently the chip cannot handle any DMA address
193 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
28488fd3
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194 */
195 error = bus_dma_tag_create(NULL, /* parent */
884508cf
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196 1, 0, /* alignment, boundary */
197 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
45e49764 198 BUS_SPACE_MAXADDR, /* highaddr */
7f186839 199 NULL, NULL, /* filter, filterarg */
884508cf
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200 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
201 0, /* num of segments */
7f186839 202 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
28488fd3 203 0, /* flags */
7f186839 204 &sc->bfe_parent_tag);
7f186839 205 if (error) {
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206 device_printf(dev, "could not allocate parent dma tag\n");
207 return(error);
7f186839 208 }
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209
210 /* tag for TX ring */
884508cf 211 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
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212 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
213 NULL, NULL,
884508cf 214 BFE_TX_LIST_SIZE, 1, BFE_TX_LIST_SIZE,
28488fd3 215 0, &sc->bfe_tx_tag);
7f186839 216 if (error) {
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217 device_printf(dev, "could not allocate dma tag for TX list\n");
218 return(error);
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219 }
220
221 /* tag for RX ring */
884508cf 222 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
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223 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
224 NULL, NULL,
884508cf 225 BFE_RX_LIST_SIZE, 1, BFE_RX_LIST_SIZE,
28488fd3 226 0, &sc->bfe_rx_tag);
7f186839 227 if (error) {
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228 device_printf(dev, "could not allocate dma tag for RX list\n");
229 return(error);
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230 }
231
96f2b7e7 232 /* Tag for RX mbufs */
7f186839 233 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
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234 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
235 NULL, NULL,
884508cf 236 MCLBYTES, 1, MCLBYTES,
96f2b7e7 237 BUS_DMA_ALLOCNOW, &sc->bfe_rxbuf_tag);
7f186839 238 if (error) {
96f2b7e7 239 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
250ace3d 240 return(error);
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241 }
242
96f2b7e7
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243 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0, &sc->bfe_rx_tmpmap);
244 if (error) {
245 device_printf(dev, "could not create RX mbuf tmp map\n");
246 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
247 sc->bfe_rxbuf_tag = NULL;
248 return error;
249 }
250ace3d 250
96f2b7e7 251 /* Allocate dma maps for RX list */
7f186839 252 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
96f2b7e7 253 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0,
28488fd3 254 &sc->bfe_rx_ring[i].bfe_map);
7f186839 255 if (error) {
250ace3d 256 rx_pos = i;
7f186839 257 device_printf(dev, "cannot create DMA map for RX\n");
250ace3d 258 goto ring_fail;
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259 }
260 }
250ace3d 261 rx_pos = BFE_RX_LIST_CNT;
7f186839 262
96f2b7e7
SZ
263 /* Tag for TX mbufs */
264 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
265 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
266 NULL, NULL,
267 MCLBYTES, 1, MCLBYTES,
268 BUS_DMA_ALLOCNOW, &sc->bfe_txbuf_tag);
269 if (error) {
270 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
271 return(error);
272 }
273
274 /* Allocate dmamaps for TX list */
7f186839 275 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
96f2b7e7 276 error = bus_dmamap_create(sc->bfe_txbuf_tag, 0,
28488fd3 277 &sc->bfe_tx_ring[i].bfe_map);
7f186839 278 if (error) {
250ace3d 279 tx_pos = i;
7f186839 280 device_printf(dev, "cannot create DMA map for TX\n");
250ace3d 281 goto ring_fail;
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282 }
283 }
284
285 /* Alloc dma for rx ring */
286 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
28488fd3
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287 BUS_DMA_WAITOK | BUS_DMA_ZERO,
288 &sc->bfe_rx_map);
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289 if (error) {
290 device_printf(dev, "cannot allocate DMA mem for RX\n");
291 return(error);
292 }
7f186839 293
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294 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
295 sc->bfe_rx_list, sizeof(struct bfe_desc),
28488fd3 296 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
250ace3d
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297 if (error) {
298 device_printf(dev, "cannot load DMA map for RX\n");
299 return(error);
300 }
7f186839 301
250ace3d 302 /* Alloc dma for tx ring */
28488fd3
SZ
303 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
304 BUS_DMA_WAITOK | BUS_DMA_ZERO,
305 &sc->bfe_tx_map);
250ace3d
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306 if (error) {
307 device_printf(dev, "cannot allocate DMA mem for TX\n");
308 return(error);
309 }
7f186839 310
28488fd3
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311 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
312 sc->bfe_tx_list, sizeof(struct bfe_desc),
313 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
250ace3d
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314 if (error) {
315 device_printf(dev, "cannot load DMA map for TX\n");
316 return(error);
317 }
7f186839 318
7f186839 319 return(0);
250ace3d
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320
321ring_fail:
96f2b7e7
SZ
322 if (sc->bfe_rxbuf_tag != NULL) {
323 for (i = 0; i < rx_pos; ++i) {
324 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
325 sc->bfe_rx_ring[i].bfe_map);
326 }
327 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
328 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
329 sc->bfe_rxbuf_tag = NULL;
330 }
250ace3d 331
96f2b7e7
SZ
332 if (sc->bfe_txbuf_tag != NULL) {
333 for (i = 0; i < tx_pos; ++i) {
334 bus_dmamap_destroy(sc->bfe_txbuf_tag,
335 sc->bfe_tx_ring[i].bfe_map);
336 }
337 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
338 sc->bfe_txbuf_tag = NULL;
339 }
250ace3d 340 return error;
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341}
342
343static int
344bfe_attach(device_t dev)
345{
346 struct ifnet *ifp;
347 struct bfe_softc *sc;
50b872f3 348 int error = 0, rid;
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349
350 sc = device_get_softc(dev);
351
7f186839 352 sc->bfe_dev = dev;
7fa4e3c3 353 callout_init(&sc->bfe_stat_timer);
7f186839 354
9db4b353 355#ifndef BURN_BRIDGES
7f186839
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356 /*
357 * Handle power management nonsense.
358 */
359 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
360 uint32_t membase, irq;
361
362 /* Save important PCI config data. */
363 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
364 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
365
366 /* Reset the power state. */
0e17b030 367 device_printf(dev, "chip is in D%d power mode"
50b872f3 368 " -- setting to D0\n", pci_get_powerstate(dev));
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369
370 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
371
372 /* Restore PCI config data. */
373 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
374 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
375 }
9db4b353 376#endif /* !BURN_BRIDGE */
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377
378 /*
379 * Map control/status registers.
380 */
381 pci_enable_busmaster(dev);
382
383 rid = BFE_PCI_MEMLO;
4e6d744d
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384 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
385 RF_ACTIVE);
7f186839 386 if (sc->bfe_res == NULL) {
50b872f3 387 device_printf(dev, "couldn't map memory\n");
250ace3d 388 return ENXIO;
7f186839
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389 }
390
391 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
392 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
393
394 /* Allocate interrupt */
395 rid = 0;
396
4e6d744d
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397 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
398 RF_SHAREABLE | RF_ACTIVE);
7f186839 399 if (sc->bfe_irq == NULL) {
50b872f3 400 device_printf(dev, "couldn't map interrupt\n");
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401 error = ENXIO;
402 goto fail;
403 }
404
250ace3d
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405 error = bfe_dma_alloc(dev);
406 if (error != 0) {
50b872f3 407 device_printf(dev, "failed to allocate DMA resources\n");
7f186839
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408 goto fail;
409 }
410
411 /* Set up ifnet structure */
412 ifp = &sc->arpcom.ac_if;
413 ifp->if_softc = sc;
414 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
415 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
416 ifp->if_ioctl = bfe_ioctl;
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417 ifp->if_start = bfe_start;
418 ifp->if_watchdog = bfe_watchdog;
419 ifp->if_init = bfe_init;
420 ifp->if_mtu = ETHERMTU;
0e557a3c
JS
421 ifp->if_baudrate = 100000000;
422 ifp->if_capabilities |= IFCAP_VLAN_MTU;
423 ifp->if_capenable |= IFCAP_VLAN_MTU;
424 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
0bf9a476
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425 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
426 ifq_set_ready(&ifp->if_snd);
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427
428 bfe_get_config(sc);
429
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430 /* Reset the chip and turn on the PHY */
431 bfe_chip_reset(sc);
432
433 if (mii_phy_probe(dev, &sc->bfe_miibus,
434 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
50b872f3 435 device_printf(dev, "MII without any PHY!\n");
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436 error = ENXIO;
437 goto fail;
438 }
439
78195a76 440 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
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441
442 /*
443 * Hook interrupt last to avoid having to lock softc
444 */
95893fe4 445 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
78195a76
MD
446 bfe_intr, sc, &sc->bfe_intrhand,
447 sc->arpcom.ac_if.if_serializer);
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448
449 if (error) {
0f20326f 450 ether_ifdetach(ifp);
50b872f3 451 device_printf(dev, "couldn't set up irq\n");
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452 goto fail;
453 }
9db4b353
SZ
454
455 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
456 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
250ace3d 457 return 0;
7f186839 458fail:
250ace3d 459 bfe_detach(dev);
7f186839
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460 return(error);
461}
462
463static int
464bfe_detach(device_t dev)
465{
0f20326f
JS
466 struct bfe_softc *sc = device_get_softc(dev);
467 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 468
7f186839 469 if (device_is_attached(dev)) {
cdf89432 470 lwkt_serialize_enter(ifp->if_serializer);
7f186839 471 bfe_stop(sc);
250ace3d 472 bfe_chip_reset(sc);
cdf89432
SZ
473 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
474 lwkt_serialize_exit(ifp->if_serializer);
475
476 ether_ifdetach(ifp);
7f186839 477 }
7f186839
JS
478 if (sc->bfe_miibus != NULL)
479 device_delete_child(dev, sc->bfe_miibus);
0f20326f 480 bus_generic_detach(dev);
7f186839 481
250ace3d
JS
482 if (sc->bfe_irq != NULL)
483 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
484
485 if (sc->bfe_res != NULL) {
486 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
487 sc->bfe_res);
488 }
250ace3d 489 bfe_dma_free(sc);
cdf89432 490
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491 return(0);
492}
493
494/*
495 * Stop all chip I/O so that the kernel's probe routines don't
496 * get confused by errant DMAs when rebooting.
497 */
498static void
499bfe_shutdown(device_t dev)
500{
0f20326f 501 struct bfe_softc *sc = device_get_softc(dev);
78195a76 502 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 503
78195a76 504 lwkt_serialize_enter(ifp->if_serializer);
7f186839 505 bfe_stop(sc);
78195a76 506 lwkt_serialize_exit(ifp->if_serializer);
7f186839
JS
507}
508
509static int
510bfe_miibus_readreg(device_t dev, int phy, int reg)
511{
512 struct bfe_softc *sc;
513 uint32_t ret;
514
515 sc = device_get_softc(dev);
516 if (phy != sc->bfe_phyaddr)
517 return(0);
518 bfe_readphy(sc, reg, &ret);
519
520 return(ret);
521}
522
523static int
524bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
525{
526 struct bfe_softc *sc;
527
528 sc = device_get_softc(dev);
529 if (phy != sc->bfe_phyaddr)
530 return(0);
531 bfe_writephy(sc, reg, val);
532
533 return(0);
534}
535
536static void
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537bfe_tx_ring_free(struct bfe_softc *sc)
538{
539 int i;
540
28488fd3 541 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
96f2b7e7 542 bus_dmamap_unload(sc->bfe_txbuf_tag,
28488fd3 543 sc->bfe_tx_ring[i].bfe_map);
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544 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
545 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
546 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
7f186839 547 }
28488fd3 548 }
7f186839 549 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
28488fd3 550 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
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551}
552
553static void
554bfe_rx_ring_free(struct bfe_softc *sc)
555{
556 int i;
557
28488fd3 558 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
7f186839 559 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
96f2b7e7 560 bus_dmamap_unload(sc->bfe_rxbuf_tag,
7f186839 561 sc->bfe_rx_ring[i].bfe_map);
28488fd3
SZ
562 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
563 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
7f186839 564 }
28488fd3 565 }
7f186839 566 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
28488fd3 567 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
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568}
569
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570static int
571bfe_list_rx_init(struct bfe_softc *sc)
572{
573 int i;
574
575 for (i = 0; i < BFE_RX_LIST_CNT; i++)
576 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
577 return(ENOBUFS);
578
28488fd3 579 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
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580 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
581
582 sc->bfe_rx_cons = 0;
583
584 return(0);
585}
586
587static int
588bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
589{
590 struct bfe_rxheader *rx_header;
591 struct bfe_desc *d;
592 struct bfe_data *r;
593 uint32_t ctrl;
594
595 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
596 return(EINVAL);
597
598 if (m == NULL) {
74f1caca 599 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
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600 if (m == NULL)
601 return(ENOBUFS);
602 m->m_len = m->m_pkthdr.len = MCLBYTES;
603 }
604 else
605 m->m_data = m->m_ext.ext_buf;
606
607 rx_header = mtod(m, struct bfe_rxheader *);
608 rx_header->len = 0;
609 rx_header->flags = 0;
610
611 /* Map the mbuf into DMA */
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612 d = &sc->bfe_rx_list[c];
613 r = &sc->bfe_rx_ring[c];
28488fd3 614 /* XXX error? */
96f2b7e7 615 bus_dmamap_load(sc->bfe_rxbuf_tag, r->bfe_map, mtod(m, void *),
28488fd3 616 MCLBYTES, bfe_dma_map_desc, d, BUS_DMA_NOWAIT);
96f2b7e7 617 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
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618
619 ctrl = ETHER_MAX_LEN + 32;
620
621 if(c == BFE_RX_LIST_CNT - 1)
622 ctrl |= BFE_DESC_EOT;
623
624 d->bfe_ctrl = ctrl;
625 r->bfe_mbuf = m;
28488fd3 626 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
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627 return(0);
628}
629
630static void
631bfe_get_config(struct bfe_softc *sc)
632{
633 uint8_t eeprom[128];
634
635 bfe_read_eeprom(sc, eeprom);
636
637 sc->arpcom.ac_enaddr[0] = eeprom[79];
638 sc->arpcom.ac_enaddr[1] = eeprom[78];
639 sc->arpcom.ac_enaddr[2] = eeprom[81];
640 sc->arpcom.ac_enaddr[3] = eeprom[80];
641 sc->arpcom.ac_enaddr[4] = eeprom[83];
642 sc->arpcom.ac_enaddr[5] = eeprom[82];
643
644 sc->bfe_phyaddr = eeprom[90] & 0x1f;
645 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
646
647 sc->bfe_core_unit = 0;
648 sc->bfe_dma_offset = BFE_PCI_DMA;
649}
650
651static void
652bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
653{
654 uint32_t bar_orig, pci_rev, val;
655
656 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
657 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
658 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
659
660 val = CSR_READ_4(sc, BFE_SBINTVEC);
661 val |= cores;
662 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
663
664 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
665 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
666 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
667
668 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
669}
670
671static void
672bfe_clear_stats(struct bfe_softc *sc)
673{
674 u_long reg;
7f186839 675
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676 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
677 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
678 CSR_READ_4(sc, reg);
679 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
680 CSR_READ_4(sc, reg);
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681}
682
683static int
684bfe_resetphy(struct bfe_softc *sc)
685{
686 uint32_t val;
7f186839 687
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688 bfe_writephy(sc, 0, BMCR_RESET);
689 DELAY(100);
690 bfe_readphy(sc, 0, &val);
691 if (val & BMCR_RESET) {
50b872f3
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692 if_printf(&sc->arpcom.ac_if,
693 "PHY Reset would not complete.\n");
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694 return(ENXIO);
695 }
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696 return(0);
697}
698
699static void
700bfe_chip_halt(struct bfe_softc *sc)
701{
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702 /* disable interrupts - not that it actually does..*/
703 CSR_WRITE_4(sc, BFE_IMASK, 0);
704 CSR_READ_4(sc, BFE_IMASK);
705
706 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
707 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
708
709 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
710 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
711 DELAY(10);
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712}
713
714static void
715bfe_chip_reset(struct bfe_softc *sc)
716{
717 uint32_t val;
7f186839 718
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719 /* Set the interrupt vector for the enet core */
720 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
721
722 /* is core up? */
723 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
724 if (val == BFE_CLOCK) {
725 /* It is, so shut it down */
726 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
727 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
728 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
729 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
730 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
731 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
732 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
733 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
40be5c8e 734 sc->bfe_rx_cons = 0;
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735 }
736
737 bfe_core_reset(sc);
738 bfe_clear_stats(sc);
739
740 /*
741 * We want the phy registers to be accessible even when
742 * the driver is "downed" so initialize MDC preamble, frequency,
743 * and whether internal or external phy here.
744 */
745
746 /* 4402 has 62.5Mhz SB clock and internal phy */
747 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
748
749 /* Internal or external PHY? */
750 val = CSR_READ_4(sc, BFE_DEVCTRL);
751 if (!(val & BFE_IPP))
752 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
753 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
754 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
755 DELAY(100);
756 }
757
1bcc3431
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758 /* Enable CRC32 generation and set proper LED modes */
759 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
760
761 /* Reset or clear powerdown control bit */
762 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
763
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764 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
765 BFE_LAZY_FC_MASK));
766
767 /*
768 * We don't want lazy interrupts, so just send them at the end of a
769 * frame, please
770 */
771 BFE_OR(sc, BFE_RCV_LAZY, 0);
772
773 /* Set max lengths, accounting for VLAN tags */
774 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
775 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
776
777 /* Set watermark XXX - magic */
778 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
779
780 /*
781 * Initialise DMA channels - not forgetting dma addresses need to be
782 * added to BFE_PCI_DMA
783 */
784 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
785 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
786
787 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
788 BFE_RX_CTRL_ENABLE);
789 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
790
791 bfe_resetphy(sc);
792 bfe_setupphy(sc);
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793}
794
795static void
796bfe_core_disable(struct bfe_softc *sc)
797{
798 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
799 return;
800
801 /*
802 * Set reject, wait for it set, then wait for the core to stop being busy
803 * Then set reset and reject and enable the clocks
804 */
805 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
806 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
807 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
808 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
809 BFE_RESET));
810 CSR_READ_4(sc, BFE_SBTMSLOW);
811 DELAY(10);
812 /* Leave reset and reject set */
813 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
814 DELAY(10);
815}
816
817static void
818bfe_core_reset(struct bfe_softc *sc)
819{
820 uint32_t val;
821
822 /* Disable the core */
823 bfe_core_disable(sc);
824
825 /* and bring it back up */
826 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
827 CSR_READ_4(sc, BFE_SBTMSLOW);
828 DELAY(10);
829
830 /* Chip bug, clear SERR, IB and TO if they are set. */
831 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
832 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
833 val = CSR_READ_4(sc, BFE_SBIMSTATE);
834 if (val & (BFE_IBE | BFE_TO))
835 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
836
837 /* Clear reset and allow it to move through the core */
838 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
839 CSR_READ_4(sc, BFE_SBTMSLOW);
840 DELAY(10);
841
842 /* Leave the clock set */
843 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
844 CSR_READ_4(sc, BFE_SBTMSLOW);
845 DELAY(10);
846}
847
848static void
849bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
850{
851 uint32_t val;
852
853 val = ((uint32_t) data[2]) << 24;
854 val |= ((uint32_t) data[3]) << 16;
855 val |= ((uint32_t) data[4]) << 8;
856 val |= ((uint32_t) data[5]);
857 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
858 val = (BFE_CAM_HI_VALID |
859 (((uint32_t) data[0]) << 8) |
860 (((uint32_t) data[1])));
861 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
862 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1bcc3431 863 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
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864 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
865}
866
867static void
868bfe_set_rx_mode(struct bfe_softc *sc)
869{
870 struct ifnet *ifp = &sc->arpcom.ac_if;
faeb7d30 871 struct ifmultiaddr *ifma;
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872 uint32_t val;
873 int i = 0;
874
875 val = CSR_READ_4(sc, BFE_RXCONF);
876
877 if (ifp->if_flags & IFF_PROMISC)
878 val |= BFE_RXCONF_PROMISC;
879 else
880 val &= ~BFE_RXCONF_PROMISC;
881
882 if (ifp->if_flags & IFF_BROADCAST)
883 val &= ~BFE_RXCONF_DBCAST;
884 else
885 val |= BFE_RXCONF_DBCAST;
886
887
888 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
889 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
890
faeb7d30
JS
891 if (ifp->if_flags & IFF_ALLMULTI) {
892 val |= BFE_RXCONF_ALLMULTI;
893 } else {
894 val &= ~BFE_RXCONF_ALLMULTI;
895 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
896 if (ifma->ifma_addr->sa_family != AF_LINK)
897 continue;
898 bfe_cam_write(sc,
899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
900 }
901 }
902
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903 CSR_WRITE_4(sc, BFE_RXCONF, val);
904 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
905}
906
907static void
908bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
909{
910 uint32_t *ptr;
911
912 ptr = arg;
913 *ptr = segs->ds_addr;
914}
915
916static void
917bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
918{
919 struct bfe_desc *d;
920
921 d = arg;
922 /* The chip needs all addresses to be added to BFE_PCI_DMA */
923 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
924}
925
926static void
250ace3d 927bfe_dma_free(struct bfe_softc *sc)
7f186839 928{
96f2b7e7
SZ
929 int i;
930
7f186839
JS
931 if (sc->bfe_tx_tag != NULL) {
932 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
250ace3d
JS
933 if (sc->bfe_tx_list != NULL) {
934 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
935 sc->bfe_tx_map);
936 sc->bfe_tx_list = NULL;
937 }
7f186839
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938 bus_dma_tag_destroy(sc->bfe_tx_tag);
939 sc->bfe_tx_tag = NULL;
940 }
941
942 if (sc->bfe_rx_tag != NULL) {
943 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
250ace3d
JS
944 if (sc->bfe_rx_list != NULL) {
945 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
946 sc->bfe_rx_map);
947 sc->bfe_rx_list = NULL;
948 }
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949 bus_dma_tag_destroy(sc->bfe_rx_tag);
950 sc->bfe_rx_tag = NULL;
951 }
952
96f2b7e7 953 if (sc->bfe_txbuf_tag != NULL) {
7f186839 954 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
96f2b7e7 955 bus_dmamap_destroy(sc->bfe_txbuf_tag,
7f186839
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956 sc->bfe_tx_ring[i].bfe_map);
957 }
96f2b7e7
SZ
958 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
959 sc->bfe_txbuf_tag = NULL;
960 }
961
962 if (sc->bfe_rxbuf_tag != NULL) {
250ace3d 963 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
96f2b7e7 964 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
250ace3d
JS
965 sc->bfe_rx_ring[i].bfe_map);
966 }
96f2b7e7
SZ
967 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
968 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
969 sc->bfe_rxbuf_tag = NULL;
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970 }
971
250ace3d 972 if (sc->bfe_parent_tag != NULL) {
7f186839 973 bus_dma_tag_destroy(sc->bfe_parent_tag);
250ace3d
JS
974 sc->bfe_parent_tag = NULL;
975 }
7f186839
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976}
977
978static void
979bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
980{
981 long i;
982 uint16_t *ptr = (uint16_t *)data;
983
984 for (i = 0; i < 128; i += 2)
985 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
986}
987
988static int
989bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
990 u_long timeout, const int clear)
991{
992 u_long i;
993
994 for (i = 0; i < timeout; i++) {
995 uint32_t val = CSR_READ_4(sc, reg);
996
997 if (clear && !(val & bit))
998 break;
999 if (!clear && (val & bit))
1000 break;
1001 DELAY(10);
1002 }
1003 if (i == timeout) {
50b872f3
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1004 if_printf(&sc->arpcom.ac_if,
1005 "BUG! Timeout waiting for bit %08x of register "
1006 "%x to %s.\n", bit, reg,
1007 (clear ? "clear" : "set"));
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1008 return -1;
1009 }
1010 return 0;
1011}
1012
1013static int
1014bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1015{
1016 int err;
7f186839 1017
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1018 /* Clear MII ISR */
1019 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1020 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1021 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1022 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1023 (reg << BFE_MDIO_RA_SHIFT) |
1024 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1025 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1026 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
7f186839
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1027 return(err);
1028}
1029
1030static int
1031bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1032{
1033 int status;
7f186839 1034
7f186839
JS
1035 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1036 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1037 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1038 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1039 (reg << BFE_MDIO_RA_SHIFT) |
1040 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1041 (val & BFE_MDIO_DATA_DATA)));
1042 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1043
7f186839
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1044 return status;
1045}
1046
1047/*
1048 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1049 * twice
1050 */
1051static int
1052bfe_setupphy(struct bfe_softc *sc)
1053{
1054 uint32_t val;
7f186839 1055
7f186839
JS
1056 /* Enable activity LED */
1057 bfe_readphy(sc, 26, &val);
1058 bfe_writephy(sc, 26, val & 0x7fff);
1059 bfe_readphy(sc, 26, &val);
1060
1061 /* Enable traffic meter LED mode */
1062 bfe_readphy(sc, 27, &val);
1063 bfe_writephy(sc, 27, val | (1 << 6));
1064
7f186839
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1065 return(0);
1066}
1067
1068static void
1069bfe_stats_update(struct bfe_softc *sc)
1070{
1071 u_long reg;
1072 uint32_t *val;
1073
1074 val = &sc->bfe_hwstats.tx_good_octets;
1075 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1076 *val++ += CSR_READ_4(sc, reg);
1077 val = &sc->bfe_hwstats.rx_good_octets;
1078 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1079 *val++ += CSR_READ_4(sc, reg);
1080}
1081
1082static void
1083bfe_txeof(struct bfe_softc *sc)
1084{
0f20326f 1085 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839
JS
1086 uint32_t i, chipidx;
1087
7f186839
JS
1088 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1089 chipidx /= sizeof(struct bfe_desc);
1090
1091 i = sc->bfe_tx_cons;
1092 /* Go through the mbufs and free those that have been transmitted */
1093 while (i != chipidx) {
1094 struct bfe_data *r = &sc->bfe_tx_ring[i];
28488fd3 1095
96f2b7e7 1096 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
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JS
1097 if (r->bfe_mbuf != NULL) {
1098 ifp->if_opackets++;
1099 m_freem(r->bfe_mbuf);
1100 r->bfe_mbuf = NULL;
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JS
1101 }
1102 sc->bfe_tx_cnt--;
1103 BFE_INC(i, BFE_TX_LIST_CNT);
1104 }
1105
1106 if (i != sc->bfe_tx_cons) {
1107 /* we freed up some mbufs */
1108 sc->bfe_tx_cons = i;
1109 ifp->if_flags &= ~IFF_OACTIVE;
1110 }
1111 if (sc->bfe_tx_cnt == 0)
1112 ifp->if_timer = 0;
1113 else
1114 ifp->if_timer = 5;
7f186839
JS
1115}
1116
1117/* Pass a received packet up the stack */
1118static void
1119bfe_rxeof(struct bfe_softc *sc)
1120{
0f20326f 1121 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1122 struct mbuf *m;
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JS
1123 struct bfe_rxheader *rxheader;
1124 struct bfe_data *r;
1125 uint32_t cons, status, current, len, flags;
f9142ddd 1126 struct mbuf_chain chain[MAXCPU];
7f186839 1127
7f186839
JS
1128 cons = sc->bfe_rx_cons;
1129 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1130 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1131
f9142ddd 1132 ether_input_chain_init(chain);
f9142ddd 1133
7f186839
JS
1134 while (current != cons) {
1135 r = &sc->bfe_rx_ring[cons];
1136 m = r->bfe_mbuf;
1137 rxheader = mtod(m, struct bfe_rxheader*);
96f2b7e7 1138 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_POSTREAD);
7f186839
JS
1139 len = rxheader->len;
1140 r->bfe_mbuf = NULL;
1141
96f2b7e7 1142 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
7f186839
JS
1143 flags = rxheader->flags;
1144
1145 len -= ETHER_CRC_LEN;
1146
1147 /* flag an error and try again */
1148 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1149 ifp->if_ierrors++;
1150 if (flags & BFE_RX_FLAG_SERR)
1151 ifp->if_collisions++;
1152 bfe_list_newbuf(sc, cons, m);
2ba09803 1153 BFE_INC(cons, BFE_RX_LIST_CNT);
7f186839
JS
1154 continue;
1155 }
1156
1157 /* Go past the rx header */
3013ac0e 1158 if (bfe_list_newbuf(sc, cons, NULL) != 0) {
7f186839 1159 bfe_list_newbuf(sc, cons, m);
2ba09803 1160 BFE_INC(cons, BFE_RX_LIST_CNT);
7f186839
JS
1161 ifp->if_ierrors++;
1162 continue;
1163 }
1164
3013ac0e
JS
1165 m_adj(m, BFE_RX_OFFSET);
1166 m->m_len = m->m_pkthdr.len = len;
1167
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JS
1168 ifp->if_ipackets++;
1169 m->m_pkthdr.rcvif = ifp;
1170
50098e2e 1171 ether_input_chain(ifp, m, chain);
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JS
1172 BFE_INC(cons, BFE_RX_LIST_CNT);
1173 }
f9142ddd 1174
f9142ddd 1175 ether_input_dispatch(chain);
f9142ddd 1176
7f186839 1177 sc->bfe_rx_cons = cons;
7f186839
JS
1178}
1179
1180static void
1181bfe_intr(void *xsc)
1182{
1183 struct bfe_softc *sc = xsc;
0f20326f 1184 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1185 uint32_t istat, imask, flag;
7f186839 1186
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JS
1187 istat = CSR_READ_4(sc, BFE_ISTAT);
1188 imask = CSR_READ_4(sc, BFE_IMASK);
1189
1190 /*
1191 * Defer unsolicited interrupts - This is necessary because setting the
1192 * chips interrupt mask register to 0 doesn't actually stop the
1193 * interrupts
1194 */
1195 istat &= imask;
1196 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1197 CSR_READ_4(sc, BFE_ISTAT);
1198
1199 /* not expecting this interrupt, disregard it */
1200 if (istat == 0) {
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JS
1201 return;
1202 }
1203
1204 if (istat & BFE_ISTAT_ERRORS) {
1205 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1206 if (flag & BFE_STAT_EMASK)
1207 ifp->if_oerrors++;
1208
1209 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1210 if (flag & BFE_RX_FLAG_ERRORS)
1211 ifp->if_ierrors++;
1212
1213 ifp->if_flags &= ~IFF_RUNNING;
1214 bfe_init(sc);
1215 }
1216
1217 /* A packet was received */
1218 if (istat & BFE_ISTAT_RX)
1219 bfe_rxeof(sc);
1220
1221 /* A packet was sent */
1222 if (istat & BFE_ISTAT_TX)
1223 bfe_txeof(sc);
1224
1225 /* We have packets pending, fire them out */
0bf9a476 1226 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
9db4b353 1227 if_devstart(ifp);
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JS
1228}
1229
1230static int
28488fd3 1231bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
7f186839
JS
1232{
1233 struct bfe_desc *d = NULL;
1234 struct bfe_data *r = NULL;
28488fd3
SZ
1235 struct mbuf *m;
1236 uint32_t frag, cur, cnt = 0;
1237 int error, chainlen = 0;
7f186839 1238
28488fd3
SZ
1239 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt));
1240
1241 /*
1242 * Count the number of frags in this chain to see if
1243 * we need to m_defrag. Since the descriptor list is shared
1244 * by all packets, we'll m_defrag long chains so that they
1245 * do not use up the entire list, even if they would fit.
1246 */
1247 for (m = *m_head; m != NULL; m = m->m_next)
1248 chainlen++;
1249
1250 if (chainlen > (BFE_TX_LIST_CNT / 4) ||
1251 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) {
1252 m = m_defrag(*m_head, MB_DONTWAIT);
1253 if (m == NULL) {
1254 m_freem(*m_head);
1255 return (ENOBUFS);
1256 }
1257 *m_head = m;
1258 }
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JS
1259
1260 /*
1261 * Start packing the mbufs in this chain into
1262 * the fragment pointers. Stop when we run out
1263 * of fragments or hit the end of the mbuf chain.
1264 */
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JS
1265 cur = frag = *txidx;
1266 cnt = 0;
1267
28488fd3 1268 for (m = *m_head; m != NULL; m = m->m_next) {
7f186839 1269 if (m->m_len != 0) {
28488fd3 1270 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt));
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JS
1271
1272 d = &sc->bfe_tx_list[cur];
1273 r = &sc->bfe_tx_ring[cur];
1274 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1275 /* always intterupt on completion */
1276 d->bfe_ctrl |= BFE_DESC_IOC;
28488fd3 1277 if (cnt == 0) {
7f186839
JS
1278 /* Set start of frame */
1279 d->bfe_ctrl |= BFE_DESC_SOF;
28488fd3
SZ
1280 }
1281 if (cur == BFE_TX_LIST_CNT - 1) {
7f186839
JS
1282 /*
1283 * Tell the chip to wrap to the start of the
28488fd3 1284 * descriptor list
7f186839
JS
1285 */
1286 d->bfe_ctrl |= BFE_DESC_EOT;
28488fd3
SZ
1287 }
1288
96f2b7e7 1289 error = bus_dmamap_load(sc->bfe_txbuf_tag, r->bfe_map,
28488fd3
SZ
1290 mtod(m, void *), m->m_len,
1291 bfe_dma_map_desc, d,
1292 BUS_DMA_NOWAIT);
1293 if (error) {
1294 /* XXX This should be a fatal error. */
1295 if_printf(&sc->arpcom.ac_if,
1296 "%s bus_dmamap_load failed: %d",
1297 __func__, error);
1298 m_freem(*m_head);
1299 return (ENOBUFS);
1300 }
7f186839 1301
96f2b7e7 1302 bus_dmamap_sync(sc->bfe_txbuf_tag, r->bfe_map,
28488fd3 1303 BUS_DMASYNC_PREWRITE);
7f186839
JS
1304
1305 frag = cur;
1306 BFE_INC(cur, BFE_TX_LIST_CNT);
1307 cnt++;
1308 }
1309 }
1310
7f186839 1311 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
28488fd3
SZ
1312 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1313 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
7f186839
JS
1314
1315 *txidx = cur;
1316 sc->bfe_tx_cnt += cnt;
1317 return(0);
1318}
1319
1320/*
1321 * Set up to transmit a packet
1322 */
1323static void
1324bfe_start(struct ifnet *ifp)
1325{
0f20326f 1326 struct bfe_softc *sc = ifp->if_softc;
7f186839 1327 struct mbuf *m_head = NULL;
efb8ae81 1328 int idx, need_trans;
7f186839 1329
603a5653
SZ
1330 ASSERT_SERIALIZED(ifp->if_serializer);
1331
7f186839 1332 /*
efb8ae81
JS
1333 * Not much point trying to send if the link is down
1334 * or we have nothing to send.
7f186839 1335 */
9db4b353
SZ
1336 if (!sc->bfe_link) {
1337 ifq_purge(&ifp->if_snd);
7f186839 1338 return;
9db4b353 1339 }
7f186839 1340
78195a76 1341 if (ifp->if_flags & IFF_OACTIVE)
7f186839 1342 return;
7f186839 1343
0f20326f
JS
1344 idx = sc->bfe_tx_prod;
1345
efb8ae81 1346 need_trans = 0;
7f186839 1347 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
28488fd3
SZ
1348 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) {
1349 ifp->if_flags |= IFF_OACTIVE;
1350 break;
1351 }
1352
1353 m_head = ifq_dequeue(&ifp->if_snd, NULL);
7f186839
JS
1354 if (m_head == NULL)
1355 break;
1356
1357 /*
efb8ae81
JS
1358 * Pack the data into the tx ring. If we don't have
1359 * enough room, let the chip drain the ring.
7f186839 1360 */
28488fd3 1361 if (bfe_encap(sc, &m_head, &idx)) {
7f186839
JS
1362 ifp->if_flags |= IFF_OACTIVE;
1363 break;
1364 }
efb8ae81 1365 need_trans = 1;
7f186839
JS
1366
1367 /*
1368 * If there's a BPF listener, bounce a copy of this frame
1369 * to him.
1370 */
1371 BPF_MTAP(ifp, m_head);
1372 }
1373
78195a76 1374 if (!need_trans)
efb8ae81 1375 return;
efb8ae81 1376
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JS
1377 sc->bfe_tx_prod = idx;
1378 /* Transmit - twice due to apparent hardware bug */
1379 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1380 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1381
1382 /*
1383 * Set a timeout in case the chip goes out to lunch.
1384 */
1385 ifp->if_timer = 5;
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JS
1386}
1387
1388static void
1389bfe_init(void *xsc)
1390{
1391 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1392 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1393
603a5653
SZ
1394 ASSERT_SERIALIZED(ifp->if_serializer);
1395
78195a76 1396 if (ifp->if_flags & IFF_RUNNING)
7f186839 1397 return;
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JS
1398
1399 bfe_stop(sc);
1400 bfe_chip_reset(sc);
1401
1402 if (bfe_list_rx_init(sc) == ENOBUFS) {
50b872f3
JS
1403 if_printf(ifp, "bfe_init failed. "
1404 " Not enough memory for list buffers\n");
7f186839
JS
1405 bfe_stop(sc);
1406 return;
1407 }
1408
1409 bfe_set_rx_mode(sc);
1410
1411 /* Enable the chip and core */
1412 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1413 /* Enable interrupts */
1414 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1415
1416 bfe_ifmedia_upd(ifp);
1417 ifp->if_flags |= IFF_RUNNING;
1418 ifp->if_flags &= ~IFF_OACTIVE;
1419
7fa4e3c3 1420 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
7f186839
JS
1421}
1422
1423/*
1424 * Set media options.
1425 */
1426static int
1427bfe_ifmedia_upd(struct ifnet *ifp)
1428{
0f20326f 1429 struct bfe_softc *sc = ifp->if_softc;
7f186839 1430 struct mii_data *mii;
7f186839 1431
603a5653
SZ
1432 ASSERT_SERIALIZED(ifp->if_serializer);
1433
7f186839
JS
1434 mii = device_get_softc(sc->bfe_miibus);
1435 sc->bfe_link = 0;
1436 if (mii->mii_instance) {
1437 struct mii_softc *miisc;
1438 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1439 miisc = LIST_NEXT(miisc, mii_list))
1440 mii_phy_reset(miisc);
1441 }
1442 mii_mediachg(mii);
1443
9e61439d
SZ
1444 bfe_setupphy(sc);
1445
7f186839
JS
1446 return(0);
1447}
1448
1449/*
1450 * Report current media status.
1451 */
1452static void
1453bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1454{
1455 struct bfe_softc *sc = ifp->if_softc;
1456 struct mii_data *mii;
7f186839 1457
603a5653
SZ
1458 ASSERT_SERIALIZED(ifp->if_serializer);
1459
7f186839
JS
1460 mii = device_get_softc(sc->bfe_miibus);
1461 mii_pollstat(mii);
1462 ifmr->ifm_active = mii->mii_media_active;
1463 ifmr->ifm_status = mii->mii_media_status;
7f186839
JS
1464}
1465
1466static int
bd4539cc 1467bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
7f186839
JS
1468{
1469 struct bfe_softc *sc = ifp->if_softc;
1470 struct ifreq *ifr = (struct ifreq *) data;
1471 struct mii_data *mii;
1472 int error = 0;
7f186839 1473
603a5653
SZ
1474 ASSERT_SERIALIZED(ifp->if_serializer);
1475
7f186839
JS
1476 switch (command) {
1477 case SIOCSIFFLAGS:
1478 if (ifp->if_flags & IFF_UP)
1479 if (ifp->if_flags & IFF_RUNNING)
1480 bfe_set_rx_mode(sc);
1481 else
1482 bfe_init(sc);
1483 else if (ifp->if_flags & IFF_RUNNING)
1484 bfe_stop(sc);
1485 break;
1486 case SIOCADDMULTI:
1487 case SIOCDELMULTI:
1488 if (ifp->if_flags & IFF_RUNNING)
1489 bfe_set_rx_mode(sc);
1490 break;
1491 case SIOCGIFMEDIA:
1492 case SIOCSIFMEDIA:
1493 mii = device_get_softc(sc->bfe_miibus);
1494 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1495 command);
1496 break;
7f186839 1497 default:
4cde4dd5 1498 error = ether_ioctl(ifp, command, data);
7f186839
JS
1499 break;
1500 }
7f186839
JS
1501 return error;
1502}
1503
1504static void
1505bfe_watchdog(struct ifnet *ifp)
1506{
0f20326f 1507 struct bfe_softc *sc = ifp->if_softc;
7f186839 1508
603a5653
SZ
1509 ASSERT_SERIALIZED(ifp->if_serializer);
1510
50b872f3 1511 if_printf(ifp, "watchdog timeout -- resetting\n");
7f186839
JS
1512
1513 ifp->if_flags &= ~IFF_RUNNING;
1514 bfe_init(sc);
1515
1516 ifp->if_oerrors++;
7f186839
JS
1517}
1518
1519static void
1520bfe_tick(void *xsc)
1521{
1522 struct bfe_softc *sc = xsc;
1523 struct mii_data *mii;
78195a76 1524 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839
JS
1525
1526 mii = device_get_softc(sc->bfe_miibus);
1527
78195a76
MD
1528 lwkt_serialize_enter(ifp->if_serializer);
1529
7f186839 1530 bfe_stats_update(sc);
7fa4e3c3 1531 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
7f186839 1532
3641b7ca 1533 if (sc->bfe_link == 0) {
78195a76
MD
1534 mii_tick(mii);
1535 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1536 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1537 sc->bfe_link++;
1538 }
1539 if (!sc->bfe_link)
1540 sc->bfe_link++;
7f186839 1541 }
78195a76 1542 lwkt_serialize_exit(ifp->if_serializer);
7f186839
JS
1543}
1544
1545/*
1546 * Stop the adapter and free any mbufs allocated to the
1547 * RX and TX lists.
1548 */
1549static void
1550bfe_stop(struct bfe_softc *sc)
1551{
0f20326f 1552 struct ifnet *ifp = &sc->arpcom.ac_if;
7f186839 1553
603a5653
SZ
1554 ASSERT_SERIALIZED(ifp->if_serializer);
1555
7fa4e3c3 1556 callout_stop(&sc->bfe_stat_timer);
7f186839 1557
7f186839
JS
1558 bfe_chip_halt(sc);
1559 bfe_tx_ring_free(sc);
1560 bfe_rx_ring_free(sc);
1561
1562 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
7f186839 1563}