Remove unused bfe_softc fields
[dragonfly.git] / sys / dev / netif / bfe / if_bfereg.h
CommitLineData
7f186839
JS
1/* Copyright (c) 2003 Stuart Walsh */
2/* $FreeBSD: src/sys/dev/bfe/if_bfereg.h,v 1.1.4.3 2004/02/13 21:36:34 julian Exp $ */
50b872f3 3/* $DragonFly: src/sys/dev/netif/bfe/if_bfereg.h,v 1.4 2005/05/23 18:05:58 joerg Exp $ */
7f186839
JS
4
5#ifndef _BFE_H
6#define _BFE_H
7
8/* PCI registers */
9#define BFE_PCI_MEMLO 0x10
10#define BFE_PCI_MEMHIGH 0x14
11#define BFE_PCI_INTLINE 0x3C
12
13/* Register layout. */
14#define BFE_DEVCTRL 0x00000000 /* Device Control */
15#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
16#define BFE_IPP 0x00000400 /* Internal EPHY Present */
17#define BFE_EPR 0x00008000 /* EPHY Reset */
18#define BFE_PME 0x00001000 /* PHY Mode Enable */
19#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
20#define BFE_PADDR 0x0007c000 /* PHY Address */
21#define BFE_PADDR_SHIFT 18
22
23#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
24#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */
25
26#define BFE_ISTAT 0x00000020 /* Interrupt Status */
27#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */
28#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */
29#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */
30#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */
31#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
32#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
33#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
34#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
35#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
36#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
37#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
38#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
39#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
40#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | \
41 BFE_ISTAT_DPE | BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
42
43#define BFE_IMASK 0x00000024 /* Interrupt Mask */
44#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | \
45 BFE_ISTAT_RX | BFE_ISTAT_TX)
46
47#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
48#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
49#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
50#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */
51#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */
52#define BFE_CTRL_LED_SHIFT 5
53
54#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */
55#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */
56#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */
57#define BFE_LAZY_FC_SHIFT 24
58
59#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
60#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
61#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
62#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
63#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */
64#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */
65
66#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */
67#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */
68#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */
69#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
70#define BFE_STAT_SMASK 0x0000f000 /* State Mask */
71#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */
72#define BFE_STAT_SACTIVE 0x00001000 /* State Active */
73#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */
74#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */
75#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */
76#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
77#define BFE_STAT_ENONE 0x00000000 /* Error None */
78#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
79#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
80#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
81#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
82#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */
83
84#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
85#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
86#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
87#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
88
89#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
90#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
91#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
92
93#define BFE_RXCONF 0x00000400 /* EMAC RX Config */
94#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */
95#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */
96#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */
97#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
98#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
99#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
100#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
101#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */
102
103#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
104#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */
105
106#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */
107#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */
108#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
109
110#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */
111#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */
112#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */
113#define BFE_MDIO_TA_SHIFT 16
114#define BFE_MDIO_TA_VALID 2
115
116#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */
117#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */
118#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */
119#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */
120#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */
121#define BFE_MDIO_RA_SHIFT 18
122#define BFE_MDIO_PMD_SHIFT 23
123#define BFE_MDIO_OP_SHIFT 28
124#define BFE_MDIO_OP_WRITE 1
125#define BFE_MDIO_OP_READ 2
126#define BFE_MDIO_SB_SHIFT 30
127
128#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
129#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */
130#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
131#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
132#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
133
134#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */
135#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */
136#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */
137
138#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */
139#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
140#define BFE_CAM_MSEL 0x00000002 /* Mask Select */
141#define BFE_CAM_READ 0x00000004 /* Read */
142#define BFE_CAM_WRITE 0x00000008 /* Read */
143#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
144#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */
145#define BFE_CAM_INDEX_SHIFT 16
146
147#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */
148#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
149#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */
150#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */
151#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */
152
153#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */
154#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */
155#define BFE_TX_FMODE 0x00000002 /* Flow Mode */
156#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
157#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */
158
159#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */
160
161#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
162#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */
163
164/* Status registers */
165#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
166#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
167#define BFE_TX_O 0x00000508 /* MIB TX Octets */
168#define BFE_TX_P 0x0000050C /* MIB TX Packets */
169#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
170#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
171#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
172#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
173#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */
174#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */
175#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */
176#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */
177#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */
178#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */
179#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */
180#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */
181#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */
182#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */
183#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */
184#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */
185#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */
186#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */
187#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */
188#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */
189#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
190#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
191#define BFE_RX_O 0x00000588 /* MIB RX Octets */
192#define BFE_RX_P 0x0000058C /* MIB RX Packets */
193#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
194#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
195#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
196#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
197#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
198#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
199#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
200#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
201#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
202#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
203#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
204#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
205#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
206#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
207#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
208#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
209#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
210#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
211#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
212
213#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */
214#define BFE_PC 0x0000000f /* Pipe Count */
215#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */
216#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */
217#define BFE_AP_TS 0x00000010 /* Use timeslices only */
218#define BFE_AP_TK 0x00000020 /* Use token only */
219#define BFE_AP_RSV 0x00000030 /* Reserved */
220#define BFE_IBE 0x00020000 /* In Band Error */
221#define BFE_TO 0x00040000 /* Timeout */
222
223
224/*
225 * Seems the bcm440x has a fairly generic core, we only need be concerned with
226 * a couple of these
227 */
228#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
229#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
230#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
231#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
232#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
233#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
234#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
235#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
236
237#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */
238#define BFE_RESET 0x00000001 /* Reset */
239#define BFE_REJECT 0x00000002 /* Reject */
240#define BFE_CLOCK 0x00010000 /* Clock Enable */
241#define BFE_FGC 0x00020000 /* Force Gated Clocks On */
242#define BFE_PE 0x40000000 /* Power Management Enable */
243#define BFE_BE 0x80000000 /* BIST Enable */
244
245#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */
246#define BFE_SERR 0x00000001 /* S-error */
247#define BFE_INT 0x00000002 /* Interrupt */
248#define BFE_BUSY 0x00000004 /* Busy */
249#define BFE_GCR 0x20000000 /* Gated Clock Request */
250#define BFE_BISTF 0x40000000 /* BIST Failed */
251#define BFE_BISTD 0x80000000 /* BIST Done */
252
253#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
254#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */
255#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */
256#define BFE_TAB0_SHIFT 0
257#define BFE_TAB1_SHIFT 16
258
259#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */
260#define BFE_STO_MASK 0x00000003 /* Service Timeout */
261#define BFE_RTO_MASK 0x00000030 /* Request Timeout */
262#define BFE_CID_MASK 0x00ff0000 /* Connection ID */
263#define BFE_RTO_SHIFT 4
264#define BFE_CID_SHIFT 16
265
266#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */
267#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
268#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
269#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
270#define BFE_TEM_SHIFT 4
271#define BFE_BEM_SHIFT 6
272
273#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */
274#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
275#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
276#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
277#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
278#define BFE_LOW_CO_SHIFT 11
279#define BFE_LOW_IF_SHIFT 18
280#define BFE_LOW_IM_SHIFT 24
281
282#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */
283#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
284#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
285#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
286#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
287#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
288#define BFE_HIGH_RM_SHIFT 2
289#define BFE_HIGH_SM_SHIFT 4
290#define BFE_HIGH_EM_SHIFT 8
291#define BFE_HIGH_IM_SHIFT 10
292
293#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */
294#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */
295#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */
296#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */
297#define BFE_MAX0_SHIFT 16
298#define BFE_MAX1_SHIFT 20
299
300#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */
301#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */
302#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */
303
304#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */
305#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
306
307#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */
308#define BFE_CS_MASK 0x00000003 /* Config Space Mask */
309#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */
310#define BFE_SYNCH 0x00000040 /* Sync */
311#define BFE_INIT 0x00000080 /* Initiator */
312#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */
313#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */
314#define BFE_FIRST 0x00010000 /* This Initiator is First */
315#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */
316#define BFE_TP_MASK 0x00f00000 /* Target Ports */
317#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */
318#define BFE_AR_SHIFT 3
319#define BFE_MINLAT_SHIFT 8
320#define BFE_MAXLAT_SHIFT 12
321#define BFE_CW_SHIFT 18
322#define BFE_TP_SHIFT 20
323#define BFE_IP_SHIFT 24
324
325#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */
326#define BFE_RC_MASK 0x0000000f /* Revision Code */
327#define BFE_CC_MASK 0x0000fff0 /* Core Code */
328#define BFE_VC_MASK 0xffff0000 /* Vendor Code */
329#define BFE_CC_SHIFT 4
330#define BFE_VC_SHIFT 16
331
332#define BFE_CORE_ILINE20 0x801
333#define BFE_CORE_SDRAM 0x803
334#define BFE_CORE_PCI 0x804
335#define BFE_CORE_MIPS 0x805
336#define BFE_CORE_ENET 0x806
337#define BFE_CORE_CODEC 0x807
338#define BFE_CORE_USB 0x808
339#define BFE_CORE_ILINE100 0x80a
340#define BFE_CORE_EXTIF 0x811
341
342/* SSB PCI config space registers. */
343#define BFE_BAR0_WIN 0x80
344#define BFE_BAR1_WIN 0x84
345#define BFE_SPROM_CONTROL 0x88
346#define BFE_BAR1_CONTROL 0x8c
347
348/* SSB core and hsot control registers. */
349#define BFE_SSB_CONTROL 0x00000000
350#define BFE_SSB_ARBCONTROL 0x00000010
351#define BFE_SSB_ISTAT 0x00000020
352#define BFE_SSB_IMASK 0x00000024
353#define BFE_SSB_MBOX 0x00000028
354#define BFE_SSB_BCAST_ADDR 0x00000050
355#define BFE_SSB_BCAST_DATA 0x00000054
356#define BFE_SSB_PCI_TRANS_0 0x00000100
357#define BFE_SSB_PCI_TRANS_1 0x00000104
358#define BFE_SSB_PCI_TRANS_2 0x00000108
359#define BFE_SSB_SPROM 0x00000800
360
361#define BFE_SSB_PCI_MEM 0x00000000
362#define BFE_SSB_PCI_IO 0x00000001
363#define BFE_SSB_PCI_CFG0 0x00000002
364#define BFE_SSB_PCI_CFG1 0x00000003
365#define BFE_SSB_PCI_PREF 0x00000004
366#define BFE_SSB_PCI_BURST 0x00000008
367#define BFE_SSB_PCI_MASK0 0xfc000000
368#define BFE_SSB_PCI_MASK1 0xfc000000
369#define BFE_SSB_PCI_MASK2 0xc0000000
370
371#define BFE_DESC_LEN 0x00001fff
372#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */
373#define BFE_DESC_EOT 0x10000000 /* End of Table */
374#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */
375#define BFE_DESC_EOF 0x40000000 /* End of Frame */
376#define BFE_DESC_SOF 0x80000000 /* Start of Frame */
377
378#define BFE_RX_CP_THRESHOLD 256
379#define BFE_RX_HEADER_LEN 28
380
381#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
382#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */
383#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
384#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
385#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
386#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
387#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
388#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
389#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
390#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
391 BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
392
393#define BFE_MCAST_TBL_SIZE 32
394#define BFE_PCI_DMA 0x40000000
395#define BFE_REG_PCI 0x18002000
396
397#define PCI_SETBIT(dev, reg, x, s) \
398 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
399#define PCI_CLRBIT(dev, reg, x, s) \
400 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
401
402#define BFE_RX_RING_SIZE 512
403#define BFE_TX_RING_SIZE 512
404#define BFE_LINK_DOWN 5
405#define BFE_TX_LIST_CNT 511
406#define BFE_RX_LIST_CNT 511
407#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc)
408#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc)
409#define BFE_RX_OFFSET 30
410#define BFE_TX_QLEN 256
411
412#define CSR_READ_4(sc, reg) \
413 bus_space_read_4(sc->bfe_btag, sc->bfe_bhandle, reg)
414
415#define CSR_WRITE_4(sc, reg, val) \
416 bus_space_write_4(sc->bfe_btag, sc->bfe_bhandle, reg, val)
417
418#define BFE_OR(sc, name, val) \
419 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
420
421#define BFE_AND(sc, name, val) \
422 CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
423
7f186839
JS
424#define ETHER_ALIGN 2
425
426#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
427
428struct bfe_data {
429 struct mbuf *bfe_mbuf;
430 bus_dmamap_t bfe_map;
431};
432
433struct bfe_desc {
434 uint32_t bfe_ctrl;
435 uint32_t bfe_addr;
436};
437
438struct bfe_rxheader {
439 uint16_t len;
440 uint16_t flags;
441 uint16_t pad[12];
442};
443
444struct bfe_hw_stats {
445 uint32_t tx_good_octets, tx_good_pkts, tx_octets;
446 uint32_t tx_pkts, tx_broadcast_pkts, tx_multicast_pkts;
447 uint32_t tx_len_64, tx_len_65_to_127, tx_len_128_to_255;
448 uint32_t tx_len_256_to_511, tx_len_512_to_1023, tx_len_1024_to_max;
449 uint32_t tx_jabber_pkts, tx_oversize_pkts, tx_fragment_pkts;
450 uint32_t tx_underruns, tx_total_cols, tx_single_cols;
451 uint32_t tx_multiple_cols, tx_excessive_cols, tx_late_cols;
452 uint32_t tx_defered, tx_carrier_lost, tx_pause_pkts;
453 uint32_t __pad1[8];
454
455 uint32_t rx_good_octets, rx_good_pkts, rx_octets;
456 uint32_t rx_pkts, rx_broadcast_pkts, rx_multicast_pkts;
457 uint32_t rx_len_64, rx_len_65_to_127, rx_len_128_to_255;
458 uint32_t rx_len_256_to_511, rx_len_512_to_1023, rx_len_1024_to_max;
459 uint32_t rx_jabber_pkts, rx_oversize_pkts, rx_fragment_pkts;
460 uint32_t rx_missed_pkts, rx_crc_align_errs, rx_undersize;
461 uint32_t rx_crc_errs, rx_align_errs, rx_symbol_errs;
462 uint32_t rx_pause_pkts, rx_nonpause_pkts;
463};
464
465struct bfe_softc
466{
467 struct arpcom arpcom; /* interface info */
468 device_t bfe_dev;
469 device_t bfe_miibus;
470 bus_space_handle_t bfe_bhandle;
471 bus_space_tag_t bfe_btag;
7f186839 472 bus_dma_tag_t bfe_parent_tag;
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473 bus_dma_tag_t bfe_rxbuf_tag;
474 bus_dmamap_t bfe_rx_tmpmap;
475 bus_dma_tag_t bfe_txbuf_tag;
476 bus_dma_tag_t bfe_tx_tag;
477 bus_dma_tag_t bfe_rx_tag;
478 bus_dmamap_t bfe_tx_map;
479 bus_dmamap_t bfe_rx_map;
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480 void *bfe_intrhand;
481 struct resource *bfe_irq;
482 struct resource *bfe_res;
7fa4e3c3 483 struct callout bfe_stat_timer;
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484 struct bfe_hw_stats bfe_hwstats;
485 struct bfe_desc *bfe_tx_list, *bfe_rx_list;
486 struct bfe_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */
487 struct bfe_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */
488 uint32_t bfe_flags;
489 uint32_t bfe_imask;
490 uint32_t bfe_dma_offset;
491 uint32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod;
40be5c8e 492 uint32_t bfe_rx_cons;
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493 uint32_t bfe_tx_dma, bfe_rx_dma;
494 uint32_t bfe_link;
495 uint8_t bfe_phyaddr; /* Address of the card's PHY */
496 uint8_t bfe_mdc_port;
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497 uint8_t bfe_core_unit;
498 uint8_t bfe_up;
499 int bfe_if_flags;
500};
501
502struct bfe_type
503{
504 uint16_t bfe_vid;
505 uint16_t bfe_did;
506 const char *bfe_name;
507};
508
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509#define BFE_BUS_SPACE_MAXADDR 0x3fffffff
510
7f186839 511#endif /* _BFE_H */