i386: Move mp_set_cpuids() from mp_machdep.c to lapic.c
[dragonfly.git] / sys / platform / pc32 / apic / lapic.c
CommitLineData
984263bc
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1/*
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 */
27
28#include <sys/param.h>
29#include <sys/systm.h>
b12a1521 30#include <sys/kernel.h>
23b08e03 31#include <sys/bus.h>
e0918665 32#include <sys/machintr.h>
72740893 33#include <machine/globaldata.h>
984263bc 34#include <machine/smp.h>
90e8a35b 35#include <machine/cputypes.h>
d595a6c0 36#include <machine/md_var.h>
ad52b37b 37#include <machine/pmap.h>
3340ac41 38#include <machine_base/apic/lapic.h>
929c940f 39#include <machine_base/apic/ioapic_abi.h>
984263bc 40#include <machine/segments.h>
96728c05 41#include <sys/thread2.h>
984263bc 42
87cf6827 43#include <machine/intr_machdep.h>
984263bc 44
cb7d6921 45volatile lapic_t *lapic;
ad52b37b 46
b52c8db0 47static void lapic_timer_calibrate(void);
086575e9 48static void lapic_timer_set_divisor(int);
a9e511df 49static void lapic_timer_fixup_handler(void *);
76c58571 50static void lapic_timer_restart_handler(void *);
c5b8324c 51
78ea5a2a
SZ
52void lapic_timer_process(void);
53void lapic_timer_process_frame(struct intrframe *);
c5b8324c 54
ef612539 55static int lapic_timer_enable = 1;
c5b8324c 56TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
b52c8db0 57
ef612539
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58static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
59static void lapic_timer_intr_enable(struct cputimer_intr *);
60static void lapic_timer_intr_restart(struct cputimer_intr *);
61static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
62
63static struct cputimer_intr lapic_cputimer_intr = {
64 .freq = 0,
65 .reload = lapic_timer_intr_reload,
66 .enable = lapic_timer_intr_enable,
67 .config = cputimer_intr_default_config,
68 .restart = lapic_timer_intr_restart,
69 .pmfixup = lapic_timer_intr_pmfixup,
70 .initclock = cputimer_intr_default_initclock,
71 .next = SLIST_ENTRY_INITIALIZER,
72 .name = "lapic",
73 .type = CPUTIMER_INTR_LAPIC,
74 .prio = CPUTIMER_INTR_PRIO_LAPIC,
75 .caps = CPUTIMER_INTR_CAP_NONE
76};
77
086575e9
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78static int lapic_timer_divisor_idx = -1;
79static const uint32_t lapic_timer_divisors[] = {
80 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
81 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
82};
c157ff7a 83#define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
086575e9 84
984263bc 85/*
68d62ec3
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86 * APIC ID logical/physical mapping structures.
87 * We oversize these to simplify boot-time config.
88 */
89int cpu_num_to_apic_id[NAPICID];
90int apic_id_to_logical[NAPICID];
91
92/*
d99d4acb 93 * Enable LAPIC, configure interrupts.
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94 */
95void
5ddeabb9 96lapic_init(boolean_t bsp)
984263bc 97{
78ea5a2a 98 uint32_t timer;
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99 u_int temp;
100
9d6bf2df 101 /*
dbfb3a5a
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102 * Install vectors
103 *
104 * Since IDT is shared between BSP and APs, these vectors
105 * only need to be installed once; we do it on BSP.
106 */
107 if (bsp) {
108 /* Install a 'Spurious INTerrupt' vector */
109 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
110 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
111
112 /* Install an inter-CPU IPI for TLB invalidation */
113 setidt(XINVLTLB_OFFSET, Xinvltlb,
114 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
115
116 /* Install an inter-CPU IPI for IPIQ messaging */
117 setidt(XIPIQ_OFFSET, Xipiq,
118 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
119
120 /* Install a timer vector */
121 setidt(XTIMER_OFFSET, Xtimer,
122 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
123
124 /* Install an inter-CPU IPI for CPU stop/restart */
125 setidt(XCPUSTOP_OFFSET, Xcpustop,
126 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
127 }
128
129 /*
d99d4acb 130 * Setup LINT0 as ExtINT on the BSP. This is theoretically an
97359a5b
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131 * aggregate interrupt input from the 8259. The INTA cycle
132 * will be routed to the external controller (the 8259) which
133 * is expected to supply the vector.
134 *
135 * Must be setup edge triggered, active high.
136 *
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137 * Disable LINT0 on BSP, if I/O APIC is enabled.
138 *
d99d4acb 139 * Disable LINT0 on the APs. It doesn't matter what delivery
97359a5b 140 * mode we use because we leave it masked.
9d6bf2df 141 */
cb7d6921 142 temp = lapic->lvt_lint0;
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143 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
144 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
4d08e038 145 if (bsp) {
9d6bf2df 146 temp |= APIC_LVT_DM_EXTINT;
4d08e038
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147 if (apic_io_enable)
148 temp |= APIC_LVT_MASKED;
149 } else {
97359a5b 150 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
4d08e038 151 }
cb7d6921 152 lapic->lvt_lint0 = temp;
984263bc 153
9d6bf2df 154 /*
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155 * Setup LINT1 as NMI.
156 *
157 * Must be setup edge trigger, active high.
158 *
159 * Enable LINT1 on BSP, if I/O APIC is enabled.
160 *
161 * Disable LINT1 on the APs.
9d6bf2df 162 */
cb7d6921 163 temp = lapic->lvt_lint1;
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164 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
165 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
166 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
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167 if (bsp && apic_io_enable)
168 temp &= ~APIC_LVT_MASKED;
cb7d6921 169 lapic->lvt_lint1 = temp;
984263bc 170
d9eea1a5 171 /*
d99d4acb 172 * Mask the LAPIC error interrupt, LAPIC performance counter
78ea5a2a 173 * interrupt.
c6a1aabe 174 */
cb7d6921
SZ
175 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
176 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
78ea5a2a 177
d99d4acb
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178 /*
179 * Set LAPIC timer vector and mask the LAPIC timer interrupt.
180 */
cb7d6921 181 timer = lapic->lvt_timer;
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182 timer &= ~APIC_LVTT_VECTOR;
183 timer |= XTIMER_OFFSET;
184 timer |= APIC_LVTT_MASKED;
cb7d6921 185 lapic->lvt_timer = timer;
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186
187 /*
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188 * Set the Task Priority Register as needed. At the moment allow
189 * interrupts on all cpus (the APs will remain CLId until they are
190 * ready to deal). We could disable all but IPIs by setting
84bf7d5a 191 * temp |= TPR_IPI for cpu != 0.
d9eea1a5 192 */
cb7d6921 193 temp = lapic->tpr;
984263bc 194 temp &= ~APIC_TPR_PRIO; /* clear priority field */
30c5f287
MN
195#ifdef SMP /* APIC-IO */
196if (!apic_io_enable) {
197#endif
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198 /*
199 * If we are NOT running the IO APICs, the LAPIC will only be used
200 * for IPIs. Set the TPR to prevent any unintentional interrupts.
201 */
84bf7d5a 202 temp |= TPR_IPI;
30c5f287
MN
203#ifdef SMP /* APIC-IO */
204}
97359a5b 205#endif
8a8d5d85 206
cb7d6921 207 lapic->tpr = temp;
984263bc 208
97359a5b 209 /*
d99d4acb 210 * Enable the LAPIC
97359a5b 211 */
cb7d6921 212 temp = lapic->svr;
d99d4acb 213 temp |= APIC_SVR_ENABLE; /* enable the LAPIC */
97359a5b 214 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
984263bc 215
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216 /*
217 * Set the spurious interrupt vector. The low 4 bits of the vector
218 * must be 1111.
219 */
220 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
984263bc 221 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
9d6bf2df
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222 temp &= ~APIC_SVR_VECTOR;
223 temp |= XSPURIOUSINT_OFFSET;
984263bc 224
cb7d6921 225 lapic->svr = temp;
984263bc 226
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227 /*
228 * Pump out a few EOIs to clean out interrupts that got through
229 * before we were able to set the TPR.
230 */
cb7d6921
SZ
231 lapic->eoi = 0;
232 lapic->eoi = 0;
233 lapic->eoi = 0;
0b692e79 234
c5b8324c 235 if (bsp) {
b52c8db0 236 lapic_timer_calibrate();
ef612539
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237 if (lapic_timer_enable) {
238 cputimer_intr_register(&lapic_cputimer_intr);
239 cputimer_intr_select(&lapic_cputimer_intr, 0);
240 }
c5b8324c 241 } else {
086575e9 242 lapic_timer_set_divisor(lapic_timer_divisor_idx);
c5b8324c 243 }
b52c8db0 244
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245 if (bootverbose)
246 apic_dump("apic_initialize()");
247}
248
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249static void
250lapic_timer_set_divisor(int divisor_idx)
251{
252 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
cb7d6921 253 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
b52c8db0
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254}
255
256static void
257lapic_timer_oneshot(u_int count)
258{
259 uint32_t value;
260
cb7d6921 261 value = lapic->lvt_timer;
b52c8db0 262 value &= ~APIC_LVTT_PERIODIC;
cb7d6921
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263 lapic->lvt_timer = value;
264 lapic->icr_timer = count;
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265}
266
267static void
6198c499
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268lapic_timer_oneshot_quick(u_int count)
269{
cb7d6921 270 lapic->icr_timer = count;
6198c499
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271}
272
273static void
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274lapic_timer_calibrate(void)
275{
47bdf646 276 sysclock_t value;
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277
278 /* Try to calibrate the local APIC timer. */
279 for (lapic_timer_divisor_idx = 0;
280 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
281 lapic_timer_divisor_idx++) {
282 lapic_timer_set_divisor(lapic_timer_divisor_idx);
283 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
284 DELAY(2000000);
cb7d6921 285 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
b52c8db0
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286 if (value != APIC_TIMER_MAX_COUNT)
287 break;
288 }
289 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
290 panic("lapic: no proper timer divisor?!\n");
ef612539 291 lapic_cputimer_intr.freq = value / 2;
b52c8db0 292
47bdf646 293 kprintf("lapic: divisor index %d, frequency %u Hz\n",
ef612539 294 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
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295}
296
c5b8324c
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297static void
298lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
299{
300 sysclock_t count;
301
302 gd->gd_timer_running = 0;
303
304 count = sys_cputimer->count();
305 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
306 systimer_intr(&count, 0, frame);
307}
308
78ea5a2a
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309void
310lapic_timer_process(void)
311{
ae48d6cd 312 lapic_timer_process_oncpu(mycpu, NULL);
78ea5a2a
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313}
314
315void
316lapic_timer_process_frame(struct intrframe *frame)
317{
ae48d6cd 318 lapic_timer_process_oncpu(mycpu, frame);
b12a1521
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319}
320
c5b8324c 321static void
ef612539 322lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
c5b8324c
SZ
323{
324 struct globaldata *gd = mycpu;
325
ef612539 326 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
c5b8324c
SZ
327 if (reload < 2)
328 reload = 2;
329
330 if (gd->gd_timer_running) {
cb7d6921 331 if (reload < lapic->ccr_timer)
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332 lapic_timer_oneshot_quick(reload);
333 } else {
334 gd->gd_timer_running = 1;
335 lapic_timer_oneshot_quick(reload);
336 }
337}
338
ef612539
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339static void
340lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
6198c499
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341{
342 uint32_t timer;
343
cb7d6921 344 timer = lapic->lvt_timer;
6198c499 345 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
cb7d6921 346 lapic->lvt_timer = timer;
a9e511df
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347
348 lapic_timer_fixup_handler(NULL);
349}
350
351static void
76c58571 352lapic_timer_fixup_handler(void *arg)
a9e511df 353{
76c58571
SZ
354 int *started = arg;
355
356 if (started != NULL)
357 *started = 0;
358
90e8a35b 359 if (cpu_vendor_id == CPU_VENDOR_AMD) {
a9e511df
SZ
360 /*
361 * Detect the presence of C1E capability mostly on latest
362 * dual-cores (or future) k8 family. This feature renders
363 * the local APIC timer dead, so we disable it by reading
364 * the Interrupt Pending Message register and clearing both
365 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
366 *
367 * Reference:
368 * "BIOS and Kernel Developer's Guide for AMD NPT
369 * Family 0Fh Processors"
370 * #32559 revision 3.00
371 */
372 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
373 (cpu_id & 0x0fff0000) >= 0x00040000) {
374 uint64_t msr;
375
376 msr = rdmsr(0xc0010055);
377 if (msr & 0x18000000) {
378 struct globaldata *gd = mycpu;
379
380 kprintf("cpu%d: AMD C1E detected\n",
381 gd->gd_cpuid);
382 wrmsr(0xc0010055, msr & ~0x18000000ULL);
383
384 /*
385 * We are kinda stalled;
386 * kick start again.
387 */
388 gd->gd_timer_running = 1;
389 lapic_timer_oneshot_quick(2);
76c58571
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390
391 if (started != NULL)
392 *started = 1;
a9e511df
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393 }
394 }
395 }
396}
397
76c58571
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398static void
399lapic_timer_restart_handler(void *dummy __unused)
400{
401 int started;
402
403 lapic_timer_fixup_handler(&started);
404 if (!started) {
405 struct globaldata *gd = mycpu;
406
407 gd->gd_timer_running = 1;
408 lapic_timer_oneshot_quick(2);
409 }
410}
411
a9e511df
SZ
412/*
413 * This function is called only by ACPI-CA code currently:
414 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
415 * module controls PM. So once ACPI-CA is attached, we try
416 * to apply the fixup to prevent LAPIC timer from hanging.
417 */
ef612539
SZ
418static void
419lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
a9e511df 420{
ef612539
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421 lwkt_send_ipiq_mask(smp_active_mask,
422 lapic_timer_fixup_handler, NULL);
6198c499
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423}
424
ef612539
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425static void
426lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
76c58571 427{
76c58571
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428 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
429}
430
b52c8db0 431
984263bc
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432/*
433 * dump contents of local APIC registers
434 */
435void
436apic_dump(char* str)
437{
26be20a0
SW
438 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
439 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
cb7d6921 440 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
984263bc
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441}
442
984263bc
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443/*
444 * Inter Processor Interrupt functions.
445 */
446
984263bc
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447/*
448 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
449 *
450 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
451 * vector is any valid SYSTEM INT vector
452 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
96728c05
MD
453 *
454 * A backlog of requests can create a deadlock between cpus. To avoid this
455 * we have to be able to accept IPIs at the same time we are trying to send
456 * them. The critical section prevents us from attempting to send additional
457 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
458 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
459 * to occur but fortunately it does not happen too often.
984263bc 460 */
984263bc
MD
461int
462apic_ipi(int dest_type, int vector, int delivery_mode)
463{
464 u_long icr_lo;
465
96728c05 466 crit_enter();
cb7d6921 467 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
468 unsigned int eflags = read_eflags();
469 cpu_enable_intr();
cfaeae2a 470 DEBUG_PUSH_INFO("apic_ipi");
cb7d6921 471 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
472 lwkt_process_ipiq();
473 }
cfaeae2a 474 DEBUG_POP_INFO();
96728c05 475 write_eflags(eflags);
984263bc 476 }
984263bc 477
cb7d6921 478 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
96728c05 479 delivery_mode | vector;
cb7d6921 480 lapic->icr_lo = icr_lo;
96728c05 481 crit_exit();
984263bc
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482 return 0;
483}
484
41a01a4d
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485void
486single_apic_ipi(int cpu, int vector, int delivery_mode)
984263bc
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487{
488 u_long icr_lo;
489 u_long icr_hi;
984263bc 490
41a01a4d 491 crit_enter();
cb7d6921 492 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
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493 unsigned int eflags = read_eflags();
494 cpu_enable_intr();
cfaeae2a 495 DEBUG_PUSH_INFO("single_apic_ipi");
cb7d6921 496 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
96728c05
MD
497 lwkt_process_ipiq();
498 }
cfaeae2a 499 DEBUG_POP_INFO();
96728c05 500 write_eflags(eflags);
984263bc 501 }
cb7d6921 502 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
984263bc 503 icr_hi |= (CPU_TO_ID(cpu) << 24);
cb7d6921 504 lapic->icr_hi = icr_hi;
984263bc 505
b2f93ae9 506 /* build ICR_LOW */
cb7d6921 507 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
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508 | APIC_DEST_DESTFLD | delivery_mode | vector;
509
510 /* write APIC ICR */
cb7d6921 511 lapic->icr_lo = icr_lo;
41a01a4d 512 crit_exit();
984263bc
MD
513}
514
41a01a4d
MD
515#if 0
516
517/*
518 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
519 *
520 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
521 * to the target, and the scheduler does not 'poll' for IPI messages.
522 */
523int
524single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
525{
526 u_long icr_lo;
527 u_long icr_hi;
528
529 crit_enter();
cb7d6921 530 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
41a01a4d
MD
531 crit_exit();
532 return(0);
533 }
cb7d6921 534 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
41a01a4d 535 icr_hi |= (CPU_TO_ID(cpu) << 24);
cb7d6921 536 lapic->icr_hi = icr_hi;
41a01a4d
MD
537
538 /* build IRC_LOW */
cb7d6921 539 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
41a01a4d
MD
540 | APIC_DEST_DESTFLD | delivery_mode | vector;
541
542 /* write APIC ICR */
cb7d6921 543 lapic->icr_lo = icr_lo;
41a01a4d
MD
544 crit_exit();
545 return(1);
546}
547
548#endif
549
984263bc
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550/*
551 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
552 *
96728c05
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553 * target is a bitmask of destination cpus. Vector is any
554 * valid system INT vector. Delivery mode may be either
555 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
984263bc 556 */
41a01a4d 557void
da23a592 558selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
984263bc 559{
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560 crit_enter();
561 while (target) {
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562 int n = BSFCPUMASK(target);
563 target &= ~CPUMASK(n);
41a01a4d 564 single_apic_ipi(n, vector, delivery_mode);
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565 }
566 crit_exit();
984263bc 567}
984263bc 568
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569/*
570 * Timer code, in development...
571 * - suggested by rgrimes@gndrsh.aac.dev.com
572 */
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573int
574get_apic_timer_frequency(void)
575{
576 return(lapic_cputimer_intr.freq);
577}
984263bc 578
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579/*
580 * Load a 'downcount time' in uSeconds.
581 */
582void
2942ed63 583set_apic_timer(int us)
984263bc 584{
2942ed63 585 u_int count;
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586
587 /*
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588 * When we reach here, lapic timer's frequency
589 * must have been calculated as well as the
590 * divisor (lapic.dcr_timer is setup during the
591 * divisor calculation).
984263bc 592 */
ef612539 593 KKASSERT(lapic_cputimer_intr.freq != 0 &&
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594 lapic_timer_divisor_idx >= 0);
595
ef612539 596 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
2942ed63 597 lapic_timer_oneshot(count);
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598}
599
600
601/*
602 * Read remaining time in timer.
603 */
604int
605read_apic_timer(void)
606{
607#if 0
608 /** XXX FIXME: we need to return the actual remaining time,
609 * for now we just return the remaining count.
610 */
611#else
cb7d6921 612 return lapic->ccr_timer;
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613#endif
614}
615
616
617/*
618 * Spin-style delay, set delay time in uS, spin till it drains.
619 */
620void
621u_sleep(int count)
622{
623 set_apic_timer(count);
624 while (read_apic_timer())
625 /* spin */ ;
626}
ad52b37b 627
11bae9b8 628int
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629lapic_unused_apic_id(int start)
630{
631 int i;
632
633 for (i = start; i < NAPICID; ++i) {
634 if (ID_TO_CPU(i) == -1)
635 return i;
636 }
637 return NAPICID;
638}
639
ad52b37b 640void
84cc808b 641lapic_map(vm_offset_t lapic_addr)
ad52b37b 642{
cb7d6921 643 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
ad52b37b 644
d557216f 645 kprintf("lapic: at %p\n", (void *)lapic_addr);
ad52b37b 646}
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647
648static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
649 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
650
651void
652lapic_config(void)
653{
654 struct lapic_enumerator *e;
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655 int error, i;
656
657 for (i = 0; i < NAPICID; ++i)
658 ID_TO_CPU(i) = -1;
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659
660 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
661 error = e->lapic_probe(e);
662 if (!error)
663 break;
664 }
665 if (e == NULL)
666 panic("can't config lapic\n");
667
668 e->lapic_enumerate(e);
669}
670
671void
672lapic_enumerator_register(struct lapic_enumerator *ne)
673{
674 struct lapic_enumerator *e;
675
676 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
677 if (e->lapic_prio < ne->lapic_prio) {
678 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
679 return;
680 }
681 }
682 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);
683}
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684
685void
686lapic_set_cpuid(int cpu_id, int apic_id)
687{
688 CPU_TO_ID(cpu_id) = apic_id;
689 ID_TO_CPU(apic_id) = cpu_id;
690}