pci: Add function to get PCIe max read request size
[dragonfly.git] / sys / bus / pci / pci.c
CommitLineData
4d28e78f
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1/*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
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5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83c1faaa
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27 *
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
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29 */
30
4d28e78f 31#include "opt_bus.h"
92683a33 32#include "opt_acpi.h"
6951547b 33#include "opt_compat_oldpci.h"
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34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/malloc.h>
38#include <sys/module.h>
4d28e78f 39#include <sys/linker.h>
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40#include <sys/fcntl.h>
41#include <sys/conf.h>
42#include <sys/kernel.h>
43#include <sys/queue.h>
638744c5 44#include <sys/sysctl.h>
4d28e78f 45#include <sys/endian.h>
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46
47#include <vm/vm.h>
48#include <vm/pmap.h>
49#include <vm/vm_extern.h>
50
51#include <sys/bus.h>
984263bc 52#include <sys/rman.h>
4d28e78f 53#include <sys/device.h>
984263bc 54
dc5a7bd2 55#include <sys/pciio.h>
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56#include <bus/pci/pcireg.h>
57#include <bus/pci/pcivar.h>
58#include <bus/pci/pci_private.h>
984263bc 59
4a5a2d63 60#include "pcib_if.h"
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61#include "pci_if.h"
62
63#ifdef __HAVE_ACPI
64#include <contrib/dev/acpica/acpi.h>
65#include "acpi_if.h"
66#else
67#define ACPI_PWR_FOR_SLEEP(x, y, z)
68#endif
69
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70extern struct dev_ops pcic_ops; /* XXX */
71
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72typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
73
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74static uint32_t pci_mapbase(unsigned mapreg);
75static const char *pci_maptype(unsigned mapreg);
76static int pci_mapsize(unsigned testval);
77static int pci_maprange(unsigned mapreg);
78static void pci_fixancient(pcicfgregs *cfg);
79
80static int pci_porten(device_t pcib, int b, int s, int f);
81static int pci_memen(device_t pcib, int b, int s, int f);
82static void pci_assign_interrupt(device_t bus, device_t dev,
83 int force_route);
84static int pci_add_map(device_t pcib, device_t bus, device_t dev,
85 int b, int s, int f, int reg,
86 struct resource_list *rl, int force, int prefetch);
87static int pci_probe(device_t dev);
88static int pci_attach(device_t dev);
11a49859 89static void pci_child_detached(device_t, device_t);
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90static void pci_load_vendor_data(void);
91static int pci_describe_parse_line(char **ptr, int *vendor,
92 int *device, char **desc);
93static char *pci_describe_device(device_t dev);
94static int pci_modevent(module_t mod, int what, void *arg);
95static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
96 pcicfgregs *cfg);
3a6dc23c 97static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
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98static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
99 int reg, uint32_t *data);
100#if 0
101static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t data);
103#endif
104static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
105static void pci_disable_msi(device_t dev);
106static void pci_enable_msi(device_t dev, uint64_t address,
107 uint16_t data);
108static void pci_enable_msix(device_t dev, u_int index,
109 uint64_t address, uint32_t data);
110static void pci_mask_msix(device_t dev, u_int index);
111static void pci_unmask_msix(device_t dev, u_int index);
112static int pci_msi_blacklisted(void);
113static void pci_resume_msi(device_t dev);
114static void pci_resume_msix(device_t dev);
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115static int pcie_slotimpl(const pcicfgregs *);
116static void pci_print_verbose_expr(const pcicfgregs *);
4d28e78f 117
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118static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
119static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
120static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
121static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
122static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
123static void pci_read_cap_subvendor(device_t, int, int,
124 pcicfgregs *);
125static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
d85e7311 126static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
3a6dc23c 127
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128static device_method_t pci_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_probe, pci_probe),
131 DEVMETHOD(device_attach, pci_attach),
132 DEVMETHOD(device_detach, bus_generic_detach),
133 DEVMETHOD(device_shutdown, bus_generic_shutdown),
134 DEVMETHOD(device_suspend, pci_suspend),
135 DEVMETHOD(device_resume, pci_resume),
136
137 /* Bus interface */
138 DEVMETHOD(bus_print_child, pci_print_child),
139 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
140 DEVMETHOD(bus_read_ivar, pci_read_ivar),
141 DEVMETHOD(bus_write_ivar, pci_write_ivar),
142 DEVMETHOD(bus_driver_added, pci_driver_added),
11a49859 143 DEVMETHOD(bus_child_detached, pci_child_detached),
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144 DEVMETHOD(bus_setup_intr, pci_setup_intr),
145 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
146
147 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
148 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
149 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
150 DEVMETHOD(bus_delete_resource, pci_delete_resource),
151 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
152 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
153 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
154 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
155 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
156 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
157
158 /* PCI interface */
159 DEVMETHOD(pci_read_config, pci_read_config_method),
160 DEVMETHOD(pci_write_config, pci_write_config_method),
161 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
162 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
163 DEVMETHOD(pci_enable_io, pci_enable_io_method),
164 DEVMETHOD(pci_disable_io, pci_disable_io_method),
165 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
166 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
167 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
168 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
169 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
170 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
171 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
172 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
173 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
174 DEVMETHOD(pci_release_msi, pci_release_msi_method),
175 DEVMETHOD(pci_msi_count, pci_msi_count_method),
176 DEVMETHOD(pci_msix_count, pci_msix_count_method),
177
178 { 0, 0 }
179};
180
181DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
4a5a2d63 182
4d28e78f 183static devclass_t pci_devclass;
aa2b9d05 184DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
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185MODULE_VERSION(pci, 1);
186
187static char *pci_vendordata;
188static size_t pci_vendordata_size;
dc5a7bd2 189
984263bc 190
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191static const struct pci_read_cap {
192 int cap;
193 pci_read_cap_t read_cap;
194} pci_read_caps[] = {
195 { PCIY_PMG, pci_read_cap_pmgt },
196 { PCIY_HT, pci_read_cap_ht },
197 { PCIY_MSI, pci_read_cap_msi },
198 { PCIY_MSIX, pci_read_cap_msix },
199 { PCIY_VPD, pci_read_cap_vpd },
200 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
201 { PCIY_PCIX, pci_read_cap_pcix },
d85e7311 202 { PCIY_EXPRESS, pci_read_cap_express },
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203 { 0, NULL } /* required last entry */
204};
205
984263bc 206struct pci_quirk {
4d28e78f 207 uint32_t devid; /* Vendor/device of the card */
984263bc 208 int type;
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209#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
210#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
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211 int arg1;
212 int arg2;
213};
214
215struct pci_quirk pci_quirks[] = {
4d28e78f 216 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
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217 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
218 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
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219 /* As does the Serverworks OSB4 (the SMBus mapping register) */
220 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
984263bc 221
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222 /*
223 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
224 * or the CMIC-SL (AKA ServerWorks GC_LE).
225 */
226 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
227 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
228
229 /*
230 * MSI doesn't work on earlier Intel chipsets including
231 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
232 */
233 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
234 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
235 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
236 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240
241 /*
242 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
243 * bridge.
244 */
245 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
246
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247 { 0 }
248};
249
250/* map register information */
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251#define PCI_MAPMEM 0x01 /* memory map */
252#define PCI_MAPMEMP 0x02 /* prefetchable memory map */
253#define PCI_MAPPORT 0x04 /* port map */
254
255struct devlist pci_devq;
256uint32_t pci_generation;
257uint32_t pci_numdevs = 0;
258static int pcie_chipset, pcix_chipset;
259
260/* sysctl vars */
261SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
262
263static int pci_enable_io_modes = 1;
264TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
265SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
266 &pci_enable_io_modes, 1,
267 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
268enable these bits correctly. We'd like to do this all the time, but there\n\
269are some peripherals that this causes problems with.");
984263bc 270
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271static int pci_do_power_nodriver = 0;
272TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
273SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
274 &pci_do_power_nodriver, 0,
275 "Place a function into D3 state when no driver attaches to it. 0 means\n\
276disable. 1 means conservatively place devices into D3 state. 2 means\n\
6699890a 277aggressively place devices into D3 state. 3 means put absolutely everything\n\
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278in D3 state.");
279
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280static int pci_do_power_resume = 1;
281TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
282SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
283 &pci_do_power_resume, 1,
284 "Transition from D3 -> D0 on resume.");
285
286static int pci_do_msi = 1;
287TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
288SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
289 "Enable support for MSI interrupts");
290
291static int pci_do_msix = 1;
292TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
293SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
294 "Enable support for MSI-X interrupts");
295
296static int pci_honor_msi_blacklist = 1;
297TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
298SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
299 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
300
301/* Find a device_t by bus/slot/function in domain 0 */
302
303device_t
304pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
305{
306
307 return (pci_find_dbsf(0, bus, slot, func));
308}
309
310/* Find a device_t by domain/bus/slot/function */
311
984263bc 312device_t
4d28e78f 313pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
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314{
315 struct pci_devinfo *dinfo;
316
317 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
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318 if ((dinfo->cfg.domain == domain) &&
319 (dinfo->cfg.bus == bus) &&
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320 (dinfo->cfg.slot == slot) &&
321 (dinfo->cfg.func == func)) {
322 return (dinfo->cfg.dev);
323 }
324 }
325
326 return (NULL);
327}
328
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329/* Find a device_t by vendor/device ID */
330
984263bc 331device_t
4d28e78f 332pci_find_device(uint16_t vendor, uint16_t device)
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333{
334 struct pci_devinfo *dinfo;
335
336 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
337 if ((dinfo->cfg.vendor == vendor) &&
338 (dinfo->cfg.device == device)) {
339 return (dinfo->cfg.dev);
340 }
341 }
342
343 return (NULL);
344}
345
346/* return base address of memory or port map */
347
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348static uint32_t
349pci_mapbase(uint32_t mapreg)
984263bc 350{
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351
352 if (PCI_BAR_MEM(mapreg))
353 return (mapreg & PCIM_BAR_MEM_BASE);
354 else
355 return (mapreg & PCIM_BAR_IO_BASE);
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356}
357
358/* return map type of memory or port map */
359
4d28e78f 360static const char *
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361pci_maptype(unsigned mapreg)
362{
984263bc 363
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364 if (PCI_BAR_IO(mapreg))
365 return ("I/O Port");
366 if (mapreg & PCIM_BAR_MEM_PREFETCH)
367 return ("Prefetchable Memory");
368 return ("Memory");
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369}
370
371/* return log2 of map size decoded for memory or port map */
372
373static int
4d28e78f 374pci_mapsize(uint32_t testval)
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375{
376 int ln2size;
377
378 testval = pci_mapbase(testval);
379 ln2size = 0;
380 if (testval != 0) {
381 while ((testval & 1) == 0)
382 {
383 ln2size++;
384 testval >>= 1;
385 }
386 }
387 return (ln2size);
388}
389
390/* return log2 of address range supported by map register */
391
392static int
393pci_maprange(unsigned mapreg)
394{
395 int ln2range = 0;
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396
397 if (PCI_BAR_IO(mapreg))
984263bc 398 ln2range = 32;
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399 else
400 switch (mapreg & PCIM_BAR_MEM_TYPE) {
401 case PCIM_BAR_MEM_32:
402 ln2range = 32;
403 break;
404 case PCIM_BAR_MEM_1MB:
405 ln2range = 20;
406 break;
407 case PCIM_BAR_MEM_64:
408 ln2range = 64;
409 break;
410 }
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411 return (ln2range);
412}
413
414/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
415
416static void
417pci_fixancient(pcicfgregs *cfg)
418{
419 if (cfg->hdrtype != 0)
420 return;
421
422 /* PCI to PCI bridges use header type 1 */
423 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
424 cfg->hdrtype = 1;
425}
426
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427/* extract header type specific config data */
428
429static void
4a5a2d63 430pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
984263bc 431{
4d28e78f 432#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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433 switch (cfg->hdrtype) {
434 case 0:
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435 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
436 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
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437 cfg->nummaps = PCI_MAXMAPS_0;
438 break;
439 case 1:
984263bc 440 cfg->nummaps = PCI_MAXMAPS_1;
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441#ifdef COMPAT_OLDPCI
442 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
443#endif
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444 break;
445 case 2:
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446 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
447 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
984263bc 448 cfg->nummaps = PCI_MAXMAPS_2;
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449#ifdef COMPAT_OLDPCI
450 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
451#endif
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452 break;
453 }
4a5a2d63 454#undef REG
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455}
456
4d28e78f 457/* read configuration header into pcicfgregs structure */
22457186 458struct pci_devinfo *
4d28e78f 459pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
984263bc 460{
4d28e78f 461#define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
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462 pcicfgregs *cfg = NULL;
463 struct pci_devinfo *devlist_entry;
464 struct devlist *devlist_head;
465
466 devlist_head = &pci_devq;
467
468 devlist_entry = NULL;
469
4d28e78f 470 if (REG(PCIR_DEVVENDOR, 4) != -1) {
efda3bd0 471 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
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472
473 cfg = &devlist_entry->cfg;
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474
475 cfg->domain = d;
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476 cfg->bus = b;
477 cfg->slot = s;
478 cfg->func = f;
479 cfg->vendor = REG(PCIR_VENDOR, 2);
480 cfg->device = REG(PCIR_DEVICE, 2);
481 cfg->cmdreg = REG(PCIR_COMMAND, 2);
482 cfg->statreg = REG(PCIR_STATUS, 2);
483 cfg->baseclass = REG(PCIR_CLASS, 1);
484 cfg->subclass = REG(PCIR_SUBCLASS, 1);
485 cfg->progif = REG(PCIR_PROGIF, 1);
486 cfg->revid = REG(PCIR_REVID, 1);
e126caf1 487 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
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488 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
489 cfg->lattimer = REG(PCIR_LATTIMER, 1);
490 cfg->intpin = REG(PCIR_INTPIN, 1);
491 cfg->intline = REG(PCIR_INTLINE, 1);
984263bc 492
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493 cfg->mingnt = REG(PCIR_MINGNT, 1);
494 cfg->maxlat = REG(PCIR_MAXLAT, 1);
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495
496 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
497 cfg->hdrtype &= ~PCIM_MFDEV;
498
499 pci_fixancient(cfg);
4a5a2d63 500 pci_hdrtypedata(pcib, b, s, f, cfg);
4d28e78f 501
3a6dc23c 502 pci_read_capabilities(pcib, cfg);
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503
504 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
505
4d28e78f 506 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
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507 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
508 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
509 devlist_entry->conf.pc_sel.pc_func = cfg->func;
510 devlist_entry->conf.pc_hdr = cfg->hdrtype;
511
512 devlist_entry->conf.pc_subvendor = cfg->subvendor;
513 devlist_entry->conf.pc_subdevice = cfg->subdevice;
514 devlist_entry->conf.pc_vendor = cfg->vendor;
515 devlist_entry->conf.pc_device = cfg->device;
516
517 devlist_entry->conf.pc_class = cfg->baseclass;
518 devlist_entry->conf.pc_subclass = cfg->subclass;
519 devlist_entry->conf.pc_progif = cfg->progif;
520 devlist_entry->conf.pc_revid = cfg->revid;
521
522 pci_numdevs++;
523 pci_generation++;
524 }
525 return (devlist_entry);
526#undef REG
527}
528
3a6dc23c
SZ
529static int
530pci_fixup_nextptr(int *nextptr0)
531{
532 int nextptr = *nextptr0;
533
534 /* "Next pointer" is only one byte */
535 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
536
537 if (nextptr & 0x3) {
538 /*
539 * PCI local bus spec 3.0:
540 *
541 * "... The bottom two bits of all pointers are reserved
542 * and must be implemented as 00b although software must
543 * mask them to allow for future uses of these bits ..."
544 */
545 if (bootverbose) {
546 kprintf("Illegal PCI extended capability "
547 "offset, fixup 0x%02x -> 0x%02x\n",
548 nextptr, nextptr & ~0x3);
549 }
550 nextptr &= ~0x3;
551 }
552 *nextptr0 = nextptr;
553
554 if (nextptr < 0x40) {
555 if (nextptr != 0) {
556 kprintf("Illegal PCI extended capability "
557 "offset 0x%02x", nextptr);
558 }
559 return 0;
560 }
561 return 1;
562}
563
984263bc 564static void
3a6dc23c 565pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
984263bc 566{
3a6dc23c
SZ
567#define REG(n, w) \
568 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
569
570 struct pcicfg_pp *pp = &cfg->pp;
571
572 if (pp->pp_cap)
573 return;
574
575 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
576 pp->pp_status = ptr + PCIR_POWER_STATUS;
577 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
578
579 if ((nextptr - ptr) > PCIR_POWER_DATA) {
580 /*
581 * XXX
582 * We should write to data_select and read back from
583 * data_scale to determine whether data register is
584 * implemented.
585 */
586#ifdef foo
587 pp->pp_data = ptr + PCIR_POWER_DATA;
588#else
589 pp->pp_data = 0;
590#endif
591 }
592
593#undef REG
594}
595
596static void
597pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
598{
599#ifdef notyet
b2b3ffcd 600#if defined(__i386__) || defined(__x86_64__)
3a6dc23c
SZ
601
602#define REG(n, w) \
603 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
604
605 struct pcicfg_ht *ht = &cfg->ht;
4d28e78f 606 uint64_t addr;
4d28e78f 607 uint32_t val;
3a6dc23c
SZ
608
609 /* Determine HT-specific capability type. */
610 val = REG(ptr + PCIR_HT_COMMAND, 2);
611
612 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
613 return;
614
615 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
616 /* Sanity check the mapping window. */
617 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
618 addr <<= 32;
619 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
620 if (addr != MSI_INTEL_ADDR_BASE) {
621 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
622 "has non-default MSI window 0x%llx\n",
623 cfg->domain, cfg->bus, cfg->slot, cfg->func,
624 (long long)addr);
625 }
626 } else {
627 addr = MSI_INTEL_ADDR_BASE;
628 }
629
630 ht->ht_msimap = ptr;
631 ht->ht_msictrl = val;
632 ht->ht_msiaddr = addr;
633
634#undef REG
635
b2b3ffcd 636#endif /* __i386__ || __x86_64__ */
3a6dc23c
SZ
637#endif /* notyet */
638}
639
640static void
641pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
642{
643#define REG(n, w) \
644 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
645
646 struct pcicfg_msi *msi = &cfg->msi;
647
648 msi->msi_location = ptr;
649 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
650 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
651
652#undef REG
653}
654
655static void
656pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
657{
658#define REG(n, w) \
659 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
660
661 struct pcicfg_msix *msix = &cfg->msix;
662 uint32_t val;
663
664 msix->msix_location = ptr;
665 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
666 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
667
668 val = REG(ptr + PCIR_MSIX_TABLE, 4);
669 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
670 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
671
672 val = REG(ptr + PCIR_MSIX_PBA, 4);
673 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
674 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
675
676#undef REG
677}
678
679static void
680pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
681{
682 cfg->vpd.vpd_reg = ptr;
683}
684
685static void
686pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
687{
688#define REG(n, w) \
689 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
690
691 /* Should always be true. */
692 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
693 uint32_t val;
694
695 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
696 cfg->subvendor = val & 0xffff;
697 cfg->subdevice = val >> 16;
698 }
699
700#undef REG
701}
702
703static void
704pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
705{
706 /*
707 * Assume we have a PCI-X chipset if we have
708 * at least one PCI-PCI bridge with a PCI-X
709 * capability. Note that some systems with
710 * PCI-express or HT chipsets might match on
711 * this check as well.
712 */
713 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
714 pcix_chipset = 1;
d85e7311
SZ
715
716 cfg->pcix.pcix_ptr = ptr;
717}
718
719static int
720pcie_slotimpl(const pcicfgregs *cfg)
721{
722 const struct pcicfg_expr *expr = &cfg->expr;
723 uint16_t port_type;
724
725 /*
726 * Only version 1 can be parsed currently
727 */
728 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
729 return 0;
730
731 /*
732 * - Slot implemented bit is meaningful iff current port is
733 * root port or down stream port.
734 * - Testing for root port or down stream port is meanningful
735 * iff PCI configure has type 1 header.
736 */
737
738 if (cfg->hdrtype != 1)
739 return 0;
740
741 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
742 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
743 return 0;
744
745 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
746 return 0;
747
748 return 1;
3a6dc23c
SZ
749}
750
751static void
d85e7311 752pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
3a6dc23c 753{
d85e7311
SZ
754#define REG(n, w) \
755 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
756
757 struct pcicfg_expr *expr = &cfg->expr;
758
3a6dc23c
SZ
759 /*
760 * Assume we have a PCI-express chipset if we have
761 * at least one PCI-express device.
762 */
763 pcie_chipset = 1;
d85e7311
SZ
764
765 expr->expr_ptr = ptr;
766 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
767
768 /*
769 * Only version 1 can be parsed currently
770 */
771 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
772 return;
773
774 /*
775 * Read slot capabilities. Slot capabilities exists iff
776 * current port's slot is implemented
777 */
778 if (pcie_slotimpl(cfg))
779 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
780
781#undef REG
3a6dc23c
SZ
782}
783
784static void
785pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
786{
787#define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
788#define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
789
790 uint32_t val;
791 int nextptr, ptrptr;
792
793 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
794 /* No capabilities */
795 return;
796 }
0c78fe3f 797
4d28e78f 798 switch (cfg->hdrtype & PCIM_HDRTYPE) {
984263bc 799 case 0:
81c29ce4
SZ
800 case 1:
801 ptrptr = PCIR_CAP_PTR;
984263bc
MD
802 break;
803 case 2:
4d28e78f 804 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
984263bc
MD
805 break;
806 default:
3a6dc23c 807 return; /* no capabilities support */
984263bc 808 }
4d28e78f 809 nextptr = REG(ptrptr, 1); /* sanity check? */
984263bc
MD
810
811 /*
812 * Read capability entries.
813 */
3a6dc23c
SZ
814 while (pci_fixup_nextptr(&nextptr)) {
815 const struct pci_read_cap *rc;
816 int ptr = nextptr;
817
4d28e78f 818 /* Find the next entry */
4d28e78f 819 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
984263bc
MD
820
821 /* Process this entry */
3a6dc23c
SZ
822 val = REG(ptr + PCICAP_ID, 1);
823 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
824 if (rc->cap == val) {
825 rc->read_cap(pcib, ptr, nextptr, cfg);
4d28e78f
SZ
826 break;
827 }
984263bc
MD
828 }
829 }
4d28e78f 830/* REG and WREG use carry through to next functions */
984263bc
MD
831}
832
4d28e78f
SZ
833/*
834 * PCI Vital Product Data
835 */
836
837#define PCI_VPD_TIMEOUT 1000000
984263bc 838
4d28e78f
SZ
839static int
840pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
984263bc 841{
4d28e78f 842 int count = PCI_VPD_TIMEOUT;
984263bc 843
4d28e78f 844 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
984263bc 845
4d28e78f 846 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
984263bc 847
4d28e78f
SZ
848 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
849 if (--count < 0)
850 return (ENXIO);
851 DELAY(1); /* limit looping */
852 }
853 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
984263bc 854
984263bc
MD
855 return (0);
856}
984263bc 857
4d28e78f
SZ
858#if 0
859static int
860pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
984263bc 861{
4d28e78f
SZ
862 int count = PCI_VPD_TIMEOUT;
863
864 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
865
866 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
867 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
868 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
869 if (--count < 0)
870 return (ENXIO);
871 DELAY(1); /* limit looping */
872 }
873
874 return (0);
875}
876#endif
877
878#undef PCI_VPD_TIMEOUT
879
880struct vpd_readstate {
881 device_t pcib;
882 pcicfgregs *cfg;
883 uint32_t val;
884 int bytesinval;
885 int off;
886 uint8_t cksum;
887};
888
889static int
890vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
891{
892 uint32_t reg;
893 uint8_t byte;
894
895 if (vrs->bytesinval == 0) {
896 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, &reg))
897 return (ENXIO);
898 vrs->val = le32toh(reg);
899 vrs->off += 4;
900 byte = vrs->val & 0xff;
901 vrs->bytesinval = 3;
902 } else {
903 vrs->val = vrs->val >> 8;
904 byte = vrs->val & 0xff;
905 vrs->bytesinval--;
906 }
907
908 vrs->cksum += byte;
909 *data = byte;
910 return (0);
911}
912
d85e7311
SZ
913int
914pcie_slot_implemented(device_t dev)
915{
916 struct pci_devinfo *dinfo = device_get_ivars(dev);
917
918 return pcie_slotimpl(&dinfo->cfg);
919}
920
4d28e78f
SZ
921void
922pcie_set_max_readrq(device_t dev, uint16_t rqsize)
923{
d85e7311
SZ
924 uint8_t expr_ptr;
925 uint16_t val;
926
927 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
928 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
929 panic("%s: invalid max read request size 0x%02x\n",
930 device_get_nameunit(dev), rqsize);
931 }
932
933 expr_ptr = pci_get_pciecap_ptr(dev);
934 if (!expr_ptr)
935 panic("%s: not PCIe device\n", device_get_nameunit(dev));
936
937 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
938 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
939 if (bootverbose)
940 device_printf(dev, "adjust device control 0x%04x", val);
941
942 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
943 val |= rqsize;
944 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
945
946 if (bootverbose)
947 kprintf(" -> 0x%04x\n", val);
948 }
4d28e78f
SZ
949}
950
441580ca
SZ
951uint16_t
952pcie_get_max_readrq(device_t dev)
953{
954 uint8_t expr_ptr;
955 uint16_t val;
956
957 expr_ptr = pci_get_pciecap_ptr(dev);
958 if (!expr_ptr)
959 panic("%s: not PCIe device\n", device_get_nameunit(dev));
960
961 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
962 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
963}
964
4d28e78f
SZ
965static void
966pci_read_vpd(device_t pcib, pcicfgregs *cfg)
967{
968 struct vpd_readstate vrs;
969 int state;
970 int name;
971 int remain;
972 int i;
973 int alloc, off; /* alloc/off for RO/W arrays */
974 int cksumvalid;
975 int dflen;
976 uint8_t byte;
977 uint8_t byte2;
978
979 /* init vpd reader */
980 vrs.bytesinval = 0;
981 vrs.off = 0;
982 vrs.pcib = pcib;
983 vrs.cfg = cfg;
984 vrs.cksum = 0;
985
986 state = 0;
987 name = remain = i = 0; /* shut up stupid gcc */
988 alloc = off = 0; /* shut up stupid gcc */
989 dflen = 0; /* shut up stupid gcc */
990 cksumvalid = -1;
991 while (state >= 0) {
992 if (vpd_nextbyte(&vrs, &byte)) {
993 state = -2;
994 break;
995 }
996#if 0
997 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
998 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
999 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1000#endif
1001 switch (state) {
1002 case 0: /* item name */
1003 if (byte & 0x80) {
1004 if (vpd_nextbyte(&vrs, &byte2)) {
1005 state = -2;
1006 break;
1007 }
1008 remain = byte2;
1009 if (vpd_nextbyte(&vrs, &byte2)) {
1010 state = -2;
1011 break;
1012 }
1013 remain |= byte2 << 8;
1014 if (remain > (0x7f*4 - vrs.off)) {
1015 state = -1;
1016 kprintf(
1017 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1018 cfg->domain, cfg->bus, cfg->slot,
1019 cfg->func, remain);
1020 }
1021 name = byte & 0x7f;
1022 } else {
1023 remain = byte & 0x7;
1024 name = (byte >> 3) & 0xf;
1025 }
1026 switch (name) {
1027 case 0x2: /* String */
1028 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1029 M_DEVBUF, M_WAITOK);
1030 i = 0;
1031 state = 1;
1032 break;
1033 case 0xf: /* End */
1034 state = -1;
1035 break;
1036 case 0x10: /* VPD-R */
1037 alloc = 8;
1038 off = 0;
1039 cfg->vpd.vpd_ros = kmalloc(alloc *
1040 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1041 M_WAITOK | M_ZERO);
1042 state = 2;
1043 break;
1044 case 0x11: /* VPD-W */
1045 alloc = 8;
1046 off = 0;
1047 cfg->vpd.vpd_w = kmalloc(alloc *
1048 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1049 M_WAITOK | M_ZERO);
1050 state = 5;
1051 break;
1052 default: /* Invalid data, abort */
1053 state = -1;
1054 break;
1055 }
1056 break;
1057
1058 case 1: /* Identifier String */
1059 cfg->vpd.vpd_ident[i++] = byte;
1060 remain--;
1061 if (remain == 0) {
1062 cfg->vpd.vpd_ident[i] = '\0';
1063 state = 0;
1064 }
1065 break;
1066
1067 case 2: /* VPD-R Keyword Header */
1068 if (off == alloc) {
a68a7edf 1069 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1070 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1071 M_DEVBUF, M_WAITOK | M_ZERO);
1072 }
1073 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1074 if (vpd_nextbyte(&vrs, &byte2)) {
1075 state = -2;
1076 break;
1077 }
1078 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1079 if (vpd_nextbyte(&vrs, &byte2)) {
1080 state = -2;
1081 break;
1082 }
1083 dflen = byte2;
1084 if (dflen == 0 &&
1085 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1086 2) == 0) {
1087 /*
1088 * if this happens, we can't trust the rest
1089 * of the VPD.
1090 */
1091 kprintf(
1092 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1093 cfg->domain, cfg->bus, cfg->slot,
1094 cfg->func, dflen);
1095 cksumvalid = 0;
1096 state = -1;
1097 break;
1098 } else if (dflen == 0) {
1099 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1100 sizeof(*cfg->vpd.vpd_ros[off].value),
1101 M_DEVBUF, M_WAITOK);
1102 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1103 } else
1104 cfg->vpd.vpd_ros[off].value = kmalloc(
1105 (dflen + 1) *
1106 sizeof(*cfg->vpd.vpd_ros[off].value),
1107 M_DEVBUF, M_WAITOK);
1108 remain -= 3;
1109 i = 0;
1110 /* keep in sync w/ state 3's transistions */
1111 if (dflen == 0 && remain == 0)
1112 state = 0;
1113 else if (dflen == 0)
1114 state = 2;
1115 else
1116 state = 3;
1117 break;
1118
1119 case 3: /* VPD-R Keyword Value */
1120 cfg->vpd.vpd_ros[off].value[i++] = byte;
1121 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1122 "RV", 2) == 0 && cksumvalid == -1) {
1123 if (vrs.cksum == 0)
1124 cksumvalid = 1;
1125 else {
1126 if (bootverbose)
1127 kprintf(
1128 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1129 cfg->domain, cfg->bus,
1130 cfg->slot, cfg->func,
1131 vrs.cksum);
1132 cksumvalid = 0;
1133 state = -1;
1134 break;
1135 }
1136 }
1137 dflen--;
1138 remain--;
1139 /* keep in sync w/ state 2's transistions */
1140 if (dflen == 0)
1141 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1142 if (dflen == 0 && remain == 0) {
1143 cfg->vpd.vpd_rocnt = off;
a68a7edf 1144 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
4d28e78f
SZ
1145 off * sizeof(*cfg->vpd.vpd_ros),
1146 M_DEVBUF, M_WAITOK | M_ZERO);
1147 state = 0;
1148 } else if (dflen == 0)
1149 state = 2;
1150 break;
1151
1152 case 4:
1153 remain--;
1154 if (remain == 0)
1155 state = 0;
1156 break;
1157
1158 case 5: /* VPD-W Keyword Header */
1159 if (off == alloc) {
a68a7edf 1160 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1161 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1162 M_DEVBUF, M_WAITOK | M_ZERO);
1163 }
1164 cfg->vpd.vpd_w[off].keyword[0] = byte;
1165 if (vpd_nextbyte(&vrs, &byte2)) {
1166 state = -2;
1167 break;
1168 }
1169 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1170 if (vpd_nextbyte(&vrs, &byte2)) {
1171 state = -2;
1172 break;
1173 }
1174 cfg->vpd.vpd_w[off].len = dflen = byte2;
1175 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1176 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1177 sizeof(*cfg->vpd.vpd_w[off].value),
1178 M_DEVBUF, M_WAITOK);
1179 remain -= 3;
1180 i = 0;
1181 /* keep in sync w/ state 6's transistions */
1182 if (dflen == 0 && remain == 0)
1183 state = 0;
1184 else if (dflen == 0)
1185 state = 5;
1186 else
1187 state = 6;
1188 break;
1189
1190 case 6: /* VPD-W Keyword Value */
1191 cfg->vpd.vpd_w[off].value[i++] = byte;
1192 dflen--;
1193 remain--;
1194 /* keep in sync w/ state 5's transistions */
1195 if (dflen == 0)
1196 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1197 if (dflen == 0 && remain == 0) {
1198 cfg->vpd.vpd_wcnt = off;
a68a7edf 1199 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
4d28e78f
SZ
1200 off * sizeof(*cfg->vpd.vpd_w),
1201 M_DEVBUF, M_WAITOK | M_ZERO);
1202 state = 0;
1203 } else if (dflen == 0)
1204 state = 5;
1205 break;
1206
1207 default:
1208 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1209 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1210 state);
1211 state = -1;
1212 break;
1213 }
1214 }
1215
1216 if (cksumvalid == 0 || state < -1) {
1217 /* read-only data bad, clean up */
1218 if (cfg->vpd.vpd_ros != NULL) {
1219 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1220 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1221 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1222 cfg->vpd.vpd_ros = NULL;
1223 }
1224 }
1225 if (state < -1) {
1226 /* I/O error, clean up */
1227 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1228 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1229 if (cfg->vpd.vpd_ident != NULL) {
1230 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1231 cfg->vpd.vpd_ident = NULL;
1232 }
1233 if (cfg->vpd.vpd_w != NULL) {
1234 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1235 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1236 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1237 cfg->vpd.vpd_w = NULL;
1238 }
1239 }
1240 cfg->vpd.vpd_cached = 1;
1241#undef REG
1242#undef WREG
1243}
1244
1245int
1246pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1247{
1248 struct pci_devinfo *dinfo = device_get_ivars(child);
1249 pcicfgregs *cfg = &dinfo->cfg;
1250
1251 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1252 pci_read_vpd(device_get_parent(dev), cfg);
1253
1254 *identptr = cfg->vpd.vpd_ident;
1255
1256 if (*identptr == NULL)
1257 return (ENXIO);
1258
1259 return (0);
1260}
1261
1262int
1263pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1264 const char **vptr)
1265{
1266 struct pci_devinfo *dinfo = device_get_ivars(child);
1267 pcicfgregs *cfg = &dinfo->cfg;
1268 int i;
1269
1270 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1271 pci_read_vpd(device_get_parent(dev), cfg);
1272
1273 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1274 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1275 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1276 *vptr = cfg->vpd.vpd_ros[i].value;
1277 }
1278
1279 if (i != cfg->vpd.vpd_rocnt)
1280 return (0);
1281
1282 *vptr = NULL;
1283 return (ENXIO);
1284}
1285
1286/*
1287 * Return the offset in configuration space of the requested extended
1288 * capability entry or 0 if the specified capability was not found.
1289 */
1290int
1291pci_find_extcap_method(device_t dev, device_t child, int capability,
1292 int *capreg)
1293{
1294 struct pci_devinfo *dinfo = device_get_ivars(child);
1295 pcicfgregs *cfg = &dinfo->cfg;
1296 u_int32_t status;
1297 u_int8_t ptr;
1298
1299 /*
1300 * Check the CAP_LIST bit of the PCI status register first.
1301 */
1302 status = pci_read_config(child, PCIR_STATUS, 2);
1303 if (!(status & PCIM_STATUS_CAPPRESENT))
1304 return (ENXIO);
1305
1306 /*
1307 * Determine the start pointer of the capabilities list.
1308 */
1309 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1310 case 0:
1311 case 1:
1312 ptr = PCIR_CAP_PTR;
1313 break;
1314 case 2:
1315 ptr = PCIR_CAP_PTR_2;
1316 break;
1317 default:
1318 /* XXX: panic? */
1319 return (ENXIO); /* no extended capabilities support */
1320 }
1321 ptr = pci_read_config(child, ptr, 1);
1322
1323 /*
1324 * Traverse the capabilities list.
1325 */
1326 while (ptr != 0) {
1327 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1328 if (capreg != NULL)
1329 *capreg = ptr;
1330 return (0);
1331 }
1332 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1333 }
1334
1335 return (ENOENT);
1336}
1337
1338/*
1339 * Support for MSI-X message interrupts.
1340 */
1341void
1342pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1343{
1344 struct pci_devinfo *dinfo = device_get_ivars(dev);
1345 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1346 uint32_t offset;
1347
1348 KASSERT(msix->msix_table_len > index, ("bogus index"));
1349 offset = msix->msix_table_offset + index * 16;
1350 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1351 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1352 bus_write_4(msix->msix_table_res, offset + 8, data);
1353
1354 /* Enable MSI -> HT mapping. */
1355 pci_ht_map_msi(dev, address);
1356}
1357
1358void
1359pci_mask_msix(device_t dev, u_int index)
1360{
1361 struct pci_devinfo *dinfo = device_get_ivars(dev);
1362 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1363 uint32_t offset, val;
1364
1365 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1366 offset = msix->msix_table_offset + index * 16 + 12;
1367 val = bus_read_4(msix->msix_table_res, offset);
1368 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1369 val |= PCIM_MSIX_VCTRL_MASK;
1370 bus_write_4(msix->msix_table_res, offset, val);
1371 }
1372}
1373
1374void
1375pci_unmask_msix(device_t dev, u_int index)
1376{
1377 struct pci_devinfo *dinfo = device_get_ivars(dev);
1378 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1379 uint32_t offset, val;
1380
1381 KASSERT(msix->msix_table_len > index, ("bogus index"));
1382 offset = msix->msix_table_offset + index * 16 + 12;
1383 val = bus_read_4(msix->msix_table_res, offset);
1384 if (val & PCIM_MSIX_VCTRL_MASK) {
1385 val &= ~PCIM_MSIX_VCTRL_MASK;
1386 bus_write_4(msix->msix_table_res, offset, val);
1387 }
1388}
1389
1390int
1391pci_pending_msix(device_t dev, u_int index)
1392{
1393 struct pci_devinfo *dinfo = device_get_ivars(dev);
1394 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1395 uint32_t offset, bit;
1396
1397 KASSERT(msix->msix_table_len > index, ("bogus index"));
1398 offset = msix->msix_pba_offset + (index / 32) * 4;
1399 bit = 1 << index % 32;
1400 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1401}
1402
1403/*
1404 * Restore MSI-X registers and table during resume. If MSI-X is
1405 * enabled then walk the virtual table to restore the actual MSI-X
1406 * table.
1407 */
1408static void
1409pci_resume_msix(device_t dev)
1410{
1411 struct pci_devinfo *dinfo = device_get_ivars(dev);
1412 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1413 struct msix_table_entry *mte;
1414 struct msix_vector *mv;
1415 int i;
1416
1417 if (msix->msix_alloc > 0) {
1418 /* First, mask all vectors. */
1419 for (i = 0; i < msix->msix_msgnum; i++)
1420 pci_mask_msix(dev, i);
1421
1422 /* Second, program any messages with at least one handler. */
1423 for (i = 0; i < msix->msix_table_len; i++) {
1424 mte = &msix->msix_table[i];
1425 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1426 continue;
1427 mv = &msix->msix_vectors[mte->mte_vector - 1];
1428 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1429 pci_unmask_msix(dev, i);
1430 }
1431 }
1432 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1433 msix->msix_ctrl, 2);
1434}
1435
1436/*
1437 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1438 * returned in *count. After this function returns, each message will be
1439 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1440 */
1441int
1442pci_alloc_msix_method(device_t dev, device_t child, int *count)
1443{
1444 struct pci_devinfo *dinfo = device_get_ivars(child);
1445 pcicfgregs *cfg = &dinfo->cfg;
1446 struct resource_list_entry *rle;
1447 int actual, error, i, irq, max;
1448
1449 /* Don't let count == 0 get us into trouble. */
1450 if (*count == 0)
1451 return (EINVAL);
1452
1453 /* If rid 0 is allocated, then fail. */
1454 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1455 if (rle != NULL && rle->res != NULL)
1456 return (ENXIO);
1457
1458 /* Already have allocated messages? */
1459 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1460 return (ENXIO);
1461
1462 /* If MSI is blacklisted for this system, fail. */
1463 if (pci_msi_blacklisted())
1464 return (ENXIO);
1465
1466 /* MSI-X capability present? */
1467 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1468 return (ENODEV);
1469
1470 /* Make sure the appropriate BARs are mapped. */
1471 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1472 cfg->msix.msix_table_bar);
1473 if (rle == NULL || rle->res == NULL ||
1474 !(rman_get_flags(rle->res) & RF_ACTIVE))
1475 return (ENXIO);
1476 cfg->msix.msix_table_res = rle->res;
1477 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1478 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1479 cfg->msix.msix_pba_bar);
1480 if (rle == NULL || rle->res == NULL ||
1481 !(rman_get_flags(rle->res) & RF_ACTIVE))
1482 return (ENXIO);
1483 }
1484 cfg->msix.msix_pba_res = rle->res;
1485
1486 if (bootverbose)
1487 device_printf(child,
1488 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1489 *count, cfg->msix.msix_msgnum);
1490 max = min(*count, cfg->msix.msix_msgnum);
1491 for (i = 0; i < max; i++) {
1492 /* Allocate a message. */
1493 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1494 if (error)
1495 break;
1496 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1497 irq, 1);
1498 }
1499 actual = i;
1500
14ae4dce
MN
1501 if (actual == 0) {
1502 if (bootverbose) {
1503 device_printf(child,
1504 "could not allocate any MSI-X vectors\n");
1505 }
1506 return (ENXIO);
1507 }
1508
4d28e78f
SZ
1509 if (bootverbose) {
1510 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1511 if (actual == 1)
1512 device_printf(child, "using IRQ %lu for MSI-X\n",
1513 rle->start);
1514 else {
1515 int run;
1516
1517 /*
1518 * Be fancy and try to print contiguous runs of
1519 * IRQ values as ranges. 'irq' is the previous IRQ.
1520 * 'run' is true if we are in a range.
1521 */
1522 device_printf(child, "using IRQs %lu", rle->start);
1523 irq = rle->start;
1524 run = 0;
1525 for (i = 1; i < actual; i++) {
1526 rle = resource_list_find(&dinfo->resources,
1527 SYS_RES_IRQ, i + 1);
1528
1529 /* Still in a run? */
1530 if (rle->start == irq + 1) {
1531 run = 1;
1532 irq++;
1533 continue;
1534 }
1535
1536 /* Finish previous range. */
1537 if (run) {
1538 kprintf("-%d", irq);
1539 run = 0;
1540 }
1541
1542 /* Start new range. */
1543 kprintf(",%lu", rle->start);
1544 irq = rle->start;
1545 }
1546
1547 /* Unfinished range? */
1548 if (run)
1549 kprintf("-%d", irq);
1550 kprintf(" for MSI-X\n");
1551 }
1552 }
1553
1554 /* Mask all vectors. */
1555 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1556 pci_mask_msix(child, i);
1557
1558 /* Allocate and initialize vector data and virtual table. */
1559 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1560 M_DEVBUF, M_WAITOK | M_ZERO);
1561 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1562 M_DEVBUF, M_WAITOK | M_ZERO);
1563 for (i = 0; i < actual; i++) {
1564 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1565 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1566 cfg->msix.msix_table[i].mte_vector = i + 1;
1567 }
1568
1569 /* Update control register to enable MSI-X. */
1570 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1571 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1572 cfg->msix.msix_ctrl, 2);
1573
1574 /* Update counts of alloc'd messages. */
1575 cfg->msix.msix_alloc = actual;
1576 cfg->msix.msix_table_len = actual;
1577 *count = actual;
1578 return (0);
1579}
1580
1581/*
1582 * By default, pci_alloc_msix() will assign the allocated IRQ
1583 * resources consecutively to the first N messages in the MSI-X table.
1584 * However, device drivers may want to use different layouts if they
1585 * either receive fewer messages than they asked for, or they wish to
1586 * populate the MSI-X table sparsely. This method allows the driver
1587 * to specify what layout it wants. It must be called after a
1588 * successful pci_alloc_msix() but before any of the associated
1589 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1590 *
1591 * The 'vectors' array contains 'count' message vectors. The array
1592 * maps directly to the MSI-X table in that index 0 in the array
1593 * specifies the vector for the first message in the MSI-X table, etc.
1594 * The vector value in each array index can either be 0 to indicate
1595 * that no vector should be assigned to a message slot, or it can be a
1596 * number from 1 to N (where N is the count returned from a
1597 * succcessful call to pci_alloc_msix()) to indicate which message
1598 * vector (IRQ) to be used for the corresponding message.
1599 *
1600 * On successful return, each message with a non-zero vector will have
1601 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1602 * 1. Additionally, if any of the IRQs allocated via the previous
1603 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1604 * will be kfreed back to the system automatically.
1605 *
1606 * For example, suppose a driver has a MSI-X table with 6 messages and
1607 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1608 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1609 * C. After the call to pci_alloc_msix(), the device will be setup to
1610 * have an MSI-X table of ABC--- (where - means no vector assigned).
1611 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1612 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1613 * be kfreed back to the system. This device will also have valid
1614 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1615 *
1616 * In any case, the SYS_RES_IRQ rid X will always map to the message
1617 * at MSI-X table index X - 1 and will only be valid if a vector is
1618 * assigned to that table entry.
1619 */
1620int
1621pci_remap_msix_method(device_t dev, device_t child, int count,
1622 const u_int *vectors)
1623{
1624 struct pci_devinfo *dinfo = device_get_ivars(child);
1625 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1626 struct resource_list_entry *rle;
1627 int i, irq, j, *used;
1628
1629 /*
1630 * Have to have at least one message in the table but the
1631 * table can't be bigger than the actual MSI-X table in the
1632 * device.
1633 */
1634 if (count == 0 || count > msix->msix_msgnum)
1635 return (EINVAL);
1636
1637 /* Sanity check the vectors. */
1638 for (i = 0; i < count; i++)
1639 if (vectors[i] > msix->msix_alloc)
1640 return (EINVAL);
1641
1642 /*
1643 * Make sure there aren't any holes in the vectors to be used.
1644 * It's a big pain to support it, and it doesn't really make
1645 * sense anyway. Also, at least one vector must be used.
1646 */
1647 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1648 M_ZERO);
1649 for (i = 0; i < count; i++)
1650 if (vectors[i] != 0)
1651 used[vectors[i] - 1] = 1;
1652 for (i = 0; i < msix->msix_alloc - 1; i++)
1653 if (used[i] == 0 && used[i + 1] == 1) {
1654 kfree(used, M_DEVBUF);
1655 return (EINVAL);
1656 }
1657 if (used[0] != 1) {
1658 kfree(used, M_DEVBUF);
1659 return (EINVAL);
1660 }
1661
1662 /* Make sure none of the resources are allocated. */
1663 for (i = 0; i < msix->msix_table_len; i++) {
1664 if (msix->msix_table[i].mte_vector == 0)
1665 continue;
1666 if (msix->msix_table[i].mte_handlers > 0)
1667 return (EBUSY);
1668 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1669 KASSERT(rle != NULL, ("missing resource"));
1670 if (rle->res != NULL)
1671 return (EBUSY);
1672 }
1673
1674 /* Free the existing resource list entries. */
1675 for (i = 0; i < msix->msix_table_len; i++) {
1676 if (msix->msix_table[i].mte_vector == 0)
1677 continue;
1678 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1679 }
1680
1681 /*
1682 * Build the new virtual table keeping track of which vectors are
1683 * used.
1684 */
1685 kfree(msix->msix_table, M_DEVBUF);
1686 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1687 M_DEVBUF, M_WAITOK | M_ZERO);
1688 for (i = 0; i < count; i++)
1689 msix->msix_table[i].mte_vector = vectors[i];
1690 msix->msix_table_len = count;
1691
1692 /* Free any unused IRQs and resize the vectors array if necessary. */
1693 j = msix->msix_alloc - 1;
1694 if (used[j] == 0) {
1695 struct msix_vector *vec;
1696
1697 while (used[j] == 0) {
1698 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1699 msix->msix_vectors[j].mv_irq);
1700 j--;
1701 }
1702 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1703 M_WAITOK);
1704 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1705 (j + 1));
1706 kfree(msix->msix_vectors, M_DEVBUF);
1707 msix->msix_vectors = vec;
1708 msix->msix_alloc = j + 1;
1709 }
1710 kfree(used, M_DEVBUF);
1711
1712 /* Map the IRQs onto the rids. */
1713 for (i = 0; i < count; i++) {
1714 if (vectors[i] == 0)
1715 continue;
1716 irq = msix->msix_vectors[vectors[i]].mv_irq;
1717 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1718 irq, 1);
1719 }
1720
1721 if (bootverbose) {
1722 device_printf(child, "Remapped MSI-X IRQs as: ");
1723 for (i = 0; i < count; i++) {
1724 if (i != 0)
1725 kprintf(", ");
1726 if (vectors[i] == 0)
1727 kprintf("---");
1728 else
1729 kprintf("%d",
1730 msix->msix_vectors[vectors[i]].mv_irq);
1731 }
1732 kprintf("\n");
1733 }
1734
1735 return (0);
1736}
1737
1738static int
1739pci_release_msix(device_t dev, device_t child)
1740{
1741 struct pci_devinfo *dinfo = device_get_ivars(child);
1742 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1743 struct resource_list_entry *rle;
1744 int i;
1745
1746 /* Do we have any messages to release? */
1747 if (msix->msix_alloc == 0)
1748 return (ENODEV);
1749
1750 /* Make sure none of the resources are allocated. */
1751 for (i = 0; i < msix->msix_table_len; i++) {
1752 if (msix->msix_table[i].mte_vector == 0)
1753 continue;
1754 if (msix->msix_table[i].mte_handlers > 0)
1755 return (EBUSY);
1756 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1757 KASSERT(rle != NULL, ("missing resource"));
1758 if (rle->res != NULL)
1759 return (EBUSY);
1760 }
1761
1762 /* Update control register to disable MSI-X. */
1763 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1764 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1765 msix->msix_ctrl, 2);
1766
1767 /* Free the resource list entries. */
1768 for (i = 0; i < msix->msix_table_len; i++) {
1769 if (msix->msix_table[i].mte_vector == 0)
1770 continue;
1771 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1772 }
1773 kfree(msix->msix_table, M_DEVBUF);
1774 msix->msix_table_len = 0;
1775
1776 /* Release the IRQs. */
1777 for (i = 0; i < msix->msix_alloc; i++)
1778 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1779 msix->msix_vectors[i].mv_irq);
1780 kfree(msix->msix_vectors, M_DEVBUF);
1781 msix->msix_alloc = 0;
1782 return (0);
1783}
1784
1785/*
1786 * Return the max supported MSI-X messages this device supports.
1787 * Basically, assuming the MD code can alloc messages, this function
1788 * should return the maximum value that pci_alloc_msix() can return.
1789 * Thus, it is subject to the tunables, etc.
1790 */
1791int
1792pci_msix_count_method(device_t dev, device_t child)
1793{
1794 struct pci_devinfo *dinfo = device_get_ivars(child);
1795 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1796
1797 if (pci_do_msix && msix->msix_location != 0)
1798 return (msix->msix_msgnum);
1799 return (0);
1800}
1801
1802/*
1803 * HyperTransport MSI mapping control
1804 */
1805void
1806pci_ht_map_msi(device_t dev, uint64_t addr)
1807{
1808 struct pci_devinfo *dinfo = device_get_ivars(dev);
1809 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1810
1811 if (!ht->ht_msimap)
1812 return;
1813
1814 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1815 ht->ht_msiaddr >> 20 == addr >> 20) {
1816 /* Enable MSI -> HT mapping. */
1817 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1818 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1819 ht->ht_msictrl, 2);
1820 }
1821
1822 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1823 /* Disable MSI -> HT mapping. */
1824 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1825 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1826 ht->ht_msictrl, 2);
1827 }
1828}
1829
1830/*
1831 * Support for MSI message signalled interrupts.
1832 */
1833void
1834pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1835{
1836 struct pci_devinfo *dinfo = device_get_ivars(dev);
1837 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1838
1839 /* Write data and address values. */
1840 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1841 address & 0xffffffff, 4);
1842 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1843 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1844 address >> 32, 4);
1845 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1846 data, 2);
1847 } else
1848 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1849 2);
1850
1851 /* Enable MSI in the control register. */
1852 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1853 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1854 2);
1855
1856 /* Enable MSI -> HT mapping. */
1857 pci_ht_map_msi(dev, address);
1858}
1859
1860void
1861pci_disable_msi(device_t dev)
1862{
1863 struct pci_devinfo *dinfo = device_get_ivars(dev);
1864 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1865
1866 /* Disable MSI -> HT mapping. */
1867 pci_ht_map_msi(dev, 0);
1868
1869 /* Disable MSI in the control register. */
1870 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1871 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1872 2);
1873}
1874
1875/*
1876 * Restore MSI registers during resume. If MSI is enabled then
1877 * restore the data and address registers in addition to the control
1878 * register.
1879 */
1880static void
1881pci_resume_msi(device_t dev)
1882{
1883 struct pci_devinfo *dinfo = device_get_ivars(dev);
1884 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1885 uint64_t address;
1886 uint16_t data;
1887
1888 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1889 address = msi->msi_addr;
1890 data = msi->msi_data;
1891 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1892 address & 0xffffffff, 4);
1893 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1894 pci_write_config(dev, msi->msi_location +
1895 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1896 pci_write_config(dev, msi->msi_location +
1897 PCIR_MSI_DATA_64BIT, data, 2);
1898 } else
1899 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1900 data, 2);
1901 }
1902 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1903 2);
1904}
1905
1906int
1907pci_remap_msi_irq(device_t dev, u_int irq)
1908{
1909 struct pci_devinfo *dinfo = device_get_ivars(dev);
1910 pcicfgregs *cfg = &dinfo->cfg;
1911 struct resource_list_entry *rle;
1912 struct msix_table_entry *mte;
1913 struct msix_vector *mv;
1914 device_t bus;
1915 uint64_t addr;
1916 uint32_t data;
1917 int error, i, j;
1918
1919 bus = device_get_parent(dev);
1920
1921 /*
1922 * Handle MSI first. We try to find this IRQ among our list
1923 * of MSI IRQs. If we find it, we request updated address and
1924 * data registers and apply the results.
1925 */
1926 if (cfg->msi.msi_alloc > 0) {
1927
1928 /* If we don't have any active handlers, nothing to do. */
1929 if (cfg->msi.msi_handlers == 0)
1930 return (0);
1931 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1932 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1933 i + 1);
1934 if (rle->start == irq) {
1935 error = PCIB_MAP_MSI(device_get_parent(bus),
1936 dev, irq, &addr, &data);
1937 if (error)
1938 return (error);
1939 pci_disable_msi(dev);
1940 dinfo->cfg.msi.msi_addr = addr;
1941 dinfo->cfg.msi.msi_data = data;
1942 pci_enable_msi(dev, addr, data);
1943 return (0);
1944 }
1945 }
1946 return (ENOENT);
1947 }
1948
1949 /*
1950 * For MSI-X, we check to see if we have this IRQ. If we do,
1951 * we request the updated mapping info. If that works, we go
1952 * through all the slots that use this IRQ and update them.
1953 */
1954 if (cfg->msix.msix_alloc > 0) {
1955 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1956 mv = &cfg->msix.msix_vectors[i];
1957 if (mv->mv_irq == irq) {
1958 error = PCIB_MAP_MSI(device_get_parent(bus),
1959 dev, irq, &addr, &data);
1960 if (error)
1961 return (error);
1962 mv->mv_address = addr;
1963 mv->mv_data = data;
1964 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1965 mte = &cfg->msix.msix_table[j];
1966 if (mte->mte_vector != i + 1)
1967 continue;
1968 if (mte->mte_handlers == 0)
1969 continue;
1970 pci_mask_msix(dev, j);
1971 pci_enable_msix(dev, j, addr, data);
1972 pci_unmask_msix(dev, j);
1973 }
1974 }
1975 }
1976 return (ENOENT);
1977 }
1978
1979 return (ENOENT);
1980}
1981
1982/*
1983 * Returns true if the specified device is blacklisted because MSI
1984 * doesn't work.
1985 */
1986int
1987pci_msi_device_blacklisted(device_t dev)
1988{
1989 struct pci_quirk *q;
1990
1991 if (!pci_honor_msi_blacklist)
1992 return (0);
1993
1994 for (q = &pci_quirks[0]; q->devid; q++) {
1995 if (q->devid == pci_get_devid(dev) &&
1996 q->type == PCI_QUIRK_DISABLE_MSI)
1997 return (1);
1998 }
1999 return (0);
2000}
2001
2002/*
2003 * Determine if MSI is blacklisted globally on this sytem. Currently,
2004 * we just check for blacklisted chipsets as represented by the
2005 * host-PCI bridge at device 0:0:0. In the future, it may become
2006 * necessary to check other system attributes, such as the kenv values
2007 * that give the motherboard manufacturer and model number.
2008 */
2009static int
2010pci_msi_blacklisted(void)
2011{
2012 device_t dev;
2013
2014 if (!pci_honor_msi_blacklist)
2015 return (0);
2016
2017 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2018 if (!(pcie_chipset || pcix_chipset))
2019 return (1);
2020
2021 dev = pci_find_bsf(0, 0, 0);
2022 if (dev != NULL)
2023 return (pci_msi_device_blacklisted(dev));
2024 return (0);
2025}
2026
2027/*
2028 * Attempt to allocate *count MSI messages. The actual number allocated is
2029 * returned in *count. After this function returns, each message will be
2030 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2031 */
2032int
2033pci_alloc_msi_method(device_t dev, device_t child, int *count)
2034{
2035 struct pci_devinfo *dinfo = device_get_ivars(child);
2036 pcicfgregs *cfg = &dinfo->cfg;
2037 struct resource_list_entry *rle;
2038 int actual, error, i, irqs[32];
2039 uint16_t ctrl;
2040
2041 /* Don't let count == 0 get us into trouble. */
2042 if (*count == 0)
2043 return (EINVAL);
2044
2045 /* If rid 0 is allocated, then fail. */
2046 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2047 if (rle != NULL && rle->res != NULL)
2048 return (ENXIO);
2049
2050 /* Already have allocated messages? */
2051 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2052 return (ENXIO);
2053
2054 /* If MSI is blacklisted for this system, fail. */
2055 if (pci_msi_blacklisted())
2056 return (ENXIO);
2057
2058 /* MSI capability present? */
2059 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2060 return (ENODEV);
2061
2062 if (bootverbose)
2063 device_printf(child,
2064 "attempting to allocate %d MSI vectors (%d supported)\n",
2065 *count, cfg->msi.msi_msgnum);
2066
2067 /* Don't ask for more than the device supports. */
2068 actual = min(*count, cfg->msi.msi_msgnum);
2069
2070 /* Don't ask for more than 32 messages. */
2071 actual = min(actual, 32);
2072
2073 /* MSI requires power of 2 number of messages. */
2074 if (!powerof2(actual))
2075 return (EINVAL);
2076
2077 for (;;) {
2078 /* Try to allocate N messages. */
2079 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2080 cfg->msi.msi_msgnum, irqs);
2081 if (error == 0)
2082 break;
2083 if (actual == 1)
2084 return (error);
2085
2086 /* Try N / 2. */
2087 actual >>= 1;
2088 }
2089
2090 /*
2091 * We now have N actual messages mapped onto SYS_RES_IRQ
2092 * resources in the irqs[] array, so add new resources
2093 * starting at rid 1.
2094 */
2095 for (i = 0; i < actual; i++)
2096 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2097 irqs[i], irqs[i], 1);
2098
2099 if (bootverbose) {
2100 if (actual == 1)
2101 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2102 else {
2103 int run;
2104
2105 /*
2106 * Be fancy and try to print contiguous runs
2107 * of IRQ values as ranges. 'run' is true if
2108 * we are in a range.
2109 */
2110 device_printf(child, "using IRQs %d", irqs[0]);
2111 run = 0;
2112 for (i = 1; i < actual; i++) {
2113
2114 /* Still in a run? */
2115 if (irqs[i] == irqs[i - 1] + 1) {
2116 run = 1;
2117 continue;
2118 }
2119
2120 /* Finish previous range. */
2121 if (run) {
2122 kprintf("-%d", irqs[i - 1]);
2123 run = 0;
2124 }
2125
2126 /* Start new range. */
2127 kprintf(",%d", irqs[i]);
2128 }
2129
2130 /* Unfinished range? */
2131 if (run)
2132 kprintf("-%d", irqs[actual - 1]);
2133 kprintf(" for MSI\n");
2134 }
2135 }
2136
2137 /* Update control register with actual count. */
2138 ctrl = cfg->msi.msi_ctrl;
2139 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2140 ctrl |= (ffs(actual) - 1) << 4;
2141 cfg->msi.msi_ctrl = ctrl;
2142 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2143
2144 /* Update counts of alloc'd messages. */
2145 cfg->msi.msi_alloc = actual;
2146 cfg->msi.msi_handlers = 0;
2147 *count = actual;
2148 return (0);
2149}
2150
2151/* Release the MSI messages associated with this device. */
2152int
2153pci_release_msi_method(device_t dev, device_t child)
2154{
2155 struct pci_devinfo *dinfo = device_get_ivars(child);
2156 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2157 struct resource_list_entry *rle;
2158 int error, i, irqs[32];
2159
2160 /* Try MSI-X first. */
2161 error = pci_release_msix(dev, child);
2162 if (error != ENODEV)
2163 return (error);
2164
2165 /* Do we have any messages to release? */
2166 if (msi->msi_alloc == 0)
2167 return (ENODEV);
2168 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2169
2170 /* Make sure none of the resources are allocated. */
2171 if (msi->msi_handlers > 0)
2172 return (EBUSY);
2173 for (i = 0; i < msi->msi_alloc; i++) {
2174 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2175 KASSERT(rle != NULL, ("missing MSI resource"));
2176 if (rle->res != NULL)
2177 return (EBUSY);
2178 irqs[i] = rle->start;
2179 }
2180
2181 /* Update control register with 0 count. */
2182 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2183 ("%s: MSI still enabled", __func__));
2184 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2185 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2186 msi->msi_ctrl, 2);
2187
2188 /* Release the messages. */
2189 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2190 for (i = 0; i < msi->msi_alloc; i++)
2191 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2192
2193 /* Update alloc count. */
2194 msi->msi_alloc = 0;
2195 msi->msi_addr = 0;
2196 msi->msi_data = 0;
2197 return (0);
2198}
2199
2200/*
2201 * Return the max supported MSI messages this device supports.
2202 * Basically, assuming the MD code can alloc messages, this function
2203 * should return the maximum value that pci_alloc_msi() can return.
2204 * Thus, it is subject to the tunables, etc.
2205 */
2206int
2207pci_msi_count_method(device_t dev, device_t child)
2208{
2209 struct pci_devinfo *dinfo = device_get_ivars(child);
2210 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2211
2212 if (pci_do_msi && msi->msi_location != 0)
2213 return (msi->msi_msgnum);
2214 return (0);
2215}
2216
2217/* kfree pcicfgregs structure and all depending data structures */
2218
2219int
2220pci_freecfg(struct pci_devinfo *dinfo)
2221{
2222 struct devlist *devlist_head;
2223 int i;
2224
2225 devlist_head = &pci_devq;
2226
2227 if (dinfo->cfg.vpd.vpd_reg) {
2228 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2229 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2230 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2231 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2232 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2233 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2234 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2235 }
2236 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2237 kfree(dinfo, M_DEVBUF);
2238
2239 /* increment the generation count */
2240 pci_generation++;
2241
2242 /* we're losing one device */
2243 pci_numdevs--;
2244 return (0);
2245}
2246
2247/*
2248 * PCI power manangement
2249 */
2250int
2251pci_set_powerstate_method(device_t dev, device_t child, int state)
2252{
2253 struct pci_devinfo *dinfo = device_get_ivars(child);
2254 pcicfgregs *cfg = &dinfo->cfg;
f4754a59
HT
2255 uint16_t status;
2256 int result, oldstate, highest, delay;
984263bc 2257
4d28e78f 2258 if (cfg->pp.pp_cap == 0)
f4754a59
HT
2259 return (EOPNOTSUPP);
2260
2261 /*
2262 * Optimize a no state change request away. While it would be OK to
2263 * write to the hardware in theory, some devices have shown odd
2264 * behavior when going from D3 -> D3.
2265 */
2266 oldstate = pci_get_powerstate(child);
2267 if (oldstate == state)
2268 return (0);
2269
2270 /*
2271 * The PCI power management specification states that after a state
2272 * transition between PCI power states, system software must
2273 * guarantee a minimal delay before the function accesses the device.
2274 * Compute the worst case delay that we need to guarantee before we
2275 * access the device. Many devices will be responsive much more
2276 * quickly than this delay, but there are some that don't respond
2277 * instantly to state changes. Transitions to/from D3 state require
2278 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2279 * is done below with DELAY rather than a sleeper function because
2280 * this function can be called from contexts where we cannot sleep.
2281 */
2282 highest = (oldstate > state) ? oldstate : state;
2283 if (highest == PCI_POWERSTATE_D3)
2284 delay = 10000;
2285 else if (highest == PCI_POWERSTATE_D2)
2286 delay = 200;
2287 else
2288 delay = 0;
4d28e78f 2289 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
f4754a59
HT
2290 & ~PCIM_PSTAT_DMASK;
2291 result = 0;
2292 switch (state) {
2293 case PCI_POWERSTATE_D0:
2294 status |= PCIM_PSTAT_D0;
2295 break;
2296 case PCI_POWERSTATE_D1:
4d28e78f 2297 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
f4754a59
HT
2298 return (EOPNOTSUPP);
2299 status |= PCIM_PSTAT_D1;
2300 break;
2301 case PCI_POWERSTATE_D2:
4d28e78f 2302 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
f4754a59
HT
2303 return (EOPNOTSUPP);
2304 status |= PCIM_PSTAT_D2;
2305 break;
2306 case PCI_POWERSTATE_D3:
2307 status |= PCIM_PSTAT_D3;
2308 break;
2309 default:
2310 return (EINVAL);
984263bc 2311 }
f4754a59
HT
2312
2313 if (bootverbose)
2314 kprintf(
4d28e78f
SZ
2315 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2316 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2317 dinfo->cfg.func, oldstate, state);
f4754a59 2318
4d28e78f 2319 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
f4754a59
HT
2320 if (delay)
2321 DELAY(delay);
2322 return (0);
984263bc
MD
2323}
2324
e126caf1 2325int
984263bc
MD
2326pci_get_powerstate_method(device_t dev, device_t child)
2327{
2328 struct pci_devinfo *dinfo = device_get_ivars(child);
2329 pcicfgregs *cfg = &dinfo->cfg;
f4754a59 2330 uint16_t status;
984263bc
MD
2331 int result;
2332
4d28e78f
SZ
2333 if (cfg->pp.pp_cap != 0) {
2334 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
984263bc
MD
2335 switch (status & PCIM_PSTAT_DMASK) {
2336 case PCIM_PSTAT_D0:
2337 result = PCI_POWERSTATE_D0;
2338 break;
2339 case PCIM_PSTAT_D1:
2340 result = PCI_POWERSTATE_D1;
2341 break;
2342 case PCIM_PSTAT_D2:
2343 result = PCI_POWERSTATE_D2;
2344 break;
2345 case PCIM_PSTAT_D3:
2346 result = PCI_POWERSTATE_D3;
2347 break;
2348 default:
2349 result = PCI_POWERSTATE_UNKNOWN;
2350 break;
2351 }
2352 } else {
2353 /* No support, device is always at D0 */
2354 result = PCI_POWERSTATE_D0;
2355 }
f4754a59 2356 return (result);
984263bc
MD
2357}
2358
2359/*
2360 * Some convenience functions for PCI device drivers.
2361 */
2362
2363static __inline void
4d28e78f 2364pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
984263bc 2365{
4d28e78f 2366 uint16_t command;
984263bc 2367
4d28e78f
SZ
2368 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2369 command |= bit;
2370 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2371}
2372
2373static __inline void
4d28e78f
SZ
2374pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2375{
2376 uint16_t command;
984263bc 2377
4d28e78f
SZ
2378 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2379 command &= ~bit;
2380 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
984263bc
MD
2381}
2382
4d28e78f
SZ
2383int
2384pci_enable_busmaster_method(device_t dev, device_t child)
2385{
2386 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2387 return (0);
2388}
984263bc 2389
4d28e78f
SZ
2390int
2391pci_disable_busmaster_method(device_t dev, device_t child)
2392{
2393 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2394 return (0);
2395}
984263bc 2396
4d28e78f
SZ
2397int
2398pci_enable_io_method(device_t dev, device_t child, int space)
ed1bd994 2399{
4d28e78f
SZ
2400 uint16_t command;
2401 uint16_t bit;
2402 char *error;
ed1bd994 2403
4d28e78f
SZ
2404 bit = 0;
2405 error = NULL;
2406
2407 switch(space) {
2408 case SYS_RES_IOPORT:
2409 bit = PCIM_CMD_PORTEN;
2410 error = "port";
ed1bd994 2411 break;
4d28e78f
SZ
2412 case SYS_RES_MEMORY:
2413 bit = PCIM_CMD_MEMEN;
2414 error = "memory";
ed1bd994
MD
2415 break;
2416 default:
4d28e78f 2417 return (EINVAL);
ed1bd994 2418 }
4d28e78f
SZ
2419 pci_set_command_bit(dev, child, bit);
2420 /* Some devices seem to need a brief stall here, what do to? */
2421 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2422 if (command & bit)
2423 return (0);
2424 device_printf(child, "failed to enable %s mapping!\n", error);
2425 return (ENXIO);
ed1bd994 2426}
984263bc 2427
4d28e78f
SZ
2428int
2429pci_disable_io_method(device_t dev, device_t child, int space)
b4c0a845 2430{
4d28e78f
SZ
2431 uint16_t command;
2432 uint16_t bit;
2433 char *error;
b4c0a845 2434
4d28e78f
SZ
2435 bit = 0;
2436 error = NULL;
b4c0a845 2437
4d28e78f
SZ
2438 switch(space) {
2439 case SYS_RES_IOPORT:
2440 bit = PCIM_CMD_PORTEN;
2441 error = "port";
b4c0a845 2442 break;
4d28e78f
SZ
2443 case SYS_RES_MEMORY:
2444 bit = PCIM_CMD_MEMEN;
2445 error = "memory";
b4c0a845
SZ
2446 break;
2447 default:
4d28e78f 2448 return (EINVAL);
b4c0a845 2449 }
4d28e78f
SZ
2450 pci_clear_command_bit(dev, child, bit);
2451 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2452 if (command & bit) {
2453 device_printf(child, "failed to disable %s mapping!\n", error);
2454 return (ENXIO);
b4c0a845 2455 }
4d28e78f 2456 return (0);
b4c0a845
SZ
2457}
2458
4d28e78f
SZ
2459/*
2460 * New style pci driver. Parent device is either a pci-host-bridge or a
2461 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2462 */
2463
22457186 2464void
984263bc
MD
2465pci_print_verbose(struct pci_devinfo *dinfo)
2466{
4d28e78f 2467
984263bc
MD
2468 if (bootverbose) {
2469 pcicfgregs *cfg = &dinfo->cfg;
2470
4d28e78f
SZ
2471 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2472 cfg->vendor, cfg->device, cfg->revid);
2473 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2474 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2475 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2476 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2477 cfg->mfdev);
2478 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2479 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
85f8e2ea 2480 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
4d28e78f
SZ
2481 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2482 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
984263bc 2483 if (cfg->intpin > 0)
4d28e78f
SZ
2484 kprintf("\tintpin=%c, irq=%d\n",
2485 cfg->intpin +'a' -1, cfg->intline);
2486 if (cfg->pp.pp_cap) {
2487 uint16_t status;
2488
2489 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2490 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2491 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2492 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2493 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2494 status & PCIM_PSTAT_DMASK);
2495 }
2496 if (cfg->msi.msi_location) {
2497 int ctrl;
2498
2499 ctrl = cfg->msi.msi_ctrl;
2500 kprintf("\tMSI supports %d message%s%s%s\n",
2501 cfg->msi.msi_msgnum,
2502 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2503 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2504 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2505 }
2506 if (cfg->msix.msix_location) {
2507 kprintf("\tMSI-X supports %d message%s ",
2508 cfg->msix.msix_msgnum,
2509 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2510 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2511 kprintf("in map 0x%x\n",
2512 cfg->msix.msix_table_bar);
2513 else
2514 kprintf("in maps 0x%x and 0x%x\n",
2515 cfg->msix.msix_table_bar,
2516 cfg->msix.msix_pba_bar);
2517 }
d85e7311 2518 pci_print_verbose_expr(cfg);
984263bc
MD
2519 }
2520}
2521
d85e7311
SZ
2522static void
2523pci_print_verbose_expr(const pcicfgregs *cfg)
2524{
2525 const struct pcicfg_expr *expr = &cfg->expr;
2526 const char *port_name;
2527 uint16_t port_type;
2528
2529 if (!bootverbose)
2530 return;
2531
2532 if (expr->expr_ptr == 0) /* No PCI Express capability */
2533 return;
2534
2535 kprintf("\tPCI Express ver.%d cap=0x%04x",
2536 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2537 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2538 goto back;
2539
2540 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2541
2542 switch (port_type) {
2543 case PCIE_END_POINT:
2544 port_name = "DEVICE";
2545 break;
2546 case PCIE_LEG_END_POINT:
2547 port_name = "LEGDEV";
2548 break;
2549 case PCIE_ROOT_PORT:
2550 port_name = "ROOT";
2551 break;
2552 case PCIE_UP_STREAM_PORT:
2553 port_name = "UPSTREAM";
2554 break;
2555 case PCIE_DOWN_STREAM_PORT:
2556 port_name = "DOWNSTRM";
2557 break;
2558 case PCIE_PCIE2PCI_BRIDGE:
2559 port_name = "PCIE2PCI";
2560 break;
2561 case PCIE_PCI2PCIE_BRIDGE:
2562 port_name = "PCI2PCIE";
2563 break;
2564 default:
2565 port_name = NULL;
2566 break;
2567 }
2568 if ((port_type == PCIE_ROOT_PORT ||
2569 port_type == PCIE_DOWN_STREAM_PORT) &&
2570 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2571 port_name = NULL;
2572 if (port_name != NULL)
2573 kprintf("[%s]", port_name);
2574
2575 if (pcie_slotimpl(cfg)) {
2576 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2577 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2578 kprintf("[HOTPLUG]");
2579 }
2580back:
2581 kprintf("\n");
2582}
2583
984263bc 2584static int
4a5a2d63 2585pci_porten(device_t pcib, int b, int s, int f)
984263bc 2586{
4a5a2d63
JS
2587 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2588 & PCIM_CMD_PORTEN) != 0;
984263bc
MD
2589}
2590
2591static int
4a5a2d63 2592pci_memen(device_t pcib, int b, int s, int f)
984263bc 2593{
4a5a2d63
JS
2594 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2595 & PCIM_CMD_MEMEN) != 0;
984263bc
MD
2596}
2597
2598/*
2599 * Add a resource based on a pci map register. Return 1 if the map
2600 * register is a 32bit map register or 2 if it is a 64bit register.
2601 */
2602static int
4d28e78f
SZ
2603pci_add_map(device_t pcib, device_t bus, device_t dev,
2604 int b, int s, int f, int reg, struct resource_list *rl, int force,
2605 int prefetch)
2606{
2607 uint32_t map;
2608 pci_addr_t base;
2609 pci_addr_t start, end, count;
2610 uint8_t ln2size;
2611 uint8_t ln2range;
2612 uint32_t testval;
2613 uint16_t cmd;
984263bc 2614 int type;
4d28e78f
SZ
2615 int barlen;
2616 struct resource *res;
984263bc 2617
4a5a2d63 2618 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
4a5a2d63
JS
2619 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2620 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2621 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
984263bc 2622
4d28e78f 2623 if (PCI_BAR_MEM(map)) {
984263bc 2624 type = SYS_RES_MEMORY;
4d28e78f
SZ
2625 if (map & PCIM_BAR_MEM_PREFETCH)
2626 prefetch = 1;
2627 } else
984263bc
MD
2628 type = SYS_RES_IOPORT;
2629 ln2size = pci_mapsize(testval);
2630 ln2range = pci_maprange(testval);
4d28e78f
SZ
2631 base = pci_mapbase(map);
2632 barlen = ln2range == 64 ? 2 : 1;
2633
2634 /*
2635 * For I/O registers, if bottom bit is set, and the next bit up
2636 * isn't clear, we know we have a BAR that doesn't conform to the
2637 * spec, so ignore it. Also, sanity check the size of the data
2638 * areas to the type of memory involved. Memory must be at least
2639 * 16 bytes in size, while I/O ranges must be at least 4.
2640 */
2641 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2642 return (barlen);
2643 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2644 (type == SYS_RES_IOPORT && ln2size < 2))
2645 return (barlen);
2646
2647 if (ln2range == 64)
984263bc 2648 /* Read the other half of a 64bit map register */
4d28e78f
SZ
2649 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2650 if (bootverbose) {
2651 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2652 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2653 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2654 kprintf(", port disabled\n");
2655 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2656 kprintf(", memory disabled\n");
2657 else
2658 kprintf(", enabled\n");
984263bc
MD
2659 }
2660
984263bc 2661 /*
4d28e78f
SZ
2662 * If base is 0, then we have problems. It is best to ignore
2663 * such entries for the moment. These will be allocated later if
2664 * the driver specifically requests them. However, some
2665 * removable busses look better when all resources are allocated,
2666 * so allow '0' to be overriden.
2667 *
2668 * Similarly treat maps whose values is the same as the test value
2669 * read back. These maps have had all f's written to them by the
2670 * BIOS in an attempt to disable the resources.
984263bc 2671 */
4d28e78f
SZ
2672 if (!force && (base == 0 || map == testval))
2673 return (barlen);
2674 if ((u_long)base != base) {
2675 device_printf(bus,
2676 "pci%d:%d:%d:%d bar %#x too many address bits",
2677 pci_get_domain(dev), b, s, f, reg);
2678 return (barlen);
984263bc 2679 }
984263bc 2680
4d28e78f
SZ
2681 /*
2682 * This code theoretically does the right thing, but has
2683 * undesirable side effects in some cases where peripherals
2684 * respond oddly to having these bits enabled. Let the user
2685 * be able to turn them off (since pci_enable_io_modes is 1 by
2686 * default).
2687 */
2688 if (pci_enable_io_modes) {
2689 /* Turn on resources that have been left off by a lazy BIOS */
2690 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2691 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2692 cmd |= PCIM_CMD_PORTEN;
2693 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2694 }
2695 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2696 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2697 cmd |= PCIM_CMD_MEMEN;
2698 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2699 }
2700 } else {
2701 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2702 return (barlen);
2703 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2704 return (barlen);
2705 }
984263bc 2706
4d28e78f
SZ
2707 count = 1 << ln2size;
2708 if (base == 0 || base == pci_mapbase(testval)) {
2709 start = 0; /* Let the parent decide. */
2710 end = ~0ULL;
2711 } else {
2712 start = base;
2713 end = base + (1 << ln2size) - 1;
984263bc 2714 }
4d28e78f 2715 resource_list_add(rl, type, reg, start, end, count);
984263bc 2716
4d28e78f
SZ
2717 /*
2718 * Try to allocate the resource for this BAR from our parent
2719 * so that this resource range is already reserved. The
2720 * driver for this device will later inherit this resource in
2721 * pci_alloc_resource().
2722 */
2723 res = resource_list_alloc(rl, bus, dev, type, &reg, start, end, count,
2724 prefetch ? RF_PREFETCHABLE : 0);
2725 if (res == NULL) {
2726 /*
d0c4beb1
SZ
2727 * If the allocation fails, delete the resource list
2728 * entry to force pci_alloc_resource() to allocate
2729 * resources from the parent.
4d28e78f
SZ
2730 */
2731 resource_list_delete(rl, type, reg);
d0c4beb1
SZ
2732#ifdef PCI_BAR_CLEAR
2733 /* Clear the BAR */
4d28e78f 2734 start = 0;
d0c4beb1
SZ
2735#else /* !PCI_BAR_CLEAR */
2736 /*
2737 * Don't clear BAR here. Some BIOS lists HPET as a
2738 * PCI function, clearing the BAR causes HPET timer
2739 * stop ticking.
2740 */
2741 if (bootverbose) {
2742 kprintf("pci:%d:%d:%d: resource reservation failed "
bfc09ba0
MD
2743 "%#jx - %#jx\n", b, s, f,
2744 (intmax_t)start, (intmax_t)end);
d0c4beb1
SZ
2745 }
2746 return (barlen);
2747#endif /* PCI_BAR_CLEAR */
2748 } else {
4d28e78f 2749 start = rman_get_start(res);
d0c4beb1 2750 }
4d28e78f
SZ
2751 pci_write_config(dev, reg, start, 4);
2752 if (ln2range == 64)
2753 pci_write_config(dev, reg + 4, start >> 32, 4);
2754 return (barlen);
984263bc
MD
2755}
2756
201eb0a7 2757/*
4d28e78f 2758 * For ATA devices we need to decide early what addressing mode to use.
201eb0a7
TS
2759 * Legacy demands that the primary and secondary ATA ports sits on the
2760 * same addresses that old ISA hardware did. This dictates that we use
4d28e78f 2761 * those addresses and ignore the BAR's if we cannot set PCI native
201eb0a7
TS
2762 * addressing mode.
2763 */
2764static void
4d28e78f
SZ
2765pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2766 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
201eb0a7
TS
2767{
2768 int rid, type, progif;
2769#if 0
2770 /* if this device supports PCI native addressing use it */
2771 progif = pci_read_config(dev, PCIR_PROGIF, 1);
4d28e78f 2772 if ((progif & 0x8a) == 0x8a) {
201eb0a7
TS
2773 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2774 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
85f8e2ea 2775 kprintf("Trying ATA native PCI addressing mode\n");
201eb0a7
TS
2776 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2777 }
2778 }
2779#endif
201eb0a7
TS
2780 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2781 type = SYS_RES_IOPORT;
2782 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
4d28e78f
SZ
2783 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2784 prefetchmask & (1 << 0));
2785 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2786 prefetchmask & (1 << 1));
201eb0a7
TS
2787 } else {
2788 rid = PCIR_BAR(0);
2789 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2790 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
4d28e78f 2791 0);
201eb0a7
TS
2792 rid = PCIR_BAR(1);
2793 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2794 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
4d28e78f 2795 0);
201eb0a7
TS
2796 }
2797 if (progif & PCIP_STORAGE_IDE_MODESEC) {
4d28e78f
SZ
2798 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2799 prefetchmask & (1 << 2));
2800 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2801 prefetchmask & (1 << 3));
201eb0a7
TS
2802 } else {
2803 rid = PCIR_BAR(2);
2804 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2805 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
4d28e78f 2806 0);
201eb0a7
TS
2807 rid = PCIR_BAR(3);
2808 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2809 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
4d28e78f 2810 0);
201eb0a7 2811 }
4d28e78f
SZ
2812 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2813 prefetchmask & (1 << 4));
2814 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2815 prefetchmask & (1 << 5));
201eb0a7 2816}
201eb0a7 2817
984263bc 2818static void
4d28e78f
SZ
2819pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2820{
2821 struct pci_devinfo *dinfo = device_get_ivars(dev);
2822 pcicfgregs *cfg = &dinfo->cfg;
2823 char tunable_name[64];
2824 int irq;
2825
2826 /* Has to have an intpin to have an interrupt. */
2827 if (cfg->intpin == 0)
2828 return;
2829
2830 /* Let the user override the IRQ with a tunable. */
2831 irq = PCI_INVALID_IRQ;
2832 ksnprintf(tunable_name, sizeof(tunable_name),
2833 "hw.pci%d.%d.%d.INT%c.irq",
2834 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2835 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2836 irq = PCI_INVALID_IRQ;
2837
2838 /*
2839 * If we didn't get an IRQ via the tunable, then we either use the
2840 * IRQ value in the intline register or we ask the bus to route an
2841 * interrupt for us. If force_route is true, then we only use the
2842 * value in the intline register if the bus was unable to assign an
2843 * IRQ.
2844 */
2845 if (!PCI_INTERRUPT_VALID(irq)) {
2846 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2847 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2848 if (!PCI_INTERRUPT_VALID(irq))
2849 irq = cfg->intline;
2850 }
2851
2852 /* If after all that we don't have an IRQ, just bail. */
2853 if (!PCI_INTERRUPT_VALID(irq))
2854 return;
2855
2856 /* Update the config register if it changed. */
2857 if (irq != cfg->intline) {
2858 cfg->intline = irq;
2859 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2860 }
2861
2862 /* Add this IRQ as rid 0 interrupt resource. */
2863 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2864}
2865
2866void
2867pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
984263bc
MD
2868{
2869 struct pci_devinfo *dinfo = device_get_ivars(dev);
4a5a2d63 2870 pcicfgregs *cfg = &dinfo->cfg;
984263bc
MD
2871 struct resource_list *rl = &dinfo->resources;
2872 struct pci_quirk *q;
e126caf1 2873 int b, i, f, s;
984263bc 2874
e126caf1
MD
2875 b = cfg->bus;
2876 s = cfg->slot;
2877 f = cfg->func;
4d28e78f
SZ
2878
2879 /* ATA devices needs special map treatment */
201eb0a7
TS
2880 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2881 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
d3d1ea7a
MD
2882 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2883 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2884 !pci_read_config(dev, PCIR_BAR(2), 4))) )
4d28e78f 2885 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
201eb0a7 2886 else
4d28e78f
SZ
2887 for (i = 0; i < cfg->nummaps;)
2888 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2889 rl, force, prefetchmask & (1 << i));
984263bc 2890
4d28e78f
SZ
2891 /*
2892 * Add additional, quirked resources.
2893 */
984263bc
MD
2894 for (q = &pci_quirks[0]; q->devid; q++) {
2895 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2896 && q->type == PCI_QUIRK_MAP_REG)
4d28e78f
SZ
2897 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2898 force, 0);
984263bc
MD
2899 }
2900
4d28e78f 2901 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4d28e78f
SZ
2902 /*
2903 * Try to re-route interrupts. Sometimes the BIOS or
2904 * firmware may leave bogus values in these registers.
2905 * If the re-route fails, then just stick with what we
2906 * have.
2907 */
2908 pci_assign_interrupt(bus, dev, 1);
4d28e78f 2909 }
984263bc
MD
2910}
2911
e126caf1 2912void
4d28e78f 2913pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
984263bc 2914{
4d28e78f 2915#define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
4a5a2d63 2916 device_t pcib = device_get_parent(dev);
e126caf1 2917 struct pci_devinfo *dinfo;
4a5a2d63 2918 int maxslots;
e126caf1
MD
2919 int s, f, pcifunchigh;
2920 uint8_t hdrtype;
2921
4d28e78f
SZ
2922 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2923 ("dinfo_size too small"));
4a5a2d63 2924 maxslots = PCIB_MAXSLOTS(pcib);
57e943f7 2925 for (s = 0; s <= maxslots; s++) {
e126caf1
MD
2926 pcifunchigh = 0;
2927 f = 0;
4d28e78f 2928 DELAY(1);
e126caf1
MD
2929 hdrtype = REG(PCIR_HDRTYPE, 1);
2930 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2931 continue;
2932 if (hdrtype & PCIM_MFDEV)
2933 pcifunchigh = PCI_FUNCMAX;
5e658043 2934 for (f = 0; f <= pcifunchigh; f++) {
4d28e78f
SZ
2935 dinfo = pci_read_device(pcib, domain, busno, s, f,
2936 dinfo_size);
984263bc 2937 if (dinfo != NULL) {
e126caf1 2938 pci_add_child(dev, dinfo);
984263bc
MD
2939 }
2940 }
2941 }
e126caf1
MD
2942#undef REG
2943}
2944
2945void
2946pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2947{
2948 device_t pcib;
2949
2950 pcib = device_get_parent(bus);
2951 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2952 device_set_ivars(dinfo->cfg.dev, dinfo);
4d28e78f 2953 resource_list_init(&dinfo->resources);
638744c5
HT
2954 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2955 pci_cfg_restore(dinfo->cfg.dev, dinfo);
e126caf1 2956 pci_print_verbose(dinfo);
4d28e78f 2957 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
984263bc
MD
2958}
2959
2960static int
4a5a2d63 2961pci_probe(device_t dev)
984263bc 2962{
984263bc 2963 device_set_desc(dev, "PCI bus");
4a5a2d63 2964
4d28e78f
SZ
2965 /* Allow other subclasses to override this driver. */
2966 return (-1000);
984263bc
MD
2967}
2968
e126caf1
MD
2969static int
2970pci_attach(device_t dev)
2971{
4d28e78f
SZ
2972 int busno, domain;
2973
2974 /*
2975 * Since there can be multiple independantly numbered PCI
2976 * busses on systems with multiple PCI domains, we can't use
2977 * the unit number to decide which bus we are probing. We ask
2978 * the parent pcib what our domain and bus numbers are.
2979 */
2980 domain = pcib_get_domain(dev);
2981 busno = pcib_get_bus(dev);
2982 if (bootverbose)
2983 device_printf(dev, "domain=%d, physical bus=%d\n",
2984 domain, busno);
e4c9c0c8 2985
4d28e78f 2986 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
e126caf1 2987
4d28e78f
SZ
2988 return (bus_generic_attach(dev));
2989}
2990
2991int
2992pci_suspend(device_t dev)
2993{
2994 int dstate, error, i, numdevs;
2995 device_t acpi_dev, child, *devlist;
2996 struct pci_devinfo *dinfo;
2997
2998 /*
2999 * Save the PCI configuration space for each child and set the
3000 * device in the appropriate power state for this sleep state.
3001 */
3002 acpi_dev = NULL;
3003 if (pci_do_power_resume)
3004 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3005 device_get_children(dev, &devlist, &numdevs);
3006 for (i = 0; i < numdevs; i++) {
3007 child = devlist[i];
3008 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3009 pci_cfg_save(child, dinfo, 0);
3010 }
e126caf1 3011
4d28e78f
SZ
3012 /* Suspend devices before potentially powering them down. */
3013 error = bus_generic_suspend(dev);
3014 if (error) {
3015 kfree(devlist, M_TEMP);
3016 return (error);
3017 }
e126caf1 3018
4d28e78f
SZ
3019 /*
3020 * Always set the device to D3. If ACPI suggests a different
3021 * power state, use it instead. If ACPI is not present, the
3022 * firmware is responsible for managing device power. Skip
3023 * children who aren't attached since they are powered down
3024 * separately. Only manage type 0 devices for now.
3025 */
3026 for (i = 0; acpi_dev && i < numdevs; i++) {
3027 child = devlist[i];
3028 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3029 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3030 dstate = PCI_POWERSTATE_D3;
3031 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3032 pci_set_powerstate(child, dstate);
3033 }
3034 }
3035 kfree(devlist, M_TEMP);
3036 return (0);
e126caf1
MD
3037}
3038
4d28e78f
SZ
3039int
3040pci_resume(device_t dev)
984263bc 3041{
4d28e78f
SZ
3042 int i, numdevs;
3043 device_t acpi_dev, child, *devlist;
3044 struct pci_devinfo *dinfo;
3045
3046 /*
3047 * Set each child to D0 and restore its PCI configuration space.
3048 */
3049 acpi_dev = NULL;
3050 if (pci_do_power_resume)
3051 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3052 device_get_children(dev, &devlist, &numdevs);
3053 for (i = 0; i < numdevs; i++) {
3054 /*
3055 * Notify ACPI we're going to D0 but ignore the result. If
3056 * ACPI is not present, the firmware is responsible for
3057 * managing device power. Only manage type 0 devices for now.
3058 */
3059 child = devlist[i];
3060 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3061 if (acpi_dev && device_is_attached(child) &&
3062 dinfo->cfg.hdrtype == 0) {
3063 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3064 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3065 }
3066
3067 /* Now the device is powered up, restore its config space. */
3068 pci_cfg_restore(child, dinfo);
3069 }
3070 kfree(devlist, M_TEMP);
3071 return (bus_generic_resume(dev));
3072}
3073
3074static void
3075pci_load_vendor_data(void)
3076{
3077 caddr_t vendordata, info;
3078
3079 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3080 info = preload_search_info(vendordata, MODINFO_ADDR);
3081 pci_vendordata = *(char **)info;
3082 info = preload_search_info(vendordata, MODINFO_SIZE);
3083 pci_vendordata_size = *(size_t *)info;
3084 /* terminate the database */
3085 pci_vendordata[pci_vendordata_size] = '\n';
3086 }
3087}
3088
3089void
3090pci_driver_added(device_t dev, driver_t *driver)
3091{
3092 int numdevs;
3093 device_t *devlist;
3094 device_t child;
3095 struct pci_devinfo *dinfo;
3096 int i;
3097
3098 if (bootverbose)
3099 device_printf(dev, "driver added\n");
3100 DEVICE_IDENTIFY(driver, dev);
3101 device_get_children(dev, &devlist, &numdevs);
3102 for (i = 0; i < numdevs; i++) {
3103 child = devlist[i];
3104 if (device_get_state(child) != DS_NOTPRESENT)
3105 continue;
3106 dinfo = device_get_ivars(child);
3107 pci_print_verbose(dinfo);
3108 if (bootverbose)
3109 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3110 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3111 dinfo->cfg.func);
3112 pci_cfg_restore(child, dinfo);
3113 if (device_probe_and_attach(child) != 0)
3114 pci_cfg_save(child, dinfo, 1);
3115 }
3116 kfree(devlist, M_TEMP);
3117}
3118
11a49859
SZ
3119static void
3120pci_child_detached(device_t parent __unused, device_t child)
3121{
3122 /* Turn child's power off */
3123 pci_cfg_save(child, device_get_ivars(child), 1);
3124}
3125
4d28e78f
SZ
3126int
3127pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3128 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3129{
3130#ifdef MSI
3131 struct pci_devinfo *dinfo;
3132 struct msix_table_entry *mte;
3133 struct msix_vector *mv;
3134 uint64_t addr;
3135 uint32_t data;
35b72619 3136 int rid;
4d28e78f 3137#endif
35b72619 3138 int error;
4d28e78f
SZ
3139 void *cookie;
3140 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3141 arg, &cookie, serializer);
3142 if (error)
3143 return (error);
3144
3145 /* If this is not a direct child, just bail out. */
3146 if (device_get_parent(child) != dev) {
3147 *cookiep = cookie;
3148 return(0);
3149 }
3150
3151 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3152#ifdef MSI
3153 rid = rman_get_rid(irq);
3154 if (rid == 0) {
3155 /* Make sure that INTx is enabled */
3156 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3157 } else {
3158 /*
3159 * Check to see if the interrupt is MSI or MSI-X.
3160 * Ask our parent to map the MSI and give
3161 * us the address and data register values.
3162 * If we fail for some reason, teardown the
3163 * interrupt handler.
3164 */
3165 dinfo = device_get_ivars(child);
3166 if (dinfo->cfg.msi.msi_alloc > 0) {
3167 if (dinfo->cfg.msi.msi_addr == 0) {
3168 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3169 ("MSI has handlers, but vectors not mapped"));
3170 error = PCIB_MAP_MSI(device_get_parent(dev),
3171 child, rman_get_start(irq), &addr, &data);
3172 if (error)
3173 goto bad;
3174 dinfo->cfg.msi.msi_addr = addr;
3175 dinfo->cfg.msi.msi_data = data;
3176 pci_enable_msi(child, addr, data);
984263bc 3177 }
4d28e78f
SZ
3178 dinfo->cfg.msi.msi_handlers++;
3179 } else {
3180 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3181 ("No MSI or MSI-X interrupts allocated"));
3182 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3183 ("MSI-X index too high"));
3184 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3185 KASSERT(mte->mte_vector != 0, ("no message vector"));
3186 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3187 KASSERT(mv->mv_irq == rman_get_start(irq),
3188 ("IRQ mismatch"));
3189 if (mv->mv_address == 0) {
3190 KASSERT(mte->mte_handlers == 0,
3191 ("MSI-X table entry has handlers, but vector not mapped"));
3192 error = PCIB_MAP_MSI(device_get_parent(dev),
3193 child, rman_get_start(irq), &addr, &data);
3194 if (error)
3195 goto bad;
3196 mv->mv_address = addr;
3197 mv->mv_data = data;
3198 }
3199 if (mte->mte_handlers == 0) {
3200 pci_enable_msix(child, rid - 1, mv->mv_address,
3201 mv->mv_data);
3202 pci_unmask_msix(child, rid - 1);
3203 }
3204 mte->mte_handlers++;
3205 }
3206
3207 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3208 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3209 bad:
3210 if (error) {
3211 (void)bus_generic_teardown_intr(dev, child, irq,
3212 cookie);
3213 return (error);
3214 }
3215 }
3216#endif
3217 *cookiep = cookie;
3218 return (0);
3219}
3220
3221int
3222pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3223 void *cookie)
3224{
3225#ifdef MSI
3226 struct msix_table_entry *mte;
3227 struct resource_list_entry *rle;
3228 struct pci_devinfo *dinfo;
35b72619 3229 int rid;
4d28e78f 3230#endif
35b72619 3231 int error;
4d28e78f
SZ
3232
3233 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3234 return (EINVAL);
3235
3236 /* If this isn't a direct child, just bail out */
3237 if (device_get_parent(child) != dev)
3238 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3239
3240 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3241#ifdef MSI
3242 rid = rman_get_rid(irq);
3243 if (rid == 0) {
3244 /* Mask INTx */
3245 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3246 } else {
3247 /*
3248 * Check to see if the interrupt is MSI or MSI-X. If so,
3249 * decrement the appropriate handlers count and mask the
3250 * MSI-X message, or disable MSI messages if the count
3251 * drops to 0.
3252 */
3253 dinfo = device_get_ivars(child);
3254 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3255 if (rle->res != irq)
3256 return (EINVAL);
3257 if (dinfo->cfg.msi.msi_alloc > 0) {
3258 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3259 ("MSI-X index too high"));
3260 if (dinfo->cfg.msi.msi_handlers == 0)
3261 return (EINVAL);
3262 dinfo->cfg.msi.msi_handlers--;
3263 if (dinfo->cfg.msi.msi_handlers == 0)
3264 pci_disable_msi(child);
3265 } else {
3266 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3267 ("No MSI or MSI-X interrupts allocated"));
3268 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3269 ("MSI-X index too high"));
3270 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3271 if (mte->mte_handlers == 0)
3272 return (EINVAL);
3273 mte->mte_handlers--;
3274 if (mte->mte_handlers == 0)
3275 pci_mask_msix(child, rid - 1);
984263bc
MD
3276 }
3277 }
4d28e78f
SZ
3278 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3279 if (rid > 0)
3280 KASSERT(error == 0,
3281 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3282#endif
3283 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3284 return (error);
984263bc
MD
3285}
3286
e126caf1 3287int
984263bc
MD
3288pci_print_child(device_t dev, device_t child)
3289{
3290 struct pci_devinfo *dinfo;
3291 struct resource_list *rl;
984263bc
MD
3292 int retval = 0;
3293
3294 dinfo = device_get_ivars(child);
984263bc
MD
3295 rl = &dinfo->resources;
3296
3297 retval += bus_print_child_header(dev, child);
3298
4d28e78f
SZ
3299 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3300 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3301 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
984263bc 3302 if (device_get_flags(dev))
85f8e2ea 3303 retval += kprintf(" flags %#x", device_get_flags(dev));
984263bc 3304
85f8e2ea 3305 retval += kprintf(" at device %d.%d", pci_get_slot(child),
4d28e78f 3306 pci_get_function(child));
984263bc
MD
3307
3308 retval += bus_print_child_footer(dev, child);
3309
3310 return (retval);
3311}
3312
4d28e78f
SZ
3313static struct
3314{
3315 int class;
3316 int subclass;
3317 char *desc;
3318} pci_nomatch_tab[] = {
3319 {PCIC_OLD, -1, "old"},
3320 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3321 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3322 {PCIC_STORAGE, -1, "mass storage"},
3323 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3324 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3325 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3326 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3327 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3328 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3329 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3330 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3331 {PCIC_NETWORK, -1, "network"},
3332 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3333 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3334 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3335 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3336 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3337 {PCIC_DISPLAY, -1, "display"},
3338 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3339 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3340 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3341 {PCIC_MULTIMEDIA, -1, "multimedia"},
3342 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3343 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3344 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3345 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3346 {PCIC_MEMORY, -1, "memory"},
3347 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3348 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3349 {PCIC_BRIDGE, -1, "bridge"},
3350 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3351 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3352 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3353 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3354 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3355 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3356 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3357 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3358 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3359 {PCIC_SIMPLECOMM, -1, "simple comms"},
3360 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3361 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3362 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3363 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3364 {PCIC_BASEPERIPH, -1, "base peripheral"},
3365 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3366 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3367 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3368 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3369 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3370 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3371 {PCIC_INPUTDEV, -1, "input device"},
3372 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3373 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3374 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3375 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3376 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3377 {PCIC_DOCKING, -1, "docking station"},
3378 {PCIC_PROCESSOR, -1, "processor"},
3379 {PCIC_SERIALBUS, -1, "serial bus"},
3380 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3381 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3382 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3383 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3384 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3385 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3386 {PCIC_WIRELESS, -1, "wireless controller"},
3387 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3388 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3389 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3390 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3391 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3392 {PCIC_SATCOM, -1, "satellite communication"},
3393 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3394 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3395 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3396 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3397 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3398 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3399 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3400 {PCIC_DASP, -1, "dasp"},
3401 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3402 {0, 0, NULL}
3403};
3404
e126caf1 3405void
984263bc
MD
3406pci_probe_nomatch(device_t dev, device_t child)
3407{
4d28e78f
SZ
3408 int i;
3409 char *cp, *scp, *device;
984263bc 3410
4d28e78f
SZ
3411 /*
3412 * Look for a listing for this device in a loaded device database.
3413 */
3414 if ((device = pci_describe_device(child)) != NULL) {
3415 device_printf(dev, "<%s>", device);
3416 kfree(device, M_DEVBUF);
3417 } else {
3418 /*
3419 * Scan the class/subclass descriptions for a general
3420 * description.
3421 */
3422 cp = "unknown";
3423 scp = NULL;
3424 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3425 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3426 if (pci_nomatch_tab[i].subclass == -1) {
3427 cp = pci_nomatch_tab[i].desc;
3428 } else if (pci_nomatch_tab[i].subclass ==
3429 pci_get_subclass(child)) {
3430 scp = pci_nomatch_tab[i].desc;
3431 }
3432 }
3433 }
3434 device_printf(dev, "<%s%s%s>",
3435 cp ? cp : "",
3436 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3437 scp ? scp : "");
3438 }
6a45dbfa
SZ
3439 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3440 pci_get_vendor(child), pci_get_device(child),
3441 pci_get_slot(child), pci_get_function(child));
3442 if (pci_get_intpin(child) > 0) {
3443 int irq;
3444
3445 irq = pci_get_irq(child);
3446 if (PCI_INTERRUPT_VALID(irq))
3447 kprintf(" irq %d", irq);
3448 }
3449 kprintf("\n");
3450
638744c5 3451 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
984263bc
MD
3452}
3453
4d28e78f
SZ
3454/*
3455 * Parse the PCI device database, if loaded, and return a pointer to a
3456 * description of the device.
3457 *
3458 * The database is flat text formatted as follows:
3459 *
3460 * Any line not in a valid format is ignored.
3461 * Lines are terminated with newline '\n' characters.
3462 *
3463 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3464 * the vendor name.
3465 *
3466 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3467 * - devices cannot be listed without a corresponding VENDOR line.
3468 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3469 * another TAB, then the device name.
3470 */
3471
3472/*
3473 * Assuming (ptr) points to the beginning of a line in the database,
3474 * return the vendor or device and description of the next entry.
3475 * The value of (vendor) or (device) inappropriate for the entry type
3476 * is set to -1. Returns nonzero at the end of the database.
3477 *
3478 * Note that this is slightly unrobust in the face of corrupt data;
3479 * we attempt to safeguard against this by spamming the end of the
3480 * database with a newline when we initialise.
3481 */
3482static int
3483pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3484{
3485 char *cp = *ptr;
3486 int left;
3487
3488 *device = -1;
3489 *vendor = -1;
3490 **desc = '\0';
3491 for (;;) {
3492 left = pci_vendordata_size - (cp - pci_vendordata);
3493 if (left <= 0) {
3494 *ptr = cp;
3495 return(1);
3496 }
3497
3498 /* vendor entry? */
3499 if (*cp != '\t' &&
3500 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3501 break;
3502 /* device entry? */
3503 if (*cp == '\t' &&
3504 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3505 break;
3506
3507 /* skip to next line */
3508 while (*cp != '\n' && left > 0) {
3509 cp++;
3510 left--;
3511 }
3512 if (*cp == '\n') {
3513 cp++;
3514 left--;
3515 }
3516 }
3517 /* skip to next line */
3518 while (*cp != '\n' && left > 0) {
3519 cp++;
3520 left--;
3521 }
3522 if (*cp == '\n' && left > 0)
3523 cp++;
3524 *ptr = cp;
3525 return(0);
3526}
3527
3528static char *
3529pci_describe_device(device_t dev)
3530{
3531 int vendor, device;
3532 char *desc, *vp, *dp, *line;
3533
3534 desc = vp = dp = NULL;
3535
3536 /*
3537 * If we have no vendor data, we can't do anything.
3538 */
3539 if (pci_vendordata == NULL)
3540 goto out;
3541
3542 /*
3543 * Scan the vendor data looking for this device
3544 */
3545 line = pci_vendordata;
3546 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3547 goto out;
3548 for (;;) {
3549 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3550 goto out;
3551 if (vendor == pci_get_vendor(dev))
3552 break;
3553 }
3554 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3555 goto out;
3556 for (;;) {
3557 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3558 *dp = 0;
3559 break;
3560 }
3561 if (vendor != -1) {
3562 *dp = 0;
3563 break;
3564 }
3565 if (device == pci_get_device(dev))
3566 break;
3567 }
3568 if (dp[0] == '\0')
3569 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3570 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3571 NULL)
3572 ksprintf(desc, "%s, %s", vp, dp);
3573 out:
3574 if (vp != NULL)
3575 kfree(vp, M_DEVBUF);
3576 if (dp != NULL)
3577 kfree(dp, M_DEVBUF);
3578 return(desc);
3579}
3580
22457186 3581int
4a5a2d63 3582pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
984263bc
MD
3583{
3584 struct pci_devinfo *dinfo;
3585 pcicfgregs *cfg;
3586
3587 dinfo = device_get_ivars(child);
3588 cfg = &dinfo->cfg;
3589
3590 switch (which) {
4d28e78f
SZ
3591 case PCI_IVAR_ETHADDR:
3592 /*
3593 * The generic accessor doesn't deal with failure, so
3594 * we set the return value, then return an error.
3595 */
3596 *((uint8_t **) result) = NULL;
3597 return (EINVAL);
984263bc
MD
3598 case PCI_IVAR_SUBVENDOR:
3599 *result = cfg->subvendor;
3600 break;
3601 case PCI_IVAR_SUBDEVICE:
3602 *result = cfg->subdevice;
3603 break;
3604 case PCI_IVAR_VENDOR:
3605 *result = cfg->vendor;
3606 break;
3607 case PCI_IVAR_DEVICE:
3608 *result = cfg->device;
3609 break;
3610 case PCI_IVAR_DEVID:
3611 *result = (cfg->device << 16) | cfg->vendor;
3612 break;
3613 case PCI_IVAR_CLASS:
3614 *result = cfg->baseclass;
3615 break;
3616 case PCI_IVAR_SUBCLASS:
3617 *result = cfg->subclass;
3618 break;
3619 case PCI_IVAR_PROGIF:
3620 *result = cfg->progif;
3621 break;
3622 case PCI_IVAR_REVID:
3623 *result = cfg->revid;
3624 break;
3625 case PCI_IVAR_INTPIN:
3626 *result = cfg->intpin;
3627 break;
3628 case PCI_IVAR_IRQ:
3629 *result = cfg->intline;
3630 break;
4d28e78f
SZ
3631 case PCI_IVAR_DOMAIN:
3632 *result = cfg->domain;
3633 break;
984263bc
MD
3634 case PCI_IVAR_BUS:
3635 *result = cfg->bus;
3636 break;
3637 case PCI_IVAR_SLOT:
3638 *result = cfg->slot;
3639 break;
3640 case PCI_IVAR_FUNCTION:
3641 *result = cfg->func;
3642 break;
4d28e78f
SZ
3643 case PCI_IVAR_CMDREG:
3644 *result = cfg->cmdreg;
984263bc 3645 break;
4d28e78f
SZ
3646 case PCI_IVAR_CACHELNSZ:
3647 *result = cfg->cachelnsz;
984263bc 3648 break;
4d28e78f
SZ
3649 case PCI_IVAR_MINGNT:
3650 *result = cfg->mingnt;
c7e4e7eb 3651 break;
4d28e78f
SZ
3652 case PCI_IVAR_MAXLAT:
3653 *result = cfg->maxlat;
c7e4e7eb 3654 break;
4d28e78f
SZ
3655 case PCI_IVAR_LATTIMER:
3656 *result = cfg->lattimer;
0254566f 3657 break;
d85e7311
SZ
3658 case PCI_IVAR_PCIXCAP_PTR:
3659 *result = cfg->pcix.pcix_ptr;
3660 break;
3661 case PCI_IVAR_PCIECAP_PTR:
3662 *result = cfg->expr.expr_ptr;
3663 break;
3664 case PCI_IVAR_VPDCAP_PTR:
3665 *result = cfg->vpd.vpd_reg;
3666 break;
984263bc 3667 default:
4d28e78f 3668 return (ENOENT);
984263bc 3669 }
4d28e78f 3670 return (0);
984263bc
MD
3671}
3672
22457186 3673int
984263bc
MD
3674pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3675{
3676 struct pci_devinfo *dinfo;
984263bc
MD
3677
3678 dinfo = device_get_ivars(child);
984263bc
MD
3679
3680 switch (which) {
4d28e78f
SZ
3681 case PCI_IVAR_INTPIN:
3682 dinfo->cfg.intpin = value;
3683 return (0);
3684 case PCI_IVAR_ETHADDR:
984263bc
MD
3685 case PCI_IVAR_SUBVENDOR:
3686 case PCI_IVAR_SUBDEVICE:
3687 case PCI_IVAR_VENDOR:
3688 case PCI_IVAR_DEVICE:
3689 case PCI_IVAR_DEVID:
3690 case PCI_IVAR_CLASS:
3691 case PCI_IVAR_SUBCLASS:
3692 case PCI_IVAR_PROGIF:
3693 case PCI_IVAR_REVID:
984263bc 3694 case PCI_IVAR_IRQ:
4d28e78f 3695 case PCI_IVAR_DOMAIN:
984263bc
MD
3696 case PCI_IVAR_BUS:
3697 case PCI_IVAR_SLOT:
3698 case PCI_IVAR_FUNCTION:
4d28e78f 3699 return (EINVAL); /* disallow for now */
984263bc 3700
984263bc 3701 default:
4d28e78f
SZ
3702 return (ENOENT);
3703 }
3704}
3705#ifdef notyet
3706#include "opt_ddb.h"
3707#ifdef DDB
3708#include <ddb/ddb.h>
3709#include <sys/cons.h>
3710
3711/*
3712 * List resources based on pci map registers, used for within ddb
3713 */
3714
3715DB_SHOW_COMMAND(pciregs, db_pci_dump)
3716{
3717 struct pci_devinfo *dinfo;
3718 struct devlist *devlist_head;
3719 struct pci_conf *p;
3720 const char *name;
3721 int i, error, none_count;
3722
3723 none_count = 0;
3724 /* get the head of the device queue */
3725 devlist_head = &pci_devq;
3726
3727 /*
3728 * Go through the list of devices and print out devices
3729 */
3730 for (error = 0, i = 0,
3731 dinfo = STAILQ_FIRST(devlist_head);
3732 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3733 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3734
3735 /* Populate pd_name and pd_unit */
3736 name = NULL;
3737 if (dinfo->cfg.dev)
3738 name = device_get_name(dinfo->cfg.dev);
3739
3740 p = &dinfo->conf;
3741 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3742 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3743 (name && *name) ? name : "none",
3744 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3745 none_count++,
3746 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3747 p->pc_sel.pc_func, (p->pc_class << 16) |
3748 (p->pc_subclass << 8) | p->pc_progif,
3749 (p->pc_subdevice << 16) | p->pc_subvendor,
3750 (p->pc_device << 16) | p->pc_vendor,
3751 p->pc_revid, p->pc_hdr);
984263bc 3752 }
984263bc 3753}
4d28e78f
SZ
3754#endif /* DDB */
3755#endif
984263bc 3756
201eb0a7 3757static struct resource *
4d28e78f
SZ
3758pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3759 u_long start, u_long end, u_long count, u_int flags)
201eb0a7
TS
3760{
3761 struct pci_devinfo *dinfo = device_get_ivars(child);
3762 struct resource_list *rl = &dinfo->resources;
3763 struct resource_list_entry *rle;
3764 struct resource *res;
4d28e78f 3765 pci_addr_t map, testval;
201eb0a7
TS
3766 int mapsize;
3767
3768 /*
3769 * Weed out the bogons, and figure out how large the BAR/map
4d28e78f 3770 * is. Bars that read back 0 here are bogus and unimplemented.
201eb0a7 3771 * Note: atapci in legacy mode are special and handled elsewhere
4d28e78f 3772 * in the code. If you have a atapci device in legacy mode and
201eb0a7
TS
3773 * it fails here, that other code is broken.
3774 */
3775 res = NULL;
3776 map = pci_read_config(child, *rid, 4);
3777 pci_write_config(child, *rid, 0xffffffff, 4);
3778 testval = pci_read_config(child, *rid, 4);
4d28e78f
SZ
3779 if (pci_maprange(testval) == 64)
3780 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
201eb0a7
TS
3781 if (pci_mapbase(testval) == 0)
3782 goto out;
4d28e78f
SZ
3783
3784 /*
3785 * Restore the original value of the BAR. We may have reprogrammed
3786 * the BAR of the low-level console device and when booting verbose,
3787 * we need the console device addressable.
3788 */
3789 pci_write_config(child, *rid, map, 4);
3790
3791 if (PCI_BAR_MEM(testval)) {
201eb0a7
TS
3792 if (type != SYS_RES_MEMORY) {
3793 if (bootverbose)
4d28e78f
SZ
3794 device_printf(dev,
3795 "child %s requested type %d for rid %#x,"
3796 " but the BAR says it is an memio\n",
3797 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3798 goto out;
3799 }
3800 } else {
3801 if (type != SYS_RES_IOPORT) {
3802 if (bootverbose)
4d28e78f
SZ
3803 device_printf(dev,
3804 "child %s requested type %d for rid %#x,"
3805 " but the BAR says it is an ioport\n",
3806 device_get_nameunit(child), type, *rid);
201eb0a7
TS
3807 goto out;
3808 }
3809 }
3810 /*
3811 * For real BARs, we need to override the size that
3812 * the driver requests, because that's what the BAR
3813 * actually uses and we would otherwise have a
3814 * situation where we might allocate the excess to
3815 * another driver, which won't work.
3816 */
3817 mapsize = pci_mapsize(testval);
4d28e78f 3818 count = 1UL << mapsize;
201eb0a7 3819 if (RF_ALIGNMENT(flags) < mapsize)
4d28e78f
SZ
3820 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3821 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3822 flags |= RF_PREFETCHABLE;
3823
201eb0a7
TS
3824 /*
3825 * Allocate enough resource, and then write back the
4d28e78f 3826 * appropriate bar for that resource.
201eb0a7
TS
3827 */
3828 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
4d28e78f 3829 start, end, count, flags);
201eb0a7 3830 if (res == NULL) {
4d28e78f
SZ
3831 device_printf(child,
3832 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3833 count, *rid, type, start, end);
201eb0a7
TS
3834 goto out;
3835 }
3836 resource_list_add(rl, type, *rid, start, end, count);
3837 rle = resource_list_find(rl, type, *rid);
3838 if (rle == NULL)
3839 panic("pci_alloc_map: unexpectedly can't find resource.");
3840 rle->res = res;
3841 rle->start = rman_get_start(res);
3842 rle->end = rman_get_end(res);
3843 rle->count = count;
3844 if (bootverbose)
4d28e78f
SZ
3845 device_printf(child,
3846 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3847 count, *rid, type, rman_get_start(res));
201eb0a7
TS
3848 map = rman_get_start(res);
3849out:;
3850 pci_write_config(child, *rid, map, 4);
4d28e78f
SZ
3851 if (pci_maprange(testval) == 64)
3852 pci_write_config(child, *rid + 4, map >> 32, 4);
3853 return (res);
201eb0a7 3854}
4d28e78f 3855
201eb0a7 3856
261fa16d 3857struct resource *
984263bc
MD
3858pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3859 u_long start, u_long end, u_long count, u_int flags)
3860{
3861 struct pci_devinfo *dinfo = device_get_ivars(child);
3862 struct resource_list *rl = &dinfo->resources;
201eb0a7 3863 struct resource_list_entry *rle;
984263bc 3864 pcicfgregs *cfg = &dinfo->cfg;
09e7d9f3 3865
984263bc
MD
3866 /*
3867 * Perform lazy resource allocation
984263bc
MD
3868 */
3869 if (device_get_parent(child) == dev) {
de67e43b
JS
3870 switch (type) {
3871 case SYS_RES_IRQ:
4d28e78f
SZ
3872 /*
3873 * Can't alloc legacy interrupt once MSI messages
3874 * have been allocated.
3875 */
3876#ifdef MSI
3877 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3878 cfg->msix.msix_alloc > 0))
3879 return (NULL);
de67e43b 3880#endif
4d28e78f
SZ
3881 /*
3882 * If the child device doesn't have an
3883 * interrupt routed and is deserving of an
3884 * interrupt, try to assign it one.
3885 */
3886 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3887 (cfg->intpin != 0))
3888 pci_assign_interrupt(dev, child, 0);
3889 break;
de67e43b
JS
3890 case SYS_RES_IOPORT:
3891 case SYS_RES_MEMORY:
3892 if (*rid < PCIR_BAR(cfg->nummaps)) {
3893 /*
3894 * Enable the I/O mode. We should
3895 * also be assigning resources too
3896 * when none are present. The
3897 * resource_list_alloc kind of sorta does
3898 * this...
3899 */
3900 if (PCI_ENABLE_IO(dev, child, type))
3901 return (NULL);
984263bc 3902 }
201eb0a7
TS
3903 rle = resource_list_find(rl, type, *rid);
3904 if (rle == NULL)
4d28e78f
SZ
3905 return (pci_alloc_map(dev, child, type, rid,
3906 start, end, count, flags));
820c1612 3907 break;
984263bc 3908 }
201eb0a7
TS
3909 /*
3910 * If we've already allocated the resource, then
4d28e78f 3911 * return it now. But first we may need to activate
201eb0a7 3912 * it, since we don't allocate the resource as active
4d28e78f 3913 * above. Normally this would be done down in the
201eb0a7 3914 * nexus, but since we short-circuit that path we have
4d28e78f 3915 * to do its job here. Not sure if we should kfree the
201eb0a7 3916 * resource if it fails to activate.
201eb0a7
TS
3917 */
3918 rle = resource_list_find(rl, type, *rid);
3919 if (rle != NULL && rle->res != NULL) {
3920 if (bootverbose)
4d28e78f
SZ
3921 device_printf(child,
3922 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3923 rman_get_size(rle->res), *rid, type,
3924 rman_get_start(rle->res));
201eb0a7
TS
3925 if ((flags & RF_ACTIVE) &&
3926 bus_generic_activate_resource(dev, child, type,
4d28e78f
SZ
3927 *rid, rle->res) != 0)
3928 return (NULL);
3929 return (rle->res);
201eb0a7 3930 }
984263bc 3931 }
4d28e78f
SZ
3932 return (resource_list_alloc(rl, dev, child, type, rid,
3933 start, end, count, flags));
984263bc
MD
3934}
3935
4d28e78f
SZ
3936void
3937pci_delete_resource(device_t dev, device_t child, int type, int rid)
984263bc 3938{
4d28e78f
SZ
3939 struct pci_devinfo *dinfo;
3940 struct resource_list *rl;
984263bc
MD
3941 struct resource_list_entry *rle;
3942
4d28e78f
SZ
3943 if (device_get_parent(child) != dev)
3944 return;
984263bc 3945
4d28e78f
SZ
3946 dinfo = device_get_ivars(child);
3947 rl = &dinfo->resources;
3948 rle = resource_list_find(rl, type, rid);
3949 if (rle) {
3950 if (rle->res) {
3951 if (rman_get_device(rle->res) != dev ||
3952 rman_get_flags(rle->res) & RF_ACTIVE) {
3953 device_printf(dev, "delete_resource: "
3954 "Resource still owned by child, oops. "
3955 "(type=%d, rid=%d, addr=%lx)\n",
3956 rle->type, rle->rid,
3957 rman_get_start(rle->res));
3958 return;
3959 }
3960 bus_release_resource(dev, type, rid, rle->res);
3961 }
3962 resource_list_delete(rl, type, rid);
3963 }
3964 /*
3965 * Why do we turn off the PCI configuration BAR when we delete a
3966 * resource? -- imp
3967 */
3968 pci_write_config(child, rid, 0, 4);
3969 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
984263bc
MD
3970}
3971
e126caf1
MD
3972struct resource_list *
3973pci_get_resource_list (device_t dev, device_t child)
3974{
4d28e78f 3975 struct pci_devinfo *dinfo = device_get_ivars(child);
e126caf1 3976
bcc66dfa
SZ
3977 if (dinfo == NULL)
3978 return (NULL);
3979
b0486c83 3980 return (&dinfo->resources);
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MD
3981}
3982
4d28e78f 3983uint32_t
984263bc
MD
3984pci_read_config_method(device_t dev, device_t child, int reg, int width)
3985{
3986 struct pci_devinfo *dinfo = device_get_ivars(child);
3987 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63 3988
4d28e78f
SZ
3989 return (PCIB_READ_CONFIG(device_get_parent(dev),
3990 cfg->bus, cfg->slot, cfg->func, reg, width));
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MD
3991}
3992
e126caf1 3993void
984263bc 3994pci_write_config_method(device_t dev, device_t child, int reg,
4d28e78f 3995 uint32_t val, int width)
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MD
3996{
3997 struct pci_devinfo *dinfo = device_get_ivars(child);
3998 pcicfgregs *cfg = &dinfo->cfg;
4a5a2d63
JS
3999
4000 PCIB_WRITE_CONFIG(device_get_parent(dev),
4d28e78f 4001 cfg->bus, cfg->slot, cfg->func, reg, val, width);
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MD
4002}
4003
e126caf1 4004int
4d28e78f 4005pci_child_location_str_method(device_t dev, device_t child, char *buf,
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MD
4006 size_t buflen)
4007{
e126caf1 4008
f8c7a42d 4009 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
e126caf1
MD
4010 pci_get_function(child));
4011 return (0);
4012}
4013
4014int
4d28e78f 4015pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
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MD
4016 size_t buflen)
4017{
4018 struct pci_devinfo *dinfo;
4019 pcicfgregs *cfg;
4020
4021 dinfo = device_get_ivars(child);
4022 cfg = &dinfo->cfg;
f8c7a42d 4023 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
e126caf1
MD
4024 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4025 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,