network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / ale / if_ale.c
CommitLineData
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1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
28 */
29
30/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31
32#include <sys/param.h>
33#include <sys/endian.h>
34#include <sys/kernel.h>
35#include <sys/bus.h>
36#include <sys/interrupt.h>
37#include <sys/malloc.h>
38#include <sys/proc.h>
39#include <sys/rman.h>
40#include <sys/serialize.h>
41#include <sys/socket.h>
42#include <sys/sockio.h>
43#include <sys/sysctl.h>
44
45#include <net/ethernet.h>
46#include <net/if.h>
47#include <net/bpf.h>
48#include <net/if_arp.h>
49#include <net/if_dl.h>
50#include <net/if_llc.h>
51#include <net/if_media.h>
52#include <net/ifq_var.h>
53#include <net/vlan/if_vlan_var.h>
54#include <net/vlan/if_vlan_ether.h>
55
56#include <netinet/ip.h>
57
e3326a9a 58#include <dev/netif/mii_layer/mii.h>
99fe2010 59#include <dev/netif/mii_layer/miivar.h>
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60
61#include <bus/pci/pcireg.h>
62#include <bus/pci/pcivar.h>
63#include <bus/pci/pcidevs.h>
64
65#include <dev/netif/ale/if_alereg.h>
66#include <dev/netif/ale/if_alevar.h>
67
68/* "device miibus" required. See GENERIC if you get errors here. */
69#include "miibus_if.h"
70
71/* For more information about Tx checksum offload issues see ale_encap(). */
72#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
73
74struct ale_dmamap_ctx {
75 int nsegs;
76 bus_dma_segment_t *segs;
77};
78
79static int ale_probe(device_t);
80static int ale_attach(device_t);
81static int ale_detach(device_t);
82static int ale_shutdown(device_t);
83static int ale_suspend(device_t);
84static int ale_resume(device_t);
85
86static int ale_miibus_readreg(device_t, int, int);
87static int ale_miibus_writereg(device_t, int, int, int);
88static void ale_miibus_statchg(device_t);
89
90static void ale_init(void *);
91static void ale_start(struct ifnet *);
92static int ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
93static void ale_watchdog(struct ifnet *);
94static int ale_mediachange(struct ifnet *);
95static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
96
97static void ale_intr(void *);
98static int ale_rxeof(struct ale_softc *sc);
99static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
100 uint32_t, uint32_t *);
101static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
102static void ale_txeof(struct ale_softc *);
103
104static int ale_dma_alloc(struct ale_softc *);
105static void ale_dma_free(struct ale_softc *);
106static int ale_check_boundary(struct ale_softc *);
107static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
108static void ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
109 bus_size_t, int);
110static int ale_encap(struct ale_softc *, struct mbuf **);
111static void ale_init_rx_pages(struct ale_softc *);
112static void ale_init_tx_ring(struct ale_softc *);
113
114static void ale_stop(struct ale_softc *);
115static void ale_tick(void *);
116static void ale_get_macaddr(struct ale_softc *);
117static void ale_mac_config(struct ale_softc *);
118static void ale_phy_reset(struct ale_softc *);
119static void ale_reset(struct ale_softc *);
120static void ale_rxfilter(struct ale_softc *);
121static void ale_rxvlan(struct ale_softc *);
122static void ale_stats_clear(struct ale_softc *);
123static void ale_stats_update(struct ale_softc *);
124static void ale_stop_mac(struct ale_softc *);
125#ifdef notyet
126static void ale_setlinkspeed(struct ale_softc *);
127static void ale_setwol(struct ale_softc *);
128#endif
129
130static void ale_sysctl_node(struct ale_softc *);
131static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
132
133/*
134 * Devices supported by this driver.
135 */
136static struct ale_dev {
137 uint16_t ale_vendorid;
138 uint16_t ale_deviceid;
139 const char *ale_name;
140} ale_devs[] = {
141 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
142 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
143};
144
145static device_method_t ale_methods[] = {
146 /* Device interface. */
147 DEVMETHOD(device_probe, ale_probe),
148 DEVMETHOD(device_attach, ale_attach),
149 DEVMETHOD(device_detach, ale_detach),
150 DEVMETHOD(device_shutdown, ale_shutdown),
151 DEVMETHOD(device_suspend, ale_suspend),
152 DEVMETHOD(device_resume, ale_resume),
153
154 /* Bus interface. */
155 DEVMETHOD(bus_print_child, bus_generic_print_child),
156 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
157
158 /* MII interface. */
159 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
160 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
161 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
162
163 { NULL, NULL }
164};
165
166static driver_t ale_driver = {
167 "ale",
168 ale_methods,
169 sizeof(struct ale_softc)
170};
171
172static devclass_t ale_devclass;
173
174DECLARE_DUMMY_MODULE(if_ale);
175MODULE_DEPEND(if_ale, miibus, 1, 1, 1);
176DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, 0, 0);
177DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
178
179static int
180ale_miibus_readreg(device_t dev, int phy, int reg)
181{
182 struct ale_softc *sc;
183 uint32_t v;
184 int i;
185
186 sc = device_get_softc(dev);
187
188 if (phy != sc->ale_phyaddr)
189 return (0);
190
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191 if (sc->ale_flags & ALE_FLAG_FASTETHER) {
192 if (reg == MII_100T2CR || reg == MII_100T2SR ||
193 reg == MII_EXTSR)
194 return (0);
195 }
196
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197 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
198 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
199 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
200 DELAY(5);
201 v = CSR_READ_4(sc, ALE_MDIO);
202 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
203 break;
204 }
205
206 if (i == 0) {
207 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
208 return (0);
209 }
210
211 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
212}
213
214static int
215ale_miibus_writereg(device_t dev, int phy, int reg, int val)
216{
217 struct ale_softc *sc;
218 uint32_t v;
219 int i;
220
221 sc = device_get_softc(dev);
222
223 if (phy != sc->ale_phyaddr)
224 return (0);
225
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226 if (sc->ale_flags & ALE_FLAG_FASTETHER) {
227 if (reg == MII_100T2CR || reg == MII_100T2SR ||
228 reg == MII_EXTSR)
229 return (0);
230 }
231
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232 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
233 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
234 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
235 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
236 DELAY(5);
237 v = CSR_READ_4(sc, ALE_MDIO);
238 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
239 break;
240 }
241
242 if (i == 0)
243 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
244
245 return (0);
246}
247
248static void
249ale_miibus_statchg(device_t dev)
250{
251 struct ale_softc *sc = device_get_softc(dev);
252 struct ifnet *ifp = &sc->arpcom.ac_if;
253 struct mii_data *mii;
254 uint32_t reg;
255
256 ASSERT_SERIALIZED(ifp->if_serializer);
257
258 if ((ifp->if_flags & IFF_RUNNING) == 0)
259 return;
260
261 mii = device_get_softc(sc->ale_miibus);
262
263 sc->ale_flags &= ~ALE_FLAG_LINK;
264 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
265 (IFM_ACTIVE | IFM_AVALID)) {
266 switch (IFM_SUBTYPE(mii->mii_media_active)) {
267 case IFM_10_T:
268 case IFM_100_TX:
269 sc->ale_flags |= ALE_FLAG_LINK;
270 break;
271
272 case IFM_1000_T:
273 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
274 sc->ale_flags |= ALE_FLAG_LINK;
275 break;
276
277 default:
278 break;
279 }
280 }
281
282 /* Stop Rx/Tx MACs. */
283 ale_stop_mac(sc);
284
285 /* Program MACs with resolved speed/duplex/flow-control. */
286 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
287 ale_mac_config(sc);
288 /* Reenable Tx/Rx MACs. */
289 reg = CSR_READ_4(sc, ALE_MAC_CFG);
290 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
291 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
292 }
293}
294
295static void
296ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
297{
298 struct ale_softc *sc = ifp->if_softc;
299 struct mii_data *mii = device_get_softc(sc->ale_miibus);
300
301 ASSERT_SERIALIZED(ifp->if_serializer);
302
303 mii_pollstat(mii);
304 ifmr->ifm_status = mii->mii_media_status;
305 ifmr->ifm_active = mii->mii_media_active;
306}
307
308static int
309ale_mediachange(struct ifnet *ifp)
310{
311 struct ale_softc *sc = ifp->if_softc;
312 struct mii_data *mii = device_get_softc(sc->ale_miibus);
313 int error;
314
315 ASSERT_SERIALIZED(ifp->if_serializer);
316
317 if (mii->mii_instance != 0) {
318 struct mii_softc *miisc;
319
320 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
321 mii_phy_reset(miisc);
322 }
323 error = mii_mediachg(mii);
324
325 return (error);
326}
327
328static int
329ale_probe(device_t dev)
330{
331 struct ale_dev *sp;
332 int i;
333 uint16_t vendor, devid;
334
335 vendor = pci_get_vendor(dev);
336 devid = pci_get_device(dev);
337 sp = ale_devs;
338 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
339 if (vendor == sp->ale_vendorid &&
340 devid == sp->ale_deviceid) {
341 device_set_desc(dev, sp->ale_name);
342 return (0);
343 }
344 sp++;
345 }
346
347 return (ENXIO);
348}
349
350static void
351ale_get_macaddr(struct ale_softc *sc)
352{
353 uint32_t ea[2], reg;
354 int i, vpdc;
355
356 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
357 if ((reg & SPI_VPD_ENB) != 0) {
358 reg &= ~SPI_VPD_ENB;
359 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
360 }
361
362 vpdc = pci_get_vpdcap_ptr(sc->ale_dev);
363 if (vpdc) {
364 /*
365 * PCI VPD capability found, let TWSI reload EEPROM.
366 * This will set ethernet address of controller.
367 */
368 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
369 TWSI_CTRL_SW_LD_START);
370 for (i = 100; i > 0; i--) {
371 DELAY(1000);
372 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
373 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
374 break;
375 }
376 if (i == 0)
377 device_printf(sc->ale_dev,
378 "reloading EEPROM timeout!\n");
379 } else {
380 if (bootverbose)
381 device_printf(sc->ale_dev,
382 "PCI VPD capability not found!\n");
383 }
384
385 ea[0] = CSR_READ_4(sc, ALE_PAR0);
386 ea[1] = CSR_READ_4(sc, ALE_PAR1);
387 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
388 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
389 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
390 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
391 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
392 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
393}
394
395static void
396ale_phy_reset(struct ale_softc *sc)
397{
398 /* Reset magic from Linux. */
399 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
400 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
401 GPHY_CTRL_PHY_PLL_ON);
402 DELAY(1000);
403 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
404 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
405 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
406 DELAY(1000);
407
408#define ATPHY_DBG_ADDR 0x1D
409#define ATPHY_DBG_DATA 0x1E
410
411 /* Enable hibernation mode. */
412 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
413 ATPHY_DBG_ADDR, 0x0B);
414 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
415 ATPHY_DBG_DATA, 0xBC00);
416 /* Set Class A/B for all modes. */
417 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
418 ATPHY_DBG_ADDR, 0x00);
419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
420 ATPHY_DBG_DATA, 0x02EF);
421 /* Enable 10BT power saving. */
422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
423 ATPHY_DBG_ADDR, 0x12);
424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 ATPHY_DBG_DATA, 0x4C04);
426 /* Adjust 1000T power. */
427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
428 ATPHY_DBG_ADDR, 0x04);
429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 ATPHY_DBG_ADDR, 0x8BBB);
431 /* 10BT center tap voltage. */
432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
433 ATPHY_DBG_ADDR, 0x05);
434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 ATPHY_DBG_ADDR, 0x2C46);
436
437#undef ATPHY_DBG_ADDR
438#undef ATPHY_DBG_DATA
439 DELAY(1000);
440}
441
442static int
443ale_attach(device_t dev)
444{
445 struct ale_softc *sc = device_get_softc(dev);
446 struct ifnet *ifp = &sc->arpcom.ac_if;
447 int error = 0;
448 uint32_t rxf_len, txf_len;
449 uint8_t pcie_ptr;
450
451 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
452 sc->ale_dev = dev;
453
454 callout_init(&sc->ale_tick_ch);
455
456#ifndef BURN_BRIDGES
457 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
458 uint32_t irq, mem;
459
460 irq = pci_read_config(dev, PCIR_INTLINE, 4);
461 mem = pci_read_config(dev, ALE_PCIR_BAR, 4);
462
463 device_printf(dev, "chip is in D%d power mode "
464 "-- setting to D0\n", pci_get_powerstate(dev));
465
466 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
467
468 pci_write_config(dev, PCIR_INTLINE, irq, 4);
469 pci_write_config(dev, ALE_PCIR_BAR, mem, 4);
470 }
471#endif /* !BURN_BRIDGE */
472
473 /* Enable bus mastering */
474 pci_enable_busmaster(dev);
475
476 /*
477 * Allocate memory mapped IO
478 */
479 sc->ale_mem_rid = ALE_PCIR_BAR;
480 sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
481 &sc->ale_mem_rid, RF_ACTIVE);
482 if (sc->ale_mem_res == NULL) {
483 device_printf(dev, "can't allocate IO memory\n");
484 return ENXIO;
485 }
486 sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res);
487 sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res);
488
489 /*
490 * Allocate IRQ
491 */
492 sc->ale_irq_rid = 0;
493 sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
494 &sc->ale_irq_rid,
495 RF_SHAREABLE | RF_ACTIVE);
496 if (sc->ale_irq_res == NULL) {
497 device_printf(dev, "can't allocate irq\n");
498 error = ENXIO;
499 goto fail;
500 }
501
502 /* Set PHY address. */
503 sc->ale_phyaddr = ALE_PHY_ADDR;
504
505 /* Reset PHY. */
506 ale_phy_reset(sc);
507
508 /* Reset the ethernet controller. */
509 ale_reset(sc);
510
511 /* Get PCI and chip id/revision. */
512 sc->ale_rev = pci_get_revid(dev);
513 if (sc->ale_rev >= 0xF0) {
514 /* L2E Rev. B. AR8114 */
515 sc->ale_flags |= ALE_FLAG_FASTETHER;
516 } else {
517 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
518 /* L1E AR8121 */
519 sc->ale_flags |= ALE_FLAG_JUMBO;
520 } else {
521 /* L2E Rev. A. AR8113 */
522 sc->ale_flags |= ALE_FLAG_FASTETHER;
523 }
524 }
525
526 /*
527 * All known controllers seems to require 4 bytes alignment
528 * of Tx buffers to make Tx checksum offload with custom
529 * checksum generation method work.
530 */
531 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
532
533 /*
534 * All known controllers seems to have issues on Rx checksum
535 * offload for fragmented IP datagrams.
536 */
537 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
538
539 /*
540 * Don't use Tx CMB. It is known to cause RRS update failure
541 * under certain circumstances. Typical phenomenon of the
542 * issue would be unexpected sequence number encountered in
543 * Rx handler.
544 */
545 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
546 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
547 MASTER_CHIP_REV_SHIFT;
548 if (bootverbose) {
549 device_printf(dev, "PCI device revision : 0x%04x\n",
550 sc->ale_rev);
551 device_printf(dev, "Chip id/revision : 0x%04x\n",
552 sc->ale_chip_rev);
553 }
554
555 /*
556 * Uninitialized hardware returns an invalid chip id/revision
557 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
558 */
559 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
560 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
561 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
562 rxf_len == 0xFFFFFFF) {
563 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
564 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
565 txf_len, rxf_len);
566 error = ENXIO;
567 goto fail;
568 }
569 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
570
571 /* Get DMA parameters from PCIe device control register. */
572 pcie_ptr = pci_get_pciecap_ptr(dev);
573 if (pcie_ptr) {
574 uint16_t devctl;
575
576 sc->ale_flags |= ALE_FLAG_PCIE;
577 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
578 /* Max read request size. */
579 sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) <<
580 DMA_CFG_RD_BURST_SHIFT;
581 /* Max payload size. */
582 sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) <<
583 DMA_CFG_WR_BURST_SHIFT;
584 if (bootverbose) {
585 device_printf(dev, "Read request size : %d bytes.\n",
586 128 << ((devctl >> 12) & 0x07));
587 device_printf(dev, "TLP payload size : %d bytes.\n",
588 128 << ((devctl >> 5) & 0x07));
589 }
590 } else {
591 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
592 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
593 }
594
595 /* Create device sysctl node. */
596 ale_sysctl_node(sc);
597
598 if ((error = ale_dma_alloc(sc) != 0))
599 goto fail;
600
601 /* Load station address. */
602 ale_get_macaddr(sc);
603
604 ifp->if_softc = sc;
605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
606 ifp->if_ioctl = ale_ioctl;
607 ifp->if_start = ale_start;
608 ifp->if_init = ale_init;
609 ifp->if_watchdog = ale_watchdog;
610 ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1);
611 ifq_set_ready(&ifp->if_snd);
612
9d911346 613 ifp->if_capabilities = IFCAP_RXCSUM |
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614 IFCAP_VLAN_MTU |
615 IFCAP_VLAN_HWTAGGING;
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616#ifdef notyet
617 ifp->if_capabilities |= IFCAP_TXCSUM;
99fe2010 618 ifp->if_hwassist = ALE_CSUM_FEATURES;
9d911346 619#endif
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620 ifp->if_capenable = ifp->if_capabilities;
621
622 /* Set up MII bus. */
623 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
624 ale_mediastatus)) != 0) {
625 device_printf(dev, "no PHY found!\n");
626 goto fail;
627 }
628
629 ether_ifattach(ifp, sc->ale_eaddr, NULL);
630
631 /* Tell the upper layer(s) we support long frames. */
632 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
633
634 error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc,
635 &sc->ale_irq_handle, ifp->if_serializer);
636 if (error) {
637 device_printf(dev, "could not set up interrupt handler.\n");
638 ether_ifdetach(ifp);
639 goto fail;
640 }
641
642 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->ale_irq_res));
643 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
644 return 0;
645fail:
646 ale_detach(dev);
647 return (error);
648}
649
650static int
651ale_detach(device_t dev)
652{
653 struct ale_softc *sc = device_get_softc(dev);
654
655 if (device_is_attached(dev)) {
656 struct ifnet *ifp = &sc->arpcom.ac_if;
657
658 lwkt_serialize_enter(ifp->if_serializer);
659 sc->ale_flags |= ALE_FLAG_DETACH;
660 ale_stop(sc);
661 bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle);
662 lwkt_serialize_exit(ifp->if_serializer);
663
664 ether_ifdetach(ifp);
665 }
666
667 if (sc->ale_sysctl_tree != NULL)
668 sysctl_ctx_free(&sc->ale_sysctl_ctx);
669
670 if (sc->ale_miibus != NULL)
671 device_delete_child(dev, sc->ale_miibus);
672 bus_generic_detach(dev);
673
674 if (sc->ale_irq_res != NULL) {
675 bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid,
676 sc->ale_irq_res);
677 }
678 if (sc->ale_mem_res != NULL) {
679 bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid,
680 sc->ale_mem_res);
681 }
682
683 ale_dma_free(sc);
684
685 return (0);
686}
687
688#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
689 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
690#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
691 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
692
693static void
694ale_sysctl_node(struct ale_softc *sc)
695{
696 struct sysctl_ctx_list *ctx;
697 struct sysctl_oid_list *child, *parent;
698 struct sysctl_oid *tree;
699 struct ale_hw_stats *stats;
700 int error;
701
702 sysctl_ctx_init(&sc->ale_sysctl_ctx);
703 sc->ale_sysctl_tree = SYSCTL_ADD_NODE(&sc->ale_sysctl_ctx,
704 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
705 device_get_nameunit(sc->ale_dev),
706 CTLFLAG_RD, 0, "");
707 if (sc->ale_sysctl_tree == NULL) {
708 device_printf(sc->ale_dev, "can't add sysctl node\n");
709 return;
710 }
711
712 stats = &sc->ale_stats;
713 ctx = &sc->ale_sysctl_ctx;
714 child = SYSCTL_CHILDREN(sc->ale_sysctl_tree);
715
716 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
717 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
718 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
719 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
720 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
721 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
722
723 /*
724 * Pull in device tunables.
725 */
726 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
727 error = resource_int_value(device_get_name(sc->ale_dev),
728 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
729 if (error == 0) {
730 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
731 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
732 device_printf(sc->ale_dev, "int_rx_mod value out of "
733 "range; using default: %d\n",
734 ALE_IM_RX_TIMER_DEFAULT);
735 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
736 }
737 }
738
739 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
740 error = resource_int_value(device_get_name(sc->ale_dev),
741 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
742 if (error == 0) {
743 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
744 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
745 device_printf(sc->ale_dev, "int_tx_mod value out of "
746 "range; using default: %d\n",
747 ALE_IM_TX_TIMER_DEFAULT);
748 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
749 }
750 }
751
752 /* Misc statistics. */
753 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
754 &stats->reset_brk_seq,
755 "Controller resets due to broken Rx sequnce number");
756
757 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
758 NULL, "ATE statistics");
759 parent = SYSCTL_CHILDREN(tree);
760
761 /* Rx statistics. */
762 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
763 NULL, "Rx MAC statistics");
764 child = SYSCTL_CHILDREN(tree);
765 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
766 &stats->rx_frames, "Good frames");
767 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
768 &stats->rx_bcast_frames, "Good broadcast frames");
769 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
770 &stats->rx_mcast_frames, "Good multicast frames");
771 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
772 &stats->rx_pause_frames, "Pause control frames");
773 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
774 &stats->rx_control_frames, "Control frames");
775 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
776 &stats->rx_crcerrs, "CRC errors");
777 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
778 &stats->rx_lenerrs, "Frames with length mismatched");
779 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
780 &stats->rx_bytes, "Good octets");
781 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
782 &stats->rx_bcast_bytes, "Good broadcast octets");
783 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
784 &stats->rx_mcast_bytes, "Good multicast octets");
785 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
786 &stats->rx_runts, "Too short frames");
787 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
788 &stats->rx_fragments, "Fragmented frames");
789 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
790 &stats->rx_pkts_64, "64 bytes frames");
791 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
792 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
793 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
794 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
795 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
796 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
797 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
798 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
799 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
800 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
801 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
802 &stats->rx_pkts_1519_max, "1519 to max frames");
803 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
804 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
805 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
806 &stats->rx_fifo_oflows, "FIFO overflows");
807 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
808 &stats->rx_rrs_errs, "Return status write-back errors");
809 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
810 &stats->rx_alignerrs, "Alignment errors");
811 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
812 &stats->rx_pkts_filtered,
813 "Frames dropped due to address filtering");
814
815 /* Tx statistics. */
816 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
817 NULL, "Tx MAC statistics");
818 child = SYSCTL_CHILDREN(tree);
819 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
820 &stats->tx_frames, "Good frames");
821 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
822 &stats->tx_bcast_frames, "Good broadcast frames");
823 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
824 &stats->tx_mcast_frames, "Good multicast frames");
825 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
826 &stats->tx_pause_frames, "Pause control frames");
827 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
828 &stats->tx_control_frames, "Control frames");
829 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
830 &stats->tx_excess_defer, "Frames with excessive derferrals");
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
832 &stats->tx_excess_defer, "Frames with derferrals");
833 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
834 &stats->tx_bytes, "Good octets");
835 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
836 &stats->tx_bcast_bytes, "Good broadcast octets");
837 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
838 &stats->tx_mcast_bytes, "Good multicast octets");
839 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
840 &stats->tx_pkts_64, "64 bytes frames");
841 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
842 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
844 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
845 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
846 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
847 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
848 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
849 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
850 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
852 &stats->tx_pkts_1519_max, "1519 to max frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
854 &stats->tx_single_colls, "Single collisions");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
856 &stats->tx_multi_colls, "Multiple collisions");
857 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
858 &stats->tx_late_colls, "Late collisions");
859 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
860 &stats->tx_excess_colls, "Excessive collisions");
861 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
862 &stats->tx_abort, "Aborted frames due to Excessive collisions");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
864 &stats->tx_underrun, "FIFO underruns");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
866 &stats->tx_desc_underrun, "Descriptor write-back errors");
867 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
868 &stats->tx_lenerrs, "Frames with length mismatched");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
870 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
871}
872
873#undef ALE_SYSCTL_STAT_ADD32
874#undef ALE_SYSCTL_STAT_ADD64
875
876struct ale_dmamap_arg {
877 bus_addr_t ale_busaddr;
878};
879
880static void
881ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
882{
883 struct ale_dmamap_arg *ctx;
884
885 if (error != 0)
886 return;
887
888 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
889
890 ctx = (struct ale_dmamap_arg *)arg;
891 ctx->ale_busaddr = segs[0].ds_addr;
892}
893
894/*
895 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
896 * which specifies high address region of DMA blocks. Therefore these
897 * blocks should have the same high address of given 4GB address
898 * space(i.e. crossing 4GB boundary is not allowed).
899 */
900static int
901ale_check_boundary(struct ale_softc *sc)
902{
903 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
904 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
905
906 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
907 sc->ale_pagesize;
908 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
909 sc->ale_pagesize;
910 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
911 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
912 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
913 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
914
915 if ((ALE_ADDR_HI(tx_ring_end) !=
916 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
917 (ALE_ADDR_HI(rx_page_end[0]) !=
918 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
919 (ALE_ADDR_HI(rx_page_end[1]) !=
920 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
921 (ALE_ADDR_HI(tx_cmb_end) !=
922 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
923 (ALE_ADDR_HI(rx_cmb_end[0]) !=
924 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
925 (ALE_ADDR_HI(rx_cmb_end[1]) !=
926 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
927 return (EFBIG);
928
929 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
930 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
931 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
932 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
933 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
934 return (EFBIG);
935
936 return (0);
937}
938
939static int
940ale_dma_alloc(struct ale_softc *sc)
941{
942 struct ale_txdesc *txd;
943 bus_addr_t lowaddr;
944 struct ale_dmamap_arg ctx;
945 int error, guard_size, i;
946
947 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
948 guard_size = ALE_JUMBO_FRAMELEN;
949 else
950 guard_size = ALE_MAX_FRAMELEN;
951 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
952 ALE_RX_PAGE_ALIGN);
953 lowaddr = BUS_SPACE_MAXADDR;
954again:
955 /* Create parent DMA tag. */
956 error = bus_dma_tag_create(
957 NULL, /* parent */
958 1, 0, /* alignment, boundary */
959 lowaddr, /* lowaddr */
960 BUS_SPACE_MAXADDR, /* highaddr */
961 NULL, NULL, /* filter, filterarg */
962 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
963 0, /* nsegments */
964 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
965 0, /* flags */
966 &sc->ale_cdata.ale_parent_tag);
967 if (error != 0) {
968 device_printf(sc->ale_dev,
969 "could not create parent DMA tag.\n");
970 goto fail;
971 }
972
973 /* Create DMA tag for Tx descriptor ring. */
974 error = bus_dma_tag_create(
975 sc->ale_cdata.ale_parent_tag, /* parent */
976 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
977 BUS_SPACE_MAXADDR, /* lowaddr */
978 BUS_SPACE_MAXADDR, /* highaddr */
979 NULL, NULL, /* filter, filterarg */
980 ALE_TX_RING_SZ, /* maxsize */
981 1, /* nsegments */
982 ALE_TX_RING_SZ, /* maxsegsize */
983 0, /* flags */
984 &sc->ale_cdata.ale_tx_ring_tag);
985 if (error != 0) {
986 device_printf(sc->ale_dev,
987 "could not create Tx ring DMA tag.\n");
988 goto fail;
989 }
990
991 /* Create DMA tag for Rx pages. */
992 for (i = 0; i < ALE_RX_PAGES; i++) {
993 error = bus_dma_tag_create(
994 sc->ale_cdata.ale_parent_tag, /* parent */
995 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
996 BUS_SPACE_MAXADDR, /* lowaddr */
997 BUS_SPACE_MAXADDR, /* highaddr */
998 NULL, NULL, /* filter, filterarg */
999 sc->ale_pagesize, /* maxsize */
1000 1, /* nsegments */
1001 sc->ale_pagesize, /* maxsegsize */
1002 0, /* flags */
1003 &sc->ale_cdata.ale_rx_page[i].page_tag);
1004 if (error != 0) {
1005 device_printf(sc->ale_dev,
1006 "could not create Rx page %d DMA tag.\n", i);
1007 goto fail;
1008 }
1009 }
1010
1011 /* Create DMA tag for Tx coalescing message block. */
1012 error = bus_dma_tag_create(
1013 sc->ale_cdata.ale_parent_tag, /* parent */
1014 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1015 BUS_SPACE_MAXADDR, /* lowaddr */
1016 BUS_SPACE_MAXADDR, /* highaddr */
1017 NULL, NULL, /* filter, filterarg */
1018 ALE_TX_CMB_SZ, /* maxsize */
1019 1, /* nsegments */
1020 ALE_TX_CMB_SZ, /* maxsegsize */
1021 0, /* flags */
1022 &sc->ale_cdata.ale_tx_cmb_tag);
1023 if (error != 0) {
1024 device_printf(sc->ale_dev,
1025 "could not create Tx CMB DMA tag.\n");
1026 goto fail;
1027 }
1028
1029 /* Create DMA tag for Rx coalescing message block. */
1030 for (i = 0; i < ALE_RX_PAGES; i++) {
1031 error = bus_dma_tag_create(
1032 sc->ale_cdata.ale_parent_tag, /* parent */
1033 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1034 BUS_SPACE_MAXADDR, /* lowaddr */
1035 BUS_SPACE_MAXADDR, /* highaddr */
1036 NULL, NULL, /* filter, filterarg */
1037 ALE_RX_CMB_SZ, /* maxsize */
1038 1, /* nsegments */
1039 ALE_RX_CMB_SZ, /* maxsegsize */
1040 0, /* flags */
1041 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1042 if (error != 0) {
1043 device_printf(sc->ale_dev,
1044 "could not create Rx page %d CMB DMA tag.\n", i);
1045 goto fail;
1046 }
1047 }
1048
1049 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1050 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1051 (void **)&sc->ale_cdata.ale_tx_ring,
1052 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1053 &sc->ale_cdata.ale_tx_ring_map);
1054 if (error != 0) {
1055 device_printf(sc->ale_dev,
1056 "could not allocate DMA'able memory for Tx ring.\n");
1057 goto fail;
1058 }
1059 ctx.ale_busaddr = 0;
1060 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1061 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1062 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1063 if (error != 0 || ctx.ale_busaddr == 0) {
1064 device_printf(sc->ale_dev,
1065 "could not load DMA'able memory for Tx ring.\n");
1066 goto fail;
1067 }
1068 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1069
1070 /* Rx pages. */
1071 for (i = 0; i < ALE_RX_PAGES; i++) {
1072 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1073 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1074 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1075 &sc->ale_cdata.ale_rx_page[i].page_map);
1076 if (error != 0) {
1077 device_printf(sc->ale_dev,
1078 "could not allocate DMA'able memory for "
1079 "Rx page %d.\n", i);
1080 goto fail;
1081 }
1082 ctx.ale_busaddr = 0;
1083 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1084 sc->ale_cdata.ale_rx_page[i].page_map,
1085 sc->ale_cdata.ale_rx_page[i].page_addr,
1086 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1087 if (error != 0 || ctx.ale_busaddr == 0) {
1088 device_printf(sc->ale_dev,
1089 "could not load DMA'able memory for "
1090 "Rx page %d.\n", i);
1091 goto fail;
1092 }
1093 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1094 }
1095
1096 /* Tx CMB. */
1097 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1098 (void **)&sc->ale_cdata.ale_tx_cmb,
1099 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1100 &sc->ale_cdata.ale_tx_cmb_map);
1101 if (error != 0) {
1102 device_printf(sc->ale_dev,
1103 "could not allocate DMA'able memory for Tx CMB.\n");
1104 goto fail;
1105 }
1106 ctx.ale_busaddr = 0;
1107 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1108 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1109 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1110 if (error != 0 || ctx.ale_busaddr == 0) {
1111 device_printf(sc->ale_dev,
1112 "could not load DMA'able memory for Tx CMB.\n");
1113 goto fail;
1114 }
1115 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1116
1117 /* Rx CMB. */
1118 for (i = 0; i < ALE_RX_PAGES; i++) {
1119 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1120 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1121 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1122 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1123 if (error != 0) {
1124 device_printf(sc->ale_dev, "could not allocate "
1125 "DMA'able memory for Rx page %d CMB.\n", i);
1126 goto fail;
1127 }
1128 ctx.ale_busaddr = 0;
1129 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1130 sc->ale_cdata.ale_rx_page[i].cmb_map,
1131 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1132 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1133 if (error != 0 || ctx.ale_busaddr == 0) {
1134 device_printf(sc->ale_dev, "could not load DMA'able "
1135 "memory for Rx page %d CMB.\n", i);
1136 goto fail;
1137 }
1138 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1139 }
1140
1141 /*
1142 * Tx descriptors/RXF0/CMB DMA blocks share the same
1143 * high address region of 64bit DMA address space.
1144 */
1145 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1146 (error = ale_check_boundary(sc)) != 0) {
1147 device_printf(sc->ale_dev, "4GB boundary crossed, "
1148 "switching to 32bit DMA addressing mode.\n");
1149 ale_dma_free(sc);
1150 /*
1151 * Limit max allowable DMA address space to 32bit
1152 * and try again.
1153 */
1154 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1155 goto again;
1156 }
1157
1158 /*
1159 * Create Tx buffer parent tag.
1160 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1161 * needs separate parent DMA tag as parent DMA address space
1162 * could be restricted to be within 32bit address space by
1163 * 4GB boundary crossing.
1164 */
1165 error = bus_dma_tag_create(
1166 NULL, /* parent */
1167 1, 0, /* alignment, boundary */
1168 BUS_SPACE_MAXADDR, /* lowaddr */
1169 BUS_SPACE_MAXADDR, /* highaddr */
1170 NULL, NULL, /* filter, filterarg */
1171 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1172 0, /* nsegments */
1173 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1174 0, /* flags */
1175 &sc->ale_cdata.ale_buffer_tag);
1176 if (error != 0) {
1177 device_printf(sc->ale_dev,
1178 "could not create parent buffer DMA tag.\n");
1179 goto fail;
1180 }
1181
1182 /* Create DMA tag for Tx buffers. */
1183 error = bus_dma_tag_create(
1184 sc->ale_cdata.ale_buffer_tag, /* parent */
1185 1, 0, /* alignment, boundary */
1186 BUS_SPACE_MAXADDR, /* lowaddr */
1187 BUS_SPACE_MAXADDR, /* highaddr */
1188 NULL, NULL, /* filter, filterarg */
1189 ALE_TSO_MAXSIZE, /* maxsize */
1190 ALE_MAXTXSEGS, /* nsegments */
1191 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1192 0, /* flags */
1193 &sc->ale_cdata.ale_tx_tag);
1194 if (error != 0) {
1195 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1196 goto fail;
1197 }
1198
1199 /* Create DMA maps for Tx buffers. */
1200 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1201 txd = &sc->ale_cdata.ale_txdesc[i];
1202 txd->tx_m = NULL;
1203 txd->tx_dmamap = NULL;
1204 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1205 &txd->tx_dmamap);
1206 if (error != 0) {
1207 device_printf(sc->ale_dev,
1208 "could not create Tx dmamap.\n");
1209 goto fail;
1210 }
1211 }
1212fail:
1213 return (error);
1214}
1215
1216static void
1217ale_dma_free(struct ale_softc *sc)
1218{
1219 struct ale_txdesc *txd;
1220 int i;
1221
1222 /* Tx buffers. */
1223 if (sc->ale_cdata.ale_tx_tag != NULL) {
1224 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1225 txd = &sc->ale_cdata.ale_txdesc[i];
1226 if (txd->tx_dmamap != NULL) {
1227 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1228 txd->tx_dmamap);
1229 txd->tx_dmamap = NULL;
1230 }
1231 }
1232 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1233 sc->ale_cdata.ale_tx_tag = NULL;
1234 }
1235 /* Tx descriptor ring. */
1236 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1237 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1238 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1239 sc->ale_cdata.ale_tx_ring_map);
1240 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1241 sc->ale_cdata.ale_tx_ring != NULL)
1242 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1243 sc->ale_cdata.ale_tx_ring,
1244 sc->ale_cdata.ale_tx_ring_map);
1245 sc->ale_cdata.ale_tx_ring = NULL;
1246 sc->ale_cdata.ale_tx_ring_map = NULL;
1247 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1248 sc->ale_cdata.ale_tx_ring_tag = NULL;
1249 }
1250 /* Rx page block. */
1251 for (i = 0; i < ALE_RX_PAGES; i++) {
1252 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1253 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1254 bus_dmamap_unload(
1255 sc->ale_cdata.ale_rx_page[i].page_tag,
1256 sc->ale_cdata.ale_rx_page[i].page_map);
1257 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1258 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1259 bus_dmamem_free(
1260 sc->ale_cdata.ale_rx_page[i].page_tag,
1261 sc->ale_cdata.ale_rx_page[i].page_addr,
1262 sc->ale_cdata.ale_rx_page[i].page_map);
1263 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1264 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1265 bus_dma_tag_destroy(
1266 sc->ale_cdata.ale_rx_page[i].page_tag);
1267 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1268 }
1269 }
1270 /* Rx CMB. */
1271 for (i = 0; i < ALE_RX_PAGES; i++) {
1272 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1273 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1274 bus_dmamap_unload(
1275 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1276 sc->ale_cdata.ale_rx_page[i].cmb_map);
1277 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1278 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1279 bus_dmamem_free(
1280 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1281 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1282 sc->ale_cdata.ale_rx_page[i].cmb_map);
1283 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1284 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1285 bus_dma_tag_destroy(
1286 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1287 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1288 }
1289 }
1290 /* Tx CMB. */
1291 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1292 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1293 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1294 sc->ale_cdata.ale_tx_cmb_map);
1295 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1296 sc->ale_cdata.ale_tx_cmb != NULL)
1297 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1298 sc->ale_cdata.ale_tx_cmb,
1299 sc->ale_cdata.ale_tx_cmb_map);
1300 sc->ale_cdata.ale_tx_cmb = NULL;
1301 sc->ale_cdata.ale_tx_cmb_map = NULL;
1302 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1303 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1304 }
1305 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1306 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1307 sc->ale_cdata.ale_buffer_tag = NULL;
1308 }
1309 if (sc->ale_cdata.ale_parent_tag != NULL) {
1310 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1311 sc->ale_cdata.ale_parent_tag = NULL;
1312 }
1313}
1314
1315static int
1316ale_shutdown(device_t dev)
1317{
1318 return (ale_suspend(dev));
1319}
1320
1321#ifdef notyet
1322
1323/*
1324 * Note, this driver resets the link speed to 10/100Mbps by
1325 * restarting auto-negotiation in suspend/shutdown phase but we
1326 * don't know whether that auto-negotiation would succeed or not
1327 * as driver has no control after powering off/suspend operation.
1328 * If the renegotiation fail WOL may not work. Running at 1Gbps
1329 * will draw more power than 375mA at 3.3V which is specified in
1330 * PCI specification and that would result in complete
1331 * shutdowning power to ethernet controller.
1332 *
1333 * TODO
1334 * Save current negotiated media speed/duplex/flow-control to
1335 * softc and restore the same link again after resuming. PHY
1336 * handling such as power down/resetting to 100Mbps may be better
1337 * handled in suspend method in phy driver.
1338 */
1339static void
1340ale_setlinkspeed(struct ale_softc *sc)
1341{
1342 struct mii_data *mii;
1343 int aneg, i;
1344
1345 mii = device_get_softc(sc->ale_miibus);
1346 mii_pollstat(mii);
1347 aneg = 0;
1348 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1349 (IFM_ACTIVE | IFM_AVALID)) {
1350 switch IFM_SUBTYPE(mii->mii_media_active) {
1351 case IFM_10_T:
1352 case IFM_100_TX:
1353 return;
1354 case IFM_1000_T:
1355 aneg++;
1356 break;
1357 default:
1358 break;
1359 }
1360 }
1361 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1362 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1363 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1364 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1365 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1366 DELAY(1000);
1367 if (aneg != 0) {
1368 /*
1369 * Poll link state until ale(4) get a 10/100Mbps link.
1370 */
1371 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1372 mii_pollstat(mii);
1373 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1374 == (IFM_ACTIVE | IFM_AVALID)) {
1375 switch (IFM_SUBTYPE(
1376 mii->mii_media_active)) {
1377 case IFM_10_T:
1378 case IFM_100_TX:
1379 ale_mac_config(sc);
1380 return;
1381 default:
1382 break;
1383 }
1384 }
1385 ALE_UNLOCK(sc);
1386 pause("alelnk", hz);
1387 ALE_LOCK(sc);
1388 }
1389 if (i == MII_ANEGTICKS_GIGE)
1390 device_printf(sc->ale_dev,
1391 "establishing a link failed, WOL may not work!");
1392 }
1393 /*
1394 * No link, force MAC to have 100Mbps, full-duplex link.
1395 * This is the last resort and may/may not work.
1396 */
1397 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1398 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1399 ale_mac_config(sc);
1400}
1401
1402static void
1403ale_setwol(struct ale_softc *sc)
1404{
1405 struct ifnet *ifp;
1406 uint32_t reg, pmcs;
1407 uint16_t pmstat;
1408 int pmc;
1409
1410 ALE_LOCK_ASSERT(sc);
1411
1412 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1413 /* Disable WOL. */
1414 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1415 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1416 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1417 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1418 /* Force PHY power down. */
1419 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1420 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1421 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1422 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1423 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1424 return;
1425 }
1426
1427 ifp = sc->ale_ifp;
1428 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1429 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1430 ale_setlinkspeed(sc);
1431 }
1432
1433 pmcs = 0;
1434 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1435 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1436 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1437 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1438 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1439 MAC_CFG_BCAST);
1440 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1441 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1442 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1443 reg |= MAC_CFG_RX_ENB;
1444 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1445
1446 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1447 /* WOL disabled, PHY power down. */
1448 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1449 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1450 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1451 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1452 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1453 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1454 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1455 GPHY_CTRL_PWDOWN_HW);
1456 }
1457 /* Request PME. */
1458 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1459 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1460 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1461 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1462 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1463}
1464
1465#endif /* notyet */
1466
1467static int
1468ale_suspend(device_t dev)
1469{
1470 struct ale_softc *sc = device_get_softc(dev);
1471 struct ifnet *ifp = &sc->arpcom.ac_if;
1472
1473 lwkt_serialize_enter(ifp->if_serializer);
1474 ale_stop(sc);
1475#ifdef notyet
1476 ale_setwol(sc);
1477#endif
1478 lwkt_serialize_exit(ifp->if_serializer);
1479 return (0);
1480}
1481
1482static int
1483ale_resume(device_t dev)
1484{
1485 struct ale_softc *sc = device_get_softc(dev);
1486 struct ifnet *ifp = &sc->arpcom.ac_if;
1487 uint16_t cmd;
1488
1489 lwkt_serialize_enter(ifp->if_serializer);
1490
1491 /*
1492 * Clear INTx emulation disable for hardwares that
1493 * is set in resume event. From Linux.
1494 */
1495 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
1496 if ((cmd & 0x0400) != 0) {
1497 cmd &= ~0x0400;
1498 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
1499 }
1500
1501#ifdef notyet
1502 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1503 uint16_t pmstat;
1504 int pmc;
1505
1506 /* Disable PME and clear PME status. */
1507 pmstat = pci_read_config(sc->ale_dev,
1508 pmc + PCIR_POWER_STATUS, 2);
1509 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1510 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1511 pci_write_config(sc->ale_dev,
1512 pmc + PCIR_POWER_STATUS, pmstat, 2);
1513 }
1514 }
1515#endif
1516
1517 /* Reset PHY. */
1518 ale_phy_reset(sc);
1519 if ((ifp->if_flags & IFF_UP) != 0)
1520 ale_init(sc);
1521
1522 lwkt_serialize_exit(ifp->if_serializer);
1523 return (0);
1524}
1525
1526static int
1527ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1528{
1529 struct ale_txdesc *txd, *txd_last;
1530 struct tx_desc *desc;
1531 struct mbuf *m;
1532 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1533 struct ale_dmamap_ctx ctx;
1534 bus_dmamap_t map;
1535 uint32_t cflags, poff, vtag;
1536 int error, i, nsegs, prod, si;
1537
1538 M_ASSERTPKTHDR((*m_head));
1539
1540 m = *m_head;
1541 cflags = vtag = 0;
1542 poff = 0;
1543
1544 si = prod = sc->ale_cdata.ale_tx_prod;
1545 txd = &sc->ale_cdata.ale_txdesc[prod];
1546 txd_last = txd;
1547 map = txd->tx_dmamap;
1548
1549 ctx.nsegs = ALE_MAXTXSEGS;
1550 ctx.segs = txsegs;
1551 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1552 *m_head, ale_dmamap_buf_cb, &ctx,
1553 BUS_DMA_NOWAIT);
1554 if (error == EFBIG) {
1555 m = m_defrag(*m_head, MB_DONTWAIT);
1556 if (m == NULL) {
1557 m_freem(*m_head);
1558 *m_head = NULL;
1559 return (ENOMEM);
1560 }
1561 *m_head = m;
1562
1563 ctx.nsegs = ALE_MAXTXSEGS;
1564 ctx.segs = txsegs;
1565 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1566 *m_head, ale_dmamap_buf_cb, &ctx,
1567 BUS_DMA_NOWAIT);
1568 if (error != 0) {
1569 m_freem(*m_head);
1570 *m_head = NULL;
1571 return (error);
1572 }
1573 } else if (error != 0) {
1574 return (error);
1575 }
1576 nsegs = ctx.nsegs;
1577
1578 if (nsegs == 0) {
1579 m_freem(*m_head);
1580 *m_head = NULL;
1581 return (EIO);
1582 }
1583
1584 /* Check descriptor overrun. */
1585 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) {
1586 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1587 return (ENOBUFS);
1588 }
1589 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1590
1591 m = *m_head;
1592 /* Configure Tx checksum offload. */
1593 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1594 /*
1595 * AR81xx supports Tx custom checksum offload feature
1596 * that offloads single 16bit checksum computation.
1597 * So you can choose one among IP, TCP and UDP.
1598 * Normally driver sets checksum start/insertion
1599 * position from the information of TCP/UDP frame as
1600 * TCP/UDP checksum takes more time than that of IP.
1601 * However it seems that custom checksum offload
1602 * requires 4 bytes aligned Tx buffers due to hardware
1603 * bug.
1604 * AR81xx also supports explicit Tx checksum computation
1605 * if it is told that the size of IP header and TCP
1606 * header(for UDP, the header size does not matter
1607 * because it's fixed length). However with this scheme
1608 * TSO does not work so you have to choose one either
1609 * TSO or explicit Tx checksum offload. I chosen TSO
1610 * plus custom checksum offload with work-around which
1611 * will cover most common usage for this consumer
1612 * ethernet controller. The work-around takes a lot of
1613 * CPU cycles if Tx buffer is not aligned on 4 bytes
1614 * boundary, though.
1615 */
1616 cflags |= ALE_TD_CXSUM;
1617 /* Set checksum start offset. */
1618 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1619 /* Set checksum insertion position of TCP/UDP. */
1620 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1621 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1622 }
1623
1624 /* Configure VLAN hardware tag insertion. */
1625 if ((m->m_flags & M_VLANTAG) != 0) {
1626 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag);
1627 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1628 cflags |= ALE_TD_INSERT_VLAN_TAG;
1629 }
1630
1631 desc = NULL;
1632 for (i = 0; i < nsegs; i++) {
1633 desc = &sc->ale_cdata.ale_tx_ring[prod];
1634 desc->addr = htole64(txsegs[i].ds_addr);
1635 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1636 desc->flags = htole32(cflags);
1637 sc->ale_cdata.ale_tx_cnt++;
1638 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1639 }
1640 /* Update producer index. */
1641 sc->ale_cdata.ale_tx_prod = prod;
1642
1643 /* Finally set EOP on the last descriptor. */
1644 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1645 desc = &sc->ale_cdata.ale_tx_ring[prod];
1646 desc->flags |= htole32(ALE_TD_EOP);
1647
1648 /* Swap dmamap of the first and the last. */
1649 txd = &sc->ale_cdata.ale_txdesc[prod];
1650 map = txd_last->tx_dmamap;
1651 txd_last->tx_dmamap = txd->tx_dmamap;
1652 txd->tx_dmamap = map;
1653 txd->tx_m = m;
1654
1655 /* Sync descriptors. */
1656 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1657 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE);
1658
1659 return (0);
1660}
1661
1662static void
1663ale_start(struct ifnet *ifp)
1664{
1665 struct ale_softc *sc = ifp->if_softc;
1666 struct mbuf *m_head;
1667 int enq;
1668
1669 ASSERT_SERIALIZED(ifp->if_serializer);
1670
1671 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1672 ifq_purge(&ifp->if_snd);
1673 return;
1674 }
1675
1676 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1677 return;
1678
1679 /* Reclaim transmitted frames. */
1680 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1681 ale_txeof(sc);
1682
1683 enq = 0;
1684 while (!ifq_is_empty(&ifp->if_snd)) {
1685 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1686 if (m_head == NULL)
1687 break;
1688
1689 /*
1690 * Pack the data into the transmit ring. If we
1691 * don't have room, set the OACTIVE flag and wait
1692 * for the NIC to drain the ring.
1693 */
1694 if (ale_encap(sc, &m_head)) {
1695 if (m_head == NULL)
1696 break;
1697 ifq_prepend(&ifp->if_snd, m_head);
1698 ifp->if_flags |= IFF_OACTIVE;
1699 break;
1700 }
1701 enq = 1;
1702
1703 /*
1704 * If there's a BPF listener, bounce a copy of this frame
1705 * to him.
1706 */
1707 ETHER_BPF_MTAP(ifp, m_head);
1708 }
1709
1710 if (enq) {
1711 /* Kick. */
1712 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1713 sc->ale_cdata.ale_tx_prod);
1714
1715 /* Set a timeout in case the chip goes out to lunch. */
1716 ifp->if_timer = ALE_TX_TIMEOUT;
1717 }
1718}
1719
1720static void
1721ale_watchdog(struct ifnet *ifp)
1722{
1723 struct ale_softc *sc = ifp->if_softc;
1724
1725 ASSERT_SERIALIZED(ifp->if_serializer);
1726
1727 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1728 if_printf(ifp, "watchdog timeout (lost link)\n");
1729 ifp->if_oerrors++;
1730 ale_init(sc);
1731 return;
1732 }
1733
1734 if_printf(ifp, "watchdog timeout -- resetting\n");
1735 ifp->if_oerrors++;
1736 ale_init(sc);
1737
1738 if (!ifq_is_empty(&ifp->if_snd))
1739 if_devstart(ifp);
1740}
1741
1742static int
1743ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1744{
1745 struct ale_softc *sc;
1746 struct ifreq *ifr;
1747 struct mii_data *mii;
1748 int error, mask;
1749
1750 ASSERT_SERIALIZED(ifp->if_serializer);
1751
1752 sc = ifp->if_softc;
1753 ifr = (struct ifreq *)data;
1754 error = 0;
1755
1756 switch (cmd) {
1757 case SIOCSIFMTU:
1758 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1759 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1760 ifr->ifr_mtu > ETHERMTU))
1761 error = EINVAL;
1762 else if (ifp->if_mtu != ifr->ifr_mtu) {
1763 ifp->if_mtu = ifr->ifr_mtu;
1764 if ((ifp->if_flags & IFF_RUNNING) != 0)
1765 ale_init(sc);
1766 }
1767 break;
1768
1769 case SIOCSIFFLAGS:
1770 if ((ifp->if_flags & IFF_UP) != 0) {
1771 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1772 if (((ifp->if_flags ^ sc->ale_if_flags)
1773 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1774 ale_rxfilter(sc);
1775 } else {
1776 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1777 ale_init(sc);
1778 }
1779 } else {
1780 if ((ifp->if_flags & IFF_RUNNING) != 0)
1781 ale_stop(sc);
1782 }
1783 sc->ale_if_flags = ifp->if_flags;
1784 break;
1785
1786 case SIOCADDMULTI:
1787 case SIOCDELMULTI:
1788 if ((ifp->if_flags & IFF_RUNNING) != 0)
1789 ale_rxfilter(sc);
1790 break;
1791
1792 case SIOCSIFMEDIA:
1793 case SIOCGIFMEDIA:
1794 mii = device_get_softc(sc->ale_miibus);
1795 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1796 break;
1797
1798 case SIOCSIFCAP:
1799 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1800 if ((mask & IFCAP_TXCSUM) != 0 &&
1801 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1802 ifp->if_capenable ^= IFCAP_TXCSUM;
1803 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1804 ifp->if_hwassist |= ALE_CSUM_FEATURES;
1805 else
1806 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
1807 }
1808 if ((mask & IFCAP_RXCSUM) != 0 &&
1809 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1810 ifp->if_capenable ^= IFCAP_RXCSUM;
1811
1812 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1813 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1814 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1815 ale_rxvlan(sc);
1816 }
1817 break;
1818
1819 default:
1820 error = ether_ioctl(ifp, cmd, data);
1821 break;
1822 }
1823 return (error);
1824}
1825
1826static void
1827ale_mac_config(struct ale_softc *sc)
1828{
1829 struct mii_data *mii;
1830 uint32_t reg;
1831
1832 mii = device_get_softc(sc->ale_miibus);
1833 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1834 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
1835 MAC_CFG_SPEED_MASK);
1836 /* Reprogram MAC with resolved speed/duplex. */
1837 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1838 case IFM_10_T:
1839 case IFM_100_TX:
1840 reg |= MAC_CFG_SPEED_10_100;
1841 break;
1842 case IFM_1000_T:
1843 reg |= MAC_CFG_SPEED_1000;
1844 break;
1845 }
1846 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1847 reg |= MAC_CFG_FULL_DUPLEX;
1848#ifdef notyet
1849 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1850 reg |= MAC_CFG_TX_FC;
1851 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1852 reg |= MAC_CFG_RX_FC;
1853#endif
1854 }
1855 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1856}
1857
1858static void
1859ale_stats_clear(struct ale_softc *sc)
1860{
1861 struct smb sb;
1862 uint32_t *reg;
1863 int i;
1864
1865 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1866 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1867 i += sizeof(uint32_t);
1868 }
1869 /* Read Tx statistics. */
1870 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1871 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1872 i += sizeof(uint32_t);
1873 }
1874}
1875
1876static void
1877ale_stats_update(struct ale_softc *sc)
1878{
1879 struct ale_hw_stats *stat;
1880 struct smb sb, *smb;
1881 struct ifnet *ifp;
1882 uint32_t *reg;
1883 int i;
1884
1885 ifp = &sc->arpcom.ac_if;
1886 stat = &sc->ale_stats;
1887 smb = &sb;
1888
1889 /* Read Rx statistics. */
1890 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1891 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1892 i += sizeof(uint32_t);
1893 }
1894 /* Read Tx statistics. */
1895 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1896 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1897 i += sizeof(uint32_t);
1898 }
1899
1900 /* Rx stats. */
1901 stat->rx_frames += smb->rx_frames;
1902 stat->rx_bcast_frames += smb->rx_bcast_frames;
1903 stat->rx_mcast_frames += smb->rx_mcast_frames;
1904 stat->rx_pause_frames += smb->rx_pause_frames;
1905 stat->rx_control_frames += smb->rx_control_frames;
1906 stat->rx_crcerrs += smb->rx_crcerrs;
1907 stat->rx_lenerrs += smb->rx_lenerrs;
1908 stat->rx_bytes += smb->rx_bytes;
1909 stat->rx_runts += smb->rx_runts;
1910 stat->rx_fragments += smb->rx_fragments;
1911 stat->rx_pkts_64 += smb->rx_pkts_64;
1912 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1913 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1914 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1915 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1916 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1917 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1918 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1919 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1920 stat->rx_rrs_errs += smb->rx_rrs_errs;
1921 stat->rx_alignerrs += smb->rx_alignerrs;
1922 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1923 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1924 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1925
1926 /* Tx stats. */
1927 stat->tx_frames += smb->tx_frames;
1928 stat->tx_bcast_frames += smb->tx_bcast_frames;
1929 stat->tx_mcast_frames += smb->tx_mcast_frames;
1930 stat->tx_pause_frames += smb->tx_pause_frames;
1931 stat->tx_excess_defer += smb->tx_excess_defer;
1932 stat->tx_control_frames += smb->tx_control_frames;
1933 stat->tx_deferred += smb->tx_deferred;
1934 stat->tx_bytes += smb->tx_bytes;
1935 stat->tx_pkts_64 += smb->tx_pkts_64;
1936 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1937 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1938 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1939 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1940 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1941 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1942 stat->tx_single_colls += smb->tx_single_colls;
1943 stat->tx_multi_colls += smb->tx_multi_colls;
1944 stat->tx_late_colls += smb->tx_late_colls;
1945 stat->tx_excess_colls += smb->tx_excess_colls;
1946 stat->tx_abort += smb->tx_abort;
1947 stat->tx_underrun += smb->tx_underrun;
1948 stat->tx_desc_underrun += smb->tx_desc_underrun;
1949 stat->tx_lenerrs += smb->tx_lenerrs;
1950 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1951 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1952 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1953
1954 /* Update counters in ifnet. */
1955 ifp->if_opackets += smb->tx_frames;
1956
1957 ifp->if_collisions += smb->tx_single_colls +
1958 smb->tx_multi_colls * 2 + smb->tx_late_colls +
1959 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
1960
1961 /*
1962 * XXX
1963 * tx_pkts_truncated counter looks suspicious. It constantly
1964 * increments with no sign of Tx errors. This may indicate
1965 * the counter name is not correct one so I've removed the
1966 * counter in output errors.
1967 */
1968 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
1969 smb->tx_underrun;
1970
1971 ifp->if_ipackets += smb->rx_frames;
1972
1973 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
1974 smb->rx_runts + smb->rx_pkts_truncated +
1975 smb->rx_fifo_oflows + smb->rx_rrs_errs +
1976 smb->rx_alignerrs;
1977}
1978
1979static void
1980ale_intr(void *xsc)
1981{
1982 struct ale_softc *sc = xsc;
1983 struct ifnet *ifp = &sc->arpcom.ac_if;
1984 uint32_t status;
1985
1986 ASSERT_SERIALIZED(ifp->if_serializer);
1987
1988 status = CSR_READ_4(sc, ALE_INTR_STATUS);
1989 if ((status & ALE_INTRS) == 0)
1990 return;
1991
1992 /* Acknowledge and disable interrupts. */
1993 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1994
1995 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1996 int error;
1997
1998 error = ale_rxeof(sc);
1999 if (error) {
2000 sc->ale_stats.reset_brk_seq++;
2001 ale_init(sc);
2002 return;
2003 }
2004
2005 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2006 if ((status & INTR_DMA_RD_TO_RST) != 0)
2007 device_printf(sc->ale_dev,
2008 "DMA read error! -- resetting\n");
2009 if ((status & INTR_DMA_WR_TO_RST) != 0)
2010 device_printf(sc->ale_dev,
2011 "DMA write error! -- resetting\n");
2012 ale_init(sc);
2013 return;
2014 }
2015
2016 ale_txeof(sc);
2017 if (!ifq_is_empty(&ifp->if_snd))
2018 if_devstart(ifp);
2019 }
2020
2021 /* Re-enable interrupts. */
2022 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2023}
2024
2025static void
2026ale_txeof(struct ale_softc *sc)
2027{
2028 struct ifnet *ifp = &sc->arpcom.ac_if;
2029 struct ale_txdesc *txd;
2030 uint32_t cons, prod;
2031 int prog;
2032
2033 if (sc->ale_cdata.ale_tx_cnt == 0)
2034 return;
2035
2036 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2037 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD);
2038 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2039 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2040 sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD);
2041 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2042 } else
2043 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2044 cons = sc->ale_cdata.ale_tx_cons;
2045 /*
2046 * Go through our Tx list and free mbufs for those
2047 * frames which have been transmitted.
2048 */
2049 for (prog = 0; cons != prod; prog++,
2050 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2051 if (sc->ale_cdata.ale_tx_cnt <= 0)
2052 break;
2053 prog++;
2054 ifp->if_flags &= ~IFF_OACTIVE;
2055 sc->ale_cdata.ale_tx_cnt--;
2056 txd = &sc->ale_cdata.ale_txdesc[cons];
2057 if (txd->tx_m != NULL) {
2058 /* Reclaim transmitted mbufs. */
2059 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2060 txd->tx_dmamap);
2061 m_freem(txd->tx_m);
2062 txd->tx_m = NULL;
2063 }
2064 }
2065
2066 if (prog > 0) {
2067 sc->ale_cdata.ale_tx_cons = cons;
2068 /*
2069 * Unarm watchdog timer only when there is no pending
2070 * Tx descriptors in queue.
2071 */
2072 if (sc->ale_cdata.ale_tx_cnt == 0)
2073 ifp->if_timer = 0;
2074 }
2075}
2076
2077static void
2078ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2079 uint32_t length, uint32_t *prod)
2080{
2081 struct ale_rx_page *rx_page;
2082
2083 rx_page = *page;
2084 /* Update consumer position. */
2085 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2086 ALE_RX_PAGE_ALIGN);
2087 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2088 /*
2089 * End of Rx page reached, let hardware reuse
2090 * this page.
2091 */
2092 rx_page->cons = 0;
2093 *rx_page->cmb_addr = 0;
2094 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2095 BUS_DMASYNC_PREWRITE);
2096 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2097 RXF_VALID);
2098 /* Switch to alternate Rx page. */
2099 sc->ale_cdata.ale_rx_curp ^= 1;
2100 rx_page = *page =
2101 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2102 /* Page flipped, sync CMB and Rx page. */
2103 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2104 BUS_DMASYNC_POSTREAD);
2105 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2106 BUS_DMASYNC_POSTREAD);
2107 /* Sync completed, cache updated producer index. */
2108 *prod = *rx_page->cmb_addr;
2109 }
2110}
2111
2112
2113/*
2114 * It seems that AR81xx controller can compute partial checksum.
2115 * The partial checksum value can be used to accelerate checksum
2116 * computation for fragmented TCP/UDP packets. Upper network stack
2117 * already takes advantage of the partial checksum value in IP
2118 * reassembly stage. But I'm not sure the correctness of the
2119 * partial hardware checksum assistance due to lack of data sheet.
2120 * In addition, the Rx feature of controller that requires copying
2121 * for every frames effectively nullifies one of most nice offload
2122 * capability of controller.
2123 */
2124static void
2125ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2126{
2127 struct ifnet *ifp = &sc->arpcom.ac_if;
2128 struct ip *ip;
2129 char *p;
2130
2131 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2132 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2133 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2134
2135 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2136 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2137 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2138 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2139 m->m_pkthdr.csum_flags |=
2140 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2141 m->m_pkthdr.csum_data = 0xffff;
2142 }
2143 } else {
2144 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2145 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2146 p = mtod(m, char *);
2147 p += ETHER_HDR_LEN;
2148 if ((status & ALE_RD_802_3) != 0)
2149 p += LLC_SNAPFRAMELEN;
2150 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2151 (status & ALE_RD_VLAN) != 0)
2152 p += EVL_ENCAPLEN;
2153 ip = (struct ip *)p;
2154 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2155 return;
2156 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2157 CSUM_PSEUDO_HDR;
2158 m->m_pkthdr.csum_data = 0xffff;
2159 }
2160 }
2161 /*
2162 * Don't mark bad checksum for TCP/UDP frames
2163 * as fragmented frames may always have set
2164 * bad checksummed bit of frame status.
2165 */
2166}
2167
2168/* Process received frames. */
2169static int
2170ale_rxeof(struct ale_softc *sc)
2171{
2172 struct ifnet *ifp = &sc->arpcom.ac_if;
2173 struct ale_rx_page *rx_page;
2174 struct rx_rs *rs;
2175 struct mbuf *m;
2176 uint32_t length, prod, seqno, status, vtags;
2177 int prog;
2178
2179 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2180 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2181 BUS_DMASYNC_POSTREAD);
2182 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2183 BUS_DMASYNC_POSTREAD);
2184 /*
2185 * Don't directly access producer index as hardware may
2186 * update it while Rx handler is in progress. It would
2187 * be even better if there is a way to let hardware
2188 * know how far driver processed its received frames.
2189 * Alternatively, hardware could provide a way to disable
2190 * CMB updates until driver acknowledges the end of CMB
2191 * access.
2192 */
2193 prod = *rx_page->cmb_addr;
2194 for (prog = 0; ; prog++) {
2195 if (rx_page->cons >= prod)
2196 break;
2197 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2198 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2199 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2200 /*
2201 * Normally I believe this should not happen unless
2202 * severe driver bug or corrupted memory. However
2203 * it seems to happen under certain conditions which
2204 * is triggered by abrupt Rx events such as initiation
2205 * of bulk transfer of remote host. It's not easy to
2206 * reproduce this and I doubt it could be related
2207 * with FIFO overflow of hardware or activity of Tx
2208 * CMB updates. I also remember similar behaviour
2209 * seen on RealTek 8139 which uses resembling Rx
2210 * scheme.
2211 */
2212 if (bootverbose)
2213 device_printf(sc->ale_dev,
2214 "garbled seq: %u, expected: %u -- "
2215 "resetting!\n", seqno,
2216 sc->ale_cdata.ale_rx_seqno);
2217 return (EIO);
2218 }
2219 /* Frame received. */
2220 sc->ale_cdata.ale_rx_seqno++;
2221 length = ALE_RX_BYTES(le32toh(rs->length));
2222 status = le32toh(rs->flags);
2223 if ((status & ALE_RD_ERROR) != 0) {
2224 /*
2225 * We want to pass the following frames to upper
2226 * layer regardless of error status of Rx return
2227 * status.
2228 *
2229 * o IP/TCP/UDP checksum is bad.
2230 * o frame length and protocol specific length
2231 * does not match.
2232 */
2233 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2234 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2235 ALE_RD_TRUNC)) != 0) {
2236 ale_rx_update_page(sc, &rx_page, length, &prod);
2237 continue;
2238 }
2239 }
2240 /*
2241 * m_devget(9) is major bottle-neck of ale(4)(It comes
2242 * from hardware limitation). For jumbo frames we could
2243 * get a slightly better performance if driver use
2244 * m_getjcl(9) with proper buffer size argument. However
2245 * that would make code more complicated and I don't
2246 * think users would expect good Rx performance numbers
2247 * on these low-end consumer ethernet controller.
2248 */
2249 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2250 ETHER_ALIGN, ifp, NULL);
2251 if (m == NULL) {
2252 ifp->if_iqdrops++;
2253 ale_rx_update_page(sc, &rx_page, length, &prod);
2254 continue;
2255 }
2256 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2257 (status & ALE_RD_IPV4) != 0)
2258 ale_rxcsum(sc, m, status);
2259 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2260 (status & ALE_RD_VLAN) != 0) {
2261 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2262 m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags);
2263 m->m_flags |= M_VLANTAG;
2264 }
2265
2266 /* Pass it to upper layer. */
2267 ifp->if_input(ifp, m);
2268
2269 ale_rx_update_page(sc, &rx_page, length, &prod);
2270 }
2271 return 0;
2272}
2273
2274static void
2275ale_tick(void *xsc)
2276{
2277 struct ale_softc *sc = xsc;
2278 struct ifnet *ifp = &sc->arpcom.ac_if;
2279 struct mii_data *mii;
2280
2281 lwkt_serialize_enter(ifp->if_serializer);
2282
2283 mii = device_get_softc(sc->ale_miibus);
2284 mii_tick(mii);
2285 ale_stats_update(sc);
2286
2287 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2288
2289 lwkt_serialize_exit(ifp->if_serializer);
2290}
2291
2292static void
2293ale_reset(struct ale_softc *sc)
2294{
2295 uint32_t reg;
2296 int i;
2297
2298 /* Initialize PCIe module. From Linux. */
2299 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2300
2301 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2302 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2303 DELAY(10);
2304 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2305 break;
2306 }
2307 if (i == 0)
2308 device_printf(sc->ale_dev, "master reset timeout!\n");
2309
2310 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2311 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2312 break;
2313 DELAY(10);
2314 }
2315
2316 if (i == 0)
2317 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2318}
2319
2320static void
2321ale_init(void *xsc)
2322{
2323 struct ale_softc *sc = xsc;
2324 struct ifnet *ifp = &sc->arpcom.ac_if;
2325 struct mii_data *mii;
2326 uint8_t eaddr[ETHER_ADDR_LEN];
2327 bus_addr_t paddr;
2328 uint32_t reg, rxf_hi, rxf_lo;
2329
2330 ASSERT_SERIALIZED(ifp->if_serializer);
2331
2332 mii = device_get_softc(sc->ale_miibus);
2333
2334 /*
2335 * Cancel any pending I/O.
2336 */
2337 ale_stop(sc);
2338
2339 /*
2340 * Reset the chip to a known state.
2341 */
2342 ale_reset(sc);
2343
2344 /* Initialize Tx descriptors, DMA memory blocks. */
2345 ale_init_rx_pages(sc);
2346 ale_init_tx_ring(sc);
2347
2348 /* Reprogram the station address. */
2349 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2350 CSR_WRITE_4(sc, ALE_PAR0,
2351 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2352 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2353
2354 /*
2355 * Clear WOL status and disable all WOL feature as WOL
2356 * would interfere Rx operation under normal environments.
2357 */
2358 CSR_READ_4(sc, ALE_WOL_CFG);
2359 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2360
2361 /*
2362 * Set Tx descriptor/RXF0/CMB base addresses. They share
2363 * the same high address part of DMAable region.
2364 */
2365 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2366 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2367 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2368 CSR_WRITE_4(sc, ALE_TPD_CNT,
2369 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2370
2371 /* Set Rx page base address, note we use single queue. */
2372 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2373 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2374 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2375 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2376
2377 /* Set Tx/Rx CMB addresses. */
2378 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2379 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2380 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2381 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2382 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2383 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2384
2385 /* Mark RXF0 is valid. */
2386 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2387 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2388 /*
2389 * No need to initialize RFX1/RXF2/RXF3. We don't use
2390 * multi-queue yet.
2391 */
2392
2393 /* Set Rx page size, excluding guard frame size. */
2394 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2395
2396 /* Tell hardware that we're ready to load DMA blocks. */
2397 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2398
2399 /* Set Rx/Tx interrupt trigger threshold. */
2400 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2401 (4 << INT_TRIG_TX_THRESH_SHIFT));
2402 /*
2403 * XXX
2404 * Set interrupt trigger timer, its purpose and relation
2405 * with interrupt moderation mechanism is not clear yet.
2406 */
2407 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2408 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2409 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2410
2411 /* Configure interrupt moderation timer. */
2412 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2413 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2414 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2415 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2416 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2417 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2418 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2419 reg |= MASTER_IM_RX_TIMER_ENB;
2420 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2421 reg |= MASTER_IM_TX_TIMER_ENB;
2422 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2423 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2424
2425 /* Set Maximum frame size of controller. */
2426 if (ifp->if_mtu < ETHERMTU)
2427 sc->ale_max_frame_size = ETHERMTU;
2428 else
2429 sc->ale_max_frame_size = ifp->if_mtu;
2430 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN;
2431 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2432
2433 /* Configure IPG/IFG parameters. */
2434 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2435 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2436 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2437 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2438 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2439
2440 /* Set parameters for half-duplex media. */
2441 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2442 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2443 HDPX_CFG_LCOL_MASK) |
2444 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2445 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2446 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2447 HDPX_CFG_ABEBT_MASK) |
2448 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2449 HDPX_CFG_JAMIPG_MASK));
2450
2451 /* Configure Tx jumbo frame parameters. */
2452 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2453 if (ifp->if_mtu < ETHERMTU)
2454 reg = sc->ale_max_frame_size;
2455 else if (ifp->if_mtu < 6 * 1024)
2456 reg = (sc->ale_max_frame_size * 2) / 3;
2457 else
2458 reg = sc->ale_max_frame_size / 2;
2459 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2460 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2461 TX_JUMBO_THRESH_UNIT_SHIFT);
2462 }
2463
2464 /* Configure TxQ. */
2465 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2466 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2467 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2468 TXQ_CFG_TPD_BURST_MASK;
2469 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2470
2471 /* Configure Rx jumbo frame & flow control parameters. */
2472 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2473 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2474 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2475 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2476 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2477 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2478 RX_JUMBO_LKAH_MASK));
2479 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2480 rxf_hi = (reg * 7) / 10;
2481 rxf_lo = (reg * 3)/ 10;
2482 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2483 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2484 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2485 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2486 RX_FIFO_PAUSE_THRESH_HI_MASK));
2487 }
2488
2489 /* Disable RSS. */
2490 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2491 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2492
2493 /* Configure RxQ. */
2494 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2495 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2496
2497 /* Configure DMA parameters. */
2498 reg = 0;
2499 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2500 reg |= DMA_CFG_TXCMB_ENB;
2501 CSR_WRITE_4(sc, ALE_DMA_CFG,
2502 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2503 sc->ale_dma_rd_burst | reg |
2504 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2505 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2506 DMA_CFG_RD_DELAY_CNT_MASK) |
2507 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2508 DMA_CFG_WR_DELAY_CNT_MASK));
2509
2510 /*
2511 * Hardware can be configured to issue SMB interrupt based
2512 * on programmed interval. Since there is a callout that is
2513 * invoked for every hz in driver we use that instead of
2514 * relying on periodic SMB interrupt.
2515 */
2516 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2517
2518 /* Clear MAC statistics. */
2519 ale_stats_clear(sc);
2520
2521 /*
2522 * Configure Tx/Rx MACs.
2523 * - Auto-padding for short frames.
2524 * - Enable CRC generation.
2525 * Actual reconfiguration of MAC for resolved speed/duplex
2526 * is followed after detection of link establishment.
2527 * AR81xx always does checksum computation regardless of
2528 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2529 * cause Rx handling issue for fragmented IP datagrams due
2530 * to silicon bug.
2531 */
2532 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2533 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2534 MAC_CFG_PREAMBLE_MASK);
2535 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2536 reg |= MAC_CFG_SPEED_10_100;
2537 else
2538 reg |= MAC_CFG_SPEED_1000;
2539 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2540
2541 /* Set up the receive filter. */
2542 ale_rxfilter(sc);
2543 ale_rxvlan(sc);
2544
2545 /* Acknowledge all pending interrupts and clear it. */
2546 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2547 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2548 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2549
2550 sc->ale_flags &= ~ALE_FLAG_LINK;
2551
2552 /* Switch to the current media. */
2553 mii_mediachg(mii);
2554
2555 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2556
2557 ifp->if_flags |= IFF_RUNNING;
2558 ifp->if_flags &= ~IFF_OACTIVE;
2559}
2560
2561static void
2562ale_stop(struct ale_softc *sc)
2563{
2564 struct ifnet *ifp = &sc->arpcom.ac_if;
2565 struct ale_txdesc *txd;
2566 uint32_t reg;
2567 int i;
2568
2569 ASSERT_SERIALIZED(ifp->if_serializer);
2570
2571 /*
2572 * Mark the interface down and cancel the watchdog timer.
2573 */
2574 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2575 ifp->if_timer = 0;
2576
2577 callout_stop(&sc->ale_tick_ch);
2578 sc->ale_flags &= ~ALE_FLAG_LINK;
2579
2580 ale_stats_update(sc);
2581
2582 /* Disable interrupts. */
2583 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2584 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2585
2586 /* Disable queue processing and DMA. */
2587 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2588 reg &= ~TXQ_CFG_ENB;
2589 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2590 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2591 reg &= ~RXQ_CFG_ENB;
2592 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2593 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2594 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2595 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2596 DELAY(1000);
2597
2598 /* Stop Rx/Tx MACs. */
2599 ale_stop_mac(sc);
2600
2601 /* Disable interrupts again? XXX */
2602 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2603
2604 /*
2605 * Free TX mbufs still in the queues.
2606 */
2607 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2608 txd = &sc->ale_cdata.ale_txdesc[i];
2609 if (txd->tx_m != NULL) {
2610 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2611 txd->tx_dmamap);
2612 m_freem(txd->tx_m);
2613 txd->tx_m = NULL;
2614 }
2615 }
2616}
2617
2618static void
2619ale_stop_mac(struct ale_softc *sc)
2620{
2621 uint32_t reg;
2622 int i;
2623
2624 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2625 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2626 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2627 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2628 }
2629
2630 for (i = ALE_TIMEOUT; i > 0; i--) {
2631 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2632 if (reg == 0)
2633 break;
2634 DELAY(10);
2635 }
2636 if (i == 0)
2637 device_printf(sc->ale_dev,
2638 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2639}
2640
2641static void
2642ale_init_tx_ring(struct ale_softc *sc)
2643{
2644 struct ale_txdesc *txd;
2645 int i;
2646
2647 sc->ale_cdata.ale_tx_prod = 0;
2648 sc->ale_cdata.ale_tx_cons = 0;
2649 sc->ale_cdata.ale_tx_cnt = 0;
2650
2651 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2652 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2653 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2654 txd = &sc->ale_cdata.ale_txdesc[i];
2655 txd->tx_m = NULL;
2656 }
2657 *sc->ale_cdata.ale_tx_cmb = 0;
2658 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2659 sc->ale_cdata.ale_tx_cmb_map,
2660 BUS_DMASYNC_PREWRITE);
2661 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2662 sc->ale_cdata.ale_tx_ring_map,
2663 BUS_DMASYNC_PREWRITE);
2664}
2665
2666static void
2667ale_init_rx_pages(struct ale_softc *sc)
2668{
2669 struct ale_rx_page *rx_page;
2670 int i;
2671
2672 sc->ale_cdata.ale_rx_seqno = 0;
2673 sc->ale_cdata.ale_rx_curp = 0;
2674
2675 for (i = 0; i < ALE_RX_PAGES; i++) {
2676 rx_page = &sc->ale_cdata.ale_rx_page[i];
2677 bzero(rx_page->page_addr, sc->ale_pagesize);
2678 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2679 rx_page->cons = 0;
2680 *rx_page->cmb_addr = 0;
2681 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2682 BUS_DMASYNC_PREWRITE);
2683 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2684 BUS_DMASYNC_PREWRITE);
2685 }
2686}
2687
2688static void
2689ale_rxvlan(struct ale_softc *sc)
2690{
2691 struct ifnet *ifp;
2692 uint32_t reg;
2693
2694 ifp = &sc->arpcom.ac_if;
2695 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2696 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2697 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2698 reg |= MAC_CFG_VLAN_TAG_STRIP;
2699 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2700}
2701
2702static void
2703ale_rxfilter(struct ale_softc *sc)
2704{
2705 struct ifnet *ifp;
2706 struct ifmultiaddr *ifma;
2707 uint32_t crc;
2708 uint32_t mchash[2];
2709 uint32_t rxcfg;
2710
2711 ifp = &sc->arpcom.ac_if;
2712
2713 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
2714 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2715 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2716 rxcfg |= MAC_CFG_BCAST;
2717 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2718 if ((ifp->if_flags & IFF_PROMISC) != 0)
2719 rxcfg |= MAC_CFG_PROMISC;
2720 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2721 rxcfg |= MAC_CFG_ALLMULTI;
2722 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
2723 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
2724 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2725 return;
2726 }
2727
2728 /* Program new filter. */
2729 bzero(mchash, sizeof(mchash));
2730
441d34b2 2731 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
99fe2010
SZ
2732 if (ifma->ifma_addr->sa_family != AF_LINK)
2733 continue;
2734 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2735 ifma->ifma_addr), ETHER_ADDR_LEN);
2736 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2737 }
2738
2739 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2740 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2741 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2742}
2743
2744static int
2745sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
2746{
2747 return (sysctl_int_range(oidp, arg1, arg2, req,
2748 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
2749}
2750
2751static void
2752ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
2753 bus_size_t mapsz __unused, int error)
2754{
2755 struct ale_dmamap_ctx *ctx = xctx;
2756 int i;
2757
2758 if (error)
2759 return;
2760
2761 if (nsegs > ctx->nsegs) {
2762 ctx->nsegs = 0;
2763 return;
2764 }
2765
2766 ctx->nsegs = nsegs;
2767 for (i = 0; i < nsegs; ++i)
2768 ctx->segs[i] = segs[i];
2769}