network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / emx / if_emx.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
3 *
4 * Copyright (c) 2001-2008, Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 *
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
35 *
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
64 * SUCH DAMAGE.
65 */
66
b3a7093f 67#include "opt_ifpoll.h"
8434a83b 68#include "opt_rss.h"
e6cde6e6 69#include "opt_emx.h"
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70
71#include <sys/param.h>
72#include <sys/bus.h>
73#include <sys/endian.h>
74#include <sys/interrupt.h>
75#include <sys/kernel.h>
76#include <sys/ktr.h>
77#include <sys/malloc.h>
78#include <sys/mbuf.h>
79#include <sys/proc.h>
80#include <sys/rman.h>
81#include <sys/serialize.h>
bc197380 82#include <sys/serialize2.h>
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83#include <sys/socket.h>
84#include <sys/sockio.h>
85#include <sys/sysctl.h>
86#include <sys/systm.h>
87
88#include <net/bpf.h>
89#include <net/ethernet.h>
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/if_dl.h>
93#include <net/if_media.h>
94#include <net/ifq_var.h>
89d8e73d 95#include <net/toeplitz.h>
9cc86e17 96#include <net/toeplitz2.h>
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97#include <net/vlan/if_vlan_var.h>
98#include <net/vlan/if_vlan_ether.h>
b3a7093f 99#include <net/if_poll.h>
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100
101#include <netinet/in_systm.h>
102#include <netinet/in.h>
103#include <netinet/ip.h>
104#include <netinet/tcp.h>
105#include <netinet/udp.h>
106
107#include <bus/pci/pcivar.h>
108#include <bus/pci/pcireg.h>
109
110#include <dev/netif/ig_hal/e1000_api.h>
111#include <dev/netif/ig_hal/e1000_82571.h>
112#include <dev/netif/emx/if_emx.h>
113
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114#ifdef EMX_RSS_DEBUG
115#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116do { \
89d8e73d 117 if (sc->rss_debug >= lvl) \
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118 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119} while (0)
120#else /* !EMX_RSS_DEBUG */
121#define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
122#endif /* EMX_RSS_DEBUG */
123
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124#define EMX_NAME "Intel(R) PRO/1000 "
125
126#define EMX_DEVICE(id) \
127 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
128#define EMX_DEVICE_NULL { 0, 0, NULL }
129
130static const struct emx_device {
131 uint16_t vid;
132 uint16_t did;
133 const char *desc;
134} emx_devices[] = {
135 EMX_DEVICE(82571EB_COPPER),
136 EMX_DEVICE(82571EB_FIBER),
137 EMX_DEVICE(82571EB_SERDES),
138 EMX_DEVICE(82571EB_SERDES_DUAL),
139 EMX_DEVICE(82571EB_SERDES_QUAD),
140 EMX_DEVICE(82571EB_QUAD_COPPER),
75a5634e 141 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
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142 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
143 EMX_DEVICE(82571EB_QUAD_FIBER),
144 EMX_DEVICE(82571PT_QUAD_COPPER),
145
146 EMX_DEVICE(82572EI_COPPER),
147 EMX_DEVICE(82572EI_FIBER),
148 EMX_DEVICE(82572EI_SERDES),
149 EMX_DEVICE(82572EI),
150
151 EMX_DEVICE(82573E),
152 EMX_DEVICE(82573E_IAMT),
153 EMX_DEVICE(82573L),
154
155 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
156 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
157 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
159
160 EMX_DEVICE(82574L),
161
162 /* required last entry */
163 EMX_DEVICE_NULL
164};
165
166static int emx_probe(device_t);
167static int emx_attach(device_t);
168static int emx_detach(device_t);
169static int emx_shutdown(device_t);
170static int emx_suspend(device_t);
171static int emx_resume(device_t);
172
173static void emx_init(void *);
174static void emx_stop(struct emx_softc *);
175static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
176static void emx_start(struct ifnet *);
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177#ifdef IFPOLL_ENABLE
178static void emx_qpoll(struct ifnet *, struct ifpoll_info *);
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179#endif
180static void emx_watchdog(struct ifnet *);
181static void emx_media_status(struct ifnet *, struct ifmediareq *);
182static int emx_media_change(struct ifnet *);
183static void emx_timer(void *);
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184static void emx_serialize(struct ifnet *, enum ifnet_serialize);
185static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
186static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
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187#ifdef INVARIANTS
188static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
189 boolean_t);
190#endif
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191
192static void emx_intr(void *);
c39e3a1f 193static void emx_rxeof(struct emx_softc *, int, int);
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194static void emx_txeof(struct emx_softc *);
195static void emx_tx_collect(struct emx_softc *);
196static void emx_tx_purge(struct emx_softc *);
197static void emx_enable_intr(struct emx_softc *);
198static void emx_disable_intr(struct emx_softc *);
199
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200static int emx_dma_alloc(struct emx_softc *);
201static void emx_dma_free(struct emx_softc *);
5330213c 202static void emx_init_tx_ring(struct emx_softc *);
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203static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
204static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 205static int emx_create_tx_ring(struct emx_softc *);
c39e3a1f 206static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
5330213c 207static void emx_destroy_tx_ring(struct emx_softc *, int);
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208static void emx_destroy_rx_ring(struct emx_softc *,
209 struct emx_rxdata *, int);
210static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
5330213c 211static int emx_encap(struct emx_softc *, struct mbuf **);
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212static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
213static int emx_txcsum(struct emx_softc *, struct mbuf *,
214 uint32_t *, uint32_t *);
215
216static int emx_is_valid_eaddr(const uint8_t *);
217static int emx_hw_init(struct emx_softc *);
218static void emx_setup_ifp(struct emx_softc *);
219static void emx_init_tx_unit(struct emx_softc *);
220static void emx_init_rx_unit(struct emx_softc *);
221static void emx_update_stats(struct emx_softc *);
222static void emx_set_promisc(struct emx_softc *);
223static void emx_disable_promisc(struct emx_softc *);
224static void emx_set_multi(struct emx_softc *);
225static void emx_update_link_status(struct emx_softc *);
226static void emx_smartspeed(struct emx_softc *);
227
228static void emx_print_debug_info(struct emx_softc *);
229static void emx_print_nvm_info(struct emx_softc *);
230static void emx_print_hw_stats(struct emx_softc *);
231
232static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
233static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
234static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
235static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
236static void emx_add_sysctl(struct emx_softc *);
237
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238static void emx_serialize_skipmain(struct emx_softc *);
239static void emx_deserialize_skipmain(struct emx_softc *);
240
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241/* Management and WOL Support */
242static void emx_get_mgmt(struct emx_softc *);
243static void emx_rel_mgmt(struct emx_softc *);
244static void emx_get_hw_control(struct emx_softc *);
245static void emx_rel_hw_control(struct emx_softc *);
246static void emx_enable_wol(device_t);
247
248static device_method_t emx_methods[] = {
249 /* Device interface */
250 DEVMETHOD(device_probe, emx_probe),
251 DEVMETHOD(device_attach, emx_attach),
252 DEVMETHOD(device_detach, emx_detach),
253 DEVMETHOD(device_shutdown, emx_shutdown),
254 DEVMETHOD(device_suspend, emx_suspend),
255 DEVMETHOD(device_resume, emx_resume),
256 { 0, 0 }
257};
258
259static driver_t emx_driver = {
260 "emx",
261 emx_methods,
262 sizeof(struct emx_softc),
263};
264
265static devclass_t emx_devclass;
266
267DECLARE_DUMMY_MODULE(if_emx);
268MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
269DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0);
270
271/*
272 * Tunables
273 */
274static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
275static int emx_rxd = EMX_DEFAULT_RXD;
276static int emx_txd = EMX_DEFAULT_TXD;
277static int emx_smart_pwr_down = FALSE;
278
279/* Controls whether promiscuous also shows bad packets */
280static int emx_debug_sbp = FALSE;
281
282static int emx_82573_workaround = TRUE;
283
284TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
285TUNABLE_INT("hw.emx.rxd", &emx_rxd);
286TUNABLE_INT("hw.emx.txd", &emx_txd);
287TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
288TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
289TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
290
291/* Global used in WOL setup with multiport cards */
292static int emx_global_quad_port_a = 0;
293
294/* Set this to one to display debug statistics */
295static int emx_display_debug_stats = 0;
296
297#if !defined(KTR_IF_EMX)
298#define KTR_IF_EMX KTR_ALL
299#endif
300KTR_INFO_MASTER(if_emx);
301KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
302KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
303KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
304KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
305KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
306#define logif(name) KTR_LOG(if_emx_ ## name)
307
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308static __inline void
309emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
310{
311 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
3f939c23 312 /* DD bit must be cleared */
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313 rxd->rxd_staterr = 0;
314}
315
316static __inline void
317emx_rxcsum(uint32_t staterr, struct mbuf *mp)
318{
319 /* Ignore Checksum bit is set */
320 if (staterr & E1000_RXD_STAT_IXSM)
321 return;
322
323 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
324 E1000_RXD_STAT_IPCS)
325 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
326
327 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
328 E1000_RXD_STAT_TCPCS) {
329 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
330 CSUM_PSEUDO_HDR |
331 CSUM_FRAG_NOT_CHECKED;
332 mp->m_pkthdr.csum_data = htons(0xffff);
333 }
334}
335
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336static __inline struct pktinfo *
337emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
338 uint32_t mrq, uint32_t hash, uint32_t staterr)
339{
340 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
341 case EMX_RXDMRQ_IPV4_TCP:
342 pi->pi_netisr = NETISR_IP;
343 pi->pi_flags = 0;
344 pi->pi_l3proto = IPPROTO_TCP;
345 break;
346
347 case EMX_RXDMRQ_IPV6_TCP:
348 pi->pi_netisr = NETISR_IPV6;
349 pi->pi_flags = 0;
350 pi->pi_l3proto = IPPROTO_TCP;
351 break;
352
353 case EMX_RXDMRQ_IPV4:
354 if (staterr & E1000_RXD_STAT_IXSM)
355 return NULL;
356
357 if ((staterr &
358 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
359 E1000_RXD_STAT_TCPCS) {
360 pi->pi_netisr = NETISR_IP;
361 pi->pi_flags = 0;
362 pi->pi_l3proto = IPPROTO_UDP;
363 break;
364 }
365 /* FALL THROUGH */
366 default:
367 return NULL;
368 }
369
370 m->m_flags |= M_HASH;
371 m->m_pkthdr.hash = toeplitz_hash(hash);
372 return pi;
373}
374
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375static int
376emx_probe(device_t dev)
377{
378 const struct emx_device *d;
379 uint16_t vid, did;
380
381 vid = pci_get_vendor(dev);
382 did = pci_get_device(dev);
383
384 for (d = emx_devices; d->desc != NULL; ++d) {
385 if (vid == d->vid && did == d->did) {
386 device_set_desc(dev, d->desc);
387 device_set_async_attach(dev, TRUE);
388 return 0;
389 }
390 }
391 return ENXIO;
392}
393
394static int
395emx_attach(device_t dev)
396{
397 struct emx_softc *sc = device_get_softc(dev);
398 struct ifnet *ifp = &sc->arpcom.ac_if;
6d435846 399 int error = 0, i;
5330213c
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400 uint16_t eeprom_data, device_id;
401
6d435846
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402 lwkt_serialize_init(&sc->main_serialize);
403 lwkt_serialize_init(&sc->tx_serialize);
404 for (i = 0; i < EMX_NRX_RING; ++i)
405 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
406
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407 i = 0;
408 sc->serializes[i++] = &sc->main_serialize;
409 sc->serializes[i++] = &sc->tx_serialize;
410 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
411 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
412 KKASSERT(i == EMX_NSERIALIZE);
413
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414 callout_init(&sc->timer);
415
416 sc->dev = sc->osdep.dev = dev;
417
418 /*
419 * Determine hardware and mac type
420 */
421 sc->hw.vendor_id = pci_get_vendor(dev);
422 sc->hw.device_id = pci_get_device(dev);
423 sc->hw.revision_id = pci_get_revid(dev);
424 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
425 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
426
427 if (e1000_set_mac_type(&sc->hw))
428 return ENXIO;
429
430 /* Enable bus mastering */
431 pci_enable_busmaster(dev);
432
433 /*
434 * Allocate IO memory
435 */
436 sc->memory_rid = EMX_BAR_MEM;
437 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
438 &sc->memory_rid, RF_ACTIVE);
439 if (sc->memory == NULL) {
440 device_printf(dev, "Unable to allocate bus resource: memory\n");
441 error = ENXIO;
442 goto fail;
443 }
444 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
445 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
446
447 /* XXX This is quite goofy, it is not actually used */
448 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
449
450 /*
451 * Allocate interrupt
452 */
453 sc->intr_rid = 0;
454 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
455 RF_SHAREABLE | RF_ACTIVE);
456 if (sc->intr_res == NULL) {
457 device_printf(dev, "Unable to allocate bus resource: "
458 "interrupt\n");
459 error = ENXIO;
460 goto fail;
461 }
462
463 /* Save PCI command register for Shared Code */
464 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
465 sc->hw.back = &sc->osdep;
466
467 /* Do Shared Code initialization */
468 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
469 device_printf(dev, "Setup of Shared code failed\n");
470 error = ENXIO;
471 goto fail;
472 }
473 e1000_get_bus_info(&sc->hw);
474
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475 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
476 sc->hw.phy.autoneg_wait_to_complete = FALSE;
477 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
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478
479 /*
480 * Interrupt throttle rate
481 */
482 if (emx_int_throttle_ceil == 0) {
483 sc->int_throttle_ceil = 0;
484 } else {
485 int throttle = emx_int_throttle_ceil;
486
487 if (throttle < 0)
488 throttle = EMX_DEFAULT_ITR;
489
490 /* Recalculate the tunable value to get the exact frequency. */
491 throttle = 1000000000 / 256 / throttle;
492
493 /* Upper 16bits of ITR is reserved and should be zero */
494 if (throttle & 0xffff0000)
495 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
496
497 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
498 }
499
500 e1000_init_script_state_82541(&sc->hw, TRUE);
501 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
502
503 /* Copper options */
504 if (sc->hw.phy.media_type == e1000_media_type_copper) {
505 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
506 sc->hw.phy.disable_polarity_correction = FALSE;
507 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
508 }
509
510 /* Set the frame limits assuming standard ethernet sized frames. */
511 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
512 sc->min_frame_size = ETHER_MIN_LEN;
513
514 /* This controls when hardware reports transmit completion status. */
515 sc->hw.mac.report_tx_early = 1;
516
8434a83b 517#ifdef RSS
65c7a6af 518 /* Calculate # of RX rings */
8434a83b 519 if (ncpus > 1)
65c7a6af
SZ
520 sc->rx_ring_cnt = EMX_NRX_RING;
521 else
8434a83b 522#endif
65c7a6af 523 sc->rx_ring_cnt = 1;
8434a83b 524 sc->rx_ring_inuse = sc->rx_ring_cnt;
65c7a6af 525
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526 /* Allocate RX/TX rings' busdma(9) stuffs */
527 error = emx_dma_alloc(sc);
528 if (error)
e5b3bcc4 529 goto fail;
e5b3bcc4 530
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531 /* Make sure we have a good EEPROM before we read from it */
532 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
533 /*
534 * Some PCI-E parts fail the first check due to
535 * the link being in sleep state, call it again,
536 * if it fails a second time its a real issue.
537 */
538 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
539 device_printf(dev,
540 "The EEPROM Checksum Is Not Valid\n");
541 error = EIO;
542 goto fail;
543 }
544 }
545
546 /* Initialize the hardware */
547 error = emx_hw_init(sc);
548 if (error) {
549 device_printf(dev, "Unable to initialize the hardware\n");
550 goto fail;
551 }
552
553 /* Copy the permanent MAC address out of the EEPROM */
554 if (e1000_read_mac_addr(&sc->hw) < 0) {
555 device_printf(dev, "EEPROM read error while reading MAC"
556 " address\n");
557 error = EIO;
558 goto fail;
559 }
560 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
561 device_printf(dev, "Invalid MAC address\n");
562 error = EIO;
563 goto fail;
564 }
565
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566 /* Manually turn off all interrupts */
567 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
568
569 /* Setup OS specific network interface */
570 emx_setup_ifp(sc);
571
572 /* Add sysctl tree, must after emx_setup_ifp() */
573 emx_add_sysctl(sc);
574
575 /* Initialize statistics */
576 emx_update_stats(sc);
577
578 sc->hw.mac.get_link_status = 1;
579 emx_update_link_status(sc);
580
581 /* Indicate SOL/IDER usage */
582 if (e1000_check_reset_block(&sc->hw)) {
583 device_printf(dev,
584 "PHY reset is blocked due to SOL/IDER session.\n");
585 }
586
587 /* Determine if we have to control management hardware */
588 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
589
590 /*
591 * Setup Wake-on-Lan
592 */
593 switch (sc->hw.mac.type) {
594 case e1000_82571:
595 case e1000_80003es2lan:
596 if (sc->hw.bus.func == 1) {
597 e1000_read_nvm(&sc->hw,
598 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
599 } else {
600 e1000_read_nvm(&sc->hw,
601 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
602 }
603 eeprom_data &= EMX_EEPROM_APME;
604 break;
605
606 default:
607 /* APME bit in EEPROM is mapped to WUC.APME */
608 eeprom_data =
609 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
610 break;
611 }
612 if (eeprom_data)
613 sc->wol = E1000_WUFC_MAG;
614 /*
615 * We have the eeprom settings, now apply the special cases
616 * where the eeprom may be wrong or the board won't support
617 * wake on lan on a particular port
618 */
619 device_id = pci_get_device(dev);
620 switch (device_id) {
621 case E1000_DEV_ID_82571EB_FIBER:
622 /*
623 * Wake events only supported on port A for dual fiber
624 * regardless of eeprom setting
625 */
626 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
627 E1000_STATUS_FUNC_1)
628 sc->wol = 0;
629 break;
630
631 case E1000_DEV_ID_82571EB_QUAD_COPPER:
632 case E1000_DEV_ID_82571EB_QUAD_FIBER:
633 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
634 /* if quad port sc, disable WoL on all but port A */
635 if (emx_global_quad_port_a != 0)
636 sc->wol = 0;
637 /* Reset for multiple quad port adapters */
638 if (++emx_global_quad_port_a == 4)
639 emx_global_quad_port_a = 0;
640 break;
641 }
642
643 /* XXX disable wol */
644 sc->wol = 0;
645
646 sc->spare_tx_desc = EMX_TX_SPARE;
647
648 /*
649 * Keep following relationship between spare_tx_desc, oact_tx_desc
650 * and tx_int_nsegs:
651 * (spare_tx_desc + EMX_TX_RESERVED) <=
652 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
653 */
654 sc->oact_tx_desc = sc->num_tx_desc / 8;
655 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
656 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
657 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
658 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
659
660 sc->tx_int_nsegs = sc->num_tx_desc / 16;
661 if (sc->tx_int_nsegs < sc->oact_tx_desc)
662 sc->tx_int_nsegs = sc->oact_tx_desc;
663
664 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
6d435846 665 &sc->intr_tag, &sc->main_serialize);
5330213c
SZ
666 if (error) {
667 device_printf(dev, "Failed to register interrupt handler");
668 ether_ifdetach(&sc->arpcom.ac_if);
669 goto fail;
670 }
671
672 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res));
673 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
674 return (0);
675fail:
676 emx_detach(dev);
677 return (error);
678}
679
680static int
681emx_detach(device_t dev)
682{
683 struct emx_softc *sc = device_get_softc(dev);
684
685 if (device_is_attached(dev)) {
686 struct ifnet *ifp = &sc->arpcom.ac_if;
687
6d435846 688 ifnet_serialize_all(ifp);
5330213c
SZ
689
690 emx_stop(sc);
691
692 e1000_phy_hw_reset(&sc->hw);
693
694 emx_rel_mgmt(sc);
695
696 if (sc->hw.mac.type == e1000_82573 &&
697 e1000_check_mng_mode(&sc->hw))
698 emx_rel_hw_control(sc);
699
700 if (sc->wol) {
701 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
702 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
703 emx_enable_wol(dev);
704 }
705
706 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
707
6d435846 708 ifnet_deserialize_all(ifp);
5330213c
SZ
709
710 ether_ifdetach(ifp);
711 }
712 bus_generic_detach(dev);
713
714 if (sc->intr_res != NULL) {
715 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
716 sc->intr_res);
717 }
718
719 if (sc->memory != NULL) {
720 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
721 sc->memory);
722 }
723
071699f8 724 emx_dma_free(sc);
5330213c
SZ
725
726 /* Free sysctl tree */
727 if (sc->sysctl_tree != NULL)
728 sysctl_ctx_free(&sc->sysctl_ctx);
729
730 return (0);
731}
732
733static int
734emx_shutdown(device_t dev)
735{
736 return emx_suspend(dev);
737}
738
739static int
740emx_suspend(device_t dev)
741{
742 struct emx_softc *sc = device_get_softc(dev);
743 struct ifnet *ifp = &sc->arpcom.ac_if;
744
6d435846 745 ifnet_serialize_all(ifp);
5330213c
SZ
746
747 emx_stop(sc);
748
749 emx_rel_mgmt(sc);
750
751 if (sc->hw.mac.type == e1000_82573 &&
752 e1000_check_mng_mode(&sc->hw))
753 emx_rel_hw_control(sc);
754
755 if (sc->wol) {
756 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
757 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
758 emx_enable_wol(dev);
759 }
760
6d435846 761 ifnet_deserialize_all(ifp);
5330213c
SZ
762
763 return bus_generic_suspend(dev);
764}
765
766static int
767emx_resume(device_t dev)
768{
769 struct emx_softc *sc = device_get_softc(dev);
770 struct ifnet *ifp = &sc->arpcom.ac_if;
771
6d435846 772 ifnet_serialize_all(ifp);
5330213c
SZ
773
774 emx_init(sc);
775 emx_get_mgmt(sc);
776 if_devstart(ifp);
777
6d435846 778 ifnet_deserialize_all(ifp);
5330213c
SZ
779
780 return bus_generic_resume(dev);
781}
782
783static void
784emx_start(struct ifnet *ifp)
785{
786 struct emx_softc *sc = ifp->if_softc;
787 struct mbuf *m_head;
788
6d435846 789 ASSERT_SERIALIZED(&sc->tx_serialize);
5330213c
SZ
790
791 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
792 return;
793
794 if (!sc->link_active) {
795 ifq_purge(&ifp->if_snd);
796 return;
797 }
798
799 while (!ifq_is_empty(&ifp->if_snd)) {
800 /* Now do we at least have a minimal? */
801 if (EMX_IS_OACTIVE(sc)) {
802 emx_tx_collect(sc);
803 if (EMX_IS_OACTIVE(sc)) {
804 ifp->if_flags |= IFF_OACTIVE;
805 sc->no_tx_desc_avail1++;
806 break;
807 }
808 }
809
810 logif(pkt_txqueue);
811 m_head = ifq_dequeue(&ifp->if_snd, NULL);
812 if (m_head == NULL)
813 break;
814
815 if (emx_encap(sc, &m_head)) {
816 ifp->if_oerrors++;
817 emx_tx_collect(sc);
818 continue;
819 }
820
821 /* Send a copy of the frame to the BPF listener */
822 ETHER_BPF_MTAP(ifp, m_head);
823
824 /* Set timeout in case hardware has problems transmitting. */
825 ifp->if_timer = EMX_TX_TIMEOUT;
826 }
827}
828
829static int
830emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
831{
832 struct emx_softc *sc = ifp->if_softc;
833 struct ifreq *ifr = (struct ifreq *)data;
834 uint16_t eeprom_data = 0;
835 int max_frame_size, mask, reinit;
836 int error = 0;
837
2c9effcf 838 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
839
840 switch (command) {
841 case SIOCSIFMTU:
842 switch (sc->hw.mac.type) {
843 case e1000_82573:
844 /*
845 * 82573 only supports jumbo frames
846 * if ASPM is disabled.
847 */
848 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
849 &eeprom_data);
850 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
851 max_frame_size = ETHER_MAX_LEN;
852 break;
853 }
854 /* FALL THROUGH */
855
856 /* Limit Jumbo Frame size */
857 case e1000_82571:
858 case e1000_82572:
859 case e1000_82574:
860 case e1000_80003es2lan:
861 max_frame_size = 9234;
862 break;
863
864 default:
865 max_frame_size = MAX_JUMBO_FRAME_SIZE;
866 break;
867 }
868 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
869 ETHER_CRC_LEN) {
870 error = EINVAL;
871 break;
872 }
873
874 ifp->if_mtu = ifr->ifr_mtu;
875 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
876 ETHER_CRC_LEN;
877
878 if (ifp->if_flags & IFF_RUNNING)
879 emx_init(sc);
880 break;
881
882 case SIOCSIFFLAGS:
883 if (ifp->if_flags & IFF_UP) {
884 if ((ifp->if_flags & IFF_RUNNING)) {
885 if ((ifp->if_flags ^ sc->if_flags) &
886 (IFF_PROMISC | IFF_ALLMULTI)) {
887 emx_disable_promisc(sc);
888 emx_set_promisc(sc);
889 }
890 } else {
891 emx_init(sc);
892 }
893 } else if (ifp->if_flags & IFF_RUNNING) {
894 emx_stop(sc);
895 }
896 sc->if_flags = ifp->if_flags;
897 break;
898
899 case SIOCADDMULTI:
900 case SIOCDELMULTI:
901 if (ifp->if_flags & IFF_RUNNING) {
902 emx_disable_intr(sc);
903 emx_set_multi(sc);
b3a7093f
SZ
904#ifdef IFPOLL_ENABLE
905 if (!(ifp->if_flags & IFF_NPOLLING))
5330213c
SZ
906#endif
907 emx_enable_intr(sc);
908 }
909 break;
910
911 case SIOCSIFMEDIA:
912 /* Check SOL/IDER usage */
913 if (e1000_check_reset_block(&sc->hw)) {
914 device_printf(sc->dev, "Media change is"
915 " blocked due to SOL/IDER session.\n");
916 break;
917 }
918 /* FALL THROUGH */
919
920 case SIOCGIFMEDIA:
921 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
922 break;
923
924 case SIOCSIFCAP:
925 reinit = 0;
926 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
927 if (mask & IFCAP_HWCSUM) {
928 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
929 reinit = 1;
930 }
931 if (mask & IFCAP_VLAN_HWTAGGING) {
932 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
933 reinit = 1;
934 }
8434a83b
SZ
935 if (mask & IFCAP_RSS) {
936 ifp->if_capenable ^= IFCAP_RSS;
937 reinit = 1;
938 }
5330213c
SZ
939 if (reinit && (ifp->if_flags & IFF_RUNNING))
940 emx_init(sc);
941 break;
942
943 default:
944 error = ether_ioctl(ifp, command, data);
945 break;
946 }
947 return (error);
948}
949
950static void
951emx_watchdog(struct ifnet *ifp)
952{
953 struct emx_softc *sc = ifp->if_softc;
954
2c9effcf 955 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
956
957 /*
958 * The timer is set to 5 every time start queues a packet.
959 * Then txeof keeps resetting it as long as it cleans at
960 * least one descriptor.
961 * Finally, anytime all descriptors are clean the timer is
962 * set to 0.
963 */
964
965 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
966 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
967 /*
968 * If we reach here, all TX jobs are completed and
969 * the TX engine should have been idled for some time.
970 * We don't need to call if_devstart() here.
971 */
972 ifp->if_flags &= ~IFF_OACTIVE;
973 ifp->if_timer = 0;
974 return;
975 }
976
977 /*
978 * If we are in this routine because of pause frames, then
979 * don't reset the hardware.
980 */
981 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
982 ifp->if_timer = EMX_TX_TIMEOUT;
983 return;
984 }
985
986 if (e1000_check_for_link(&sc->hw) == 0)
987 if_printf(ifp, "watchdog timeout -- resetting\n");
988
989 ifp->if_oerrors++;
990 sc->watchdog_events++;
991
992 emx_init(sc);
993
994 if (!ifq_is_empty(&ifp->if_snd))
995 if_devstart(ifp);
996}
997
998static void
999emx_init(void *xsc)
1000{
1001 struct emx_softc *sc = xsc;
1002 struct ifnet *ifp = &sc->arpcom.ac_if;
1003 device_t dev = sc->dev;
1004 uint32_t pba;
3f939c23 1005 int i;
5330213c 1006
2c9effcf 1007 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1008
1009 emx_stop(sc);
1010
1011 /*
1012 * Packet Buffer Allocation (PBA)
1013 * Writing PBA sets the receive portion of the buffer
1014 * the remainder is used for the transmit buffer.
1015 */
1016 switch (sc->hw.mac.type) {
1017 /* Total Packet Buffer on these is 48K */
1018 case e1000_82571:
1019 case e1000_82572:
1020 case e1000_80003es2lan:
1021 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1022 break;
1023
1024 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1025 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1026 break;
1027
1028 case e1000_82574:
1029 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1030 break;
1031
1032 default:
1033 /* Devices before 82547 had a Packet Buffer of 64K. */
1034 if (sc->max_frame_size > 8192)
1035 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1036 else
1037 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1038 }
1039 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1040
1041 /* Get the latest mac address, User can use a LAA */
1042 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1043
1044 /* Put the address into the Receive Address Array */
1045 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1046
1047 /*
1048 * With the 82571 sc, RAR[0] may be overwritten
1049 * when the other port is reset, we make a duplicate
1050 * in RAR[14] for that eventuality, this assures
1051 * the interface continues to function.
1052 */
1053 if (sc->hw.mac.type == e1000_82571) {
1054 e1000_set_laa_state_82571(&sc->hw, TRUE);
1055 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1056 E1000_RAR_ENTRIES - 1);
1057 }
1058
1059 /* Initialize the hardware */
1060 if (emx_hw_init(sc)) {
1061 device_printf(dev, "Unable to initialize the hardware\n");
1062 /* XXX emx_stop()? */
1063 return;
1064 }
1065 emx_update_link_status(sc);
1066
1067 /* Setup VLAN support, basic and offload if available */
1068 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1069
1070 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1071 uint32_t ctrl;
1072
1073 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1074 ctrl |= E1000_CTRL_VME;
1075 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1076 }
1077
1078 /* Set hardware offload abilities */
1079 if (ifp->if_capenable & IFCAP_TXCSUM)
1080 ifp->if_hwassist = EMX_CSUM_FEATURES;
1081 else
1082 ifp->if_hwassist = 0;
1083
1084 /* Configure for OS presence */
1085 emx_get_mgmt(sc);
1086
1087 /* Prepare transmit descriptors and buffers */
1088 emx_init_tx_ring(sc);
1089 emx_init_tx_unit(sc);
1090
1091 /* Setup Multicast table */
1092 emx_set_multi(sc);
1093
8434a83b
SZ
1094 /*
1095 * Adjust # of RX ring to be used based on IFCAP_RSS
1096 */
1097 if (ifp->if_capenable & IFCAP_RSS)
1098 sc->rx_ring_inuse = sc->rx_ring_cnt;
1099 else
1100 sc->rx_ring_inuse = 1;
1101
5330213c 1102 /* Prepare receive descriptors and buffers */
8434a83b 1103 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
1104 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1105 device_printf(dev,
1106 "Could not setup receive structures\n");
1107 emx_stop(sc);
1108 return;
1109 }
5330213c
SZ
1110 }
1111 emx_init_rx_unit(sc);
1112
1113 /* Don't lose promiscuous settings */
1114 emx_set_promisc(sc);
1115
1116 ifp->if_flags |= IFF_RUNNING;
1117 ifp->if_flags &= ~IFF_OACTIVE;
1118
1119 callout_reset(&sc->timer, hz, emx_timer, sc);
1120 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1121
1122 /* MSI/X configuration for 82574 */
1123 if (sc->hw.mac.type == e1000_82574) {
1124 int tmp;
1125
1126 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1127 tmp |= E1000_CTRL_EXT_PBA_CLR;
1128 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1129 /*
1130 * Set the IVAR - interrupt vector routing.
1131 * Each nibble represents a vector, high bit
1132 * is enable, other 3 bits are the MSIX table
1133 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1134 * Link (other) to 2, hence the magic number.
1135 */
1136 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1137 }
1138
b3a7093f 1139#ifdef IFPOLL_ENABLE
5330213c
SZ
1140 /*
1141 * Only enable interrupts if we are not polling, make sure
1142 * they are off otherwise.
1143 */
b3a7093f 1144 if (ifp->if_flags & IFF_NPOLLING)
5330213c
SZ
1145 emx_disable_intr(sc);
1146 else
b3a7093f 1147#endif /* IFPOLL_ENABLE */
5330213c
SZ
1148 emx_enable_intr(sc);
1149
1150 /* Don't reset the phy next time init gets called */
1151 sc->hw.phy.reset_disable = TRUE;
1152}
1153
5330213c
SZ
1154static void
1155emx_intr(void *xsc)
1156{
1157 struct emx_softc *sc = xsc;
1158 struct ifnet *ifp = &sc->arpcom.ac_if;
1159 uint32_t reg_icr;
1160
1161 logif(intr_beg);
6d435846 1162 ASSERT_SERIALIZED(&sc->main_serialize);
5330213c
SZ
1163
1164 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1165
1166 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1167 logif(intr_end);
1168 return;
1169 }
1170
1171 /*
1172 * XXX: some laptops trigger several spurious interrupts
df50f778 1173 * on emx(4) when in the resume cycle. The ICR register
5330213c
SZ
1174 * reports all-ones value in this case. Processing such
1175 * interrupts would lead to a freeze. I don't know why.
1176 */
1177 if (reg_icr == 0xffffffff) {
1178 logif(intr_end);
1179 return;
1180 }
1181
1182 if (ifp->if_flags & IFF_RUNNING) {
1183 if (reg_icr &
3f939c23
SZ
1184 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1185 int i;
1186
6d435846
SZ
1187 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1188 lwkt_serialize_enter(
1189 &sc->rx_data[i].rx_serialize);
3f939c23 1190 emx_rxeof(sc, i, -1);
6d435846
SZ
1191 lwkt_serialize_exit(
1192 &sc->rx_data[i].rx_serialize);
1193 }
3f939c23 1194 }
6446af7b 1195 if (reg_icr & E1000_ICR_TXDW) {
6d435846 1196 lwkt_serialize_enter(&sc->tx_serialize);
5330213c
SZ
1197 emx_txeof(sc);
1198 if (!ifq_is_empty(&ifp->if_snd))
1199 if_devstart(ifp);
6d435846 1200 lwkt_serialize_exit(&sc->tx_serialize);
5330213c
SZ
1201 }
1202 }
1203
1204 /* Link status change */
1205 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
bca7c435 1206 emx_serialize_skipmain(sc);
6d435846 1207
5330213c
SZ
1208 callout_stop(&sc->timer);
1209 sc->hw.mac.get_link_status = 1;
1210 emx_update_link_status(sc);
1211
1212 /* Deal with TX cruft when link lost */
1213 emx_tx_purge(sc);
1214
1215 callout_reset(&sc->timer, hz, emx_timer, sc);
6d435846 1216
bca7c435 1217 emx_deserialize_skipmain(sc);
5330213c
SZ
1218 }
1219
1220 if (reg_icr & E1000_ICR_RXO)
1221 sc->rx_overruns++;
1222
1223 logif(intr_end);
1224}
1225
1226static void
1227emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1228{
1229 struct emx_softc *sc = ifp->if_softc;
1230
2c9effcf 1231 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1232
1233 emx_update_link_status(sc);
1234
1235 ifmr->ifm_status = IFM_AVALID;
1236 ifmr->ifm_active = IFM_ETHER;
1237
1238 if (!sc->link_active)
1239 return;
1240
1241 ifmr->ifm_status |= IFM_ACTIVE;
1242
1243 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1244 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1245 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1246 } else {
1247 switch (sc->link_speed) {
1248 case 10:
1249 ifmr->ifm_active |= IFM_10_T;
1250 break;
1251 case 100:
1252 ifmr->ifm_active |= IFM_100_TX;
1253 break;
1254
1255 case 1000:
1256 ifmr->ifm_active |= IFM_1000_T;
1257 break;
1258 }
1259 if (sc->link_duplex == FULL_DUPLEX)
1260 ifmr->ifm_active |= IFM_FDX;
1261 else
1262 ifmr->ifm_active |= IFM_HDX;
1263 }
1264}
1265
1266static int
1267emx_media_change(struct ifnet *ifp)
1268{
1269 struct emx_softc *sc = ifp->if_softc;
1270 struct ifmedia *ifm = &sc->media;
1271
2c9effcf 1272 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1273
1274 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1275 return (EINVAL);
1276
1277 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1278 case IFM_AUTO:
1279 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1280 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1281 break;
1282
1283 case IFM_1000_LX:
1284 case IFM_1000_SX:
1285 case IFM_1000_T:
1286 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1287 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1288 break;
1289
1290 case IFM_100_TX:
1291 sc->hw.mac.autoneg = FALSE;
1292 sc->hw.phy.autoneg_advertised = 0;
1293 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1294 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1295 else
1296 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1297 break;
1298
1299 case IFM_10_T:
1300 sc->hw.mac.autoneg = FALSE;
1301 sc->hw.phy.autoneg_advertised = 0;
1302 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1303 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1304 else
1305 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1306 break;
1307
1308 default:
1309 if_printf(ifp, "Unsupported media type\n");
1310 break;
1311 }
1312
1313 /*
1314 * As the speed/duplex settings my have changed we need to
1315 * reset the PHY.
1316 */
1317 sc->hw.phy.reset_disable = FALSE;
1318
1319 emx_init(sc);
1320
1321 return (0);
1322}
1323
1324static int
1325emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1326{
1327 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1328 bus_dmamap_t map;
323e5ecd 1329 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
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SZ
1330 struct e1000_tx_desc *ctxd = NULL;
1331 struct mbuf *m_head = *m_headp;
1332 uint32_t txd_upper, txd_lower, cmd = 0;
1333 int maxsegs, nsegs, i, j, first, last = 0, error;
1334
3752657e 1335 if (m_head->m_len < EMX_TXCSUM_MINHL &&
5330213c
SZ
1336 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1337 /*
1338 * Make sure that ethernet header and ip.ip_hl are in
1339 * contiguous memory, since if TXCSUM is enabled, later
1340 * TX context descriptor's setup need to access ip.ip_hl.
1341 */
1342 error = emx_txcsum_pullup(sc, m_headp);
1343 if (error) {
1344 KKASSERT(*m_headp == NULL);
1345 return error;
1346 }
1347 m_head = *m_headp;
1348 }
1349
1350 txd_upper = txd_lower = 0;
1351
1352 /*
1353 * Capture the first descriptor index, this descriptor
1354 * will have the index of the EOP which is the only one
1355 * that now gets a DONE bit writeback.
1356 */
1357 first = sc->next_avail_tx_desc;
323e5ecd 1358 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
1359 tx_buffer_mapped = tx_buffer;
1360 map = tx_buffer->map;
1361
1362 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1363 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1364 if (maxsegs > EMX_MAX_SCATTER)
1365 maxsegs = EMX_MAX_SCATTER;
1366
1367 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1368 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1369 if (error) {
1370 if (error == ENOBUFS)
1371 sc->mbuf_alloc_failed++;
1372 else
1373 sc->no_tx_dma_setup++;
1374
1375 m_freem(*m_headp);
1376 *m_headp = NULL;
1377 return error;
1378 }
1379 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1380
1381 m_head = *m_headp;
1382 sc->tx_nsegs += nsegs;
1383
1384 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1385 /* TX csum offloading will consume one TX desc */
1386 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1387 }
1388 i = sc->next_avail_tx_desc;
1389
1390 /* Set up our transmit descriptors */
1391 for (j = 0; j < nsegs; j++) {
323e5ecd 1392 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1393 ctxd = &sc->tx_desc_base[i];
1394
1395 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1396 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1397 txd_lower | segs[j].ds_len);
1398 ctxd->upper.data = htole32(txd_upper);
1399
1400 last = i;
1401 if (++i == sc->num_tx_desc)
1402 i = 0;
5330213c
SZ
1403 }
1404
1405 sc->next_avail_tx_desc = i;
1406
1407 KKASSERT(sc->num_tx_desc_avail > nsegs);
1408 sc->num_tx_desc_avail -= nsegs;
1409
1410 /* Handle VLAN tag */
1411 if (m_head->m_flags & M_VLANTAG) {
1412 /* Set the vlan id. */
1413 ctxd->upper.fields.special =
1414 htole16(m_head->m_pkthdr.ether_vlantag);
1415
1416 /* Tell hardware to add tag */
1417 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1418 }
1419
1420 tx_buffer->m_head = m_head;
1421 tx_buffer_mapped->map = tx_buffer->map;
1422 tx_buffer->map = map;
1423
1424 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1425 sc->tx_nsegs = 0;
4e4e8481
SZ
1426
1427 /*
1428 * Report Status (RS) is turned on
1429 * every tx_int_nsegs descriptors.
1430 */
5330213c
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1431 cmd = E1000_TXD_CMD_RS;
1432
b4b0a2b4
SZ
1433 /*
1434 * Keep track of the descriptor, which will
1435 * be written back by hardware.
1436 */
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SZ
1437 sc->tx_dd[sc->tx_dd_tail] = last;
1438 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1439 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1440 }
1441
1442 /*
1443 * Last Descriptor of Packet needs End Of Packet (EOP)
5330213c
SZ
1444 */
1445 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1446
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1447 /*
1448 * Advance the Transmit Descriptor Tail (TDT), this tells
1449 * the E1000 that this frame is available to transmit.
1450 */
1451 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1452
1453 return (0);
1454}
1455
1456static void
1457emx_set_promisc(struct emx_softc *sc)
1458{
1459 struct ifnet *ifp = &sc->arpcom.ac_if;
1460 uint32_t reg_rctl;
1461
1462 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1463
1464 if (ifp->if_flags & IFF_PROMISC) {
1465 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1466 /* Turn this on if you want to see bad packets */
1467 if (emx_debug_sbp)
1468 reg_rctl |= E1000_RCTL_SBP;
1469 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1470 } else if (ifp->if_flags & IFF_ALLMULTI) {
1471 reg_rctl |= E1000_RCTL_MPE;
1472 reg_rctl &= ~E1000_RCTL_UPE;
1473 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1474 }
1475}
1476
1477static void
1478emx_disable_promisc(struct emx_softc *sc)
1479{
1480 uint32_t reg_rctl;
1481
1482 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1483
1484 reg_rctl &= ~E1000_RCTL_UPE;
1485 reg_rctl &= ~E1000_RCTL_MPE;
1486 reg_rctl &= ~E1000_RCTL_SBP;
1487 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1488}
1489
1490static void
1491emx_set_multi(struct emx_softc *sc)
1492{
1493 struct ifnet *ifp = &sc->arpcom.ac_if;
1494 struct ifmultiaddr *ifma;
1495 uint32_t reg_rctl = 0;
1496 uint8_t mta[512]; /* Largest MTS is 4096 bits */
1497 int mcnt = 0;
1498
441d34b2 1499 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5330213c
SZ
1500 if (ifma->ifma_addr->sa_family != AF_LINK)
1501 continue;
1502
1503 if (mcnt == EMX_MCAST_ADDR_MAX)
1504 break;
1505
1506 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1507 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1508 mcnt++;
1509 }
1510
1511 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1512 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1513 reg_rctl |= E1000_RCTL_MPE;
1514 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1515 } else {
1516 e1000_update_mc_addr_list(&sc->hw, mta,
1517 mcnt, 1, sc->hw.mac.rar_entry_count);
1518 }
1519}
1520
1521/*
1522 * This routine checks for link status and updates statistics.
1523 */
1524static void
1525emx_timer(void *xsc)
1526{
1527 struct emx_softc *sc = xsc;
1528 struct ifnet *ifp = &sc->arpcom.ac_if;
1529
6d435846 1530 ifnet_serialize_all(ifp);
5330213c
SZ
1531
1532 emx_update_link_status(sc);
1533 emx_update_stats(sc);
1534
1535 /* Reset LAA into RAR[0] on 82571 */
1536 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1537 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1538
1539 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1540 emx_print_hw_stats(sc);
1541
1542 emx_smartspeed(sc);
1543
1544 callout_reset(&sc->timer, hz, emx_timer, sc);
1545
6d435846 1546 ifnet_deserialize_all(ifp);
5330213c
SZ
1547}
1548
1549static void
1550emx_update_link_status(struct emx_softc *sc)
1551{
1552 struct e1000_hw *hw = &sc->hw;
1553 struct ifnet *ifp = &sc->arpcom.ac_if;
1554 device_t dev = sc->dev;
1555 uint32_t link_check = 0;
1556
1557 /* Get the cached link value or read phy for real */
1558 switch (hw->phy.media_type) {
1559 case e1000_media_type_copper:
1560 if (hw->mac.get_link_status) {
1561 /* Do the work to read phy */
1562 e1000_check_for_link(hw);
1563 link_check = !hw->mac.get_link_status;
1564 if (link_check) /* ESB2 fix */
1565 e1000_cfg_on_link_up(hw);
1566 } else {
1567 link_check = TRUE;
1568 }
1569 break;
1570
1571 case e1000_media_type_fiber:
1572 e1000_check_for_link(hw);
1573 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1574 break;
1575
1576 case e1000_media_type_internal_serdes:
1577 e1000_check_for_link(hw);
1578 link_check = sc->hw.mac.serdes_has_link;
1579 break;
1580
1581 case e1000_media_type_unknown:
1582 default:
1583 break;
1584 }
1585
1586 /* Now check for a transition */
1587 if (link_check && sc->link_active == 0) {
1588 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1589 &sc->link_duplex);
1590
1591 /*
1592 * Check if we should enable/disable SPEED_MODE bit on
1593 * 82571EB/82572EI
1594 */
1595 if (hw->mac.type == e1000_82571 ||
1596 hw->mac.type == e1000_82572) {
1597 int tarc0;
1598
1599 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1600 if (sc->link_speed != SPEED_1000)
1601 tarc0 &= ~EMX_TARC_SPEED_MODE;
1602 else
1603 tarc0 |= EMX_TARC_SPEED_MODE;
1604 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1605 }
1606 if (bootverbose) {
1607 device_printf(dev, "Link is up %d Mbps %s\n",
1608 sc->link_speed,
1609 ((sc->link_duplex == FULL_DUPLEX) ?
1610 "Full Duplex" : "Half Duplex"));
1611 }
1612 sc->link_active = 1;
1613 sc->smartspeed = 0;
1614 ifp->if_baudrate = sc->link_speed * 1000000;
1615 ifp->if_link_state = LINK_STATE_UP;
1616 if_link_state_change(ifp);
1617 } else if (!link_check && sc->link_active == 1) {
1618 ifp->if_baudrate = sc->link_speed = 0;
1619 sc->link_duplex = 0;
1620 if (bootverbose)
1621 device_printf(dev, "Link is Down\n");
1622 sc->link_active = 0;
1623#if 0
1624 /* Link down, disable watchdog */
1625 if->if_timer = 0;
1626#endif
1627 ifp->if_link_state = LINK_STATE_DOWN;
1628 if_link_state_change(ifp);
1629 }
1630}
1631
1632static void
1633emx_stop(struct emx_softc *sc)
1634{
1635 struct ifnet *ifp = &sc->arpcom.ac_if;
1636 int i;
1637
2c9effcf 1638 ASSERT_IFNET_SERIALIZED_ALL(ifp);
5330213c
SZ
1639
1640 emx_disable_intr(sc);
1641
1642 callout_stop(&sc->timer);
1643
1644 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1645 ifp->if_timer = 0;
1646
3f939c23
SZ
1647 /*
1648 * Disable multiple receive queues.
1649 *
1650 * NOTE:
1651 * We should disable multiple receive queues before
1652 * resetting the hardware.
1653 */
1654 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1655
5330213c
SZ
1656 e1000_reset_hw(&sc->hw);
1657 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1658
1659 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1660 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1661
1662 if (tx_buffer->m_head != NULL) {
1663 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1664 m_freem(tx_buffer->m_head);
1665 tx_buffer->m_head = NULL;
1666 }
1667 }
1668
8434a83b 1669 for (i = 0; i < sc->rx_ring_inuse; ++i)
3f939c23 1670 emx_free_rx_ring(sc, &sc->rx_data[i]);
5330213c
SZ
1671
1672 sc->csum_flags = 0;
1673 sc->csum_ehlen = 0;
1674 sc->csum_iphlen = 0;
1675
1676 sc->tx_dd_head = 0;
1677 sc->tx_dd_tail = 0;
1678 sc->tx_nsegs = 0;
1679}
1680
1681static int
1682emx_hw_init(struct emx_softc *sc)
1683{
1684 device_t dev = sc->dev;
1685 uint16_t rx_buffer_size;
1686
1687 /* Issue a global reset */
1688 e1000_reset_hw(&sc->hw);
1689
1690 /* Get control from any management/hw control */
1691 if (sc->hw.mac.type == e1000_82573 &&
1692 e1000_check_mng_mode(&sc->hw))
1693 emx_get_hw_control(sc);
1694
1695 /* Set up smart power down as default off on newer adapters. */
1696 if (!emx_smart_pwr_down &&
1697 (sc->hw.mac.type == e1000_82571 ||
1698 sc->hw.mac.type == e1000_82572)) {
1699 uint16_t phy_tmp = 0;
1700
1701 /* Speed up time to link by disabling smart power down. */
1702 e1000_read_phy_reg(&sc->hw,
1703 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1704 phy_tmp &= ~IGP02E1000_PM_SPD;
1705 e1000_write_phy_reg(&sc->hw,
1706 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1707 }
1708
1709 /*
1710 * These parameters control the automatic generation (Tx) and
1711 * response (Rx) to Ethernet PAUSE frames.
1712 * - High water mark should allow for at least two frames to be
1713 * received after sending an XOFF.
1714 * - Low water mark works best when it is very near the high water mark.
1715 * This allows the receiver to restart by sending XON when it has
1716 * drained a bit. Here we use an arbitary value of 1500 which will
1717 * restart after one full frame is pulled from the buffer. There
1718 * could be several smaller frames in the buffer and if so they will
1719 * not trigger the XON until their total number reduces the buffer
1720 * by 1500.
1721 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1722 */
1723 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1724
1725 sc->hw.fc.high_water = rx_buffer_size -
1726 roundup2(sc->max_frame_size, 1024);
1727 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1728
1729 if (sc->hw.mac.type == e1000_80003es2lan)
1730 sc->hw.fc.pause_time = 0xFFFF;
1731 else
1732 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1733 sc->hw.fc.send_xon = TRUE;
1734 sc->hw.fc.requested_mode = e1000_fc_full;
1735
1736 if (e1000_init_hw(&sc->hw) < 0) {
1737 device_printf(dev, "Hardware Initialization Failed\n");
1738 return (EIO);
1739 }
1740
1741 e1000_check_for_link(&sc->hw);
1742
1743 return (0);
1744}
1745
1746static void
1747emx_setup_ifp(struct emx_softc *sc)
1748{
1749 struct ifnet *ifp = &sc->arpcom.ac_if;
1750
1751 if_initname(ifp, device_get_name(sc->dev),
1752 device_get_unit(sc->dev));
1753 ifp->if_softc = sc;
1754 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1755 ifp->if_init = emx_init;
1756 ifp->if_ioctl = emx_ioctl;
1757 ifp->if_start = emx_start;
b3a7093f
SZ
1758#ifdef IFPOLL_ENABLE
1759 ifp->if_qpoll = emx_qpoll;
5330213c
SZ
1760#endif
1761 ifp->if_watchdog = emx_watchdog;
6d435846
SZ
1762 ifp->if_serialize = emx_serialize;
1763 ifp->if_deserialize = emx_deserialize;
1764 ifp->if_tryserialize = emx_tryserialize;
2c9effcf
SZ
1765#ifdef INVARIANTS
1766 ifp->if_serialize_assert = emx_serialize_assert;
1767#endif
5330213c
SZ
1768 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1769 ifq_set_ready(&ifp->if_snd);
1770
ae474cfa 1771 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
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SZ
1772
1773 ifp->if_capabilities = IFCAP_HWCSUM |
1774 IFCAP_VLAN_HWTAGGING |
1775 IFCAP_VLAN_MTU;
8434a83b
SZ
1776 if (sc->rx_ring_cnt > 1)
1777 ifp->if_capabilities |= IFCAP_RSS;
5330213c
SZ
1778 ifp->if_capenable = ifp->if_capabilities;
1779 ifp->if_hwassist = EMX_CSUM_FEATURES;
1780
1781 /*
1782 * Tell the upper layer(s) we support long frames.
1783 */
1784 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1785
1786 /*
1787 * Specify the media types supported by this sc and register
1788 * callbacks to update media and link information
1789 */
1790 ifmedia_init(&sc->media, IFM_IMASK,
1791 emx_media_change, emx_media_status);
1792 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1793 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1794 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1795 0, NULL);
1796 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1797 } else {
1798 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1799 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1800 0, NULL);
1801 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1802 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1803 0, NULL);
1804 if (sc->hw.phy.type != e1000_phy_ife) {
1805 ifmedia_add(&sc->media,
1806 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1807 ifmedia_add(&sc->media,
1808 IFM_ETHER | IFM_1000_T, 0, NULL);
1809 }
1810 }
1811 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1812 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1813}
1814
1815/*
1816 * Workaround for SmartSpeed on 82541 and 82547 controllers
1817 */
1818static void
1819emx_smartspeed(struct emx_softc *sc)
1820{
1821 uint16_t phy_tmp;
1822
1823 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1824 sc->hw.mac.autoneg == 0 ||
1825 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1826 return;
1827
1828 if (sc->smartspeed == 0) {
1829 /*
1830 * If Master/Slave config fault is asserted twice,
1831 * we assume back-to-back
1832 */
1833 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1834 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1835 return;
1836 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1837 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1838 e1000_read_phy_reg(&sc->hw,
1839 PHY_1000T_CTRL, &phy_tmp);
1840 if (phy_tmp & CR_1000T_MS_ENABLE) {
1841 phy_tmp &= ~CR_1000T_MS_ENABLE;
1842 e1000_write_phy_reg(&sc->hw,
1843 PHY_1000T_CTRL, phy_tmp);
1844 sc->smartspeed++;
1845 if (sc->hw.mac.autoneg &&
1846 !e1000_phy_setup_autoneg(&sc->hw) &&
1847 !e1000_read_phy_reg(&sc->hw,
1848 PHY_CONTROL, &phy_tmp)) {
1849 phy_tmp |= MII_CR_AUTO_NEG_EN |
1850 MII_CR_RESTART_AUTO_NEG;
1851 e1000_write_phy_reg(&sc->hw,
1852 PHY_CONTROL, phy_tmp);
1853 }
1854 }
1855 }
1856 return;
1857 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1858 /* If still no link, perhaps using 2/3 pair cable */
1859 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1860 phy_tmp |= CR_1000T_MS_ENABLE;
1861 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1862 if (sc->hw.mac.autoneg &&
1863 !e1000_phy_setup_autoneg(&sc->hw) &&
1864 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1865 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1866 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1867 }
1868 }
1869
1870 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1871 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1872 sc->smartspeed = 0;
1873}
1874
5330213c
SZ
1875static int
1876emx_create_tx_ring(struct emx_softc *sc)
1877{
1878 device_t dev = sc->dev;
323e5ecd 1879 struct emx_txbuf *tx_buffer;
bdca134f
SZ
1880 int error, i, tsize;
1881
1882 /*
1883 * Validate number of transmit descriptors. It must not exceed
1884 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1885 */
1886 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1887 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1888 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1889 EMX_DEFAULT_TXD, emx_txd);
1890 sc->num_tx_desc = EMX_DEFAULT_TXD;
1891 } else {
1892 sc->num_tx_desc = emx_txd;
1893 }
1894
1895 /*
1896 * Allocate Transmit Descriptor ring
1897 */
1898 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1899 EMX_DBA_ALIGN);
a596084c
SZ
1900 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1901 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1902 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1903 &sc->tx_desc_paddr);
1904 if (sc->tx_desc_base == NULL) {
bdca134f 1905 device_printf(dev, "Unable to allocate tx_desc memory\n");
a596084c 1906 return ENOMEM;
bdca134f 1907 }
5330213c 1908
323e5ecd
SZ
1909 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1910 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
1911
1912 /*
1913 * Create DMA tags for tx buffers
1914 */
1915 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1916 1, 0, /* alignment, bounds */
1917 BUS_SPACE_MAXADDR, /* lowaddr */
1918 BUS_SPACE_MAXADDR, /* highaddr */
1919 NULL, NULL, /* filter, filterarg */
1920 EMX_TSO_SIZE, /* maxsize */
1921 EMX_MAX_SCATTER, /* nsegments */
1922 EMX_MAX_SEGSIZE, /* maxsegsize */
1923 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1924 BUS_DMA_ONEBPAGE, /* flags */
1925 &sc->txtag);
1926 if (error) {
1927 device_printf(dev, "Unable to allocate TX DMA tag\n");
323e5ecd
SZ
1928 kfree(sc->tx_buf, M_DEVBUF);
1929 sc->tx_buf = NULL;
5330213c
SZ
1930 return error;
1931 }
1932
1933 /*
1934 * Create DMA maps for tx buffers
1935 */
1936 for (i = 0; i < sc->num_tx_desc; i++) {
323e5ecd 1937 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
1938
1939 error = bus_dmamap_create(sc->txtag,
1940 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1941 &tx_buffer->map);
1942 if (error) {
1943 device_printf(dev, "Unable to create TX DMA map\n");
1944 emx_destroy_tx_ring(sc, i);
1945 return error;
1946 }
1947 }
1948 return (0);
1949}
1950
1951static void
1952emx_init_tx_ring(struct emx_softc *sc)
1953{
1954 /* Clear the old ring contents */
1955 bzero(sc->tx_desc_base,
1956 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
1957
1958 /* Reset state */
1959 sc->next_avail_tx_desc = 0;
1960 sc->next_tx_to_clean = 0;
1961 sc->num_tx_desc_avail = sc->num_tx_desc;
1962}
1963
1964static void
1965emx_init_tx_unit(struct emx_softc *sc)
1966{
1967 uint32_t tctl, tarc, tipg = 0;
1968 uint64_t bus_addr;
1969
1970 /* Setup the Base and Length of the Tx Descriptor Ring */
a596084c 1971 bus_addr = sc->tx_desc_paddr;
5330213c
SZ
1972 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
1973 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1974 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
1975 (uint32_t)(bus_addr >> 32));
1976 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
1977 (uint32_t)bus_addr);
1978 /* Setup the HW Tx Head and Tail descriptor pointers */
1979 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
1980 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
1981
1982 /* Set the default values for the Tx Inter Packet Gap timer */
1983 switch (sc->hw.mac.type) {
1984 case e1000_80003es2lan:
1985 tipg = DEFAULT_82543_TIPG_IPGR1;
1986 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
1987 E1000_TIPG_IPGR2_SHIFT;
1988 break;
1989
1990 default:
1991 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1992 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
1993 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1994 else
1995 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1996 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1997 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1998 break;
1999 }
2000
2001 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2002
2003 /* NOTE: 0 is not allowed for TIDV */
2004 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2005 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2006
2007 if (sc->hw.mac.type == e1000_82571 ||
2008 sc->hw.mac.type == e1000_82572) {
2009 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2010 tarc |= EMX_TARC_SPEED_MODE;
2011 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2012 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2013 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2014 tarc |= 1;
2015 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2016 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2017 tarc |= 1;
2018 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2019 }
2020
2021 /* Program the Transmit Control Register */
2022 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2023 tctl &= ~E1000_TCTL_CT;
2024 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2025 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2026 tctl |= E1000_TCTL_MULR;
2027
2028 /* This write will effectively turn on the transmit unit. */
2029 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2030}
2031
2032static void
2033emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2034{
323e5ecd 2035 struct emx_txbuf *tx_buffer;
5330213c
SZ
2036 int i;
2037
bdca134f 2038 /* Free Transmit Descriptor ring */
a596084c
SZ
2039 if (sc->tx_desc_base) {
2040 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2041 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2042 sc->tx_desc_dmap);
2043 bus_dma_tag_destroy(sc->tx_desc_dtag);
2044
2045 sc->tx_desc_base = NULL;
2046 }
bdca134f 2047
323e5ecd 2048 if (sc->tx_buf == NULL)
5330213c
SZ
2049 return;
2050
2051 for (i = 0; i < ndesc; i++) {
323e5ecd 2052 tx_buffer = &sc->tx_buf[i];
5330213c
SZ
2053
2054 KKASSERT(tx_buffer->m_head == NULL);
2055 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2056 }
2057 bus_dma_tag_destroy(sc->txtag);
2058
323e5ecd
SZ
2059 kfree(sc->tx_buf, M_DEVBUF);
2060 sc->tx_buf = NULL;
5330213c
SZ
2061}
2062
2063/*
2064 * The offload context needs to be set when we transfer the first
2065 * packet of a particular protocol (TCP/UDP). This routine has been
2066 * enhanced to deal with inserted VLAN headers.
2067 *
2068 * If the new packet's ether header length, ip header length and
2069 * csum offloading type are same as the previous packet, we should
2070 * avoid allocating a new csum context descriptor; mainly to take
2071 * advantage of the pipeline effect of the TX data read request.
2072 *
2073 * This function returns number of TX descrptors allocated for
2074 * csum context.
2075 */
2076static int
2077emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2078 uint32_t *txd_upper, uint32_t *txd_lower)
2079{
2080 struct e1000_context_desc *TXD;
323e5ecd 2081 struct emx_txbuf *tx_buffer;
5330213c
SZ
2082 struct ether_vlan_header *eh;
2083 struct ip *ip;
2084 int curr_txd, ehdrlen, csum_flags;
2085 uint32_t cmd, hdr_len, ip_hlen;
2086 uint16_t etype;
2087
2088 /*
2089 * Determine where frame payload starts.
2090 * Jump over vlan headers if already present,
2091 * helpful for QinQ too.
2092 */
2093 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2094 ("emx_txcsum_pullup is not called (eh)?\n"));
2095 eh = mtod(mp, struct ether_vlan_header *);
2096 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2097 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2098 ("emx_txcsum_pullup is not called (evh)?\n"));
2099 etype = ntohs(eh->evl_proto);
2100 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2101 } else {
2102 etype = ntohs(eh->evl_encap_proto);
2103 ehdrlen = ETHER_HDR_LEN;
2104 }
2105
2106 /*
2107 * We only support TCP/UDP for IPv4 for the moment.
2108 * TODO: Support SCTP too when it hits the tree.
2109 */
2110 if (etype != ETHERTYPE_IP)
2111 return 0;
2112
2113 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2114 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2115
2116 /* NOTE: We could only safely access ip.ip_vhl part */
2117 ip = (struct ip *)(mp->m_data + ehdrlen);
2118 ip_hlen = ip->ip_hl << 2;
2119
2120 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2121
2122 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2123 sc->csum_flags == csum_flags) {
2124 /*
2125 * Same csum offload context as the previous packets;
2126 * just return.
2127 */
2128 *txd_upper = sc->csum_txd_upper;
2129 *txd_lower = sc->csum_txd_lower;
2130 return 0;
2131 }
2132
2133 /*
2134 * Setup a new csum offload context.
2135 */
2136
2137 curr_txd = sc->next_avail_tx_desc;
323e5ecd 2138 tx_buffer = &sc->tx_buf[curr_txd];
5330213c
SZ
2139 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2140
2141 cmd = 0;
2142
2143 /* Setup of IP header checksum. */
2144 if (csum_flags & CSUM_IP) {
2145 /*
2146 * Start offset for header checksum calculation.
2147 * End offset for header checksum calculation.
2148 * Offset of place to put the checksum.
2149 */
2150 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2151 TXD->lower_setup.ip_fields.ipcse =
2152 htole16(ehdrlen + ip_hlen - 1);
2153 TXD->lower_setup.ip_fields.ipcso =
2154 ehdrlen + offsetof(struct ip, ip_sum);
2155 cmd |= E1000_TXD_CMD_IP;
2156 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2157 }
2158 hdr_len = ehdrlen + ip_hlen;
2159
2160 if (csum_flags & CSUM_TCP) {
2161 /*
2162 * Start offset for payload checksum calculation.
2163 * End offset for payload checksum calculation.
2164 * Offset of place to put the checksum.
2165 */
2166 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2167 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2168 TXD->upper_setup.tcp_fields.tucso =
2169 hdr_len + offsetof(struct tcphdr, th_sum);
2170 cmd |= E1000_TXD_CMD_TCP;
2171 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2172 } else if (csum_flags & CSUM_UDP) {
2173 /*
2174 * Start offset for header checksum calculation.
2175 * End offset for header checksum calculation.
2176 * Offset of place to put the checksum.
2177 */
2178 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2179 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2180 TXD->upper_setup.tcp_fields.tucso =
2181 hdr_len + offsetof(struct udphdr, uh_sum);
2182 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2183 }
2184
2185 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2186 E1000_TXD_DTYP_D; /* Data descr */
2187
2188 /* Save the information for this csum offloading context */
2189 sc->csum_ehlen = ehdrlen;
2190 sc->csum_iphlen = ip_hlen;
2191 sc->csum_flags = csum_flags;
2192 sc->csum_txd_upper = *txd_upper;
2193 sc->csum_txd_lower = *txd_lower;
2194
2195 TXD->tcp_seg_setup.data = htole32(0);
2196 TXD->cmd_and_length =
2197 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
5330213c
SZ
2198
2199 if (++curr_txd == sc->num_tx_desc)
2200 curr_txd = 0;
2201
2202 KKASSERT(sc->num_tx_desc_avail > 0);
2203 sc->num_tx_desc_avail--;
2204
2205 sc->next_avail_tx_desc = curr_txd;
2206 return 1;
2207}
2208
2209static int
2210emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2211{
2212 struct mbuf *m = *m0;
2213 struct ether_header *eh;
2214 int len;
2215
2216 sc->tx_csum_try_pullup++;
2217
2218 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2219
2220 if (__predict_false(!M_WRITABLE(m))) {
2221 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2222 sc->tx_csum_drop1++;
2223 m_freem(m);
2224 *m0 = NULL;
2225 return ENOBUFS;
2226 }
2227 eh = mtod(m, struct ether_header *);
2228
2229 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2230 len += EVL_ENCAPLEN;
2231
3752657e 2232 if (m->m_len < len) {
5330213c
SZ
2233 sc->tx_csum_drop2++;
2234 m_freem(m);
2235 *m0 = NULL;
2236 return ENOBUFS;
2237 }
2238 return 0;
2239 }
2240
2241 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2242 sc->tx_csum_pullup1++;
2243 m = m_pullup(m, ETHER_HDR_LEN);
2244 if (m == NULL) {
2245 sc->tx_csum_pullup1_failed++;
2246 *m0 = NULL;
2247 return ENOBUFS;
2248 }
2249 *m0 = m;
2250 }
2251 eh = mtod(m, struct ether_header *);
2252
2253 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2254 len += EVL_ENCAPLEN;
2255
3752657e 2256 if (m->m_len < len) {
5330213c
SZ
2257 sc->tx_csum_pullup2++;
2258 m = m_pullup(m, len);
2259 if (m == NULL) {
2260 sc->tx_csum_pullup2_failed++;
2261 *m0 = NULL;
2262 return ENOBUFS;
2263 }
2264 *m0 = m;
2265 }
2266 return 0;
2267}
2268
2269static void
2270emx_txeof(struct emx_softc *sc)
2271{
2272 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2273 struct emx_txbuf *tx_buffer;
5330213c
SZ
2274 int first, num_avail;
2275
2276 if (sc->tx_dd_head == sc->tx_dd_tail)
2277 return;
2278
2279 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2280 return;
2281
2282 num_avail = sc->num_tx_desc_avail;
2283 first = sc->next_tx_to_clean;
2284
2285 while (sc->tx_dd_head != sc->tx_dd_tail) {
2286 int dd_idx = sc->tx_dd[sc->tx_dd_head];
70172a73 2287 struct e1000_tx_desc *tx_desc;
5330213c
SZ
2288
2289 tx_desc = &sc->tx_desc_base[dd_idx];
5330213c
SZ
2290 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2291 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2292
2293 if (++dd_idx == sc->num_tx_desc)
2294 dd_idx = 0;
2295
2296 while (first != dd_idx) {
2297 logif(pkt_txclean);
2298
5330213c
SZ
2299 num_avail++;
2300
323e5ecd 2301 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2302 if (tx_buffer->m_head) {
2303 ifp->if_opackets++;
2304 bus_dmamap_unload(sc->txtag,
2305 tx_buffer->map);
2306 m_freem(tx_buffer->m_head);
2307 tx_buffer->m_head = NULL;
2308 }
2309
2310 if (++first == sc->num_tx_desc)
2311 first = 0;
2312 }
2313 } else {
2314 break;
2315 }
2316 }
2317 sc->next_tx_to_clean = first;
2318 sc->num_tx_desc_avail = num_avail;
2319
2320 if (sc->tx_dd_head == sc->tx_dd_tail) {
2321 sc->tx_dd_head = 0;
2322 sc->tx_dd_tail = 0;
2323 }
2324
2325 if (!EMX_IS_OACTIVE(sc)) {
2326 ifp->if_flags &= ~IFF_OACTIVE;
2327
2328 /* All clean, turn off the timer */
2329 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2330 ifp->if_timer = 0;
2331 }
2332}
2333
2334static void
2335emx_tx_collect(struct emx_softc *sc)
2336{
2337 struct ifnet *ifp = &sc->arpcom.ac_if;
323e5ecd 2338 struct emx_txbuf *tx_buffer;
5330213c
SZ
2339 int tdh, first, num_avail, dd_idx = -1;
2340
2341 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2342 return;
2343
2344 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2345 if (tdh == sc->next_tx_to_clean)
2346 return;
2347
2348 if (sc->tx_dd_head != sc->tx_dd_tail)
2349 dd_idx = sc->tx_dd[sc->tx_dd_head];
2350
2351 num_avail = sc->num_tx_desc_avail;
2352 first = sc->next_tx_to_clean;
2353
2354 while (first != tdh) {
2355 logif(pkt_txclean);
2356
5330213c
SZ
2357 num_avail++;
2358
323e5ecd 2359 tx_buffer = &sc->tx_buf[first];
5330213c
SZ
2360 if (tx_buffer->m_head) {
2361 ifp->if_opackets++;
2362 bus_dmamap_unload(sc->txtag,
2363 tx_buffer->map);
2364 m_freem(tx_buffer->m_head);
2365 tx_buffer->m_head = NULL;
2366 }
2367
2368 if (first == dd_idx) {
2369 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2370 if (sc->tx_dd_head == sc->tx_dd_tail) {
2371 sc->tx_dd_head = 0;
2372 sc->tx_dd_tail = 0;
2373 dd_idx = -1;
2374 } else {
2375 dd_idx = sc->tx_dd[sc->tx_dd_head];
2376 }
2377 }
2378
2379 if (++first == sc->num_tx_desc)
2380 first = 0;
2381 }
2382 sc->next_tx_to_clean = first;
2383 sc->num_tx_desc_avail = num_avail;
2384
2385 if (!EMX_IS_OACTIVE(sc)) {
2386 ifp->if_flags &= ~IFF_OACTIVE;
2387
2388 /* All clean, turn off the timer */
2389 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2390 ifp->if_timer = 0;
2391 }
2392}
2393
2394/*
2395 * When Link is lost sometimes there is work still in the TX ring
2396 * which will result in a watchdog, rather than allow that do an
2397 * attempted cleanup and then reinit here. Note that this has been
2398 * seens mostly with fiber adapters.
2399 */
2400static void
2401emx_tx_purge(struct emx_softc *sc)
2402{
2403 struct ifnet *ifp = &sc->arpcom.ac_if;
2404
2405 if (!sc->link_active && ifp->if_timer) {
2406 emx_tx_collect(sc);
2407 if (ifp->if_timer) {
2408 if_printf(ifp, "Link lost, TX pending, reinit\n");
2409 ifp->if_timer = 0;
2410 emx_init(sc);
2411 }
2412 }
2413}
2414
2415static int
c39e3a1f 2416emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
5330213c
SZ
2417{
2418 struct mbuf *m;
2419 bus_dma_segment_t seg;
2420 bus_dmamap_t map;
323e5ecd 2421 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2422 int error, nseg;
2423
2424 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2425 if (m == NULL) {
c39e3a1f 2426 rdata->mbuf_cluster_failed++;
5330213c
SZ
2427 if (init) {
2428 if_printf(&sc->arpcom.ac_if,
2429 "Unable to allocate RX mbuf\n");
2430 }
2431 return (ENOBUFS);
2432 }
2433 m->m_len = m->m_pkthdr.len = MCLBYTES;
2434
2435 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2436 m_adj(m, ETHER_ALIGN);
2437
c39e3a1f
SZ
2438 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2439 rdata->rx_sparemap, m,
5330213c
SZ
2440 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2441 if (error) {
2442 m_freem(m);
2443 if (init) {
2444 if_printf(&sc->arpcom.ac_if,
2445 "Unable to load RX mbuf\n");
2446 }
2447 return (error);
2448 }
2449
323e5ecd 2450 rx_buffer = &rdata->rx_buf[i];
5330213c 2451 if (rx_buffer->m_head != NULL)
c39e3a1f 2452 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
5330213c
SZ
2453
2454 map = rx_buffer->map;
c39e3a1f
SZ
2455 rx_buffer->map = rdata->rx_sparemap;
2456 rdata->rx_sparemap = map;
5330213c
SZ
2457
2458 rx_buffer->m_head = m;
235b9d30 2459 rx_buffer->paddr = seg.ds_addr;
5330213c 2460
235b9d30 2461 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
5330213c
SZ
2462 return (0);
2463}
2464
2465static int
c39e3a1f 2466emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2467{
2468 device_t dev = sc->dev;
323e5ecd 2469 struct emx_rxbuf *rx_buffer;
bdca134f
SZ
2470 int i, error, rsize;
2471
2472 /*
2473 * Validate number of receive descriptors. It must not exceed
2474 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2475 */
3f939c23 2476 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
bdca134f
SZ
2477 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2478 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2479 EMX_DEFAULT_RXD, emx_rxd);
c39e3a1f 2480 rdata->num_rx_desc = EMX_DEFAULT_RXD;
bdca134f 2481 } else {
c39e3a1f 2482 rdata->num_rx_desc = emx_rxd;
bdca134f
SZ
2483 }
2484
2485 /*
2486 * Allocate Receive Descriptor ring
2487 */
235b9d30 2488 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
bdca134f 2489 EMX_DBA_ALIGN);
235b9d30 2490 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
a596084c 2491 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
c39e3a1f
SZ
2492 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2493 &rdata->rx_desc_paddr);
235b9d30 2494 if (rdata->rx_desc == NULL) {
bdca134f 2495 device_printf(dev, "Unable to allocate rx_desc memory\n");
a596084c 2496 return ENOMEM;
bdca134f 2497 }
5330213c 2498
323e5ecd
SZ
2499 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2500 M_DEVBUF, M_WAITOK | M_ZERO);
5330213c
SZ
2501
2502 /*
2503 * Create DMA tag for rx buffers
2504 */
2505 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2506 1, 0, /* alignment, bounds */
2507 BUS_SPACE_MAXADDR, /* lowaddr */
2508 BUS_SPACE_MAXADDR, /* highaddr */
2509 NULL, NULL, /* filter, filterarg */
2510 MCLBYTES, /* maxsize */
2511 1, /* nsegments */
2512 MCLBYTES, /* maxsegsize */
2513 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
c39e3a1f 2514 &rdata->rxtag);
5330213c
SZ
2515 if (error) {
2516 device_printf(dev, "Unable to allocate RX DMA tag\n");
323e5ecd
SZ
2517 kfree(rdata->rx_buf, M_DEVBUF);
2518 rdata->rx_buf = NULL;
5330213c
SZ
2519 return error;
2520 }
2521
2522 /*
2523 * Create spare DMA map for rx buffers
2524 */
c39e3a1f
SZ
2525 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2526 &rdata->rx_sparemap);
5330213c
SZ
2527 if (error) {
2528 device_printf(dev, "Unable to create spare RX DMA map\n");
c39e3a1f 2529 bus_dma_tag_destroy(rdata->rxtag);
323e5ecd
SZ
2530 kfree(rdata->rx_buf, M_DEVBUF);
2531 rdata->rx_buf = NULL;
5330213c
SZ
2532 return error;
2533 }
2534
2535 /*
2536 * Create DMA maps for rx buffers
2537 */
c39e3a1f 2538 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2539 rx_buffer = &rdata->rx_buf[i];
5330213c 2540
c39e3a1f 2541 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
5330213c
SZ
2542 &rx_buffer->map);
2543 if (error) {
2544 device_printf(dev, "Unable to create RX DMA map\n");
c39e3a1f 2545 emx_destroy_rx_ring(sc, rdata, i);
5330213c
SZ
2546 return error;
2547 }
2548 }
2549 return (0);
2550}
2551
c39e3a1f
SZ
2552static void
2553emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2554{
2555 int i;
2556
2557 for (i = 0; i < rdata->num_rx_desc; i++) {
323e5ecd 2558 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
c39e3a1f
SZ
2559
2560 if (rx_buffer->m_head != NULL) {
2561 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2562 m_freem(rx_buffer->m_head);
2563 rx_buffer->m_head = NULL;
2564 }
2565 }
2566
2567 if (rdata->fmp != NULL)
2568 m_freem(rdata->fmp);
2569 rdata->fmp = NULL;
2570 rdata->lmp = NULL;
2571}
2572
5330213c 2573static int
c39e3a1f 2574emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
5330213c
SZ
2575{
2576 int i, error;
2577
2578 /* Reset descriptor ring */
235b9d30 2579 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
5330213c
SZ
2580
2581 /* Allocate new ones. */
c39e3a1f
SZ
2582 for (i = 0; i < rdata->num_rx_desc; i++) {
2583 error = emx_newbuf(sc, rdata, i, 1);
5330213c
SZ
2584 if (error)
2585 return (error);
2586 }
2587
2588 /* Setup our descriptor pointers */
c39e3a1f 2589 rdata->next_rx_desc_to_check = 0;
5330213c
SZ
2590
2591 return (0);
2592}
2593
2594static void
2595emx_init_rx_unit(struct emx_softc *sc)
2596{
2597 struct ifnet *ifp = &sc->arpcom.ac_if;
2598 uint64_t bus_addr;
89d8e73d 2599 uint32_t rctl, rxcsum, rfctl;
3f939c23 2600 int i;
5330213c
SZ
2601
2602 /*
2603 * Make sure receives are disabled while setting
2604 * up the descriptor ring
2605 */
2606 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2607 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2608
2609 /*
2610 * Set the interrupt throttling rate. Value is calculated
2611 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2612 */
2613 if (sc->int_throttle_ceil) {
2614 E1000_WRITE_REG(&sc->hw, E1000_ITR,
2615 1000000000 / 256 / sc->int_throttle_ceil);
2616 } else {
2617 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0);
2618 }
2619
235b9d30
SZ
2620 /* Use extended RX descriptor */
2621 rfctl = E1000_RFCTL_EXTEN;
2622
5330213c 2623 /* Disable accelerated ackknowledge */
235b9d30
SZ
2624 if (sc->hw.mac.type == e1000_82574)
2625 rfctl |= E1000_RFCTL_ACK_DIS;
2626
2627 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
5330213c
SZ
2628
2629 /* Setup the Base and Length of the Rx Descriptor Ring */
8434a83b 2630 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
2631 struct emx_rxdata *rdata = &sc->rx_data[i];
2632
2633 bus_addr = rdata->rx_desc_paddr;
2634 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2635 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2636 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2637 (uint32_t)(bus_addr >> 32));
2638 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2639 (uint32_t)bus_addr);
2640 }
5330213c
SZ
2641
2642 /* Setup the Receive Control Register */
2643 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2644 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
0acc29d6 2645 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
5330213c
SZ
2646 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2647
2648 /* Make sure VLAN Filters are off */
2649 rctl &= ~E1000_RCTL_VFE;
2650
80d8e1ca
SZ
2651 /* Don't store bad paket */
2652 rctl &= ~E1000_RCTL_SBP;
5330213c 2653
c39e3a1f
SZ
2654 /* MCLBYTES */
2655 rctl |= E1000_RCTL_SZ_2048;
5330213c
SZ
2656
2657 if (ifp->if_mtu > ETHERMTU)
2658 rctl |= E1000_RCTL_LPE;
2659 else
2660 rctl &= ~E1000_RCTL_LPE;
2661
65c7a6af
SZ
2662 /*
2663 * Receive Checksum Offload for TCP and UDP
2664 *
2665 * Checksum offloading is also enabled if multiple receive
2666 * queue is to be supported, since we need it to figure out
2667 * packet type.
2668 */
8434a83b 2669 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
5330213c 2670 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3f939c23
SZ
2671
2672 /*
2673 * NOTE:
2674 * PCSD must be enabled to enable multiple
2675 * receive queues.
2676 */
2677 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2678 E1000_RXCSUM_PCSD;
5330213c
SZ
2679 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2680 }
2681
3f939c23 2682 /*
65c7a6af 2683 * Configure multiple receive queue (RSS)
3f939c23 2684 */
8434a83b 2685 if (ifp->if_capenable & IFCAP_RSS) {
89d8e73d
SZ
2686 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2687 uint32_t reta;
2688
2689 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2690 ("invalid number of RX ring (%d)",
2691 sc->rx_ring_inuse));
2692
65c7a6af
SZ
2693 /*
2694 * NOTE:
2695 * When we reach here, RSS has already been disabled
2696 * in emx_stop(), so we could safely configure RSS key
2697 * and redirect table.
2698 */
3f939c23 2699
65c7a6af
SZ
2700 /*
2701 * Configure RSS key
2702 */
89d8e73d
SZ
2703 toeplitz_get_key(key, sizeof(key));
2704 for (i = 0; i < EMX_NRSSRK; ++i) {
2705 uint32_t rssrk;
2706
2707 rssrk = EMX_RSSRK_VAL(key, i);
2708 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2709
2710 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2711 }
3f939c23 2712
65c7a6af 2713 /*
89d8e73d
SZ
2714 * Configure RSS redirect table in following fashion:
2715 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
65c7a6af 2716 */
89d8e73d
SZ
2717 reta = 0;
2718 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2719 uint32_t q;
2720
2721 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2722 reta |= q << (8 * i);
2723 }
2724 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2725
65c7a6af
SZ
2726 for (i = 0; i < EMX_NRETA; ++i)
2727 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3f939c23 2728
65c7a6af
SZ
2729 /*
2730 * Enable multiple receive queues.
2731 * Enable IPv4 RSS standard hash functions.
2732 * Disable RSS interrupt.
2733 */
2734 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2735 E1000_MRQC_ENABLE_RSS_2Q |
2736 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2737 E1000_MRQC_RSS_FIELD_IPV4);
2738 }
3f939c23 2739
5330213c
SZ
2740 /*
2741 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2742 * long latencies are observed, like Lenovo X60. This
2743 * change eliminates the problem, but since having positive
2744 * values in RDTR is a known source of problems on other
2745 * platforms another solution is being sought.
2746 */
2747 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2748 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2749 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2750 }
2751
5330213c
SZ
2752 /*
2753 * Setup the HW Rx Head and Tail Descriptor Pointers
2754 */
8434a83b 2755 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3f939c23
SZ
2756 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2757 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2758 sc->rx_data[i].num_rx_desc - 1);
2759 }
2760
2761 /* Enable Receives */
2762 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
5330213c
SZ
2763}
2764
2765static void
c39e3a1f 2766emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
5330213c 2767{
323e5ecd 2768 struct emx_rxbuf *rx_buffer;
5330213c
SZ
2769 int i;
2770
bdca134f 2771 /* Free Receive Descriptor ring */
235b9d30 2772 if (rdata->rx_desc) {
c39e3a1f 2773 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
235b9d30 2774 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
c39e3a1f
SZ
2775 rdata->rx_desc_dmap);
2776 bus_dma_tag_destroy(rdata->rx_desc_dtag);
a596084c 2777
235b9d30 2778 rdata->rx_desc = NULL;
a596084c 2779 }
bdca134f 2780
323e5ecd 2781 if (rdata->rx_buf == NULL)
5330213c
SZ
2782 return;
2783
2784 for (i = 0; i < ndesc; i++) {
323e5ecd 2785 rx_buffer = &rdata->rx_buf[i];
5330213c
SZ
2786
2787 KKASSERT(rx_buffer->m_head == NULL);
c39e3a1f 2788 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
5330213c 2789 }
c39e3a1f
SZ
2790 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2791 bus_dma_tag_destroy(rdata->rxtag);
5330213c 2792
323e5ecd
SZ
2793 kfree(rdata->rx_buf, M_DEVBUF);
2794 rdata->rx_buf = NULL;
5330213c
SZ
2795}
2796
2797static void
c39e3a1f 2798emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
5330213c 2799{
c39e3a1f 2800 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
5330213c 2801 struct ifnet *ifp = &sc->arpcom.ac_if;
235b9d30 2802 uint32_t staterr;
235b9d30 2803 emx_rxdesc_t *current_desc;
5330213c
SZ
2804 struct mbuf *mp;
2805 int i;
2806 struct mbuf_chain chain[MAXCPU];
2807
c39e3a1f 2808 i = rdata->next_rx_desc_to_check;
235b9d30
SZ
2809 current_desc = &rdata->rx_desc[i];
2810 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2811
235b9d30 2812 if (!(staterr & E1000_RXD_STAT_DD))
5330213c
SZ
2813 return;
2814
2815 ether_input_chain_init(chain);
2816
235b9d30 2817 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
9cc86e17 2818 struct pktinfo *pi = NULL, pi0;
235b9d30 2819 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
5330213c 2820 struct mbuf *m = NULL;
0acc29d6 2821 int eop, len;
5330213c
SZ
2822
2823 logif(pkt_receive);
2824
235b9d30 2825 mp = rx_buf->m_head;
5330213c
SZ
2826
2827 /*
2828 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2829 * needs to access the last received byte in the mbuf.
2830 */
235b9d30 2831 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
5330213c
SZ
2832 BUS_DMASYNC_POSTREAD);
2833
0acc29d6 2834 len = le16toh(current_desc->rxd_length);
235b9d30 2835 if (staterr & E1000_RXD_STAT_EOP) {
5330213c
SZ
2836 count--;
2837 eop = 1;
5330213c
SZ
2838 } else {
2839 eop = 0;
5330213c
SZ
2840 }
2841
235b9d30
SZ
2842 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2843 uint16_t vlan = 0;
3f939c23 2844 uint32_t mrq, rss_hash;
235b9d30
SZ
2845
2846 /*
2847 * Save several necessary information,
2848 * before emx_newbuf() destroy it.
2849 */
2850 if ((staterr & E1000_RXD_STAT_VP) && eop)
2851 vlan = le16toh(current_desc->rxd_vlan);
5330213c 2852
3f939c23
SZ
2853 mrq = le32toh(current_desc->rxd_mrq);
2854 rss_hash = le32toh(current_desc->rxd_rss);
2855
2856 EMX_RSS_DPRINTF(sc, 10,
2857 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2858 ring_idx, mrq, rss_hash);
2859
c39e3a1f 2860 if (emx_newbuf(sc, rdata, i, 0) != 0) {
5330213c
SZ
2861 ifp->if_iqdrops++;
2862 goto discard;
2863 }
2864
2865 /* Assign correct length to the current fragment */
2866 mp->m_len = len;
2867
c39e3a1f 2868 if (rdata->fmp == NULL) {
5330213c 2869 mp->m_pkthdr.len = len;
c39e3a1f
SZ
2870 rdata->fmp = mp; /* Store the first mbuf */
2871 rdata->lmp = mp;
5330213c
SZ
2872 } else {
2873 /*
2874 * Chain mbuf's together
2875 */
c39e3a1f
SZ
2876 rdata->lmp->m_next = mp;
2877 rdata->lmp = rdata->lmp->m_next;
2878 rdata->fmp->m_pkthdr.len += len;
5330213c
SZ
2879 }
2880
2881 if (eop) {
c39e3a1f 2882 rdata->fmp->m_pkthdr.rcvif = ifp;
5330213c
SZ
2883 ifp->if_ipackets++;
2884
235b9d30
SZ
2885 if (ifp->if_capenable & IFCAP_RXCSUM)
2886 emx_rxcsum(staterr, rdata->fmp);
5330213c 2887
235b9d30 2888 if (staterr & E1000_RXD_STAT_VP) {
c39e3a1f 2889 rdata->fmp->m_pkthdr.ether_vlantag =
235b9d30 2890 vlan;
c39e3a1f 2891 rdata->fmp->m_flags |= M_VLANTAG;
5330213c 2892 }
c39e3a1f
SZ
2893 m = rdata->fmp;
2894 rdata->fmp = NULL;
2895 rdata->lmp = NULL;
3f939c23 2896
9cc86e17
SZ
2897 if (ifp->if_capenable & IFCAP_RSS) {
2898 pi = emx_rssinfo(m, &pi0, mrq,
2899 rss_hash, staterr);
2900 }
3f939c23
SZ
2901#ifdef EMX_RSS_DEBUG
2902 rdata->rx_pkts++;
2903#endif
5330213c
SZ
2904 }
2905 } else {
2906 ifp->if_ierrors++;
2907discard:
235b9d30 2908 emx_setup_rxdesc(current_desc, rx_buf);
c39e3a1f
SZ
2909 if (rdata->fmp != NULL) {
2910 m_freem(rdata->fmp);
2911 rdata->fmp = NULL;
2912 rdata->lmp = NULL;
5330213c
SZ
2913 }
2914 m = NULL;
2915 }
2916
5330213c 2917 if (m != NULL)
9cc86e17 2918 ether_input_chain(ifp, m, pi, chain);
5330213c
SZ
2919
2920 /* Advance our pointers to the next descriptor. */
c39e3a1f 2921 if (++i == rdata->num_rx_desc)
5330213c 2922 i = 0;
235b9d30
SZ
2923
2924 current_desc = &rdata->rx_desc[i];
2925 staterr = le32toh(current_desc->rxd_staterr);
5330213c 2926 }
c39e3a1f 2927 rdata->next_rx_desc_to_check = i;
5330213c
SZ
2928
2929 ether_input_dispatch(chain);
2930
3f939c23 2931 /* Advance the E1000's Receive Queue "Tail Pointer". */
5330213c 2932 if (--i < 0)
c39e3a1f 2933 i = rdata->num_rx_desc - 1;
3f939c23 2934 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
5330213c
SZ
2935}
2936
5330213c
SZ
2937static void
2938emx_enable_intr(struct emx_softc *sc)
2939{
6d435846 2940 lwkt_serialize_handler_enable(&sc->main_serialize);
5330213c
SZ
2941 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2942}
2943
2944static void
2945emx_disable_intr(struct emx_softc *sc)
2946{
2947 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
6d435846 2948 lwkt_serialize_handler_disable(&sc->main_serialize);
5330213c
SZ
2949}
2950
2951/*
2952 * Bit of a misnomer, what this really means is
2953 * to enable OS management of the system... aka
2954 * to disable special hardware management features
2955 */
2956static void
2957emx_get_mgmt(struct emx_softc *sc)
2958{
2959 /* A shared code workaround */
2960 if (sc->has_manage) {
2961 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2962 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2963
2964 /* disable hardware interception of ARP */
2965 manc &= ~(E1000_MANC_ARP_EN);
2966
2967 /* enable receiving management packets to the host */
2968 manc |= E1000_MANC_EN_MNG2HOST;
2969#define E1000_MNG2HOST_PORT_623 (1 << 5)
2970#define E1000_MNG2HOST_PORT_664 (1 << 6)
2971 manc2h |= E1000_MNG2HOST_PORT_623;
2972 manc2h |= E1000_MNG2HOST_PORT_664;
2973 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2974
2975 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2976 }
2977}
2978
2979/*
2980 * Give control back to hardware management
2981 * controller if there is one.
2982 */
2983static void
2984emx_rel_mgmt(struct emx_softc *sc)
2985{
2986 if (sc->has_manage) {
2987 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2988
2989 /* re-enable hardware interception of ARP */
2990 manc |= E1000_MANC_ARP_EN;
2991 manc &= ~E1000_MANC_EN_MNG2HOST;
2992
2993 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2994 }
2995}
2996
2997/*
2998 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
2999 * For ASF and Pass Through versions of f/w this means that
3000 * the driver is loaded. For AMT version (only with 82573)
3001 * of the f/w this means that the network i/f is open.
3002 */
3003static void
3004emx_get_hw_control(struct emx_softc *sc)
3005{
3006 uint32_t ctrl_ext, swsm;
3007
3008 /* Let firmware know the driver has taken over */
3009 switch (sc->hw.mac.type) {
3010 case e1000_82573:
3011 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3012 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3013 swsm | E1000_SWSM_DRV_LOAD);
3014 break;
3015
3016 case e1000_82571:
3017 case e1000_82572:
3018 case e1000_80003es2lan:
3019 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3020 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3021 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3022 break;
3023
3024 default:
3025 break;
3026 }
3027}
3028
3029/*
3030 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3031 * For ASF and Pass Through versions of f/w this means that the
3032 * driver is no longer loaded. For AMT version (only with 82573)
3033 * of the f/w this means that the network i/f is closed.
3034 */
3035static void
3036emx_rel_hw_control(struct emx_softc *sc)
3037{
3038 uint32_t ctrl_ext, swsm;
3039
3040 /* Let firmware taken over control of h/w */
3041 switch (sc->hw.mac.type) {
3042 case e1000_82573:
3043 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3044 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3045 swsm & ~E1000_SWSM_DRV_LOAD);
3046 break;
3047
3048 case e1000_82571:
3049 case e1000_82572:
3050 case e1000_80003es2lan:
3051 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3052 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3053 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3054 break;
3055
3056 default:
3057 break;
3058 }
3059}
3060
3061static int
3062emx_is_valid_eaddr(const uint8_t *addr)
3063{
3064 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3065
3066 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3067 return (FALSE);
3068
3069 return (TRUE);
3070}
3071
3072/*
3073 * Enable PCI Wake On Lan capability
3074 */
3075void
3076emx_enable_wol(device_t dev)
3077{
3078 uint16_t cap, status;
3079 uint8_t id;
3080
3081 /* First find the capabilities pointer*/
3082 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3083
3084 /* Read the PM Capabilities */
3085 id = pci_read_config(dev, cap, 1);
3086 if (id != PCIY_PMG) /* Something wrong */
3087 return;
3088
3089 /*
3090 * OK, we have the power capabilities,
3091 * so now get the status register
3092 */
3093 cap += PCIR_POWER_STATUS;
3094 status = pci_read_config(dev, cap, 2);
3095 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3096 pci_write_config(dev, cap, status, 2);
3097}
3098
3099static void
3100emx_update_stats(struct emx_softc *sc)
3101{
3102 struct ifnet *ifp = &sc->arpcom.ac_if;
3103
3104 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3105 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3106 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3107 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3108 }
3109 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3110 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3111 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3112 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3113
3114 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3115 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3116 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3117 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3118 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3119 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3120 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3121 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3122 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3123 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3124 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3125 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3126 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3127 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3128 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3129 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3130 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3131 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3132 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3133 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3134
3135 /* For the 64-bit byte counters the low dword must be read first. */
3136 /* Both registers clear on the read of the high dword */
3137
3138 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3139 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3140
3141 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3142 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3143 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3144 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3145 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3146
3147 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3148 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3149
3150 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3151 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3152 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3153 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3154 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3155 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3156 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3157 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3158 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3159 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3160
3161 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3162 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3163 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3164 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3165 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3166 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3167
3168 ifp->if_collisions = sc->stats.colc;
3169
3170 /* Rx Errors */
3171 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3172 sc->stats.crcerrs + sc->stats.algnerrc +
3173 sc->stats.ruc + sc->stats.roc +
3174 sc->stats.mpc + sc->stats.cexterr;
3175
3176 /* Tx Errors */
3177 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3178 sc->watchdog_events;
3179}
3180
3181static void
3182emx_print_debug_info(struct emx_softc *sc)
3183{
3184 device_t dev = sc->dev;
3185 uint8_t *hw_addr = sc->hw.hw_addr;
3186
3187 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3188 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3189 E1000_READ_REG(&sc->hw, E1000_CTRL),
3190 E1000_READ_REG(&sc->hw, E1000_RCTL));
3191 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3192 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3193 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3194 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3195 sc->hw.fc.high_water, sc->hw.fc.low_water);
3196 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3197 E1000_READ_REG(&sc->hw, E1000_TIDV),
3198 E1000_READ_REG(&sc->hw, E1000_TADV));
3199 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3200 E1000_READ_REG(&sc->hw, E1000_RDTR),
3201 E1000_READ_REG(&sc->hw, E1000_RADV));
3202 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3203 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3204 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3205 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3206 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3207 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3208 device_printf(dev, "Num Tx descriptors avail = %d\n",
3209 sc->num_tx_desc_avail);
3210 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3211 sc->no_tx_desc_avail1);
3212 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3213 sc->no_tx_desc_avail2);
3214 device_printf(dev, "Std mbuf failed = %ld\n",
3215 sc->mbuf_alloc_failed);
3216 device_printf(dev, "Std mbuf cluster failed = %ld\n",
c39e3a1f 3217 sc->rx_data[0].mbuf_cluster_failed);
5330213c
SZ
3218 device_printf(dev, "Driver dropped packets = %ld\n",
3219 sc->dropped_pkts);
3220 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3221 sc->no_tx_dma_setup);
3222
3223 device_printf(dev, "TXCSUM try pullup = %lu\n",
3224 sc->tx_csum_try_pullup);
3225 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3226 sc->tx_csum_pullup1);
3227 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3228 sc->tx_csum_pullup1_failed);
3229 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3230 sc->tx_csum_pullup2);
3231 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3232 sc->tx_csum_pullup2_failed);
3233 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3234 sc->tx_csum_drop1);
3235 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3236 sc->tx_csum_drop2);
3237}
3238
3239static void
3240emx_print_hw_stats(struct emx_softc *sc)
3241{
3242 device_t dev = sc->dev;
3243
3244 device_printf(dev, "Excessive collisions = %lld\n",
3245 (long long)sc->stats.ecol);
3246#if (DEBUG_HW > 0) /* Dont output these errors normally */
3247 device_printf(dev, "Symbol errors = %lld\n",
3248 (long long)sc->stats.symerrs);
3249#endif
3250 device_printf(dev, "Sequence errors = %lld\n",
3251 (long long)sc->stats.sec);
3252 device_printf(dev, "Defer count = %lld\n",
3253 (long long)sc->stats.dc);
3254 device_printf(dev, "Missed Packets = %lld\n",
3255 (long long)sc->stats.mpc);
3256 device_printf(dev, "Receive No Buffers = %lld\n",
3257 (long long)sc->stats.rnbc);
3258 /* RLEC is inaccurate on some hardware, calculate our own. */
3259 device_printf(dev, "Receive Length Errors = %lld\n",
3260 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3261 device_printf(dev, "Receive errors = %lld\n",
3262 (long long)sc->stats.rxerrc);
3263 device_printf(dev, "Crc errors = %lld\n",
3264 (long long)sc->stats.crcerrs);
3265 device_printf(dev, "Alignment errors = %lld\n",
3266 (long long)sc->stats.algnerrc);
3267 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3268 (long long)sc->stats.cexterr);
3269 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3270 device_printf(dev, "watchdog timeouts = %ld\n",
3271 sc->watchdog_events);
3272 device_printf(dev, "XON Rcvd = %lld\n",
3273 (long long)sc->stats.xonrxc);
3274 device_printf(dev, "XON Xmtd = %lld\n",
3275 (long long)sc->stats.xontxc);
3276 device_printf(dev, "XOFF Rcvd = %lld\n",
3277 (long long)sc->stats.xoffrxc);
3278 device_printf(dev, "XOFF Xmtd = %lld\n",
3279 (long long)sc->stats.xofftxc);
3280 device_printf(dev, "Good Packets Rcvd = %lld\n",
3281 (long long)sc->stats.gprc);
3282 device_printf(dev, "Good Packets Xmtd = %lld\n",
3283 (long long)sc->stats.gptc);
3284}
3285
3286static void
3287emx_print_nvm_info(struct emx_softc *sc)
3288{
3289 uint16_t eeprom_data;
3290 int i, j, row = 0;
3291
3292 /* Its a bit crude, but it gets the job done */
3293 kprintf("\nInterface EEPROM Dump:\n");
3294 kprintf("Offset\n0x0000 ");
3295 for (i = 0, j = 0; i < 32; i++, j++) {
3296 if (j == 8) { /* Make the offset block */
3297 j = 0; ++row;
3298 kprintf("\n0x00%x0 ",row);
3299 }
3300 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3301 kprintf("%04x ", eeprom_data);
3302 }
3303 kprintf("\n");
3304}
3305
3306static int
3307emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3308{
3309 struct emx_softc *sc;
3310 struct ifnet *ifp;
3311 int error, result;
3312
3313 result = -1;
3314 error = sysctl_handle_int(oidp, &result, 0, req);
3315 if (error || !req->newptr)
3316 return (error);
3317
3318 sc = (struct emx_softc *)arg1;
3319 ifp = &sc->arpcom.ac_if;
3320
6d435846 3321 ifnet_serialize_all(ifp);
5330213c
SZ
3322
3323 if (result == 1)
3324 emx_print_debug_info(sc);
3325
3326 /*
3327 * This value will cause a hex dump of the
3328 * first 32 16-bit words of the EEPROM to
3329 * the screen.
3330 */
3331 if (result == 2)
3332 emx_print_nvm_info(sc);
3333
6d435846 3334 ifnet_deserialize_all(ifp);
5330213c
SZ
3335
3336 return (error);
3337}
3338
3339static int
3340emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3341{
3342 int error, result;
3343
3344 result = -1;
3345 error = sysctl_handle_int(oidp, &result, 0, req);
3346 if (error || !req->newptr)
3347 return (error);
3348
3349 if (result == 1) {
3350 struct emx_softc *sc = (struct emx_softc *)arg1;
3351 struct ifnet *ifp = &sc->arpcom.ac_if;
3352
6d435846 3353 ifnet_serialize_all(ifp);
5330213c 3354 emx_print_hw_stats(sc);
6d435846 3355 ifnet_deserialize_all(ifp);
5330213c
SZ
3356 }
3357 return (error);
3358}
3359
3360static void
3361emx_add_sysctl(struct emx_softc *sc)
3362{
3f939c23
SZ
3363#ifdef EMX_RSS_DEBUG
3364 char rx_pkt[32];
3365 int i;
3366#endif
5330213c
SZ
3367
3368 sysctl_ctx_init(&sc->sysctl_ctx);
3369 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3370 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3371 device_get_nameunit(sc->dev),
3372 CTLFLAG_RD, 0, "");
3373 if (sc->sysctl_tree == NULL) {
3374 device_printf(sc->dev, "can't add sysctl node\n");
3375 return;
3376 }
3377
3378 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3379 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3380 emx_sysctl_debug_info, "I", "Debug Information");
3381
3382 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3383 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3384 emx_sysctl_stats, "I", "Statistics");
3385
3386 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f
SZ
3387 OID_AUTO, "rxd", CTLFLAG_RD,
3388 &sc->rx_data[0].num_rx_desc, 0, NULL);
5330213c 3389 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
c39e3a1f 3390 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
5330213c 3391
5330213c
SZ
3392 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3393 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3394 sc, 0, emx_sysctl_int_throttle, "I",
3395 "interrupt throttling rate");
3396 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3397 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3398 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3399 "# segments per TX interrupt");
3f939c23 3400
8434a83b
SZ
3401 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3402 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3403 &sc->rx_ring_inuse, 0, "RX ring in use");
3404
3f939c23
SZ
3405#ifdef EMX_RSS_DEBUG
3406 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3407 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3408 0, "RSS debug level");
65c7a6af 3409 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3410 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3411 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3412 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
89d8e73d 3413 rx_pkt, CTLFLAG_RW,
3f939c23
SZ
3414 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3415 }
3416#endif
5330213c
SZ
3417}
3418
3419static int
3420emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3421{
3422 struct emx_softc *sc = (void *)arg1;
3423 struct ifnet *ifp = &sc->arpcom.ac_if;
3424 int error, throttle;
3425
3426 throttle = sc->int_throttle_ceil;
3427 error = sysctl_handle_int(oidp, &throttle, 0, req);
3428 if (error || req->newptr == NULL)
3429 return error;
3430 if (throttle < 0 || throttle > 1000000000 / 256)
3431 return EINVAL;
3432
3433 if (throttle) {
3434 /*
3435 * Set the interrupt throttling rate in 256ns increments,
3436 * recalculate sysctl value assignment to get exact frequency.
3437 */
3438 throttle = 1000000000 / 256 / throttle;
3439
3440 /* Upper 16bits of ITR is reserved and should be zero */
3441 if (throttle & 0xffff0000)
3442 return EINVAL;
3443 }
3444
6d435846 3445 ifnet_serialize_all(ifp);
5330213c
SZ
3446
3447 if (throttle)
3448 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3449 else
3450 sc->int_throttle_ceil = 0;
3451
3452 if (ifp->if_flags & IFF_RUNNING)
3453 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle);
3454
6d435846 3455 ifnet_deserialize_all(ifp);
5330213c
SZ
3456
3457 if (bootverbose) {
3458 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3459 sc->int_throttle_ceil);
3460 }
3461 return 0;
3462}
3463
3464static int
3465emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3466{
3467 struct emx_softc *sc = (void *)arg1;
3468 struct ifnet *ifp = &sc->arpcom.ac_if;
3469 int error, segs;
3470
3471 segs = sc->tx_int_nsegs;
3472 error = sysctl_handle_int(oidp, &segs, 0, req);
3473 if (error || req->newptr == NULL)
3474 return error;
3475 if (segs <= 0)
3476 return EINVAL;
3477
6d435846 3478 ifnet_serialize_all(ifp);
5330213c
SZ
3479
3480 /*
3481 * Don't allow int_tx_nsegs to become:
3482 * o Less the oact_tx_desc
3483 * o Too large that no TX desc will cause TX interrupt to
3484 * be generated (OACTIVE will never recover)
3485 * o Too small that will cause tx_dd[] overflow
3486 */
3487 if (segs < sc->oact_tx_desc ||
3488 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3489 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3490 error = EINVAL;
3491 } else {
3492 error = 0;
3493 sc->tx_int_nsegs = segs;
3494 }
3495
6d435846 3496 ifnet_deserialize_all(ifp);
5330213c
SZ
3497
3498 return error;
3499}
071699f8
SZ
3500
3501static int
3502emx_dma_alloc(struct emx_softc *sc)
3503{
3f939c23 3504 int error, i;
071699f8
SZ
3505
3506 /*
3507 * Create top level busdma tag
3508 */
3509 error = bus_dma_tag_create(NULL, 1, 0,
3510 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3511 NULL, NULL,
3512 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3513 0, &sc->parent_dtag);
3514 if (error) {
3515 device_printf(sc->dev, "could not create top level DMA tag\n");
3516 return error;
3517 }
3518
3519 /*
3520 * Allocate transmit descriptors ring and buffers
3521 */
3522 error = emx_create_tx_ring(sc);
3523 if (error) {
3524 device_printf(sc->dev, "Could not setup transmit structures\n");
3525 return error;
3526 }
3527
3528 /*
3529 * Allocate receive descriptors ring and buffers
3530 */
65c7a6af 3531 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3532 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3533 if (error) {
3534 device_printf(sc->dev,
3535 "Could not setup receive structures\n");
3536 return error;
3537 }
071699f8
SZ
3538 }
3539 return 0;
3540}
3541
3542static void
3543emx_dma_free(struct emx_softc *sc)
3544{
3f939c23
SZ
3545 int i;
3546
071699f8 3547 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3f939c23 3548
65c7a6af 3549 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3f939c23
SZ
3550 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3551 sc->rx_data[i].num_rx_desc);
3552 }
071699f8
SZ
3553
3554 /* Free top level busdma tag */
3555 if (sc->parent_dtag != NULL)
3556 bus_dma_tag_destroy(sc->parent_dtag);
3557}
6d435846
SZ
3558
3559static void
3560emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3561{
3562 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3563
3564 switch (slz) {
3565 case IFNET_SERIALIZE_ALL:
f61533ad 3566 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
6d435846
SZ
3567 break;
3568
aabfe6fb
SZ
3569 case IFNET_SERIALIZE_MAIN:
3570 lwkt_serialize_enter(&sc->main_serialize);
3571 break;
3572
6d435846
SZ
3573 case IFNET_SERIALIZE_TX:
3574 lwkt_serialize_enter(&sc->tx_serialize);
3575 break;
3576
067b3d6b 3577 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3578 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3579 break;
3580
067b3d6b 3581 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3582 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3583 break;
3584
3585 default:
3586 panic("%s unsupported serialize type\n", ifp->if_xname);
3587 }
3588}
3589
3590static void
3591emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3592{
3593 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3594
3595 switch (slz) {
3596 case IFNET_SERIALIZE_ALL:
f61533ad 3597 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
6d435846
SZ
3598 break;
3599
aabfe6fb
SZ
3600 case IFNET_SERIALIZE_MAIN:
3601 lwkt_serialize_exit(&sc->main_serialize);
3602 break;
3603
6d435846
SZ
3604 case IFNET_SERIALIZE_TX:
3605 lwkt_serialize_exit(&sc->tx_serialize);
3606 break;
3607
067b3d6b 3608 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3609 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3610 break;
3611
067b3d6b 3612 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3613 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3614 break;
3615
3616 default:
3617 panic("%s unsupported serialize type\n", ifp->if_xname);
3618 }
3619}
3620
3621static int
3622emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3623{
3624 struct emx_softc *sc = ifp->if_softc;
6d435846
SZ
3625
3626 switch (slz) {
3627 case IFNET_SERIALIZE_ALL:
f61533ad
SZ
3628 return lwkt_serialize_array_try(sc->serializes,
3629 EMX_NSERIALIZE, 0);
6d435846 3630
aabfe6fb
SZ
3631 case IFNET_SERIALIZE_MAIN:
3632 return lwkt_serialize_try(&sc->main_serialize);
3633
6d435846
SZ
3634 case IFNET_SERIALIZE_TX:
3635 return lwkt_serialize_try(&sc->tx_serialize);
3636
067b3d6b 3637 case IFNET_SERIALIZE_RX(0):
6d435846
SZ
3638 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3639
067b3d6b 3640 case IFNET_SERIALIZE_RX(1):
6d435846
SZ
3641 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3642
3643 default:
3644 panic("%s unsupported serialize type\n", ifp->if_xname);
3645 }
3646}
bca7c435
SZ
3647
3648static void
3649emx_serialize_skipmain(struct emx_softc *sc)
3650{
3651 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3652}
3653
3654static void
3655emx_deserialize_skipmain(struct emx_softc *sc)
3656{
3657 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3658}
2c9effcf
SZ
3659
3660#ifdef INVARIANTS
3661
3662static void
3663emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3664 boolean_t serialized)
3665{
3666 struct emx_softc *sc = ifp->if_softc;
3667 int i;
3668
3669 switch (slz) {
3670 case IFNET_SERIALIZE_ALL:
3671 if (serialized) {
3672 for (i = 0; i < EMX_NSERIALIZE; ++i)
3673 ASSERT_SERIALIZED(sc->serializes[i]);
3674 } else {
3675 for (i = 0; i < EMX_NSERIALIZE; ++i)
3676 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3677 }
3678 break;
3679
aabfe6fb
SZ
3680 case IFNET_SERIALIZE_MAIN:
3681 if (serialized)
3682 ASSERT_SERIALIZED(&sc->main_serialize);
3683 else
3684 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3685 break;
3686
2c9effcf
SZ
3687 case IFNET_SERIALIZE_TX:
3688 if (serialized)
3689 ASSERT_SERIALIZED(&sc->tx_serialize);
3690 else
3691 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3692 break;
3693
067b3d6b 3694 case IFNET_SERIALIZE_RX(0):
2c9effcf
SZ
3695 if (serialized)
3696 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3697 else
3698 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3699 break;
3700
067b3d6b 3701 case IFNET_SERIALIZE_RX(1):
2c9effcf
SZ
3702 if (serialized)
3703 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3704 else
3705 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3706 break;
3707
3708 default:
3709 panic("%s unsupported serialize type\n", ifp->if_xname);
3710 }
3711}
3712
3713#endif /* INVARIANTS */
b3a7093f
SZ
3714
3715#ifdef IFPOLL_ENABLE
3716
3717static void
3718emx_qpoll_status(struct ifnet *ifp, int pollhz __unused)
3719{
3720 struct emx_softc *sc = ifp->if_softc;
3721 uint32_t reg_icr;
3722
3723 ASSERT_SERIALIZED(&sc->main_serialize);
3724
3725 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3726 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3cbe4103
SZ
3727 emx_serialize_skipmain(sc);
3728
3729 callout_stop(&sc->timer);
3730 sc->hw.mac.get_link_status = 1;
3731 emx_update_link_status(sc);
3732 callout_reset(&sc->timer, hz, emx_timer, sc);
3733
3734 emx_deserialize_skipmain(sc);
b3a7093f
SZ
3735 }
3736}
3737
3738static void
3739emx_qpoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3740{
3741 struct emx_softc *sc = ifp->if_softc;
3742
3743 ASSERT_SERIALIZED(&sc->tx_serialize);
3744
3745 emx_txeof(sc);
3746 if (!ifq_is_empty(&ifp->if_snd))
3747 if_devstart(ifp);
3748}
3749
3750static void
3751emx_qpoll_rx(struct ifnet *ifp, void *arg, int cycle)
3752{
3753 struct emx_softc *sc = ifp->if_softc;
3754 struct emx_rxdata *rdata = arg;
3755
3756 ASSERT_SERIALIZED(&rdata->rx_serialize);
3757
3758 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3759}
3760
3761static void
3762emx_qpoll(struct ifnet *ifp, struct ifpoll_info *info)
3763{
3764 struct emx_softc *sc = ifp->if_softc;
3765
3766 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3767
3768 if (info) {
3769 int i;
3770
3771 info->ifpi_status.status_func = emx_qpoll_status;
3772 info->ifpi_status.serializer = &sc->main_serialize;
3773
3774 info->ifpi_tx[0].poll_func = emx_qpoll_tx;
3775 info->ifpi_tx[0].arg = NULL;
3776 info->ifpi_tx[0].serializer = &sc->tx_serialize;
3777
3778 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3779 info->ifpi_rx[i].poll_func = emx_qpoll_rx;
3780 info->ifpi_rx[i].arg = &sc->rx_data[i];
3781 info->ifpi_rx[i].serializer =
3782 &sc->rx_data[i].rx_serialize;
3783 }
3784
3785 if (ifp->if_flags & IFF_RUNNING)
3786 emx_disable_intr(sc);
3787 } else if (ifp->if_flags & IFF_RUNNING) {
3788 emx_enable_intr(sc);
3789 }
3790}
3791
3792#endif /* IFPOLL_ENABLE */