network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / nge / if_nge.c
CommitLineData
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
95893fe4 34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.49 2008/08/17 04:32:34 sephe Exp $
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35 */
36
37/*
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
40 *
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
43 *
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
48 *
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
52 * components:
53 *
54 * http://www.national.com/ds/DP/DP83861.pdf
55 *
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
58 */
59
60/*
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
71 * descriptors.
72 *
73 * There are two bugs/misfeatures in the 83820/83821 that I have
74 * discovered so far:
75 *
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
78 * alignment.
79 *
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
86 *
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
89 */
90
2b71c8f1
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91#include "opt_polling.h"
92
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93#include <sys/param.h>
94#include <sys/systm.h>
95#include <sys/sockio.h>
96#include <sys/mbuf.h>
97#include <sys/malloc.h>
98#include <sys/kernel.h>
9db4b353 99#include <sys/interrupt.h>
984263bc 100#include <sys/socket.h>
78195a76 101#include <sys/serialize.h>
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102#include <sys/bus.h>
103#include <sys/rman.h>
88e7510c 104#include <sys/thread2.h>
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105
106#include <net/if.h>
0b193118 107#include <net/ifq_var.h>
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108#include <net/if_arp.h>
109#include <net/ethernet.h>
110#include <net/if_dl.h>
111#include <net/if_media.h>
112#include <net/if_types.h>
1f2de5d4 113#include <net/vlan/if_vlan_var.h>
b637f170 114#include <net/vlan/if_vlan_ether.h>
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115
116#include <net/bpf.h>
117
118#include <vm/vm.h> /* for vtophys */
119#include <vm/pmap.h> /* for vtophys */
984263bc 120
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121#include <dev/netif/mii_layer/mii.h>
122#include <dev/netif/mii_layer/miivar.h>
984263bc 123
cf908797 124#include <bus/pci/pcidevs.h>
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125#include <bus/pci/pcireg.h>
126#include <bus/pci/pcivar.h>
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127
128#define NGE_USEIOSPACE
129
1f2de5d4 130#include "if_ngereg.h"
984263bc 131
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132
133/* "controller miibus0" required. See GENERIC if you get errors here. */
134#include "miibus_if.h"
135
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136#define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
137
138/*
139 * Various supported device vendors/types and their names.
140 */
141static struct nge_type nge_devs[] = {
cf908797 142 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
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143 "National Semiconductor Gigabit Ethernet" },
144 { 0, 0, NULL }
145};
146
22bf5b21
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147static int nge_probe(device_t);
148static int nge_attach(device_t);
149static int nge_detach(device_t);
984263bc 150
22bf5b21 151static int nge_alloc_jumbo_mem(struct nge_softc *);
368e791d
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152static struct nge_jslot
153 *nge_jalloc(struct nge_softc *);
154static void nge_jfree(void *);
155static void nge_jref(void *);
156
157static int nge_newbuf(struct nge_softc *, struct nge_desc *,
158 struct mbuf *);
159static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
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160static void nge_rxeof(struct nge_softc *);
161static void nge_txeof(struct nge_softc *);
162static void nge_intr(void *);
163static void nge_tick(void *);
164static void nge_start(struct ifnet *);
368e791d 165static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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166static void nge_init(void *);
167static void nge_stop(struct nge_softc *);
168static void nge_watchdog(struct ifnet *);
169static void nge_shutdown(device_t);
170static int nge_ifmedia_upd(struct ifnet *);
171static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
172
173static void nge_delay(struct nge_softc *);
174static void nge_eeprom_idle(struct nge_softc *);
175static void nge_eeprom_putbyte(struct nge_softc *, int);
176static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
177static void nge_read_eeprom(struct nge_softc *, void *, int, int);
178
179static void nge_mii_sync(struct nge_softc *);
180static void nge_mii_send(struct nge_softc *, uint32_t, int);
181static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
182static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
183
184static int nge_miibus_readreg(device_t, int, int);
185static int nge_miibus_writereg(device_t, int, int, int);
186static void nge_miibus_statchg(device_t);
187
188static void nge_setmulti(struct nge_softc *);
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189static void nge_reset(struct nge_softc *);
190static int nge_list_rx_init(struct nge_softc *);
191static int nge_list_tx_init(struct nge_softc *);
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192#ifdef DEVICE_POLLING
193static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
194#endif
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195
196#ifdef NGE_USEIOSPACE
197#define NGE_RES SYS_RES_IOPORT
198#define NGE_RID NGE_PCI_LOIO
199#else
200#define NGE_RES SYS_RES_MEMORY
201#define NGE_RID NGE_PCI_LOMEM
202#endif
203
204static device_method_t nge_methods[] = {
205 /* Device interface */
206 DEVMETHOD(device_probe, nge_probe),
207 DEVMETHOD(device_attach, nge_attach),
208 DEVMETHOD(device_detach, nge_detach),
209 DEVMETHOD(device_shutdown, nge_shutdown),
210
211 /* bus interface */
212 DEVMETHOD(bus_print_child, bus_generic_print_child),
213 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
214
215 /* MII interface */
216 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
217 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
218 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
219
220 { 0, 0 }
221};
222
22bf5b21 223static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
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224static devclass_t nge_devclass;
225
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226DECLARE_DUMMY_MODULE(if_nge);
227MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
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228DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
229DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
230
231#define NGE_SETBIT(sc, reg, x) \
22bf5b21 232 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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233
234#define NGE_CLRBIT(sc, reg, x) \
22bf5b21 235 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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236
237#define SIO_SET(x) \
22bf5b21 238 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
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239
240#define SIO_CLR(x) \
22bf5b21 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
984263bc 242
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243static void
244nge_delay(struct nge_softc *sc)
984263bc 245{
22bf5b21 246 int idx;
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247
248 for (idx = (300 / 33) + 1; idx > 0; idx--)
249 CSR_READ_4(sc, NGE_CSR);
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250}
251
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252static void
253nge_eeprom_idle(struct nge_softc *sc)
984263bc 254{
22bf5b21 255 int i;
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256
257 SIO_SET(NGE_MEAR_EE_CSEL);
258 nge_delay(sc);
259 SIO_SET(NGE_MEAR_EE_CLK);
260 nge_delay(sc);
261
262 for (i = 0; i < 25; i++) {
263 SIO_CLR(NGE_MEAR_EE_CLK);
264 nge_delay(sc);
265 SIO_SET(NGE_MEAR_EE_CLK);
266 nge_delay(sc);
267 }
268
269 SIO_CLR(NGE_MEAR_EE_CLK);
270 nge_delay(sc);
271 SIO_CLR(NGE_MEAR_EE_CSEL);
272 nge_delay(sc);
273 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
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274}
275
276/*
277 * Send a read command and address to the EEPROM, check for ACK.
278 */
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279static void
280nge_eeprom_putbyte(struct nge_softc *sc, int addr)
984263bc 281{
22bf5b21 282 int d, i;
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283
284 d = addr | NGE_EECMD_READ;
285
286 /*
287 * Feed in each bit and stobe the clock.
288 */
289 for (i = 0x400; i; i >>= 1) {
22bf5b21 290 if (d & i)
984263bc 291 SIO_SET(NGE_MEAR_EE_DIN);
22bf5b21 292 else
984263bc 293 SIO_CLR(NGE_MEAR_EE_DIN);
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294 nge_delay(sc);
295 SIO_SET(NGE_MEAR_EE_CLK);
296 nge_delay(sc);
297 SIO_CLR(NGE_MEAR_EE_CLK);
298 nge_delay(sc);
299 }
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300}
301
302/*
303 * Read a word of data stored in the EEPROM at address 'addr.'
304 */
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305static void
306nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
984263bc 307{
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308 int i;
309 uint16_t word = 0;
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310
311 /* Force EEPROM to idle state. */
312 nge_eeprom_idle(sc);
313
314 /* Enter EEPROM access mode. */
315 nge_delay(sc);
316 SIO_CLR(NGE_MEAR_EE_CLK);
317 nge_delay(sc);
318 SIO_SET(NGE_MEAR_EE_CSEL);
319 nge_delay(sc);
320
321 /*
322 * Send address of word we want to read.
323 */
324 nge_eeprom_putbyte(sc, addr);
325
326 /*
327 * Start reading bits from EEPROM.
328 */
329 for (i = 0x8000; i; i >>= 1) {
330 SIO_SET(NGE_MEAR_EE_CLK);
331 nge_delay(sc);
332 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
333 word |= i;
334 nge_delay(sc);
335 SIO_CLR(NGE_MEAR_EE_CLK);
336 nge_delay(sc);
337 }
338
339 /* Turn off EEPROM access mode. */
340 nge_eeprom_idle(sc);
341
342 *dest = word;
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343}
344
345/*
346 * Read a sequence of words from the EEPROM.
347 */
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348static void
349nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
984263bc 350{
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351 int i;
352 uint16_t word = 0, *ptr;
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353
354 for (i = 0; i < cnt; i++) {
355 nge_eeprom_getword(sc, off + i, &word);
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356 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
357 *ptr = word;
984263bc 358 }
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359}
360
361/*
362 * Sync the PHYs by setting data bit and strobing the clock 32 times.
363 */
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364static void
365nge_mii_sync(struct nge_softc *sc)
984263bc 366{
22bf5b21 367 int i;
984263bc 368
22bf5b21 369 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
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370
371 for (i = 0; i < 32; i++) {
372 SIO_SET(NGE_MEAR_MII_CLK);
373 DELAY(1);
374 SIO_CLR(NGE_MEAR_MII_CLK);
375 DELAY(1);
376 }
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377}
378
379/*
380 * Clock a series of bits through the MII.
381 */
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382static void
383nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
984263bc 384{
22bf5b21 385 int i;
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386
387 SIO_CLR(NGE_MEAR_MII_CLK);
388
389 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
22bf5b21 390 if (bits & i)
984263bc 391 SIO_SET(NGE_MEAR_MII_DATA);
22bf5b21 392 else
984263bc 393 SIO_CLR(NGE_MEAR_MII_DATA);
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394 DELAY(1);
395 SIO_CLR(NGE_MEAR_MII_CLK);
396 DELAY(1);
397 SIO_SET(NGE_MEAR_MII_CLK);
398 }
399}
400
401/*
402 * Read an PHY register through the MII.
403 */
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404static int
405nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 406{
88e7510c 407 int ack, i;
984263bc 408
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409 /*
410 * Set up frame for RX.
411 */
412 frame->mii_stdelim = NGE_MII_STARTDELIM;
413 frame->mii_opcode = NGE_MII_READOP;
414 frame->mii_turnaround = 0;
415 frame->mii_data = 0;
22bf5b21 416
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417 CSR_WRITE_4(sc, NGE_MEAR, 0);
418
419 /*
420 * Turn on data xmit.
421 */
422 SIO_SET(NGE_MEAR_MII_DIR);
423
424 nge_mii_sync(sc);
425
426 /*
427 * Send command/address info.
428 */
429 nge_mii_send(sc, frame->mii_stdelim, 2);
430 nge_mii_send(sc, frame->mii_opcode, 2);
431 nge_mii_send(sc, frame->mii_phyaddr, 5);
432 nge_mii_send(sc, frame->mii_regaddr, 5);
433
434 /* Idle bit */
22bf5b21 435 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
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436 DELAY(1);
437 SIO_SET(NGE_MEAR_MII_CLK);
438 DELAY(1);
439
440 /* Turn off xmit. */
441 SIO_CLR(NGE_MEAR_MII_DIR);
442 /* Check for ack */
443 SIO_CLR(NGE_MEAR_MII_CLK);
444 DELAY(1);
445 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
446 SIO_SET(NGE_MEAR_MII_CLK);
447 DELAY(1);
448
449 /*
450 * Now try reading data bits. If the ack failed, we still
451 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 */
453 if (ack) {
454 for(i = 0; i < 16; i++) {
455 SIO_CLR(NGE_MEAR_MII_CLK);
456 DELAY(1);
457 SIO_SET(NGE_MEAR_MII_CLK);
458 DELAY(1);
459 }
460 goto fail;
461 }
462
463 for (i = 0x8000; i; i >>= 1) {
464 SIO_CLR(NGE_MEAR_MII_CLK);
465 DELAY(1);
466 if (!ack) {
467 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
468 frame->mii_data |= i;
469 DELAY(1);
470 }
471 SIO_SET(NGE_MEAR_MII_CLK);
472 DELAY(1);
473 }
474
475fail:
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476 SIO_CLR(NGE_MEAR_MII_CLK);
477 DELAY(1);
478 SIO_SET(NGE_MEAR_MII_CLK);
479 DELAY(1);
480
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481 if (ack)
482 return(1);
483 return(0);
484}
485
486/*
487 * Write to a PHY register through the MII.
488 */
22bf5b21
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489static int
490nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
984263bc 491{
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492 /*
493 * Set up frame for TX.
494 */
495
496 frame->mii_stdelim = NGE_MII_STARTDELIM;
497 frame->mii_opcode = NGE_MII_WRITEOP;
498 frame->mii_turnaround = NGE_MII_TURNAROUND;
499
500 /*
501 * Turn on data output.
502 */
503 SIO_SET(NGE_MEAR_MII_DIR);
504
505 nge_mii_sync(sc);
506
507 nge_mii_send(sc, frame->mii_stdelim, 2);
508 nge_mii_send(sc, frame->mii_opcode, 2);
509 nge_mii_send(sc, frame->mii_phyaddr, 5);
510 nge_mii_send(sc, frame->mii_regaddr, 5);
511 nge_mii_send(sc, frame->mii_turnaround, 2);
512 nge_mii_send(sc, frame->mii_data, 16);
513
514 /* Idle bit. */
515 SIO_SET(NGE_MEAR_MII_CLK);
516 DELAY(1);
517 SIO_CLR(NGE_MEAR_MII_CLK);
518 DELAY(1);
519
520 /*
521 * Turn off xmit.
522 */
523 SIO_CLR(NGE_MEAR_MII_DIR);
524
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525 return(0);
526}
527
22bf5b21
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528static int
529nge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 530{
22bf5b21
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531 struct nge_softc *sc = device_get_softc(dev);
532 struct nge_mii_frame frame;
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533
534 bzero((char *)&frame, sizeof(frame));
535
536 frame.mii_phyaddr = phy;
537 frame.mii_regaddr = reg;
538 nge_mii_readreg(sc, &frame);
539
540 return(frame.mii_data);
541}
542
22bf5b21
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543static int
544nge_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 545{
22bf5b21
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546 struct nge_softc *sc = device_get_softc(dev);
547 struct nge_mii_frame frame;
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548
549 bzero((char *)&frame, sizeof(frame));
550
551 frame.mii_phyaddr = phy;
552 frame.mii_regaddr = reg;
553 frame.mii_data = data;
554 nge_mii_writereg(sc, &frame);
555
556 return(0);
557}
558
22bf5b21
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559static void
560nge_miibus_statchg(device_t dev)
984263bc 561{
22bf5b21
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562 struct nge_softc *sc = device_get_softc(dev);
563 struct mii_data *mii;
564 int status;
984263bc 565
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566 if (sc->nge_tbi) {
567 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
568 == IFM_AUTO) {
569 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
570 if (status == 0 || status & NGE_TBIANAR_FDX) {
571 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
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573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
574 } else {
575 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 576 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
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577 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
578 }
984263bc
MD
579 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
580 != IFM_FDX) {
581 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 582 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
583 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 } else {
585 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 586 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
587 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
588 }
589 } else {
590 mii = device_get_softc(sc->nge_miibus);
591
592 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
593 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 594 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
595 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
596 } else {
597 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 598 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
599 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
600 }
601
602 /* If we have a 1000Mbps link, set the mode_1000 bit. */
7f259627 603 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
984263bc
MD
604 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
605 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
606 } else {
607 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
608 }
609 }
984263bc
MD
610}
611
22bf5b21
JS
612static void
613nge_setmulti(struct nge_softc *sc)
984263bc 614{
22bf5b21
JS
615 struct ifnet *ifp = &sc->arpcom.ac_if;
616 struct ifmultiaddr *ifma;
617 uint32_t filtsave, h = 0, i;
618 int bit, index;
984263bc
MD
619
620 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
621 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 622 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
984263bc
MD
623 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
624 return;
625 }
626
627 /*
628 * We have to explicitly enable the multicast hash table
629 * on the NatSemi chip if we want to use it, which we do.
630 * We also have to tell it that we don't want to use the
631 * hash table for matching unicast addresses.
632 */
633 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
634 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
22bf5b21 635 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
984263bc
MD
636
637 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
638
639 /* first, zot all the existing hash bits */
640 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
641 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
642 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
643 }
644
645 /*
646 * From the 11 bits returned by the crc routine, the top 7
647 * bits represent the 16-bit word in the mcast hash table
648 * that needs to be updated, and the lower 4 bits represent
649 * which bit within that byte needs to be set.
650 */
441d34b2 651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
652 if (ifma->ifma_addr->sa_family != AF_LINK)
653 continue;
4c6f5f4c
JS
654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
984263bc
MD
656 index = (h >> 4) & 0x7F;
657 bit = h & 0xF;
658 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
659 NGE_FILTADDR_MCAST_LO + (index * 2));
660 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
661 }
662
663 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
984263bc
MD
664}
665
22bf5b21
JS
666static void
667nge_reset(struct nge_softc *sc)
984263bc 668{
22bf5b21 669 int i;
984263bc
MD
670
671 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
672
673 for (i = 0; i < NGE_TIMEOUT; i++) {
22bf5b21 674 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
984263bc
MD
675 break;
676 }
677
678 if (i == NGE_TIMEOUT)
e3869ec7 679 kprintf("nge%d: reset never completed\n", sc->nge_unit);
984263bc
MD
680
681 /* Wait a little while for the chip to get its brains in order. */
682 DELAY(1000);
683
684 /*
685 * If this is a NetSemi chip, make sure to clear
686 * PME mode.
687 */
688 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
689 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
984263bc
MD
690}
691
692/*
693 * Probe for an NatSemi chip. Check the PCI vendor and device
694 * IDs against our list and return a device name if we find a match.
695 */
22bf5b21
JS
696static int
697nge_probe(device_t dev)
984263bc 698{
22bf5b21
JS
699 struct nge_type *t;
700 uint16_t vendor, product;
984263bc 701
22bf5b21
JS
702 vendor = pci_get_vendor(dev);
703 product = pci_get_device(dev);
984263bc 704
22bf5b21
JS
705 for (t = nge_devs; t->nge_name != NULL; t++) {
706 if (vendor == t->nge_vid && product == t->nge_did) {
984263bc
MD
707 device_set_desc(dev, t->nge_name);
708 return(0);
709 }
984263bc
MD
710 }
711
712 return(ENXIO);
713}
714
715/*
716 * Attach the interface. Allocate softc structures, do ifmedia
717 * setup and ethernet/BPF attach.
718 */
22bf5b21
JS
719static int
720nge_attach(device_t dev)
984263bc 721{
22bf5b21
JS
722 struct nge_softc *sc;
723 struct ifnet *ifp;
724 uint8_t eaddr[ETHER_ADDR_LEN];
725 uint32_t command;
88e7510c 726 int error = 0, rid, unit;
984263bc
MD
727 const char *sep = "";
728
984263bc
MD
729 sc = device_get_softc(dev);
730 unit = device_get_unit(dev);
43c4cb7e 731 callout_init(&sc->nge_stat_timer);
16dca0df 732 lwkt_serialize_init(&sc->nge_jslot_serializer);
984263bc
MD
733
734 /*
735 * Handle power management nonsense.
736 */
984263bc
MD
737 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
738 if (command == 0x01) {
984263bc
MD
739 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
740 if (command & NGE_PSTATE_MASK) {
22bf5b21 741 uint32_t iobase, membase, irq;
984263bc
MD
742
743 /* Save important PCI config data. */
744 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
745 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
746 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
747
748 /* Reset the power state. */
e3869ec7 749 kprintf("nge%d: chip is in D%d power mode "
984263bc
MD
750 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
751 command &= 0xFFFFFFFC;
752 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
753
754 /* Restore PCI config data. */
755 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
756 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
757 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
758 }
759 }
760
761 /*
762 * Map control/status registers.
763 */
764 command = pci_read_config(dev, PCIR_COMMAND, 4);
765 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
766 pci_write_config(dev, PCIR_COMMAND, command, 4);
767 command = pci_read_config(dev, PCIR_COMMAND, 4);
768
769#ifdef NGE_USEIOSPACE
770 if (!(command & PCIM_CMD_PORTEN)) {
e3869ec7 771 kprintf("nge%d: failed to enable I/O ports!\n", unit);
88e7510c
JS
772 error = ENXIO;
773 return(error);
984263bc
MD
774 }
775#else
776 if (!(command & PCIM_CMD_MEMEN)) {
e3869ec7 777 kprintf("nge%d: failed to enable memory mapping!\n", unit);
88e7510c
JS
778 error = ENXIO;
779 return(error);
984263bc
MD
780 }
781#endif
782
783 rid = NGE_RID;
4e6d744d 784 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
984263bc
MD
785
786 if (sc->nge_res == NULL) {
e3869ec7 787 kprintf("nge%d: couldn't map ports/memory\n", unit);
984263bc 788 error = ENXIO;
88e7510c 789 return(error);
984263bc
MD
790 }
791
792 sc->nge_btag = rman_get_bustag(sc->nge_res);
793 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
794
795 /* Allocate interrupt */
796 rid = 0;
4e6d744d 797 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
798 RF_SHAREABLE | RF_ACTIVE);
799
800 if (sc->nge_irq == NULL) {
e3869ec7 801 kprintf("nge%d: couldn't map interrupt\n", unit);
984263bc
MD
802 error = ENXIO;
803 goto fail;
804 }
805
984263bc
MD
806 /* Reset the adapter. */
807 nge_reset(sc);
808
809 /*
810 * Get station address from the EEPROM.
811 */
22bf5b21
JS
812 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
813 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
814 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
984263bc 815
984263bc 816 sc->nge_unit = unit;
984263bc
MD
817
818 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
e7b4468c 819 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
820
821 if (sc->nge_ldata == NULL) {
e3869ec7 822 kprintf("nge%d: no memory for list buffers!\n", unit);
984263bc
MD
823 error = ENXIO;
824 goto fail;
825 }
984263bc
MD
826
827 /* Try to allocate memory for jumbo buffers. */
828 if (nge_alloc_jumbo_mem(sc)) {
e3869ec7 829 kprintf("nge%d: jumbo buffer allocation failed\n",
984263bc 830 sc->nge_unit);
984263bc
MD
831 error = ENXIO;
832 goto fail;
833 }
834
835 ifp = &sc->arpcom.ac_if;
836 ifp->if_softc = sc;
cdb7d804 837 if_initname(ifp, "nge", unit);
984263bc
MD
838 ifp->if_mtu = ETHERMTU;
839 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
840 ifp->if_ioctl = nge_ioctl;
984263bc 841 ifp->if_start = nge_start;
9c095379
MD
842#ifdef DEVICE_POLLING
843 ifp->if_poll = nge_poll;
844#endif
984263bc
MD
845 ifp->if_watchdog = nge_watchdog;
846 ifp->if_init = nge_init;
847 ifp->if_baudrate = 1000000000;
0b193118
JS
848 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
849 ifq_set_ready(&ifp->if_snd);
984263bc 850 ifp->if_hwassist = NGE_CSUM_FEATURES;
26a4e3b9 851 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
984263bc
MD
852 ifp->if_capenable = ifp->if_capabilities;
853
854 /*
855 * Do MII setup.
856 */
857 if (mii_phy_probe(dev, &sc->nge_miibus,
858 nge_ifmedia_upd, nge_ifmedia_sts)) {
859 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
860 sc->nge_tbi = 1;
861 device_printf(dev, "Using TBI\n");
862
863 sc->nge_miibus = dev;
864
865 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
866 nge_ifmedia_sts);
867#define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
e3869ec7 868#define PRINT(s) kprintf("%s%s", sep, s); sep = ", "
984263bc
MD
869 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
870 device_printf(dev, " ");
871 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
872 PRINT("1000baseSX");
873 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
874 PRINT("1000baseSX-FDX");
875 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
876 PRINT("auto");
877
e3869ec7 878 kprintf("\n");
984263bc
MD
879#undef ADD
880#undef PRINT
881 ifmedia_set(&sc->nge_ifmedia,
882 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
883
884 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
885 | NGE_GPIO_GP4_OUT
886 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
887 | NGE_GPIO_GP3_OUTENB
888 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
889
890 } else {
e3869ec7 891 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
984263bc
MD
892 error = ENXIO;
893 goto fail;
894 }
895 }
896
897 /*
898 * Call MI attach routine.
899 */
78195a76 900 ether_ifattach(ifp, eaddr, NULL);
984263bc 901
95893fe4 902 error = bus_setup_intr(dev, sc->nge_irq, INTR_MPSAFE,
78195a76
MD
903 nge_intr, sc, &sc->nge_intrhand,
904 ifp->if_serializer);
88e7510c
JS
905 if (error) {
906 ether_ifdetach(ifp);
907 device_printf(dev, "couldn't set up irq\n");
908 goto fail;
909 }
984263bc 910
9db4b353
SZ
911 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->nge_irq));
912 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
913
88e7510c
JS
914 return(0);
915fail:
916 nge_detach(dev);
984263bc
MD
917 return(error);
918}
919
22bf5b21
JS
920static int
921nge_detach(device_t dev)
984263bc 922{
88e7510c
JS
923 struct nge_softc *sc = device_get_softc(dev);
924 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 925
88e7510c 926 if (device_is_attached(dev)) {
cdf89432 927 lwkt_serialize_enter(ifp->if_serializer);
88e7510c
JS
928 nge_reset(sc);
929 nge_stop(sc);
cdf89432
SZ
930 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
931 lwkt_serialize_exit(ifp->if_serializer);
932
88e7510c
JS
933 ether_ifdetach(ifp);
934 }
984263bc 935
88e7510c 936 if (sc->nge_miibus)
984263bc 937 device_delete_child(dev, sc->nge_miibus);
88e7510c 938 bus_generic_detach(dev);
22bf5b21 939
88e7510c
JS
940 if (sc->nge_irq)
941 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
942 if (sc->nge_res)
943 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
944 if (sc->nge_ldata) {
945 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
946 M_DEVBUF);
947 }
948 if (sc->nge_cdata.nge_jumbo_buf)
949 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
984263bc
MD
950
951 return(0);
952}
953
954/*
955 * Initialize the transmit descriptors.
956 */
22bf5b21
JS
957static int
958nge_list_tx_init(struct nge_softc *sc)
984263bc 959{
22bf5b21
JS
960 struct nge_list_data *ld;
961 struct nge_ring_data *cd;
962 int i;
984263bc
MD
963
964 cd = &sc->nge_cdata;
965 ld = sc->nge_ldata;
966
967 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
968 if (i == (NGE_TX_LIST_CNT - 1)) {
969 ld->nge_tx_list[i].nge_nextdesc =
970 &ld->nge_tx_list[0];
971 ld->nge_tx_list[i].nge_next =
972 vtophys(&ld->nge_tx_list[0]);
973 } else {
974 ld->nge_tx_list[i].nge_nextdesc =
975 &ld->nge_tx_list[i + 1];
976 ld->nge_tx_list[i].nge_next =
977 vtophys(&ld->nge_tx_list[i + 1]);
978 }
979 ld->nge_tx_list[i].nge_mbuf = NULL;
980 ld->nge_tx_list[i].nge_ptr = 0;
981 ld->nge_tx_list[i].nge_ctl = 0;
982 }
983
984 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
985
986 return(0);
987}
988
989
990/*
991 * Initialize the RX descriptors and allocate mbufs for them. Note that
992 * we arrange the descriptors in a closed ring, so that the last descriptor
993 * points back to the first.
994 */
22bf5b21
JS
995static int
996nge_list_rx_init(struct nge_softc *sc)
984263bc 997{
22bf5b21
JS
998 struct nge_list_data *ld;
999 struct nge_ring_data *cd;
1000 int i;
984263bc
MD
1001
1002 ld = sc->nge_ldata;
1003 cd = &sc->nge_cdata;
1004
1005 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1006 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1007 return(ENOBUFS);
1008 if (i == (NGE_RX_LIST_CNT - 1)) {
1009 ld->nge_rx_list[i].nge_nextdesc =
1010 &ld->nge_rx_list[0];
1011 ld->nge_rx_list[i].nge_next =
1012 vtophys(&ld->nge_rx_list[0]);
1013 } else {
1014 ld->nge_rx_list[i].nge_nextdesc =
1015 &ld->nge_rx_list[i + 1];
1016 ld->nge_rx_list[i].nge_next =
1017 vtophys(&ld->nge_rx_list[i + 1]);
1018 }
1019 }
1020
1021 cd->nge_rx_prod = 0;
1022
1023 return(0);
1024}
1025
1026/*
1027 * Initialize an RX descriptor and attach an MBUF cluster.
1028 */
22bf5b21
JS
1029static int
1030nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
984263bc 1031{
22bf5b21 1032 struct mbuf *m_new = NULL;
368e791d 1033 struct nge_jslot *buf;
984263bc
MD
1034
1035 if (m == NULL) {
74f1caca 1036 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc 1037 if (m_new == NULL) {
e3869ec7 1038 kprintf("nge%d: no memory for rx list "
984263bc
MD
1039 "-- packet dropped!\n", sc->nge_unit);
1040 return(ENOBUFS);
1041 }
1042
1043 /* Allocate the jumbo buffer */
1044 buf = nge_jalloc(sc);
1045 if (buf == NULL) {
1046#ifdef NGE_VERBOSE
e3869ec7 1047 kprintf("nge%d: jumbo allocation failed "
984263bc
MD
1048 "-- packet dropped!\n", sc->nge_unit);
1049#endif
1050 m_freem(m_new);
1051 return(ENOBUFS);
1052 }
1053 /* Attach the buffer to the mbuf */
368e791d
JS
1054 m_new->m_ext.ext_arg = buf;
1055 m_new->m_ext.ext_buf = buf->nge_buf;
b542cd49
JS
1056 m_new->m_ext.ext_free = nge_jfree;
1057 m_new->m_ext.ext_ref = nge_jref;
368e791d
JS
1058 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1059
1060 m_new->m_data = m_new->m_ext.ext_buf;
1061 m_new->m_flags |= M_EXT;
1062 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc
MD
1063 } else {
1064 m_new = m;
368e791d 1065 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
984263bc
MD
1066 m_new->m_data = m_new->m_ext.ext_buf;
1067 }
1068
22bf5b21 1069 m_adj(m_new, sizeof(uint64_t));
984263bc
MD
1070
1071 c->nge_mbuf = m_new;
1072 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1073 c->nge_ctl = m_new->m_len;
1074 c->nge_extsts = 0;
1075
1076 return(0);
1077}
1078
22bf5b21
JS
1079static int
1080nge_alloc_jumbo_mem(struct nge_softc *sc)
984263bc 1081{
22bf5b21
JS
1082 caddr_t ptr;
1083 int i;
368e791d 1084 struct nge_jslot *entry;
984263bc
MD
1085
1086 /* Grab a big chunk o' storage. */
1087 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
56ae9d75 1088 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
1089
1090 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
e3869ec7 1091 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
984263bc
MD
1092 return(ENOBUFS);
1093 }
1094
1095 SLIST_INIT(&sc->nge_jfree_listhead);
984263bc
MD
1096
1097 /*
1098 * Now divide it up into 9K pieces and save the addresses
1099 * in an array.
1100 */
1101 ptr = sc->nge_cdata.nge_jumbo_buf;
1102 for (i = 0; i < NGE_JSLOTS; i++) {
368e791d
JS
1103 entry = &sc->nge_cdata.nge_jslots[i];
1104 entry->nge_sc = sc;
1105 entry->nge_buf = ptr;
1106 entry->nge_inuse = 0;
1107 entry->nge_slot = i;
1108 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1109 ptr += NGE_JLEN;
984263bc
MD
1110 }
1111
1112 return(0);
1113}
1114
984263bc
MD
1115
1116/*
1117 * Allocate a jumbo buffer.
1118 */
368e791d 1119static struct nge_jslot *
22bf5b21 1120nge_jalloc(struct nge_softc *sc)
984263bc 1121{
368e791d 1122 struct nge_jslot *entry;
22bf5b21 1123
16dca0df 1124 lwkt_serialize_enter(&sc->nge_jslot_serializer);
984263bc 1125 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
16dca0df
MD
1126 if (entry) {
1127 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1128 entry->nge_inuse = 1;
1129 } else {
984263bc 1130#ifdef NGE_VERBOSE
e3869ec7 1131 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
984263bc 1132#endif
984263bc 1133 }
16dca0df 1134 lwkt_serialize_exit(&sc->nge_jslot_serializer);
368e791d 1135 return(entry);
984263bc
MD
1136}
1137
1138/*
1139 * Adjust usage count on a jumbo buffer. In general this doesn't
1140 * get used much because our jumbo buffers don't get passed around
1141 * a lot, but it's implemented for correctness.
1142 */
22bf5b21 1143static void
368e791d 1144nge_jref(void *arg)
984263bc 1145{
368e791d
JS
1146 struct nge_jslot *entry = (struct nge_jslot *)arg;
1147 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1148
1149 if (sc == NULL)
1150 panic("nge_jref: can't find softc pointer!");
1151
368e791d 1152 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
984263bc
MD
1153 panic("nge_jref: asked to reference buffer "
1154 "that we don't manage!");
368e791d 1155 else if (entry->nge_inuse == 0)
984263bc
MD
1156 panic("nge_jref: buffer already free!");
1157 else
16dca0df 1158 atomic_add_int(&entry->nge_inuse, 1);
984263bc
MD
1159}
1160
1161/*
1162 * Release a jumbo buffer.
1163 */
22bf5b21 1164static void
368e791d 1165nge_jfree(void *arg)
984263bc 1166{
368e791d
JS
1167 struct nge_jslot *entry = (struct nge_jslot *)arg;
1168 struct nge_softc *sc = entry->nge_sc;
984263bc
MD
1169
1170 if (sc == NULL)
368e791d
JS
1171 panic("nge_jref: can't find softc pointer!");
1172
16dca0df 1173 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
368e791d
JS
1174 panic("nge_jref: asked to reference buffer "
1175 "that we don't manage!");
16dca0df 1176 } else if (entry->nge_inuse == 0) {
368e791d 1177 panic("nge_jref: buffer already free!");
16dca0df
MD
1178 } else {
1179 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1180 atomic_subtract_int(&entry->nge_inuse, 1);
1181 if (entry->nge_inuse == 0) {
1182 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1183 entry, jslot_link);
1184 }
1185 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1186 }
984263bc
MD
1187}
1188/*
1189 * A frame has been uploaded: pass the resulting mbuf chain up to
1190 * the higher level protocols.
1191 */
22bf5b21
JS
1192static void
1193nge_rxeof(struct nge_softc *sc)
984263bc 1194{
22bf5b21
JS
1195 struct mbuf *m;
1196 struct ifnet *ifp = &sc->arpcom.ac_if;
1197 struct nge_desc *cur_rx;
1198 int i, total_len = 0;
1199 uint32_t rxstat;
984263bc 1200
984263bc
MD
1201 i = sc->nge_cdata.nge_rx_prod;
1202
1203 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
22bf5b21
JS
1204 struct mbuf *m0 = NULL;
1205 uint32_t extsts;
984263bc
MD
1206
1207#ifdef DEVICE_POLLING
46f25451 1208 if (ifp->if_flags & IFF_POLLING) {
984263bc
MD
1209 if (sc->rxcycles <= 0)
1210 break;
1211 sc->rxcycles--;
1212 }
1213#endif /* DEVICE_POLLING */
1214
1215 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1216 rxstat = cur_rx->nge_rxstat;
1217 extsts = cur_rx->nge_extsts;
1218 m = cur_rx->nge_mbuf;
1219 cur_rx->nge_mbuf = NULL;
1220 total_len = NGE_RXBYTES(cur_rx);
1221 NGE_INC(i, NGE_RX_LIST_CNT);
1222 /*
1223 * If an error occurs, update stats, clear the
1224 * status word and leave the mbuf cluster in place:
1225 * it should simply get re-used next time this descriptor
1226 * comes up in the ring.
1227 */
22bf5b21 1228 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
984263bc
MD
1229 ifp->if_ierrors++;
1230 nge_newbuf(sc, cur_rx, m);
1231 continue;
1232 }
1233
1234 /*
1235 * Ok. NatSemi really screwed up here. This is the
1236 * only gigE chip I know of with alignment constraints
1237 * on receive buffers. RX buffers must be 64-bit aligned.
1238 */
1239#ifdef __i386__
1240 /*
1241 * By popular demand, ignore the alignment problems
1242 * on the Intel x86 platform. The performance hit
1243 * incurred due to unaligned accesses is much smaller
1244 * than the hit produced by forcing buffer copies all
1245 * the time, especially with jumbo frames. We still
1246 * need to fix up the alignment everywhere else though.
1247 */
1248 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1249#endif
1250 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1251 total_len + ETHER_ALIGN, 0, ifp, NULL);
1252 nge_newbuf(sc, cur_rx, m);
1253 if (m0 == NULL) {
e3869ec7 1254 kprintf("nge%d: no receive buffers "
984263bc
MD
1255 "available -- packet dropped!\n",
1256 sc->nge_unit);
1257 ifp->if_ierrors++;
1258 continue;
1259 }
1260 m_adj(m0, ETHER_ALIGN);
1261 m = m0;
1262#ifdef __i386__
1263 } else {
1264 m->m_pkthdr.rcvif = ifp;
1265 m->m_pkthdr.len = m->m_len = total_len;
1266 }
1267#endif
1268
1269 ifp->if_ipackets++;
984263bc
MD
1270
1271 /* Do IP checksum checking. */
1272 if (extsts & NGE_RXEXTSTS_IPPKT)
1273 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1274 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1275 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1276 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
22bf5b21 1277 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
984263bc 1278 (extsts & NGE_RXEXTSTS_UDPPKT &&
22bf5b21 1279 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
984263bc 1280 m->m_pkthdr.csum_flags |=
fbb35ef0
SZ
1281 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1282 CSUM_FRAG_NOT_CHECKED;
984263bc
MD
1283 m->m_pkthdr.csum_data = 0xffff;
1284 }
1285
1286 /*
1287 * If we received a packet with a vlan tag, pass it
1288 * to vlan_input() instead of ether_input().
1289 */
e6b5847c
SZ
1290 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1291 m->m_flags |= M_VLANTAG;
1292 m->m_pkthdr.ether_vlantag =
1293 (extsts & NGE_RXEXTSTS_VTCI);
1294 }
1295 ifp->if_input(ifp, m);
984263bc
MD
1296 }
1297
1298 sc->nge_cdata.nge_rx_prod = i;
984263bc
MD
1299}
1300
1301/*
1302 * A frame was downloaded to the chip. It's safe for us to clean up
1303 * the list buffers.
1304 */
22bf5b21
JS
1305static void
1306nge_txeof(struct nge_softc *sc)
984263bc 1307{
22bf5b21
JS
1308 struct ifnet *ifp = &sc->arpcom.ac_if;
1309 struct nge_desc *cur_tx = NULL;
1310 uint32_t idx;
984263bc
MD
1311
1312 /* Clear the timeout timer. */
1313 ifp->if_timer = 0;
1314
1315 /*
1316 * Go through our tx list and free mbufs for those
1317 * frames that have been transmitted.
1318 */
1319 idx = sc->nge_cdata.nge_tx_cons;
1320 while (idx != sc->nge_cdata.nge_tx_prod) {
1321 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1322
1323 if (NGE_OWNDESC(cur_tx))
1324 break;
1325
1326 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1327 sc->nge_cdata.nge_tx_cnt--;
1328 NGE_INC(idx, NGE_TX_LIST_CNT);
1329 continue;
1330 }
1331
1332 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1333 ifp->if_oerrors++;
1334 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1335 ifp->if_collisions++;
1336 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1337 ifp->if_collisions++;
1338 }
1339
1340 ifp->if_collisions +=
1341 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1342
1343 ifp->if_opackets++;
1344 if (cur_tx->nge_mbuf != NULL) {
1345 m_freem(cur_tx->nge_mbuf);
1346 cur_tx->nge_mbuf = NULL;
1347 }
1348
1349 sc->nge_cdata.nge_tx_cnt--;
1350 NGE_INC(idx, NGE_TX_LIST_CNT);
1351 ifp->if_timer = 0;
1352 }
1353
1354 sc->nge_cdata.nge_tx_cons = idx;
1355
1356 if (cur_tx != NULL)
1357 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1358}
1359
22bf5b21
JS
1360static void
1361nge_tick(void *xsc)
984263bc 1362{
22bf5b21
JS
1363 struct nge_softc *sc = xsc;
1364 struct ifnet *ifp = &sc->arpcom.ac_if;
1365 struct mii_data *mii;
984263bc 1366
78195a76 1367 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1368
984263bc 1369 if (sc->nge_tbi) {
22bf5b21 1370 if (sc->nge_link == 0) {
984263bc
MD
1371 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1372 & NGE_TBIBMSR_ANEG_DONE) {
e3869ec7 1373 kprintf("nge%d: gigabit link up\n",
984263bc
MD
1374 sc->nge_unit);
1375 nge_miibus_statchg(sc->nge_miibus);
1376 sc->nge_link++;
0b193118 1377 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1378 if_devstart(ifp);
984263bc
MD
1379 }
1380 }
1381 } else {
1382 mii = device_get_softc(sc->nge_miibus);
1383 mii_tick(mii);
1384
22bf5b21 1385 if (sc->nge_link == 0) {
984263bc
MD
1386 if (mii->mii_media_status & IFM_ACTIVE &&
1387 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1388 sc->nge_link++;
1389 if (IFM_SUBTYPE(mii->mii_media_active)
7f259627 1390 == IFM_1000_T)
e3869ec7 1391 kprintf("nge%d: gigabit link up\n",
984263bc 1392 sc->nge_unit);
0b193118 1393 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1394 if_devstart(ifp);
984263bc
MD
1395 }
1396 }
1397 }
43c4cb7e 1398 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1399
78195a76 1400 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1401}
1402
1403#ifdef DEVICE_POLLING
984263bc
MD
1404
1405static void
1406nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1407{
22bf5b21 1408 struct nge_softc *sc = ifp->if_softc;
984263bc 1409
9c095379
MD
1410 switch(cmd) {
1411 case POLL_REGISTER:
1412 /* disable interrupts */
1413 CSR_WRITE_4(sc, NGE_IER, 0);
1414 break;
1415 case POLL_DEREGISTER:
1416 /* enable interrupts */
984263bc 1417 CSR_WRITE_4(sc, NGE_IER, 1);
9c095379
MD
1418 break;
1419 default:
1420 /*
1421 * On the nge, reading the status register also clears it.
1422 * So before returning to intr mode we must make sure that all
1423 * possible pending sources of interrupts have been served.
1424 * In practice this means run to completion the *eof routines,
1425 * and then call the interrupt routine
1426 */
1427 sc->rxcycles = count;
1428 nge_rxeof(sc);
1429 nge_txeof(sc);
1430 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1431 if_devstart(ifp);
984263bc 1432
9c095379
MD
1433 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1434 uint32_t status;
984263bc 1435
9c095379
MD
1436 /* Reading the ISR register clears all interrupts. */
1437 status = CSR_READ_4(sc, NGE_ISR);
984263bc 1438
9c095379
MD
1439 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1440 nge_rxeof(sc);
984263bc 1441
9c095379
MD
1442 if (status & (NGE_ISR_RX_IDLE))
1443 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
984263bc 1444
9c095379
MD
1445 if (status & NGE_ISR_SYSERR) {
1446 nge_reset(sc);
1447 nge_init(sc);
1448 }
984263bc 1449 }
9c095379 1450 break;
984263bc
MD
1451 }
1452}
9c095379 1453
984263bc
MD
1454#endif /* DEVICE_POLLING */
1455
22bf5b21
JS
1456static void
1457nge_intr(void *arg)
984263bc 1458{
22bf5b21
JS
1459 struct nge_softc *sc = arg;
1460 struct ifnet *ifp = &sc->arpcom.ac_if;
1461 uint32_t status;
984263bc 1462
984263bc
MD
1463 /* Supress unwanted interrupts */
1464 if (!(ifp->if_flags & IFF_UP)) {
1465 nge_stop(sc);
1466 return;
1467 }
1468
1469 /* Disable interrupts. */
1470 CSR_WRITE_4(sc, NGE_IER, 0);
1471
1472 /* Data LED on for TBI mode */
1473 if(sc->nge_tbi)
1474 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1475 | NGE_GPIO_GP3_OUT);
1476
1477 for (;;) {
1478 /* Reading the ISR register clears all interrupts. */
1479 status = CSR_READ_4(sc, NGE_ISR);
1480
1481 if ((status & NGE_INTRS) == 0)
1482 break;
1483
1484 if ((status & NGE_ISR_TX_DESC_OK) ||
1485 (status & NGE_ISR_TX_ERR) ||
1486 (status & NGE_ISR_TX_OK) ||
1487 (status & NGE_ISR_TX_IDLE))
1488 nge_txeof(sc);
1489
1490 if ((status & NGE_ISR_RX_DESC_OK) ||
1491 (status & NGE_ISR_RX_ERR) ||
1492 (status & NGE_ISR_RX_OFLOW) ||
1493 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1494 (status & NGE_ISR_RX_IDLE) ||
1495 (status & NGE_ISR_RX_OK))
1496 nge_rxeof(sc);
1497
1498 if ((status & NGE_ISR_RX_IDLE))
1499 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1500
1501 if (status & NGE_ISR_SYSERR) {
1502 nge_reset(sc);
1503 ifp->if_flags &= ~IFF_RUNNING;
1504 nge_init(sc);
1505 }
1506
1507#ifdef notyet
1508 /* mii_tick should only be called once per second */
1509 if (status & NGE_ISR_PHY_INTR) {
1510 sc->nge_link = 0;
78195a76 1511 nge_tick_serialized(sc);
984263bc
MD
1512 }
1513#endif
1514 }
1515
1516 /* Re-enable interrupts. */
1517 CSR_WRITE_4(sc, NGE_IER, 1);
1518
0b193118 1519 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1520 if_devstart(ifp);
984263bc
MD
1521
1522 /* Data LED off for TBI mode */
1523
1524 if(sc->nge_tbi)
1525 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1526 & ~NGE_GPIO_GP3_OUT);
984263bc
MD
1527}
1528
1529/*
1530 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1531 * pointers to the fragment pointers.
1532 */
22bf5b21
JS
1533static int
1534nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
984263bc 1535{
22bf5b21
JS
1536 struct nge_desc *f = NULL;
1537 struct mbuf *m;
1538 int frag, cur, cnt = 0;
984263bc
MD
1539
1540 /*
1541 * Start packing the mbufs in this chain into
1542 * the fragment pointers. Stop when we run out
1543 * of fragments or hit the end of the mbuf chain.
1544 */
984263bc
MD
1545 cur = frag = *txidx;
1546
1547 for (m = m_head; m != NULL; m = m->m_next) {
1548 if (m->m_len != 0) {
1549 if ((NGE_TX_LIST_CNT -
1550 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
9db4b353 1551 break;
984263bc
MD
1552 f = &sc->nge_ldata->nge_tx_list[frag];
1553 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1554 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1555 if (cnt != 0)
1556 f->nge_ctl |= NGE_CMDSTS_OWN;
1557 cur = frag;
1558 NGE_INC(frag, NGE_TX_LIST_CNT);
1559 cnt++;
1560 }
1561 }
9db4b353
SZ
1562 /* Caller should make sure that 'm_head' is not excessive fragmented */
1563 KASSERT(m == NULL, ("too many fragments\n"));
984263bc
MD
1564
1565 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1566 if (m_head->m_pkthdr.csum_flags) {
1567 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1568 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1569 NGE_TXEXTSTS_IPCSUM;
1570 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1571 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1572 NGE_TXEXTSTS_TCPCSUM;
1573 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1574 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1575 NGE_TXEXTSTS_UDPCSUM;
1576 }
1577
83790f85 1578 if (m_head->m_flags & M_VLANTAG) {
984263bc 1579 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
83790f85 1580 (NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag);
984263bc
MD
1581 }
1582
1583 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1584 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1585 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1586 sc->nge_cdata.nge_tx_cnt += cnt;
1587 *txidx = frag;
1588
1589 return(0);
1590}
1591
1592/*
1593 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1594 * to the mbuf data regions directly in the transmit lists. We also save a
1595 * copy of the pointers since the transmit list fragment pointers are
1596 * physical addresses.
1597 */
1598
22bf5b21
JS
1599static void
1600nge_start(struct ifnet *ifp)
984263bc 1601{
22bf5b21 1602 struct nge_softc *sc = ifp->if_softc;
9db4b353 1603 struct mbuf *m_head = NULL, *m_defragged;
22bf5b21 1604 uint32_t idx;
2f54d1d2 1605 int need_trans;
984263bc 1606
9db4b353
SZ
1607 if (!sc->nge_link) {
1608 ifq_purge(&ifp->if_snd);
984263bc 1609 return;
9db4b353 1610 }
984263bc
MD
1611
1612 idx = sc->nge_cdata.nge_tx_prod;
1613
9db4b353 1614 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
984263bc
MD
1615 return;
1616
2f54d1d2 1617 need_trans = 0;
9db4b353
SZ
1618 while (sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1619 struct mbuf *m;
1620 int cnt;
1621
1622 m_defragged = NULL;
1623 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1624 if (m_head == NULL)
1625 break;
1626
9db4b353
SZ
1627again:
1628 cnt = 0;
1629 for (m = m_head; m != NULL; m = m->m_next)
1630 ++cnt;
1631 if ((NGE_TX_LIST_CNT -
1632 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) {
1633 if (m_defragged != NULL) {
1634 /*
1635 * Even after defragmentation, there
1636 * are still too many fragments, so
1637 * drop this packet.
1638 */
1639 m_freem(m_head);
1640 ifp->if_flags |= IFF_OACTIVE;
1641 break;
1642 }
1643
1644 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1645 if (m_defragged == NULL) {
1646 m_freem(m_head);
1647 continue;
1648 }
1649 m_head = m_defragged;
1650
1651 /* Recount # of fragments */
1652 goto again;
984263bc 1653 }
9db4b353
SZ
1654
1655 nge_encap(sc, m_head, &idx);
2f54d1d2 1656 need_trans = 1;
984263bc 1657
b637f170 1658 ETHER_BPF_MTAP(ifp, m_head);
984263bc
MD
1659 }
1660
2f54d1d2
SZ
1661 if (!need_trans)
1662 return;
1663
984263bc
MD
1664 /* Transmit */
1665 sc->nge_cdata.nge_tx_prod = idx;
1666 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1667
1668 /*
1669 * Set a timeout in case the chip goes out to lunch.
1670 */
1671 ifp->if_timer = 5;
984263bc
MD
1672}
1673
22bf5b21
JS
1674static void
1675nge_init(void *xsc)
984263bc 1676{
22bf5b21
JS
1677 struct nge_softc *sc = xsc;
1678 struct ifnet *ifp = &sc->arpcom.ac_if;
1679 struct mii_data *mii;
984263bc 1680
88e7510c 1681 if (ifp->if_flags & IFF_RUNNING) {
88e7510c
JS
1682 return;
1683 }
984263bc
MD
1684
1685 /*
1686 * Cancel pending I/O and free all RX/TX buffers.
1687 */
1688 nge_stop(sc);
43c4cb7e 1689 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
984263bc 1690
22bf5b21 1691 if (sc->nge_tbi)
984263bc 1692 mii = NULL;
22bf5b21 1693 else
984263bc 1694 mii = device_get_softc(sc->nge_miibus);
984263bc
MD
1695
1696 /* Set MAC address */
1697 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1698 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1699 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
984263bc
MD
1700 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1701 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1702 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
984263bc
MD
1703 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1704 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
22bf5b21 1705 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
984263bc
MD
1706
1707 /* Init circular RX list. */
1708 if (nge_list_rx_init(sc) == ENOBUFS) {
e3869ec7 1709 kprintf("nge%d: initialization failed: no "
984263bc
MD
1710 "memory for rx buffers\n", sc->nge_unit);
1711 nge_stop(sc);
984263bc
MD
1712 return;
1713 }
1714
1715 /*
1716 * Init tx descriptors.
1717 */
1718 nge_list_tx_init(sc);
1719
1720 /*
1721 * For the NatSemi chip, we have to explicitly enable the
1722 * reception of ARP frames, as well as turn on the 'perfect
1723 * match' filter where we store the station address, otherwise
1724 * we won't receive unicasts meant for this host.
1725 */
1726 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1727 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1728
1729 /* If we want promiscuous mode, set the allframes bit. */
22bf5b21 1730 if (ifp->if_flags & IFF_PROMISC)
984263bc 1731 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
22bf5b21 1732 else
984263bc 1733 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
984263bc
MD
1734
1735 /*
1736 * Set the capture broadcast bit to capture broadcast frames.
1737 */
22bf5b21 1738 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1739 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
22bf5b21 1740 else
984263bc 1741 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
984263bc
MD
1742
1743 /*
1744 * Load the multicast filter.
1745 */
1746 nge_setmulti(sc);
1747
1748 /* Turn the receive filter on */
1749 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1750
1751 /*
1752 * Load the address of the RX and TX lists.
1753 */
1754 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1755 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1756 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1757 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1758
1759 /* Set RX configuration */
1760 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1761 /*
1762 * Enable hardware checksum validation for all IPv4
1763 * packets, do not reject packets with bad checksums.
1764 */
1765 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1766
1767 /*
1768 * Tell the chip to detect and strip VLAN tag info from
1769 * received frames. The tag will be provided in the extsts
1770 * field in the RX descriptors.
1771 */
1772 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1773 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1774
1775 /* Set TX configuration */
1776 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1777
1778 /*
1779 * Enable TX IPv4 checksumming on a per-packet basis.
1780 */
1781 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1782
1783 /*
1784 * Tell the chip to insert VLAN tags on a per-packet basis as
1785 * dictated by the code in the frame encapsulation routine.
1786 */
1787 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1788
1789 /* Set full/half duplex mode. */
1790 if (sc->nge_tbi) {
1791 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1792 == IFM_FDX) {
1793 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1794 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1795 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1796 } else {
1797 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1798 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1799 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1800 }
1801 } else {
1802 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1803 NGE_SETBIT(sc, NGE_TX_CFG,
22bf5b21 1804 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1805 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1806 } else {
1807 NGE_CLRBIT(sc, NGE_TX_CFG,
22bf5b21 1808 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
984263bc
MD
1809 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1810 }
1811 }
1812
1813 /*
1814 * Enable the delivery of PHY interrupts based on
1815 * link/speed/duplex status changes. Also enable the
1816 * extsts field in the DMA descriptors (needed for
1817 * TCP/IP checksum offload on transmit).
1818 */
22bf5b21
JS
1819 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1820 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
984263bc
MD
1821
1822 /*
1823 * Configure interrupt holdoff (moderation). We can
1824 * have the chip delay interrupt delivery for a certain
1825 * period. Units are in 100us, and the max setting
1826 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1827 */
1828 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1829
1830 /*
1831 * Enable interrupts.
1832 */
1833 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1834#ifdef DEVICE_POLLING
1835 /*
1836 * ... only enable interrupts if we are not polling, make sure
1837 * they are off otherwise.
1838 */
46f25451 1839 if (ifp->if_flags & IFF_POLLING)
984263bc
MD
1840 CSR_WRITE_4(sc, NGE_IER, 0);
1841 else
1842#endif /* DEVICE_POLLING */
1843 CSR_WRITE_4(sc, NGE_IER, 1);
1844
1845 /* Enable receiver and transmitter. */
22bf5b21 1846 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
984263bc
MD
1847 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1848
1849 nge_ifmedia_upd(ifp);
1850
1851 ifp->if_flags |= IFF_RUNNING;
1852 ifp->if_flags &= ~IFF_OACTIVE;
984263bc
MD
1853}
1854
1855/*
1856 * Set media options.
1857 */
22bf5b21
JS
1858static int
1859nge_ifmedia_upd(struct ifnet *ifp)
984263bc 1860{
22bf5b21
JS
1861 struct nge_softc *sc = ifp->if_softc;
1862 struct mii_data *mii;
984263bc
MD
1863
1864 if (sc->nge_tbi) {
1865 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1866 == IFM_AUTO) {
1867 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1868 CSR_READ_4(sc, NGE_TBI_ANAR)
1869 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1870 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1871 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1872 | NGE_TBIBMCR_RESTART_ANEG);
1873 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1874 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1875 & IFM_GMASK) == IFM_FDX) {
1876 NGE_SETBIT(sc, NGE_TX_CFG,
1877 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1878 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1879
1880 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1881 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1882 } else {
1883 NGE_CLRBIT(sc, NGE_TX_CFG,
1884 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1885 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1886
1887 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1888 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1889 }
1890
1891 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1892 & ~NGE_GPIO_GP3_OUT);
1893 } else {
1894 mii = device_get_softc(sc->nge_miibus);
1895 sc->nge_link = 0;
1896 if (mii->mii_instance) {
1897 struct mii_softc *miisc;
1898 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1899 miisc = LIST_NEXT(miisc, mii_list))
1900 mii_phy_reset(miisc);
1901 }
1902 mii_mediachg(mii);
1903 }
1904
1905 return(0);
1906}
1907
1908/*
1909 * Report current media status.
1910 */
22bf5b21
JS
1911static void
1912nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1913{
22bf5b21
JS
1914 struct nge_softc *sc = ifp->if_softc;
1915 struct mii_data *mii;
984263bc
MD
1916
1917 if (sc->nge_tbi) {
1918 ifmr->ifm_status = IFM_AVALID;
1919 ifmr->ifm_active = IFM_ETHER;
1920
22bf5b21 1921 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
984263bc 1922 ifmr->ifm_status |= IFM_ACTIVE;
984263bc
MD
1923 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1924 ifmr->ifm_active |= IFM_LOOP;
1925 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1926 ifmr->ifm_active |= IFM_NONE;
1927 ifmr->ifm_status = 0;
1928 return;
1929 }
1930 ifmr->ifm_active |= IFM_1000_SX;
1931 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1932 == IFM_AUTO) {
1933 ifmr->ifm_active |= IFM_AUTO;
1934 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1935 & NGE_TBIANAR_FDX) {
1936 ifmr->ifm_active |= IFM_FDX;
1937 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1938 & NGE_TBIANAR_HDX) {
1939 ifmr->ifm_active |= IFM_HDX;
1940 }
1941 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1942 == IFM_FDX)
1943 ifmr->ifm_active |= IFM_FDX;
1944 else
1945 ifmr->ifm_active |= IFM_HDX;
1946
1947 } else {
1948 mii = device_get_softc(sc->nge_miibus);
1949 mii_pollstat(mii);
1950 ifmr->ifm_active = mii->mii_media_active;
1951 ifmr->ifm_status = mii->mii_media_status;
1952 }
984263bc
MD
1953}
1954
22bf5b21
JS
1955static int
1956nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1957{
22bf5b21
JS
1958 struct nge_softc *sc = ifp->if_softc;
1959 struct ifreq *ifr = (struct ifreq *) data;
1960 struct mii_data *mii;
88e7510c 1961 int error = 0;
984263bc 1962
984263bc 1963 switch(command) {
984263bc 1964 case SIOCSIFMTU:
22bf5b21 1965 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
984263bc 1966 error = EINVAL;
22bf5b21 1967 } else {
984263bc
MD
1968 ifp->if_mtu = ifr->ifr_mtu;
1969 /*
1970 * Workaround: if the MTU is larger than
1971 * 8152 (TX FIFO size minus 64 minus 18), turn off
1972 * TX checksum offloading.
1973 */
1974 if (ifr->ifr_mtu >= 8152)
1975 ifp->if_hwassist = 0;
1976 else
1977 ifp->if_hwassist = NGE_CSUM_FEATURES;
1978 }
1979 break;
1980 case SIOCSIFFLAGS:
1981 if (ifp->if_flags & IFF_UP) {
1982 if (ifp->if_flags & IFF_RUNNING &&
1983 ifp->if_flags & IFF_PROMISC &&
1984 !(sc->nge_if_flags & IFF_PROMISC)) {
1985 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1986 NGE_RXFILTCTL_ALLPHYS|
1987 NGE_RXFILTCTL_ALLMULTI);
1988 } else if (ifp->if_flags & IFF_RUNNING &&
1989 !(ifp->if_flags & IFF_PROMISC) &&
1990 sc->nge_if_flags & IFF_PROMISC) {
1991 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1992 NGE_RXFILTCTL_ALLPHYS);
1993 if (!(ifp->if_flags & IFF_ALLMULTI))
1994 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1995 NGE_RXFILTCTL_ALLMULTI);
1996 } else {
1997 ifp->if_flags &= ~IFF_RUNNING;
1998 nge_init(sc);
1999 }
2000 } else {
2001 if (ifp->if_flags & IFF_RUNNING)
2002 nge_stop(sc);
2003 }
2004 sc->nge_if_flags = ifp->if_flags;
2005 error = 0;
2006 break;
2007 case SIOCADDMULTI:
2008 case SIOCDELMULTI:
2009 nge_setmulti(sc);
2010 error = 0;
2011 break;
2012 case SIOCGIFMEDIA:
2013 case SIOCSIFMEDIA:
2014 if (sc->nge_tbi) {
2015 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2016 command);
2017 } else {
2018 mii = device_get_softc(sc->nge_miibus);
2019 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2020 command);
2021 }
2022 break;
2023 default:
c1484ba2 2024 error = ether_ioctl(ifp, command, data);
984263bc
MD
2025 break;
2026 }
984263bc
MD
2027 return(error);
2028}
2029
22bf5b21
JS
2030static void
2031nge_watchdog(struct ifnet *ifp)
984263bc 2032{
22bf5b21 2033 struct nge_softc *sc = ifp->if_softc;
984263bc
MD
2034
2035 ifp->if_oerrors++;
e3869ec7 2036 kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
984263bc
MD
2037
2038 nge_stop(sc);
2039 nge_reset(sc);
2040 ifp->if_flags &= ~IFF_RUNNING;
2041 nge_init(sc);
2042
0b193118 2043 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2044 if_devstart(ifp);
984263bc
MD
2045}
2046
2047/*
2048 * Stop the adapter and free any mbufs allocated to the
2049 * RX and TX lists.
2050 */
22bf5b21
JS
2051static void
2052nge_stop(struct nge_softc *sc)
984263bc 2053{
22bf5b21
JS
2054 struct ifnet *ifp = &sc->arpcom.ac_if;
2055 struct ifmedia_entry *ifm;
2056 struct mii_data *mii;
08bec554 2057 int i, itmp, mtmp, dtmp;
984263bc 2058
984263bc 2059 ifp->if_timer = 0;
22bf5b21 2060 if (sc->nge_tbi)
984263bc 2061 mii = NULL;
22bf5b21 2062 else
984263bc 2063 mii = device_get_softc(sc->nge_miibus);
984263bc 2064
43c4cb7e 2065 callout_stop(&sc->nge_stat_timer);
984263bc
MD
2066 CSR_WRITE_4(sc, NGE_IER, 0);
2067 CSR_WRITE_4(sc, NGE_IMR, 0);
2068 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2069 DELAY(1000);
2070 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2071 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2072
2073 /*
2074 * Isolate/power down the PHY, but leave the media selection
2075 * unchanged so that things will be put back to normal when
2076 * we bring the interface back up.
2077 */
2078 itmp = ifp->if_flags;
2079 ifp->if_flags |= IFF_UP;
2080
2081 if (sc->nge_tbi)
2082 ifm = sc->nge_ifmedia.ifm_cur;
2083 else
2084 ifm = mii->mii_media.ifm_cur;
08bec554 2085
984263bc 2086 mtmp = ifm->ifm_media;
08bec554 2087 dtmp = ifm->ifm_data;
984263bc 2088 ifm->ifm_media = IFM_ETHER|IFM_NONE;
08bec554
SZ
2089 ifm->ifm_data = MII_MEDIA_NONE;
2090
984263bc
MD
2091 if (!sc->nge_tbi)
2092 mii_mediachg(mii);
2093 ifm->ifm_media = mtmp;
08bec554 2094 ifm->ifm_data = dtmp;
984263bc
MD
2095 ifp->if_flags = itmp;
2096
2097 sc->nge_link = 0;
2098
2099 /*
2100 * Free data in the RX lists.
2101 */
2102 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2103 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2104 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2105 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2106 }
2107 }
22bf5b21 2108 bzero(&sc->nge_ldata->nge_rx_list,
984263bc
MD
2109 sizeof(sc->nge_ldata->nge_rx_list));
2110
2111 /*
2112 * Free the TX list buffers.
2113 */
2114 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2115 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2116 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2117 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2118 }
2119 }
2120
22bf5b21 2121 bzero(&sc->nge_ldata->nge_tx_list,
984263bc
MD
2122 sizeof(sc->nge_ldata->nge_tx_list));
2123
2124 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
2125}
2126
2127/*
2128 * Stop all chip I/O so that the kernel's probe routines don't
2129 * get confused by errant DMAs when rebooting.
2130 */
22bf5b21
JS
2131static void
2132nge_shutdown(device_t dev)
984263bc 2133{
22bf5b21 2134 struct nge_softc *sc = device_get_softc(dev);
78195a76 2135 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 2136
78195a76 2137 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
2138 nge_reset(sc);
2139 nge_stop(sc);
78195a76 2140 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2141}
78195a76 2142