network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / rtw / rtw.c
CommitLineData
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1/*
2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $NetBSD: rtw.c,v 1.72 2006/03/28 00:48:10 dyoung Exp $
9db4b353 35 * $DragonFly: src/sys/dev/netif/rtw/rtw.c,v 1.13 2008/05/14 11:59:21 sephe Exp $
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36 */
37
38/*
39 * Copyright (c) 2004, 2005 David Young. All rights reserved.
40 *
41 * Programmed for NetBSD by David Young.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. The name of David Young may not be used to endorse or promote
52 * products derived from this software without specific prior
53 * written permission.
54 *
55 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
56 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
57 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
58 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
59 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
60 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
61 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
63 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
65 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
66 * OF SUCH DAMAGE.
67 */
68
69/*
70 * Device driver for the Realtek RTL8180 802.11 MAC/BBP.
71 */
72
73#include <sys/param.h>
b5b6e4f4 74#include <sys/bitops.h>
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75#include <sys/bus.h>
76#include <sys/endian.h>
77#include <sys/kernel.h>
9db4b353 78#include <sys/interrupt.h>
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79#include <sys/rman.h>
80#include <sys/socket.h>
81#include <sys/sockio.h>
82#include <sys/serialize.h>
83#include <sys/sysctl.h>
84
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85#include <net/if.h>
86#include <net/if_arp.h>
87#include <net/if_dl.h>
88#include <net/if_media.h>
89#include <net/ifq_var.h>
90#include <net/ethernet.h>
91#include <net/bpf.h>
92
93#include <netproto/802_11/ieee80211_var.h>
94#include <netproto/802_11/ieee80211_radiotap.h>
21028056 95#include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
44db266b 96
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97#include <dev/netif/rtw/rtwreg.h>
98#include <dev/netif/rtw/rtwvar.h>
99#include <dev/netif/rtw/rtwphyio.h>
100#include <dev/netif/rtw/rtwphy.h>
101#include <dev/netif/rtw/smc93cx6var.h>
102#include <dev/netif/rtw/sa2400reg.h>
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103
104/* XXX */
105#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
106#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
107#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
108#define IEEE80211_DUR_DS_FAST_PLCPHDR 24
109#define IEEE80211_DUR_DS_SLOW_ACK 112
110#define IEEE80211_DUR_DS_SLOW_CTS 112
111#define IEEE80211_DUR_DS_SIFS 10
112
113struct rtw_txsegs {
114 int nseg;
115 bus_dma_segment_t segs[RTW_MAXPKTSEGS];
116};
117
118devclass_t rtw_devclass;
119
120static const struct ieee80211_rateset rtw_rates_11b = { 4, { 2, 4, 11, 22 } };
121
122SYSCTL_NODE(_hw, OID_AUTO, rtw, CTLFLAG_RD, 0,
123 "Realtek RTL818x 802.11 controls");
124
b5b6e4f4 125/* [0, __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)] */
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126static int rtw_rfprog_fallback = 0;
127SYSCTL_INT(_hw_rtw, OID_AUTO, rfprog_fallback, CTLFLAG_RW,
128 &rtw_rfprog_fallback, 0, "fallback RF programming method");
129
130static int rtw_host_rfio = 0; /* 0/1 */
131SYSCTL_INT(_hw_rtw, OID_AUTO, host_rfio, CTLFLAG_RW,
132 &rtw_host_rfio, 0, "enable host control of RF I/O");
133
134#ifdef RTW_DEBUG
135int rtw_debug = 0; /* [0, RTW_DEBUG_MAX] */
136SYSCTL_INT(_hw_rtw, OID_AUTO, debug, CTLFLAG_RW, &rtw_debug, 0, "debug level");
137
138static int rtw_rxbufs_limit = RTW_RXQLEN; /* [0, RTW_RXQLEN] */
139SYSCTL_INT(_hw_rtw, OID_AUTO, rxbufs_limit, CTLFLAG_RW, &rtw_rxbufs_limit, 0,
140 "rx buffers limit");
141#endif /* RTW_DEBUG */
142
143#if 0
144static int rtw_xmtr_restart = 0;
145SYSCTL_INT(_hw_rtw, OID_AUTO, xmtr_restart, CTLFLAG_RW, &rtw_xmtr_restart, 0,
146 "gratuitously reset xmtr on rcvr error");
147
148static int rtw_ring_reset = 0;
149SYSCTL_INT(_hw_rtw, OID_AUTO, ring_reset, CTLFLAG_RW, &rtw_ring_reset, 0,
150 "reset ring pointers on rcvr error");
151#endif
152
153static int rtw_do_chip_reset = 0;
154SYSCTL_INT(_hw_rtw, OID_AUTO, chip_reset, CTLFLAG_RW, &rtw_do_chip_reset, 0,
155 "gratuitously reset chip on rcvr error");
156
157int rtw_dwelltime = 200; /* milliseconds */
158
159/* XXX */
160static struct ieee80211_cipher rtw_cipher_wep;
161
162static void rtw_led_init(struct rtw_softc *);
163static void rtw_led_newstate(struct rtw_softc *, enum ieee80211_state);
164static void rtw_led_slowblink(void *);
165static void rtw_led_fastblink(void *);
166static void rtw_led_set(struct rtw_softc *);
167
168static void rtw_init(void *);
169static void rtw_start(struct ifnet *);
170static int rtw_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
171static void rtw_watchdog(struct ifnet *);
172static void rtw_intr(void *);
173
174static void rtw_intr_rx(struct rtw_softc *, uint16_t);
175static void rtw_intr_tx(struct rtw_softc *, uint16_t);
176static void rtw_intr_beacon(struct rtw_softc *, uint16_t);
177static void rtw_intr_atim(struct rtw_softc *);
178static void rtw_intr_ioerror(struct rtw_softc *, uint16_t);
179static void rtw_intr_timeout(struct rtw_softc *);
180
181static int rtw_dequeue(struct ifnet *, struct rtw_txsoft_blk **,
182 struct rtw_txdesc_blk **, struct mbuf **,
183 struct ieee80211_node **);
184static struct mbuf *rtw_load_txbuf(struct rtw_softc *, struct rtw_txsoft *,
185 struct rtw_txsegs *, int, struct mbuf *);
186
187static void rtw_idle(struct rtw_softc *);
188static void rtw_txring_fixup(struct rtw_softc *);
189static void rtw_rxring_fixup(struct rtw_softc *);
190static int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *);
191static void rtw_reset_oactive(struct rtw_softc *);
192
193static int rtw_enable(struct rtw_softc *);
194static void rtw_disable(struct rtw_softc *);
195static void rtw_io_enable(struct rtw_softc *, uint8_t, int);
196static int rtw_pwrstate(struct rtw_softc *, enum rtw_pwrstate);
197static void rtw_set_access(struct rtw_softc *, enum rtw_access);
198
199static void rtw_continuous_tx_enable(struct rtw_softc *, int);
200static void rtw_txdac_enable(struct rtw_softc *, int);
201static void rtw_anaparm_enable(struct rtw_regs *, int);
202static void rtw_config0123_enable(struct rtw_regs *, int);
203
204static void rtw_transmit_config(struct rtw_regs *);
205static void rtw_set_rfprog(struct rtw_softc *);
206static void rtw_enable_interrupts(struct rtw_softc *);
207static void rtw_pktfilt_load(struct rtw_softc *);
208static void rtw_wep_setkeys(struct rtw_softc *);
209static void rtw_resume_ticks(struct rtw_softc *);
210static void rtw_set_nettype(struct rtw_softc *, enum ieee80211_opmode);
211
212static int rtw_reset(struct rtw_softc *);
213static int rtw_chip_reset(struct rtw_softc *);
214static int rtw_recall_eeprom(struct rtw_softc *);
215static int rtw_srom_read(struct rtw_softc *);
216static int rtw_srom_parse(struct rtw_softc *);
217static struct rtw_rf *rtw_rf_attach(struct rtw_softc *, enum rtw_rfchipid, int);
218
219static uint8_t rtw_check_phydelay(struct rtw_regs *, uint32_t);
220static void rtw_identify_country(struct rtw_softc *);
221static int rtw_identify_sta(struct rtw_softc *);
222
223static int rtw_swring_setup(struct rtw_softc *);
224static void rtw_hwring_setup(struct rtw_softc *);
225
226static int rtw_desc_blk_alloc(struct rtw_softc *);
227static void rtw_desc_blk_free(struct rtw_softc *);
228static int rtw_soft_blk_alloc(struct rtw_softc *);
229static void rtw_soft_blk_free(struct rtw_softc *);
230
231static void rtw_txdesc_blk_init_all(struct rtw_softc *);
232static void rtw_txsoft_blk_init_all(struct rtw_softc *);
233static void rtw_rxdesc_blk_init_all(struct rtw_softc *);
234static int rtw_rxsoft_blk_init_all(struct rtw_softc *);
235
236static void rtw_txdesc_blk_reset_all(struct rtw_softc *);
237
238static int rtw_rxsoft_alloc(struct rtw_softc *, struct rtw_rxsoft *, int);
239static void rtw_rxdesc_init(struct rtw_softc *, int idx, int);
240
241#ifdef RTW_DEBUG
242static void rtw_print_txdesc(struct rtw_softc *, const char *,
243 struct rtw_txsoft *, struct rtw_txdesc_blk *,
244 int);
245#endif /* RTW_DEBUG */
246
247static int rtw_newstate(struct ieee80211com *, enum ieee80211_state, int);
248static void rtw_next_scan(void *);
249
250static int rtw_key_delete(struct ieee80211com *,
251 const struct ieee80211_key *);
252static int rtw_key_set(struct ieee80211com *,
253 const struct ieee80211_key *,
254 const u_int8_t[IEEE80211_ADDR_LEN]);
255static void rtw_key_update_end(struct ieee80211com *);
256static void rtw_key_update_begin(struct ieee80211com *);
257static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int);
258
259static int rtw_compute_duration1(int, int, uint32_t, int,
260 struct rtw_duration *);
261static int rtw_compute_duration(const struct ieee80211_frame_min *,
262 const struct ieee80211_key *, int,
263 uint32_t, int, int,
264 struct rtw_duration *,
265 struct rtw_duration *, int *, int);
266
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267static int rtw_get_rssi(struct rtw_softc *, uint8_t, uint8_t);
268static int rtw_maxim_getrssi(uint8_t, uint8_t);
269static int rtw_gct_getrssi(uint8_t, uint8_t);
270static int rtw_philips_getrssi(uint8_t, uint8_t);
271
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272static void *rtw_ratectl_attach(struct ieee80211com *, u_int);
273
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274#ifdef RTW_DEBUG
275static void
276rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
277{
278#define PRINTREG32(sc, reg) \
279 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
280 ("%s: reg[ " #reg " / %03x ] = %08x\n", \
281 dvname, reg, RTW_READ(regs, reg)))
282
283#define PRINTREG16(sc, reg) \
284 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
285 ("%s: reg[ " #reg " / %03x ] = %04x\n", \
286 dvname, reg, RTW_READ16(regs, reg)))
287
288#define PRINTREG8(sc, reg) \
289 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
290 ("%s: reg[ " #reg " / %03x ] = %02x\n", \
291 dvname, reg, RTW_READ8(regs, reg)))
292
293 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where));
294
295 PRINTREG32(regs, RTW_IDR0);
296 PRINTREG32(regs, RTW_IDR1);
297 PRINTREG32(regs, RTW_MAR0);
298 PRINTREG32(regs, RTW_MAR1);
299 PRINTREG32(regs, RTW_TSFTRL);
300 PRINTREG32(regs, RTW_TSFTRH);
301 PRINTREG32(regs, RTW_TLPDA);
302 PRINTREG32(regs, RTW_TNPDA);
303 PRINTREG32(regs, RTW_THPDA);
304 PRINTREG32(regs, RTW_TCR);
305 PRINTREG32(regs, RTW_RCR);
306 PRINTREG32(regs, RTW_TINT);
307 PRINTREG32(regs, RTW_TBDA);
308 PRINTREG32(regs, RTW_ANAPARM);
309 PRINTREG32(regs, RTW_BB);
310 PRINTREG32(regs, RTW_PHYCFG);
311 PRINTREG32(regs, RTW_WAKEUP0L);
312 PRINTREG32(regs, RTW_WAKEUP0H);
313 PRINTREG32(regs, RTW_WAKEUP1L);
314 PRINTREG32(regs, RTW_WAKEUP1H);
315 PRINTREG32(regs, RTW_WAKEUP2LL);
316 PRINTREG32(regs, RTW_WAKEUP2LH);
317 PRINTREG32(regs, RTW_WAKEUP2HL);
318 PRINTREG32(regs, RTW_WAKEUP2HH);
319 PRINTREG32(regs, RTW_WAKEUP3LL);
320 PRINTREG32(regs, RTW_WAKEUP3LH);
321 PRINTREG32(regs, RTW_WAKEUP3HL);
322 PRINTREG32(regs, RTW_WAKEUP3HH);
323 PRINTREG32(regs, RTW_WAKEUP4LL);
324 PRINTREG32(regs, RTW_WAKEUP4LH);
325 PRINTREG32(regs, RTW_WAKEUP4HL);
326 PRINTREG32(regs, RTW_WAKEUP4HH);
327 PRINTREG32(regs, RTW_DK0);
328 PRINTREG32(regs, RTW_DK1);
329 PRINTREG32(regs, RTW_DK2);
330 PRINTREG32(regs, RTW_DK3);
331 PRINTREG32(regs, RTW_RETRYCTR);
332 PRINTREG32(regs, RTW_RDSAR);
333 PRINTREG32(regs, RTW_FER);
334 PRINTREG32(regs, RTW_FEMR);
335 PRINTREG32(regs, RTW_FPSR);
336 PRINTREG32(regs, RTW_FFER);
337
338 /* 16-bit registers */
339 PRINTREG16(regs, RTW_BRSR);
340 PRINTREG16(regs, RTW_IMR);
341 PRINTREG16(regs, RTW_ISR);
342 PRINTREG16(regs, RTW_BCNITV);
343 PRINTREG16(regs, RTW_ATIMWND);
344 PRINTREG16(regs, RTW_BINTRITV);
345 PRINTREG16(regs, RTW_ATIMTRITV);
346 PRINTREG16(regs, RTW_CRC16ERR);
347 PRINTREG16(regs, RTW_CRC0);
348 PRINTREG16(regs, RTW_CRC1);
349 PRINTREG16(regs, RTW_CRC2);
350 PRINTREG16(regs, RTW_CRC3);
351 PRINTREG16(regs, RTW_CRC4);
352 PRINTREG16(regs, RTW_CWR);
353
354 /* 8-bit registers */
355 PRINTREG8(regs, RTW_CR);
356 PRINTREG8(regs, RTW_9346CR);
357 PRINTREG8(regs, RTW_CONFIG0);
358 PRINTREG8(regs, RTW_CONFIG1);
359 PRINTREG8(regs, RTW_CONFIG2);
360 PRINTREG8(regs, RTW_MSR);
361 PRINTREG8(regs, RTW_CONFIG3);
362 PRINTREG8(regs, RTW_CONFIG4);
363 PRINTREG8(regs, RTW_TESTR);
364 PRINTREG8(regs, RTW_PSR);
365 PRINTREG8(regs, RTW_SCR);
366 PRINTREG8(regs, RTW_PHYDELAY);
367 PRINTREG8(regs, RTW_CRCOUNT);
368 PRINTREG8(regs, RTW_PHYADDR);
369 PRINTREG8(regs, RTW_PHYDATAW);
370 PRINTREG8(regs, RTW_PHYDATAR);
371 PRINTREG8(regs, RTW_CONFIG5);
372 PRINTREG8(regs, RTW_TPPOLL);
373
374 PRINTREG16(regs, RTW_BSSID16);
375 PRINTREG32(regs, RTW_BSSID32);
376#undef PRINTREG32
377#undef PRINTREG16
378#undef PRINTREG8
379}
380#endif /* RTW_DEBUG */
381
382static void
383rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
384{
385 struct rtw_regs *regs = &sc->sc_regs;
386 uint32_t tcr;
387
388 tcr = RTW_READ(regs, RTW_TCR);
389 tcr &= ~RTW_TCR_LBK_MASK;
390 if (enable)
391 tcr |= RTW_TCR_LBK_CONT;
392 else
393 tcr |= RTW_TCR_LBK_NORMAL;
394 RTW_WRITE(regs, RTW_TCR, tcr);
395 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
396 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
397 rtw_txdac_enable(sc, !enable);
398 rtw_set_access(sc, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
399 rtw_set_access(sc, RTW_ACCESS_NONE);
400}
401
402#ifdef RTW_DEBUG
403static const char *
404rtw_access_string(enum rtw_access access)
405{
406 switch (access) {
407 case RTW_ACCESS_NONE:
408 return "none";
409 case RTW_ACCESS_CONFIG:
410 return "config";
411 case RTW_ACCESS_ANAPARM:
412 return "anaparm";
413 default:
414 return "unknown";
415 }
416}
417#endif /* RTW_DEBUG */
418
419static void
420rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
421{
422 KKASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM);
423 KKASSERT(regs->r_access >= RTW_ACCESS_NONE &&
424 regs->r_access <= RTW_ACCESS_ANAPARM);
425
426 if (naccess == regs->r_access)
427 return;
428
429 switch (naccess) {
430 case RTW_ACCESS_NONE:
431 switch (regs->r_access) {
432 case RTW_ACCESS_ANAPARM:
433 rtw_anaparm_enable(regs, 0);
434 /*FALLTHROUGH*/
435 case RTW_ACCESS_CONFIG:
436 rtw_config0123_enable(regs, 0);
437 /*FALLTHROUGH*/
438 case RTW_ACCESS_NONE:
439 break;
440 }
441 break;
442 case RTW_ACCESS_CONFIG:
443 switch (regs->r_access) {
444 case RTW_ACCESS_NONE:
445 rtw_config0123_enable(regs, 1);
446 /*FALLTHROUGH*/
447 case RTW_ACCESS_CONFIG:
448 break;
449 case RTW_ACCESS_ANAPARM:
450 rtw_anaparm_enable(regs, 0);
451 break;
452 }
453 break;
454 case RTW_ACCESS_ANAPARM:
455 switch (regs->r_access) {
456 case RTW_ACCESS_NONE:
457 rtw_config0123_enable(regs, 1);
458 /*FALLTHROUGH*/
459 case RTW_ACCESS_CONFIG:
460 rtw_anaparm_enable(regs, 1);
461 /*FALLTHROUGH*/
462 case RTW_ACCESS_ANAPARM:
463 break;
464 }
465 break;
466 }
467}
468
469static void
470rtw_set_access(struct rtw_softc *sc, enum rtw_access access)
471{
472 struct rtw_regs *regs = &sc->sc_regs;
473
474 rtw_set_access1(regs, access);
475 RTW_DPRINTF(RTW_DEBUG_ACCESS,
476 ("%s: access %s -> %s\n", sc->sc_ic.ic_if.if_xname,
477 rtw_access_string(regs->r_access),
478 rtw_access_string(access)));
479 regs->r_access = access;
480}
481
482/*
483 * Enable registers, switch register banks.
484 */
485static void
486rtw_config0123_enable(struct rtw_regs *regs, int enable)
487{
488 uint8_t ecr;
489
490 ecr = RTW_READ8(regs, RTW_9346CR);
491 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);
492 if (enable) {
493 ecr |= RTW_9346CR_EEM_CONFIG;
494 } else {
495 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
496 ecr |= RTW_9346CR_EEM_NORMAL;
497 }
498 RTW_WRITE8(regs, RTW_9346CR, ecr);
499 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
500}
501
502/* requires rtw_config0123_enable(, 1) */
503static void
504rtw_anaparm_enable(struct rtw_regs *regs, int enable)
505{
506 uint8_t cfg3;
507
508 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
509 cfg3 |= RTW_CONFIG3_CLKRUNEN;
510 if (enable)
511 cfg3 |= RTW_CONFIG3_PARMEN;
512 else
513 cfg3 &= ~RTW_CONFIG3_PARMEN;
514 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
515 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
516}
517
518/* requires rtw_anaparm_enable(, 1) */
519static void
520rtw_txdac_enable(struct rtw_softc *sc, int enable)
521{
522 uint32_t anaparm;
523 struct rtw_regs *regs = &sc->sc_regs;
524
525 anaparm = RTW_READ(regs, RTW_ANAPARM);
526 if (enable)
527 anaparm &= ~RTW_ANAPARM_TXDACOFF;
528 else
529 anaparm |= RTW_ANAPARM_TXDACOFF;
530 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
531 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
532}
533
534static int
535rtw_chip_reset1(struct rtw_softc *sc)
536{
537 struct rtw_regs *regs = &sc->sc_regs;
538 uint8_t cr;
539 int i;
540
541 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
542
543 RTW_WBR(regs, RTW_CR, RTW_CR);
544
545 for (i = 0; i < 1000; i++) {
546 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
547 RTW_DPRINTF(RTW_DEBUG_RESET,
548 ("%s: reset in %dus\n",
549 sc->sc_ic.ic_if.if_xname, i));
550 return 0;
551 }
552 RTW_RBR(regs, RTW_CR, RTW_CR);
553 DELAY(10); /* 10us */
554 }
555
556 if_printf(&sc->sc_ic.ic_if, "reset failed\n");
557 return ETIMEDOUT;
558}
559
560static int
561rtw_chip_reset(struct rtw_softc *sc)
562{
563 struct rtw_regs *regs = &sc->sc_regs;
564 uint32_t tcr;
565
566 /* from Linux driver */
567 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 |
b5b6e4f4 568 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK);
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569
570 RTW_WRITE(regs, RTW_TCR, tcr);
571
572 RTW_WBW(regs, RTW_CR, RTW_TCR);
573
574 return rtw_chip_reset1(sc);
575}
576
577static int
578rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen)
579{
580 struct ieee80211_key keycopy;
581 const struct ieee80211_cipher *wep_cipher;
582
583 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__));
584
585 keycopy = *k;
586 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT;
587
588 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
589 KKASSERT(wep_cipher != NULL);
590
591 return wep_cipher->ic_decap(&keycopy, m, hdrlen);
592}
593
594static int
595rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
596{
597 struct rtw_softc *sc = ic->ic_ifp->if_softc;
598 u_int keyix = k->wk_keyix;
599
600 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix));
601
602 if (keyix >= IEEE80211_WEP_NKID)
603 return 0;
604 if (k->wk_keylen != 0)
605 sc->sc_flags &= ~RTW_F_DK_VALID;
606 return 1;
607}
608
609static int
610rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
611 const u_int8_t mac[IEEE80211_ADDR_LEN])
612{
613 struct rtw_softc *sc = ic->ic_ifp->if_softc;
614
615 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix));
616
617 if (k->wk_keyix >= IEEE80211_WEP_NKID)
618 return 0;
619
620 sc->sc_flags &= ~RTW_F_DK_VALID;
621 return 1;
622}
623
624static void
625rtw_key_update_begin(struct ieee80211com *ic)
626{
627#ifdef RTW_DEBUG
628 struct ifnet *ifp = ic->ic_ifp;
629 struct rtw_softc *sc = ifp->if_softc;
630#endif
631
632 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
633}
634
635static void
636rtw_key_update_end(struct ieee80211com *ic)
637{
638 struct ifnet *ifp = ic->ic_ifp;
639 struct rtw_softc *sc = ifp->if_softc;
640
641 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
642
643 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 ||
644 (sc->sc_flags & RTW_F_ENABLED) == 0 ||
645 (sc->sc_flags & RTW_F_INVALID) != 0)
646 return;
647
648 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
649 rtw_wep_setkeys(sc);
650 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE,
651 (ifp->if_flags & IFF_RUNNING) != 0);
652}
653
654static __inline int
655rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k)
656{
657 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
658 return 0;
659
660 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) ||
661 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13);
662}
663
664static void
665rtw_wep_setkeys(struct rtw_softc *sc)
666{
667 struct ieee80211com *ic = &sc->sc_ic;
668 struct ieee80211_key *wk = ic->ic_nw_keys;
669 const struct ieee80211_cipher *wep_cipher;
670 struct rtw_regs *regs = &sc->sc_regs;
671 union rtw_keys *rk = &sc->sc_keys;
672 uint8_t psr, scr;
673 int i, keylen;
674
675 memset(rk->rk_keys, 0, sizeof(rk->rk_keys));
676
677 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
678 KKASSERT(wep_cipher != NULL);
679
680 /* Temporarily use software crypto for all keys. */
681 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
682 if (wk[i].wk_cipher == &rtw_cipher_wep)
683 wk[i].wk_cipher = wep_cipher;
684 }
685
686 rtw_set_access(sc, RTW_ACCESS_CONFIG);
687
688 psr = RTW_READ8(regs, RTW_PSR);
689 scr = RTW_READ8(regs, RTW_SCR);
690 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON);
691
692 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
693 goto out;
694
695 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) {
696 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i]))
697 continue;
698 if (i == ic->ic_def_txkey) {
699 keylen = wk[i].wk_keylen;
700 break;
701 }
702 keylen = MAX(keylen, wk[i].wk_keylen);
703 }
704
705 if (keylen == 5)
706 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON;
707 else if (keylen == 13)
708 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON;
709
710 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
711 if (wk[i].wk_keylen != keylen ||
712 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
713 continue;
714 /* h/w will decrypt, s/w still strips headers */
715 wk[i].wk_cipher = &rtw_cipher_wep;
716 memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen);
717 }
718out:
719 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN);
720
721 bus_space_write_region_4(regs->r_bt, regs->r_bh, RTW_DK0, rk->rk_words,
722 sizeof(rk->rk_words) / sizeof(rk->rk_words[0]));
723
724 RTW_WBW(regs, RTW_DK0, RTW_PSR);
725 RTW_WRITE8(regs, RTW_PSR, psr);
726 RTW_WBW(regs, RTW_PSR, RTW_SCR);
727 RTW_WRITE8(regs, RTW_SCR, scr);
728 RTW_SYNC(regs, RTW_SCR, RTW_SCR);
729 rtw_set_access(sc, RTW_ACCESS_NONE);
730 sc->sc_flags |= RTW_F_DK_VALID;
731}
732
733static int
734rtw_recall_eeprom(struct rtw_softc *sc)
735{
736 struct rtw_regs *regs = &sc->sc_regs;
737 int i;
738 uint8_t ecr;
739
740 ecr = RTW_READ8(regs, RTW_9346CR);
741 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;
742 RTW_WRITE8(regs, RTW_9346CR, ecr);
743
744 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
745
746 /* wait 25ms for completion */
747 for (i = 0; i < 250; i++) {
748 ecr = RTW_READ8(regs, RTW_9346CR);
749 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {
750 RTW_DPRINTF(RTW_DEBUG_RESET,
751 ("%s: recall EEPROM in %dus\n",
752 sc->sc_ic.ic_if.if_xname, i * 100));
753 return 0;
754 }
755 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
756 DELAY(100);
757 }
758 if_printf(&sc->sc_ic.ic_if, "recall EEPROM failed\n");
759 return ETIMEDOUT;
760}
761
762static int
763rtw_reset(struct rtw_softc *sc)
764{
765 struct rtw_regs *regs = &sc->sc_regs;
766 uint8_t config1;
767 int rc;
768
769 sc->sc_flags &= ~RTW_F_DK_VALID;
770
771 rc = rtw_chip_reset(sc);
772 if (rc)
773 return rc;
774
775 rtw_recall_eeprom(sc); /* ignore err */
776
777 config1 = RTW_READ8(regs, RTW_CONFIG1);
778 RTW_WRITE8(regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN);
779 /* TBD turn off maximum power saving? */
780 return 0;
781}
782
783static int
784rtw_srom_parse(struct rtw_softc *sc)
785{
786 struct rtw_srom *sr = &sc->sc_srom;
787 char scratch[sizeof("unknown 0xXX")];
788 uint8_t mac[IEEE80211_ADDR_LEN];
789 const char *rfname, *paname;
790 uint16_t srom_version;
791 int i;
792
793 sc->sc_flags &= ~(RTW_F_DIGPHY | RTW_F_DFLANTB | RTW_F_ANTDIV);
794 sc->sc_rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
795
796 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION);
797 if_printf(&sc->sc_ic.ic_if, "SROM version %d.%d",
798 srom_version >> 8, srom_version & 0xff);
799
800 if (srom_version <= 0x0101) {
e3869ec7 801 kprintf(" is not understood, limping along with defaults\n");
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802
803 /* Default values */
804 sc->sc_flags |= (RTW_F_DIGPHY | RTW_F_ANTDIV);
805 sc->sc_csthr = RTW_SR_ENERGYDETTHR_DEFAULT;
806 sc->sc_rcr |= RTW_RCR_ENCS1;
807 sc->sc_rfchipid = RTW_RFCHIPID_PHILIPS;
808 return 0;
809 }
e3869ec7 810 kprintf("\n");
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811
812 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
813 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);
814
815 RTW_DPRINTF(RTW_DEBUG_ATTACH,
816 ("%s: EEPROM MAC %6D\n", sc->sc_ic.ic_if.if_xname, mac, ":"));
817
818 sc->sc_csthr = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);
819
820 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)
821 sc->sc_flags |= RTW_F_ANTDIV;
822
823 /*
824 * Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems
825 * to be reversed.
826 */
827 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)
828 sc->sc_flags |= RTW_F_DIGPHY;
829 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)
830 sc->sc_flags |= RTW_F_DFLANTB;
831
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832 sc->sc_rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
833 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);
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834
835 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0)
836 sc->sc_flags |= RTW_C_RXWEP_104;
837
838 sc->sc_flags |= RTW_C_RXWEP_40; /* XXX */
839
840 sc->sc_rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);
841 switch (sc->sc_rfchipid) {
842 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */
843 rfname = "GCT GRF5101";
844 paname = "Winspring WS9901";
845 break;
846 case RTW_RFCHIPID_MAXIM:
847 rfname = "Maxim MAX2820"; /* guess */
848 paname = "Maxim MAX2422"; /* guess */
849 break;
850 case RTW_RFCHIPID_INTERSIL:
851 rfname = "Intersil HFA3873"; /* guess */
852 paname = "Intersil <unknown>";
853 break;
854 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */
855 rfname = "Philips SA2400A";
856 paname = "Philips SA2411";
857 break;
858 case RTW_RFCHIPID_RFMD:
859 /* this is the same front-end as an atw(4)! */
860 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */
861 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */
862 "SYN: Silicon Labs Si4126"; /* inferred from
863 * reference driver
864 */
865 paname = "RFMD RF2189"; /* mentioned in Realtek docs */
866 break;
867 case RTW_RFCHIPID_RESERVED:
868 rfname = paname = "reserved";
869 break;
870 default:
f8c7a42d 871 ksnprintf(scratch, sizeof(scratch), "unknown 0x%02x",
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872 sc->sc_rfchipid);
873 rfname = paname = scratch;
874 }
875 if_printf(&sc->sc_ic.ic_if, "RF: %s, PA: %s\n", rfname, paname);
876
877 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {
878 case RTW_CONFIG0_GL_USA:
879 case _RTW_CONFIG0_GL_USA:
880 sc->sc_locale = RTW_LOCALE_USA;
881 break;
882 case RTW_CONFIG0_GL_EUROPE:
883 sc->sc_locale = RTW_LOCALE_EUROPE;
884 break;
885 case RTW_CONFIG0_GL_JAPAN:
886 sc->sc_locale = RTW_LOCALE_JAPAN;
887 break;
888 default:
889 sc->sc_locale = RTW_LOCALE_UNKNOWN;
890 break;
891 }
892 return 0;
893}
894
895static int
896rtw_srom_read(struct rtw_softc *sc)
897{
898 struct rtw_regs *regs = &sc->sc_regs;
899 struct rtw_srom *sr = &sc->sc_srom;
900 struct seeprom_descriptor sd;
901 uint8_t ecr;
902 int rc;
903
904 memset(&sd, 0, sizeof(sd));
905
906 ecr = RTW_READ8(regs, RTW_9346CR);
907
908 if ((sc->sc_flags & RTW_F_9356SROM) != 0) {
909 RTW_DPRINTF(RTW_DEBUG_ATTACH,
910 ("%s: 93c56 SROM\n", sc->sc_ic.ic_if.if_xname));
911 sr->sr_size = 256;
912 sd.sd_chip = C56_66;
913 } else {
914 RTW_DPRINTF(RTW_DEBUG_ATTACH,
915 ("%s: 93c46 SROM\n", sc->sc_ic.ic_if.if_xname));
916 sr->sr_size = 128;
917 sd.sd_chip = C46;
918 }
919
920 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
921 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
922 ecr |= RTW_9346CR_EEM_PROGRAM;
923
924 RTW_WRITE8(regs, RTW_9346CR, ecr);
925
efda3bd0 926 sr->sr_content = kmalloc(sr->sr_size, M_DEVBUF, M_WAITOK | M_ZERO);
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927
928 /*
929 * RTL8180 has a single 8-bit register for controlling the
930 * 93cx6 SROM. There is no "ready" bit. The RTL8180
931 * input/output sense is the reverse of read_seeprom's.
932 */
933 sd.sd_tag = regs->r_bt;
934 sd.sd_bsh = regs->r_bh;
935 sd.sd_regsize = 1;
936 sd.sd_control_offset = RTW_9346CR;
937 sd.sd_status_offset = RTW_9346CR;
938 sd.sd_dataout_offset = RTW_9346CR;
939 sd.sd_CK = RTW_9346CR_EESK;
940 sd.sd_CS = RTW_9346CR_EECS;
941 sd.sd_DI = RTW_9346CR_EEDO;
942 sd.sd_DO = RTW_9346CR_EEDI;
943 /* make read_seeprom enter EEPROM read/write mode */
944 sd.sd_MS = ecr;
945 sd.sd_RDY = 0;
946
947 /* TBD bus barriers */
948 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size / 2)) {
949 if_printf(&sc->sc_ic.ic_if, "could not read SROM\n");
efda3bd0 950 kfree(sr->sr_content, M_DEVBUF);
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951 sr->sr_content = NULL;
952 return EIO; /* XXX */
953 }
954
955 /* end EEPROM read/write mode */
956 RTW_WRITE8(regs, RTW_9346CR,
957 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);
958 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
959
960 rc = rtw_recall_eeprom(sc);
961 if (rc)
962 return rc;
963
964#ifdef RTW_DEBUG
965 {
966 int i;
967 RTW_DPRINTF(RTW_DEBUG_ATTACH,
968 ("\n%s: serial ROM:\n\t", sc->sc_ic.ic_if.if_xname));
969 for (i = 0; i < sr->sr_size/2; i++) {
970 if (((i % 8) == 0) && (i != 0))
971 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t"));
972 RTW_DPRINTF(RTW_DEBUG_ATTACH,
973 (" %04x", sr->sr_content[i]));
974 }
975 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n"));
976 }
977#endif /* RTW_DEBUG */
978 return 0;
979}
980
981static void
982rtw_set_rfprog(struct rtw_softc *sc)
983{
984 struct rtw_regs *regs = &sc->sc_regs;
985 const char *method;
986 uint8_t cfg4;
987
988 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
989
990 switch (sc->sc_rfchipid) {
991 default:
b5b6e4f4 992 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
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993 method = "fallback";
994 break;
995 case RTW_RFCHIPID_INTERSIL:
996 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;
997 method = "Intersil";
998 break;
999 case RTW_RFCHIPID_PHILIPS:
1000 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;
1001 method = "Philips";
1002 break;
1003 case RTW_RFCHIPID_GCT: /* XXX a guess */
1004 case RTW_RFCHIPID_RFMD:
1005 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;
1006 method = "RFMD";
1007 break;
1008 }
1009
1010 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
1011
1012 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
1013
1014 RTW_DPRINTF(RTW_DEBUG_INIT,
1015 ("%s: %s RF programming method, %#02x\n",
1016 sc->sc_ic.ic_if.if_xname, method,
1017 RTW_READ8(regs, RTW_CONFIG4)));
1018}
1019
1020static __inline void
1021rtw_init_channels(struct rtw_softc *sc)
1022{
1023 const char *name = NULL;
1024 struct ieee80211_channel *chans = sc->sc_ic.ic_channels;
1025 int i;
1026#define ADD_CHANNEL(_chans, _chan) do { \
1027 _chans[_chan].ic_flags = IEEE80211_CHAN_B; \
1028 _chans[_chan].ic_freq = \
1029 ieee80211_ieee2mhz(_chan, _chans[_chan].ic_flags); \
1030} while (0)
1031
1032 switch (sc->sc_locale) {
1033 case RTW_LOCALE_USA: /* 1-11 */
1034 name = "USA";
1035 for (i = 1; i <= 11; i++)
1036 ADD_CHANNEL(chans, i);
1037 break;
1038 case RTW_LOCALE_JAPAN: /* 1-14 */
1039 name = "Japan";
1040 ADD_CHANNEL(chans, 14);
1041 for (i = 1; i <= 14; i++)
1042 ADD_CHANNEL(chans, i);
1043 break;
1044 case RTW_LOCALE_EUROPE: /* 1-13 */
1045 name = "Europe";
1046 for (i = 1; i <= 13; i++)
1047 ADD_CHANNEL(chans, i);
1048 break;
1049 default: /* 10-11 allowed by most countries */
1050 name = "<unknown>";
1051 for (i = 10; i <= 11; i++)
1052 ADD_CHANNEL(chans, i);
1053 break;
1054 }
1055 if_printf(&sc->sc_ic.ic_if, "Geographic Location %s\n", name);
1056#undef ADD_CHANNEL
1057}
1058
1059
1060static void
1061rtw_identify_country(struct rtw_softc *sc)
1062{
1063 uint8_t cfg0;
1064
1065 cfg0 = RTW_READ8(&sc->sc_regs, RTW_CONFIG0);
1066 switch (cfg0 & RTW_CONFIG0_GL_MASK) {
1067 case RTW_CONFIG0_GL_USA:
1068 case _RTW_CONFIG0_GL_USA:
1069 sc->sc_locale = RTW_LOCALE_USA;
1070 break;
1071 case RTW_CONFIG0_GL_JAPAN:
1072 sc->sc_locale = RTW_LOCALE_JAPAN;
1073 break;
1074 case RTW_CONFIG0_GL_EUROPE:
1075 sc->sc_locale = RTW_LOCALE_EUROPE;
1076 break;
1077 default:
1078 sc->sc_locale = RTW_LOCALE_UNKNOWN;
1079 break;
1080 }
1081}
1082
1083static int
1084rtw_identify_sta(struct rtw_softc *sc)
1085{
1086 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
1087 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1088 };
1089 struct rtw_regs *regs = &sc->sc_regs;
1090 uint8_t *addr = sc->sc_ic.ic_myaddr;
1091 uint32_t idr0, idr1;
1092
1093 idr0 = RTW_READ(regs, RTW_IDR0);
1094 idr1 = RTW_READ(regs, RTW_IDR1);
1095
b5b6e4f4
SZ
1096 addr[0] = __SHIFTOUT(idr0, __BITS(0, 7));
1097 addr[1] = __SHIFTOUT(idr0, __BITS(8, 15));
1098 addr[2] = __SHIFTOUT(idr0, __BITS(16, 23));
1099 addr[3] = __SHIFTOUT(idr0, __BITS(24 ,31));
44db266b 1100
b5b6e4f4
SZ
1101 addr[4] = __SHIFTOUT(idr1, __BITS(0, 7));
1102 addr[5] = __SHIFTOUT(idr1, __BITS(8, 15));
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1103
1104 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) {
1105 if_printf(&sc->sc_ic.ic_if, "could not get mac address\n");
1106 return ENXIO;
1107 }
1108 return 0;
1109}
1110
1111static uint8_t
1112rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,
1113 struct ieee80211_channel *chan)
1114{
1115 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;
1116
1117 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14,
1118 ("%s: channel %d out of range", __func__,
1119 idx - RTW_SR_TXPOWER1 + 1));
1120 return RTW_SR_GET(sr, idx);
1121}
1122
1123static void
1124rtw_txdesc_blk_init_all(struct rtw_softc *sc)
1125{
1126 /* nfree: the number of free descriptors in each ring.
1127 * The beacon ring is a special case: I do not let the
1128 * driver use all of the descriptors on the beacon ring.
1129 * The reasons are two-fold:
1130 *
1131 * (1) A BEACON descriptor's OWN bit is (apparently) not
1132 * updated, so the driver cannot easily know if the descriptor
1133 * belongs to it, or if it is racing the NIC. If the NIC
1134 * does not OWN every descriptor, then the driver can safely
1135 * update the descriptors when RTW_TBDA points at tdb_next.
1136 *
1137 * (2) I hope that the NIC will process more than one BEACON
1138 * descriptor in a single beacon interval, since that will
1139 * enable multiple-BSS support. Since the NIC does not
1140 * clear the OWN bit, there is no natural place for it to
1141 * stop processing BEACON desciptors. Maybe it will *not*
1142 * stop processing them! I do not want to chance the NIC
1143 * looping around and around a saturated beacon ring, so
1144 * I will leave one descriptor unOWNed at all times.
1145 */
1146 int nfree[RTW_NTXPRI] = {
1147 RTW_NTXDESCLO,
1148 RTW_NTXDESCMD,
1149 RTW_NTXDESCHI,
1150 RTW_NTXDESCBCN - 1
1151 };
1152 struct rtw_txdesc_blk *tdb;
1153 int pri;
1154
1155 for (tdb = sc->sc_txdesc_blk, pri = 0; pri < RTW_NTXPRI; tdb++, pri++) {
1156 tdb->tdb_nfree = nfree[pri];
1157 tdb->tdb_next = 0;
1158
1159 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1160 BUS_DMASYNC_PREWRITE);
1161 }
1162}
1163
1164static void
1165rtw_txsoft_blk_init_all(struct rtw_softc *sc)
1166{
1167 struct rtw_txsoft_blk *tsb;
1168 int pri;
1169
1170 for (tsb = sc->sc_txsoft_blk, pri = 0; pri < RTW_NTXPRI; tsb++, pri++) {
1171 int i;
1172
1173 STAILQ_INIT(&tsb->tsb_dirtyq);
1174 STAILQ_INIT(&tsb->tsb_freeq);
1175 for (i = 0; i < tsb->tsb_ndesc; i++) {
1176 struct rtw_txsoft *ts;
1177
1178 ts = &tsb->tsb_desc[i];
1179 ts->ts_mbuf = NULL;
1180 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1181 }
1182 tsb->tsb_tx_timer = 0;
1183 }
1184}
1185
1186static void
1187rtw_rxbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
1188 bus_size_t mapsize, int error)
1189{
1190 if (error)
1191 return;
1192
1193 KASSERT(nseg == 1, ("too many rx mbuf seg\n"));
1194
1195 *((bus_addr_t *)arg) = seg->ds_addr;
1196}
1197
1198static int
1199rtw_rxsoft_alloc(struct rtw_softc *sc, struct rtw_rxsoft *rs, int waitok)
1200{
1201 bus_addr_t paddr;
1202 bus_dmamap_t map;
1203 struct mbuf *m;
1204 int rc;
1205
1206 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1207 if (m == NULL)
1208 return ENOBUFS;
1209
1210 m->m_pkthdr.len = m->m_len = MCLBYTES;
1211
1212 rc = bus_dmamap_load_mbuf(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap, m,
1213 rtw_rxbuf_dma_map, &paddr,
1214 waitok ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1215 if (rc) {
1216 if_printf(&sc->sc_ic.ic_if, "can't load rx mbuf\n");
1217 m_freem(m);
1218 return rc;
1219 }
1220
1221 if (rs->rs_mbuf != NULL)
1222 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
1223
1224 /* Swap DMA map */
1225 map = rs->rs_dmamap;
1226 rs->rs_dmamap = sc->sc_rxsoft_dmamap;
1227 sc->sc_rxsoft_dmamap = map;
1228
1229 rs->rs_mbuf = m;
1230 rs->rs_phyaddr = paddr;
1231
1232 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap, BUS_DMASYNC_PREREAD);
1233 return 0;
1234}
1235
1236static int
1237rtw_rxsoft_blk_init_all(struct rtw_softc *sc)
1238{
1239 int i, rc = 0;
1240
1241 for (i = 0; i < RTW_RXQLEN; i++) {
1242 struct rtw_rxsoft *rs;
1243
1244 rs = &sc->sc_rxsoft[i];
1245 /* we're in rtw_init, so there should be no mbufs allocated */
1246 KKASSERT(rs->rs_mbuf == NULL);
1247#ifdef RTW_DEBUG
1248 if (i == rtw_rxbufs_limit) {
1249 if_printf(&sc->sc_ic.ic_if,
1250 "TEST hit %d-buffer limit\n", i);
1251 rc = ENOBUFS;
1252 break;
1253 }
1254#endif /* RTW_DEBUG */
1255 rc = rtw_rxsoft_alloc(sc, rs, 1);
1256 if (rc)
1257 break;
1258 }
1259 return rc;
1260}
1261
1262static void
1263rtw_rxdesc_init(struct rtw_softc *sc, int idx, int kick)
1264{
1265 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1266 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx];
1267 struct rtw_rxsoft *rs = &sc->sc_rxsoft[idx];
1268 uint32_t ctl;
1269
1270#ifdef RTW_DEBUG
1271 uint32_t octl, obuf;
1272
1273 obuf = rd->rd_buf;
1274 octl = rd->rd_ctl;
1275#endif /* RTW_DEBUG */
1276
1277 rd->rd_buf = htole32(rs->rs_phyaddr);
1278
b5b6e4f4 1279 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
44db266b
SZ
1280 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS;
1281
1282 if (idx == rdb->rdb_ndesc - 1)
1283 ctl |= RTW_RXCTL_EOR;
1284
1285 rd->rd_ctl = htole32(ctl);
1286
1287 RTW_DPRINTF(kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK)
1288 : RTW_DEBUG_RECV_DESC,
1289 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n",
1290 sc->sc_ic.ic_if.if_xname, rd, le32toh(obuf),
1291 le32toh(rd->rd_buf), le32toh(octl), le32toh(rd->rd_ctl)));
1292}
1293
1294static void
1295rtw_rxdesc_blk_init_all(struct rtw_softc *sc)
1296{
1297 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1298 int i;
1299
1300 for (i = 0; i < rdb->rdb_ndesc; i++)
1301 rtw_rxdesc_init(sc, i, 1);
1302
1303 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_PREWRITE);
1304}
1305
1306static void
1307rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable)
1308{
1309 struct rtw_regs *regs = &sc->sc_regs;
1310 uint8_t cr;
1311
1312 RTW_DPRINTF(RTW_DEBUG_IOSTATE,
1313 ("%s: %s 0x%02x\n", sc->sc_ic.ic_if.if_xname,
1314 enable ? "enable" : "disable", flags));
1315
1316 cr = RTW_READ8(regs, RTW_CR);
1317
1318 /* XXX reference source does not enable MULRW */
1319#if 0
1320 /* enable PCI Read/Write Multiple */
1321 cr |= RTW_CR_MULRW;
1322#endif
1323
1324 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
1325 if (enable)
1326 cr |= flags;
1327 else
1328 cr &= ~flags;
1329 RTW_WRITE8(regs, RTW_CR, cr);
1330 RTW_SYNC(regs, RTW_CR, RTW_CR);
1331}
1332
1333static void
1334rtw_intr_rx(struct rtw_softc *sc, uint16_t isr)
1335{
1336#define IS_BEACON(__fc0) \
1337 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\
1338 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON))
1339
1340 /*
1341 * convert rates:
1342 * hardware -> net80211
1343 */
1344 static const int ratetbl[4] = { 2, 4, 11, 22 };
1345 struct ifnet *ifp = &sc->sc_if;
1346 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1347 int next, nproc = 0, sync = 0;
1348
1349 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1350
1351 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_POSTREAD);
1352
1353 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) {
1354 struct ieee80211_node *ni;
1355 struct ieee80211_frame_min *wh;
1356 struct rtw_rxdesc *rd;
1357 struct rtw_rxsoft *rs;
1358 struct mbuf *m;
1359 int hwrate, len, rate, rssi, sq, error;
1360 uint32_t hrssi, hstat, htsfth, htsftl;
1361
1362 rd = &rdb->rdb_desc[next];
1363 rs = &sc->sc_rxsoft[next];
1364
1365 hstat = le32toh(rd->rd_stat);
1366 hrssi = le32toh(rd->rd_rssi);
1367 htsfth = le32toh(rd->rd_tsfth);
1368 htsftl = le32toh(rd->rd_tsftl);
1369
1370 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1371 ("%s: rxdesc[%d] hstat %08x hrssi %08x "
1372 "htsft %08x%08x\n", ifp->if_xname,
1373 next, hstat, hrssi, htsfth, htsftl));
1374
1375 ++nproc;
1376
1377 /* still belongs to NIC */
1378 if (hstat & RTW_RXSTAT_OWN) {
1379 if (nproc > 1)
1380 break;
1381
1382 /* sometimes the NIC skips to the 0th descriptor */
1383 rd = &rdb->rdb_desc[0];
1384 if (rd->rd_stat & htole32(RTW_RXSTAT_OWN))
1385 break;
1386 RTW_DPRINTF(RTW_DEBUG_BUGS,
1387 ("%s: NIC skipped from rxdesc[%u] "
1388 "to rxdesc[0]\n", ifp->if_xname, next));
1389 next = rdb->rdb_ndesc - 1;
1390 continue;
1391 }
1392
1393#ifdef RTW_DEBUG
1394#define PRINTSTAT(flag) do { \
1395 if ((hstat & flag) != 0) { \
e3869ec7 1396 kprintf("%s" #flag, delim); \
44db266b
SZ
1397 delim = ","; \
1398 } \
1399} while (0)
1400 if (rtw_debug & RTW_DEBUG_RECV_DESC) {
1401 const char *delim = "<";
1402
1403 if_printf(ifp, "%s", "");
1404 if ((hstat & RTW_RXSTAT_DEBUG) != 0) {
e3869ec7 1405 kprintf("status %08x", hstat);
44db266b
SZ
1406 PRINTSTAT(RTW_RXSTAT_SPLCP);
1407 PRINTSTAT(RTW_RXSTAT_MAR);
1408 PRINTSTAT(RTW_RXSTAT_PAR);
1409 PRINTSTAT(RTW_RXSTAT_BAR);
1410 PRINTSTAT(RTW_RXSTAT_PWRMGT);
1411 PRINTSTAT(RTW_RXSTAT_CRC32);
1412 PRINTSTAT(RTW_RXSTAT_ICV);
e3869ec7 1413 kprintf(">, ");
44db266b
SZ
1414 }
1415 }
1416#endif /* RTW_DEBUG */
1417
1418 if (hstat & RTW_RXSTAT_IOERROR) {
1419 if_printf(ifp, "DMA error/FIFO overflow %08x, "
1420 "rx descriptor %d\n",
1421 hstat & RTW_RXSTAT_IOERROR, next);
1422 ifp->if_ierrors++;
1423 goto next;
1424 }
1425
b5b6e4f4 1426 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);
44db266b
SZ
1427 if (len < IEEE80211_MIN_LEN) {
1428 sc->sc_ic.ic_stats.is_rx_tooshort++;
1429 goto next;
1430 }
1431
1432 /* CRC is included with the packet; trim it off. */
1433 len -= IEEE80211_CRC_LEN;
1434
b5b6e4f4 1435 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);
44db266b
SZ
1436 if (hwrate >= sizeof(ratetbl) / sizeof(ratetbl[0])) {
1437 if_printf(ifp, "unknown rate #%d\n",
b5b6e4f4 1438 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));
44db266b
SZ
1439 ifp->if_ierrors++;
1440 goto next;
1441 }
1442 rate = ratetbl[hwrate];
1443
1444#ifdef RTW_DEBUG
1445 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1446 ("%s rate %d.%d Mb/s, time %08x%08x\n",
1447 ifp->if_xname, (rate * 5) / 10,
1448 (rate * 5) % 10, htsfth, htsftl));
1449#endif /* RTW_DEBUG */
1450
1451 if ((hstat & RTW_RXSTAT_RES) &&
1452 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
1453 goto next;
1454
1455 /* if bad flags, skip descriptor */
1456 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) {
1457 if_printf(ifp, "too many rx segments\n");
1458 goto next;
1459 }
1460
1461 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
1462 BUS_DMASYNC_POSTREAD);
1463
1464 m = rs->rs_mbuf;
1465
1466 /* if temporarily out of memory, re-use mbuf */
1467 error = rtw_rxsoft_alloc(sc, rs, 0);
1468 if (error) {
1469 if_printf(ifp, "%s: rtw_rxsoft_alloc(, %d) failed, "
1470 "dropping packet\n", ifp->if_xname, next);
1471 goto next;
1472 }
1473
b5b6e4f4
SZ
1474 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_RSSI);
1475 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ);
44db266b 1476
dcb7b49c
SZ
1477 rssi = rtw_get_rssi(sc, rssi, sq);
1478
44db266b
SZ
1479 /*
1480 * Note well: now we cannot recycle the rs_mbuf unless
1481 * we restore its original length.
1482 */
1483 m->m_pkthdr.rcvif = ifp;
1484 m->m_pkthdr.len = m->m_len = len;
1485
1486 wh = mtod(m, struct ieee80211_frame_min *);
1487
1488 if (!IS_BEACON(wh->i_fc[0]))
1489 sc->sc_led_state.ls_event |= RTW_LED_S_RX;
1490
1491 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */
1492 ni = ieee80211_find_rxnode(&sc->sc_ic, wh);
1493
1494 sc->sc_tsfth = htsfth;
1495
1496#ifdef RTW_DEBUG
1497 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
1498 (IFF_DEBUG | IFF_LINK2)) {
1499 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len,
1500 rate, rssi);
1501 }
1502#endif /* RTW_DEBUG */
1503
1504 if (sc->sc_radiobpf != NULL) {
1505 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
1506
1507 rr->rr_tsft =
1508 htole64(((uint64_t)htsfth << 32) | htsftl);
1509
1510 if ((hstat & RTW_RXSTAT_SPLCP) != 0)
1511 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE;
1512
1513 rr->rr_flags = 0;
1514 rr->rr_rate = rate;
1515 rr->rr_antsignal = rssi;
1516 rr->rr_barker_lock = htole16(sq);
1517
1518 bpf_ptap(sc->sc_radiobpf, m, rr, sizeof(sc->sc_rxtapu));
1519 }
1520
1521 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl);
1522 ieee80211_free_node(ni);
1523next:
1524 rtw_rxdesc_init(sc, next, 0);
1525 sync = 1;
1526 }
1527
1528 if (sync) {
1529 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1530 BUS_DMASYNC_PREWRITE);
1531 }
1532
1533 rdb->rdb_next = next;
1534 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1535#undef IS_BEACON
1536}
1537
1538static __inline void
1539rtw_txsoft_release(bus_dma_tag_t dmat, struct rtw_txsoft *ts,
1540 int data_retry, int rts_retry, int error, int ratectl)
1541{
1542 struct mbuf *m;
1543 struct ieee80211_node *ni;
1544
1545 if (!ts->ts_ratectl)
1546 ratectl = 0;
1547
1548 m = ts->ts_mbuf;
1549 ni = ts->ts_ni;
1550 KKASSERT(m != NULL);
1551 KKASSERT(ni != NULL);
1552 ts->ts_mbuf = NULL;
1553 ts->ts_ni = NULL;
1554
1555 if (ratectl) {
1556 struct ieee80211_ratectl_res rc_res;
1557
1558 rc_res.rc_res_rateidx = ts->ts_rateidx;
dcbaea21 1559 rc_res.rc_res_tries = data_retry + 1;
44db266b
SZ
1560
1561 ieee80211_ratectl_tx_complete(ni, m->m_pkthdr.len,
1562 &rc_res, 1,
1563 data_retry, rts_retry,
1564 error);
1565 }
1566
1567 bus_dmamap_sync(dmat, ts->ts_dmamap, BUS_DMASYNC_POSTWRITE);
1568 bus_dmamap_unload(dmat, ts->ts_dmamap);
1569 m_freem(m);
1570 ieee80211_free_node(ni);
1571}
1572
1573static __inline void
1574rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb,
1575 struct rtw_txsoft *ts, int ndesc)
1576{
1577 uint32_t hstat;
1578 int data_retry, rts_retry, error;
1579 struct rtw_txdesc *tdn;
1580 const char *condstring;
1581 struct ifnet *ifp = &sc->sc_if;
1582
1583 tdb->tdb_nfree += ndesc;
1584
1585 tdn = &tdb->tdb_desc[ts->ts_last];
1586
1587 hstat = le32toh(tdn->td_stat);
b5b6e4f4
SZ
1588 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);
1589 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);
44db266b
SZ
1590
1591 ifp->if_collisions += rts_retry + data_retry;
1592
1593 if ((hstat & RTW_TXSTAT_TOK) != 0) {
1594 condstring = "ok";
1595 error = 0;
1596 } else {
1597 ifp->if_oerrors++;
1598 condstring = "error";
1599 error = 1;
1600 }
1601
1602 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, data_retry, rts_retry,
1603 error, 1);
1604
1605 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
1606 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n",
1607 ifp->if_xname, ts, ts->ts_first, ts->ts_last,
1608 condstring, rts_retry, data_retry));
1609}
1610
1611static void
1612rtw_reset_oactive(struct rtw_softc *sc)
1613{
1614 int pri;
1615#ifdef RTW_DEBUG
1616 short oflags = sc->sc_if.if_flags;
1617#endif
1618
1619 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1620 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
1621 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1622
1623 if (!STAILQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0)
1624 sc->sc_if.if_flags &= ~IFF_OACTIVE;
1625 }
1626
1627#ifdef RTW_DEBUG
1628 if (oflags != sc->sc_if.if_flags) {
1629 DPRINTF(sc, RTW_DEBUG_OACTIVE,
1630 ("%s: reset OACTIVE\n", sc->sc_ic.ic_if.if_xname));
1631 }
1632#endif
1633}
1634
1635/* Collect transmitted packets. */
1636static __inline void
1637rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb,
1638 struct rtw_txdesc_blk *tdb, int force)
1639{
1640 struct rtw_txsoft *ts;
1641 int ndesc;
1642
1643 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1644 ndesc = 1 + ts->ts_last - ts->ts_first;
1645 if (ts->ts_last < ts->ts_first)
1646 ndesc += tdb->tdb_ndesc;
1647
1648 KKASSERT(ndesc > 0);
1649
1650 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1651 BUS_DMASYNC_POSTREAD);
1652
1653 if (force) {
1654 int i;
1655
1656 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) {
1657 tdb->tdb_desc[i].td_stat &=
1658 ~htole32(RTW_TXSTAT_OWN);
1659 if (i == ts->ts_last)
1660 break;
1661 }
1662 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1663 BUS_DMASYNC_PREWRITE);
1664 } else if ((tdb->tdb_desc[ts->ts_last].td_stat &
1665 htole32(RTW_TXSTAT_OWN)) != 0) {
1666 break;
1667 }
1668
1669 rtw_collect_txpkt(sc, tdb, ts, ndesc);
1670 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1671 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1672 }
1673 /* no more pending transmissions, cancel watchdog */
1674 if (ts == NULL)
1675 tsb->tsb_tx_timer = 0;
1676 rtw_reset_oactive(sc);
1677}
1678
1679static void
1680rtw_intr_tx(struct rtw_softc *sc, uint16_t isr)
1681{
1682 int pri;
1683
1684 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1685 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1686 &sc->sc_txdesc_blk[pri], 0);
1687 }
1688 if (isr)
1689 rtw_start(&sc->sc_ic.ic_if);
1690}
1691
1692static __inline struct mbuf *
1693rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni)
1694{
1695 struct ieee80211com *ic = &sc->sc_ic;
1696 struct ieee80211_beacon_offsets boff;
1697 struct mbuf *m;
1698
1699 m = ieee80211_beacon_alloc(ic, ni, &boff);
1700 if (m != NULL) {
1701 RTW_DPRINTF(RTW_DEBUG_BEACON,
1702 ("%s: m %p len %u\n", ic->ic_if.if_xname, m,
1703 m->m_len));
1704 }
1705 return m;
1706}
1707
1708static void
1709rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr)
1710{
1711 struct ieee80211com *ic = &sc->sc_ic;
1712 struct rtw_regs *regs = &sc->sc_regs;
1713 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN];
1714 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN];
1715
1716#ifdef RTW_DEBUG
1717 uint32_t tsfth, tsftl;
1718
1719 tsfth = RTW_READ(regs, RTW_TSFTRH);
1720 tsftl = RTW_READ(regs, RTW_TSFTRL);
1721#endif
1722
1723 if (isr & (RTW_INTR_TBDOK | RTW_INTR_TBDER)) {
1724#ifdef RTW_DEBUG
1725 int next = rtw_txring_next(regs, tdb);
1726#endif
1727
1728 RTW_DPRINTF(RTW_DEBUG_BEACON,
1729 ("%s: beacon ring %sprocessed, "
1730 "isr = %#04x, next %d expected %d, %llu\n",
1731 ic->ic_if.if_xname,
1732 (next == tdb->tdb_next) ? "" : "un",
1733 isr, next, tdb->tdb_next,
1734 (uint64_t)tsfth << 32 | tsftl));
1735
1736 if ((RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){
1737 rtw_collect_txring(sc, tsb, tdb, 1);
1738 tdb->tdb_next = 0;
1739 }
1740 }
1741 /* Start beacon transmission. */
1742
1743 if ((isr & RTW_INTR_BCNINT) && ic->ic_state == IEEE80211_S_RUN &&
1744 STAILQ_EMPTY(&tsb->tsb_dirtyq)) {
1745 struct mbuf *m;
1746
1747 RTW_DPRINTF(RTW_DEBUG_BEACON,
1748 ("%s: beacon prep. time, isr = %#04x, %llu\n",
1749 ic->ic_if.if_xname, isr,
1750 (uint64_t)tsfth << 32 | tsftl));
1751
1752 m = rtw_beacon_alloc(sc, ic->ic_bss);
1753 if (m == NULL) {
1754 if_printf(&ic->ic_if, "could not allocate beacon\n");
1755 return;
1756 }
1757
1758 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss);
1759
1760 IF_ENQUEUE(&sc->sc_beaconq, m);
1761
1762 rtw_start(&ic->ic_if);
1763 }
1764}
1765
1766static void
1767rtw_intr_atim(struct rtw_softc *sc)
1768{
1769 /* TBD */
1770 return;
1771}
1772
1773#ifdef RTW_DEBUG
1774static void
1775rtw_dump_rings(struct rtw_softc *sc)
1776{
1777 struct rtw_rxdesc_blk *rdb;
1778 int desc, pri;
1779
1780 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0)
1781 return;
1782
1783 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1784 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1785
1786 if_printf(&sc->sc_ic.ic_if, "txpri %d ndesc %d nfree %d\n",
1787 pri, tdb->tdb_ndesc, tdb->tdb_nfree);
1788 for (desc = 0; desc < tdb->tdb_ndesc; desc++)
1789 rtw_print_txdesc(sc, ".", NULL, tdb, desc);
1790 }
1791
1792 rdb = &sc->sc_rxdesc_blk;
1793
1794 for (desc = 0; desc < RTW_RXQLEN; desc++) {
1795 struct rtw_rxdesc *rd = &rdb->rdb_desc[desc];
1796
1797 if_printf(&sc->sc_ic.ic_if,
1798 "%sctl %08x rsvd0/rssi %08x buf/tsftl %08x "
1799 "rsvd1/tsfth %08x\n",
1800 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "",
1801 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi),
1802 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth));
1803 }
1804}
1805#endif /* RTW_DEBUG */
1806
1807static void
1808rtw_hwring_setup(struct rtw_softc *sc)
1809{
1810 struct rtw_regs *regs = &sc->sc_regs;
1811 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1812 int pri;
1813
1814 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1815 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1816
1817 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
1818 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC,
1819 ("%s: reg[tdb->tdb_basereg] <- %u\n",
1820 sc->sc_ic.ic_if.if_xname, tdb->tdb_base));
1821 }
1822
1823 RTW_WRITE(regs, RTW_RDSAR, rdb->rdb_base);
1824 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1825 ("%s: reg[RDSAR] <- %u\n", sc->sc_ic.ic_if.if_xname,
1826 rdb->rdb_base));
1827
1828 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
1829}
1830
1831static int
1832rtw_swring_setup(struct rtw_softc *sc)
1833{
1834 int rc;
1835
1836 rtw_txdesc_blk_init_all(sc);
1837 rtw_txsoft_blk_init_all(sc);
1838
1839 rc = rtw_rxsoft_blk_init_all(sc);
1840 if (rc) {
1841 if_printf(&sc->sc_ic.ic_if, "could not allocate rx buffers\n");
1842 return rc;
1843 }
1844
1845 rtw_rxdesc_blk_init_all(sc);
1846 sc->sc_rxdesc_blk.rdb_next = 0;
1847 return 0;
1848}
1849
1850static int
1851rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
1852{
1853 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
1854 sizeof(struct rtw_txdesc);
1855}
1856
1857static void
1858rtw_txring_fixup(struct rtw_softc *sc)
1859{
1860 struct rtw_regs *regs = &sc->sc_regs;
1861 int pri;
1862
1863 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1864 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1865 int next;
1866
1867 next = rtw_txring_next(regs, tdb);
1868 if (tdb->tdb_next == next)
1869 continue;
1870 if_printf(&sc->sc_ic.ic_if,
1871 "tx-ring %d expected next %d, read %d\n",
1872 pri, tdb->tdb_next, next);
1873 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1);
1874 }
1875}
1876
1877static void
1878rtw_rxring_fixup(struct rtw_softc *sc)
1879{
1880 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1881 uint32_t rdsar;
1882 int next;
1883
1884 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR));
1885 next = (rdsar - rdb->rdb_base) / sizeof(struct rtw_rxdesc);
1886
1887 if (rdb->rdb_next != next) {
1888 if_printf(&sc->sc_ic.ic_if,
1889 "rx-ring expected next %d, read %d\n",
1890 rdb->rdb_next, next);
1891 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1);
1892 }
1893}
1894
1895static void
1896rtw_txdesc_blk_reset_all(struct rtw_softc *sc)
1897{
1898 int pri;
1899
1900 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1901 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1902 &sc->sc_txdesc_blk[pri], 1);
1903 }
1904}
1905
1906static void
1907rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr)
1908{
1909 struct rtw_regs *regs = &sc->sc_regs;
1910 int xmtr = 0, rcvr = 0;
1911 uint8_t cr = 0;
1912
1913 if (isr & RTW_INTR_TXFOVW) {
1914 if_printf(&sc->sc_ic.ic_if, "tx fifo underflow\n");
1915 rcvr = xmtr = 1;
1916 cr |= RTW_CR_TE | RTW_CR_RE;
1917 }
1918
1919 if (isr & (RTW_INTR_RDU | RTW_INTR_RXFOVW)) {
1920 cr |= RTW_CR_RE;
1921 rcvr = 1;
1922 }
1923
1924 RTW_DPRINTF(RTW_DEBUG_BUGS,
1925 ("%s: restarting xmit/recv, isr %04x\n",
1926 sc->sc_ic.ic_if.if_xname, isr));
1927
1928#ifdef RTW_DEBUG
1929 rtw_dump_rings(sc);
1930#endif /* RTW_DEBUG */
1931
1932 rtw_io_enable(sc, cr, 0);
1933
1934 /* Collect rx'd packets. Refresh rx buffers. */
1935 if (rcvr)
1936 rtw_intr_rx(sc, 0);
1937
1938 /*
1939 * Collect tx'd packets.
1940 * XXX let's hope this stops the transmit timeouts.
1941 */
1942 if (xmtr)
1943 rtw_txdesc_blk_reset_all(sc);
1944
1945 RTW_WRITE16(regs, RTW_IMR, 0);
1946 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1947
1948 if (rtw_do_chip_reset) {
1949 rtw_chip_reset1(sc);
1950 rtw_wep_setkeys(sc);
1951 }
1952
1953 rtw_rxdesc_blk_init_all(sc);
1954
1955#ifdef RTW_DEBUG
1956 rtw_dump_rings(sc);
1957#endif /* RTW_DEBUG */
1958
1959 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
1960 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1961
1962 if (rcvr)
1963 rtw_rxring_fixup(sc);
1964
1965 rtw_io_enable(sc, cr, 1);
1966
1967 if (xmtr)
1968 rtw_txring_fixup(sc);
1969}
1970
1971static __inline void
1972rtw_suspend_ticks(struct rtw_softc *sc)
1973{
1974 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1975 ("%s: suspending ticks\n", sc->sc_ic.ic_if.if_xname));
1976 sc->sc_do_tick = 0;
1977}
1978
1979static void
1980rtw_resume_ticks(struct rtw_softc *sc)
1981{
1982 uint32_t tsftrl0, tsftrl1, next_tick;
1983 struct rtw_regs *regs = &sc->sc_regs;
1984
1985 tsftrl0 = RTW_READ(regs, RTW_TSFTRL);
1986
1987 tsftrl1 = RTW_READ(regs, RTW_TSFTRL);
1988 next_tick = tsftrl1 + 1000000;
1989 RTW_WRITE(regs, RTW_TINT, next_tick);
1990
1991 sc->sc_do_tick = 1;
1992
1993 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1994 ("%s: resume ticks delta %#08x now %#08x next %#08x\n",
1995 sc->sc_ic.ic_if.if_xname, tsftrl1 - tsftrl0, tsftrl1,
1996 next_tick));
1997}
1998
1999static void
2000rtw_intr_timeout(struct rtw_softc *sc)
2001{
2002 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
2003 ("%s: timeout\n", sc->sc_ic.ic_if.if_xname));
2004 if (sc->sc_do_tick)
2005 rtw_resume_ticks(sc);
2006}
2007
2008static void
2009rtw_intr(void *arg)
2010{
2011 struct rtw_softc *sc = arg;
2012 struct rtw_regs *regs = &sc->sc_regs;
2013 struct ifnet *ifp = &sc->sc_if;
2014 int i;
2015
2016 /*
2017 * If the interface isn't running, the interrupt couldn't
2018 * possibly have come from us.
2019 */
2020 if ((sc->sc_flags & RTW_F_ENABLED) == 0 ||
2021 (ifp->if_flags & IFF_RUNNING) == 0) {
2022 RTW_DPRINTF(RTW_DEBUG_INTR,
2023 ("%s: stray interrupt\n", ifp->if_xname));
2024 return;
2025 }
2026
2027 for (i = 0; i < 10; i++) {
2028 uint16_t isr;
2029
2030 isr = RTW_READ16(regs, RTW_ISR);
2031
2032 RTW_WRITE16(regs, RTW_ISR, isr);
2033 RTW_WBR(regs, RTW_ISR, RTW_ISR);
2034
2035 if (sc->sc_intr_ack != NULL)
2036 sc->sc_intr_ack(regs);
2037
2038 if (isr == 0)
2039 break;
2040
2041#ifdef RTW_DEBUG
2042#define PRINTINTR(flag) do { \
2043 if ((isr & flag) != 0) { \
e3869ec7 2044 kprintf("%s" #flag, delim); \
44db266b
SZ
2045 delim = ","; \
2046 } \
2047} while (0)
2048
2049 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) {
2050 const char *delim = "<";
2051
2052 if_printf(ifp, "reg[ISR] = %x", isr);
2053
2054 PRINTINTR(RTW_INTR_TXFOVW);
2055 PRINTINTR(RTW_INTR_TIMEOUT);
2056 PRINTINTR(RTW_INTR_BCNINT);
2057 PRINTINTR(RTW_INTR_ATIMINT);
2058 PRINTINTR(RTW_INTR_TBDER);
2059 PRINTINTR(RTW_INTR_TBDOK);
2060 PRINTINTR(RTW_INTR_THPDER);
2061 PRINTINTR(RTW_INTR_THPDOK);
2062 PRINTINTR(RTW_INTR_TNPDER);
2063 PRINTINTR(RTW_INTR_TNPDOK);
2064 PRINTINTR(RTW_INTR_RXFOVW);
2065 PRINTINTR(RTW_INTR_RDU);
2066 PRINTINTR(RTW_INTR_TLPDER);
2067 PRINTINTR(RTW_INTR_TLPDOK);
2068 PRINTINTR(RTW_INTR_RER);
2069 PRINTINTR(RTW_INTR_ROK);
2070
e3869ec7 2071 kprintf(">\n");
44db266b
SZ
2072 }
2073#undef PRINTINTR
2074#endif /* RTW_DEBUG */
2075
2076 if (isr & RTW_INTR_RX)
2077 rtw_intr_rx(sc, isr & RTW_INTR_RX);
2078 if (isr & RTW_INTR_TX)
2079 rtw_intr_tx(sc, isr & RTW_INTR_TX);
2080 if (isr & RTW_INTR_BEACON)
2081 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON);
2082 if (isr & RTW_INTR_ATIMINT)
2083 rtw_intr_atim(sc);
2084 if (isr & RTW_INTR_IOERROR)
2085 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR);
2086 if (isr & RTW_INTR_TIMEOUT)
2087 rtw_intr_timeout(sc);
2088 }
2089}
2090
2091/* Must be called at splnet. */
2092void
2093rtw_stop(struct rtw_softc *sc, int disable)
2094{
2095 struct ieee80211com *ic = &sc->sc_ic;
2096 struct ifnet *ifp = &ic->ic_if;
2097 struct rtw_regs *regs = &sc->sc_regs;
2098 int i;
2099
2100 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2101 return;
2102
2103 rtw_suspend_ticks(sc);
2104
2105 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2106
2107 if ((sc->sc_flags & RTW_F_INVALID) == 0) {
2108 /* Disable interrupts. */
2109 RTW_WRITE16(regs, RTW_IMR, 0);
2110
2111 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
2112
2113 /*
2114 * Stop the transmit and receive processes. First stop DMA,
2115 * then disable receiver and transmitter.
2116 */
2117 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2118
2119 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
2120
2121 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2122 }
2123
2124 /* Free pending TX mbufs */
2125 for (i = 0; i < RTW_NTXPRI; ++i) {
2126 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[i];
2127 struct rtw_txsoft *ts;
2128
2129 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
2130 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, 0, 0, 0, 0);
2131 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
2132 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
2133 }
2134 tsb->tsb_tx_timer = 0;
2135 }
2136
2137 /* Free pending RX mbufs */
2138 for (i = 0; i < RTW_RXQLEN; i++) {
2139 struct rtw_rxsoft *rs = &sc->sc_rxsoft[i];
2140
2141 if (rs->rs_mbuf != NULL) {
2142 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
2143 BUS_DMASYNC_POSTREAD);
2144 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
2145 m_freem(rs->rs_mbuf);
2146 rs->rs_mbuf = NULL;
2147 }
2148 }
2149
2150 if (disable)
2151 rtw_disable(sc);
2152
2153 /* Mark the interface as not running. Cancel the watchdog timer. */
2154 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2155 ifp->if_timer = 0;
2156}
2157
2158#ifdef RTW_DEBUG
2159const char *
2160rtw_pwrstate_string(enum rtw_pwrstate power)
2161{
2162 switch (power) {
2163 case RTW_ON:
2164 return "on";
2165 case RTW_SLEEP:
2166 return "sleep";
2167 case RTW_OFF:
2168 return "off";
2169 default:
2170 return "unknown";
2171 }
2172}
2173#endif /* RTW_DEBUG */
2174
2175/*
2176 * XXX For Maxim, I am using the RFMD settings gleaned from the
2177 * reference driver, plus a magic Maxim "ON" value that comes from
2178 * the Realtek document "Windows PG for Rtl8180."
2179 */
2180static void
2181rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2182 int before_rf, int digphy)
2183{
2184 uint32_t anaparm;
2185
2186 anaparm = RTW_READ(regs, RTW_ANAPARM);
2187 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2188
2189 switch (power) {
2190 case RTW_OFF:
2191 if (before_rf)
2192 return;
2193 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF;
2194 anaparm |= RTW_ANAPARM_TXDACOFF;
2195 break;
2196 case RTW_SLEEP:
2197 if (!before_rf)
2198 return;
2199 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP;
2200 anaparm |= RTW_ANAPARM_TXDACOFF;
2201 break;
2202 case RTW_ON:
2203 if (!before_rf)
2204 return;
2205 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON;
2206 break;
2207 }
2208 RTW_DPRINTF(RTW_DEBUG_PWR,
2209 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2210 __func__, rtw_pwrstate_string(power),
2211 (before_rf) ? "before" : "after", anaparm));
2212
2213 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2214 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2215}
2216
2217/* XXX I am using the RFMD settings gleaned from the reference
2218 * driver. They agree
2219 */
2220static void
2221rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2222 int before_rf, int digphy)
2223{
2224 uint32_t anaparm;
2225
2226 anaparm = RTW_READ(regs, RTW_ANAPARM);
2227 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2228
2229 switch (power) {
2230 case RTW_OFF:
2231 if (before_rf)
2232 return;
2233 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF;
2234 anaparm |= RTW_ANAPARM_TXDACOFF;
2235 break;
2236 case RTW_SLEEP:
2237 if (!before_rf)
2238 return;
2239 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP;
2240 anaparm |= RTW_ANAPARM_TXDACOFF;
2241 break;
2242 case RTW_ON:
2243 if (!before_rf)
2244 return;
2245 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON;
2246 break;
2247 }
2248 RTW_DPRINTF(RTW_DEBUG_PWR,
2249 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2250 __func__, rtw_pwrstate_string(power),
2251 (before_rf) ? "before" : "after", anaparm));
2252
2253 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2254 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2255}
2256
2257static void
2258rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2259 int before_rf, int digphy)
2260{
2261 uint32_t anaparm;
2262
2263 anaparm = RTW_READ(regs, RTW_ANAPARM);
2264 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2265
2266 switch (power) {
2267 case RTW_OFF:
2268 if (before_rf)
2269 return;
2270 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF;
2271 anaparm |= RTW_ANAPARM_TXDACOFF;
2272 break;
2273 case RTW_SLEEP:
2274 if (!before_rf)
2275 return;
2276 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP;
2277 anaparm |= RTW_ANAPARM_TXDACOFF;
2278 break;
2279 case RTW_ON:
2280 if (!before_rf)
2281 return;
2282 if (digphy) {
2283 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON;
2284 /* XXX guess */
2285 anaparm |= RTW_ANAPARM_TXDACOFF;
2286 } else
2287 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON;
2288 break;
2289 }
2290 RTW_DPRINTF(RTW_DEBUG_PWR,
2291 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2292 __func__, rtw_pwrstate_string(power),
2293 (before_rf) ? "before" : "after", anaparm));
2294
2295 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2296 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2297}
2298
2299static __inline void
2300rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf,
2301 int digphy)
2302{
2303 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2304 sc->sc_pwrstate_cb(&sc->sc_regs, power, before_rf, digphy);
2305 rtw_set_access(sc, RTW_ACCESS_NONE);
2306}
2307
2308static int
2309rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power)
2310{
2311 int rc;
2312
2313 RTW_DPRINTF(RTW_DEBUG_PWR,
2314 ("%s: %s->%s\n", sc->sc_ic.ic_if.if_xname,
2315 rtw_pwrstate_string(sc->sc_pwrstate),
2316 rtw_pwrstate_string(power)));
2317
2318 if (sc->sc_pwrstate == power)
2319 return 0;
2320
2321 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY);
2322 rc = rtw_rf_pwrstate(sc->sc_rf, power);
2323 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY);
2324
2325 switch (power) {
2326 case RTW_ON:
2327 /* TBD set LEDs */
2328 break;
2329 case RTW_SLEEP:
2330 /* TBD */
2331 break;
2332 case RTW_OFF:
2333 /* TBD */
2334 break;
2335 }
2336 if (rc == 0)
2337 sc->sc_pwrstate = power;
2338 else
2339 sc->sc_pwrstate = RTW_OFF;
2340 return rc;
2341}
2342
2343static int
2344rtw_tune(struct rtw_softc *sc)
2345{
2346 struct ieee80211com *ic = &sc->sc_ic;
2347 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
2348 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
2349 u_int chan;
2350 int rc, antdiv, dflantb;
2351
2352 antdiv = sc->sc_flags & RTW_F_ANTDIV;
2353 dflantb = sc->sc_flags & RTW_F_DFLANTB;
2354
2355 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2356 if (chan == IEEE80211_CHAN_ANY)
2357 panic("%s: chan == IEEE80211_CHAN_ANY\n", ic->ic_if.if_xname);
2358
2359 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2360 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2361
2362 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2363 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2364
2365 if (chan == sc->sc_cur_chan) {
2366 RTW_DPRINTF(RTW_DEBUG_TUNE,
2367 ("%s: already tuned chan #%d\n",
2368 ic->ic_if.if_xname, chan));
2369 return 0;
2370 }
2371
2372 rtw_suspend_ticks(sc);
2373
2374 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2375
2376 /* TBD wait for Tx to complete */
2377
2378 KKASSERT((sc->sc_flags & RTW_F_ENABLED) != 0);
2379
2380 rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf,
2381 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan),
2382 sc->sc_csthr, ic->ic_curchan->ic_freq, antdiv,
2383 dflantb, RTW_ON);
2384 if (rc != 0) {
2385 /* XXX condition on powersaving */
e3869ec7 2386 kprintf("%s: phy init failed\n", ic->ic_if.if_xname);
44db266b
SZ
2387 }
2388
2389 sc->sc_cur_chan = chan;
2390
2391 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2392
2393 rtw_resume_ticks(sc);
2394
2395 return rc;
2396}
2397
2398static void
2399rtw_disable(struct rtw_softc *sc)
2400{
2401 int rc;
2402
2403 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2404 return;
2405
2406 /* turn off PHY */
2407 if ((sc->sc_flags & RTW_F_INVALID) == 0 &&
2408 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0)
2409 if_printf(&sc->sc_ic.ic_if, "failed to turn off PHY\n");
2410
2411 sc->sc_flags &= ~RTW_F_ENABLED;
2412}
2413
2414static int
2415rtw_enable(struct rtw_softc *sc)
2416{
2417 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
2418 sc->sc_flags |= RTW_F_ENABLED;
2419 /*
2420 * Power may have been removed, and WEP keys thus reset.
2421 */
2422 sc->sc_flags &= ~RTW_F_DK_VALID;
2423 }
2424 return (0);
2425}
2426
2427static void
2428rtw_transmit_config(struct rtw_regs *regs)
2429{
2430 uint32_t tcr;
2431
2432 tcr = RTW_READ(regs, RTW_TCR);
2433
2434 tcr |= RTW_TCR_CWMIN;
2435 tcr &= ~RTW_TCR_MXDMA_MASK;
2436 tcr |= RTW_TCR_MXDMA_256;
2437 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */
2438 tcr &= ~RTW_TCR_LBK_MASK;
2439 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */
2440
2441 /* set short/long retry limits */
2442 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK);
b5b6e4f4 2443 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK);
44db266b
SZ
2444
2445 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */
2446
2447 RTW_WRITE(regs, RTW_TCR, tcr);
2448 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
2449}
2450
2451static void
2452rtw_enable_interrupts(struct rtw_softc *sc)
2453{
2454 struct rtw_regs *regs = &sc->sc_regs;
2455
2456 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT;
2457 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT;
2458
2459 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
2460 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2461 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2462 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2463
2464 /* XXX necessary? */
2465 if (sc->sc_intr_ack != NULL)
2466 sc->sc_intr_ack(regs);
2467}
2468
2469static void
2470rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode)
2471{
2472 struct rtw_regs *regs = &sc->sc_regs;
2473 uint8_t msr;
2474
2475 /* I'm guessing that MSR is protected as CONFIG[0123] are. */
2476 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2477
2478 msr = RTW_READ8(regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK;
2479
2480 switch (opmode) {
2481 case IEEE80211_M_AHDEMO:
2482 case IEEE80211_M_IBSS:
2483 msr |= RTW_MSR_NETYPE_ADHOC_OK;
2484 break;
2485 case IEEE80211_M_HOSTAP:
2486 msr |= RTW_MSR_NETYPE_AP_OK;
2487 break;
2488 case IEEE80211_M_MONITOR:
2489 /* XXX */
2490 msr |= RTW_MSR_NETYPE_NOLINK;
2491 break;
2492 case IEEE80211_M_STA:
2493 msr |= RTW_MSR_NETYPE_INFRA_OK;
2494 break;
2495 }
2496 RTW_WRITE8(regs, RTW_MSR, msr);
2497
2498 rtw_set_access(sc, RTW_ACCESS_NONE);
2499}
2500
2501#define rtw_calchash(addr) \
2502 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26)
2503
2504static void
2505rtw_pktfilt_load(struct rtw_softc *sc)
2506{
2507 struct rtw_regs *regs = &sc->sc_regs;
2508 struct ieee80211com *ic = &sc->sc_ic;
2509 struct ifnet *ifp = &ic->ic_if;
2510 struct ifmultiaddr *ifma;
2511 uint32_t hashes[2] = { 0, 0 };
2512 int hash;
2513
2514 /* XXX might be necessary to stop Rx/Tx engines while setting filters */
2515
2516 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK;
2517 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK);
2518
2519 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT;
2520 /* MAC auto-reset PHY (huh?) */
2521 sc->sc_rcr |= RTW_RCR_ENMARP;
2522 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */
2523 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE;
2524
2525 switch (ic->ic_opmode) {
2526 case IEEE80211_M_MONITOR:
2527 sc->sc_rcr |= RTW_RCR_MONITOR;
2528 break;
2529 case IEEE80211_M_AHDEMO:
2530 case IEEE80211_M_IBSS:
2531 /* receive broadcasts in our BSS */
2532 sc->sc_rcr |= RTW_RCR_ADD3;
2533 break;
2534 default:
2535 break;
2536 }
2537
2538 ifp->if_flags &= ~IFF_ALLMULTI;
2539
2540 /* XXX accept all broadcast if scanning */
2541 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2542 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2543
2544 if (ifp->if_flags & IFF_PROMISC) {
2545 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2546allmulti:
2547 ifp->if_flags |= IFF_ALLMULTI;
2548 goto setit;
2549 }
2550
2551 /*
2552 * Program the 64-bit multicast hash filter.
2553 */
441d34b2 2554 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
44db266b
SZ
2555 if (ifma->ifma_addr->sa_family != AF_LINK)
2556 continue;
2557
2558 hash = rtw_calchash(
2559 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
2560 hashes[hash >> 5] |= (1 << (hash & 0x1f));
2561 sc->sc_rcr |= RTW_RCR_AM;
2562 }
2563
2564 /* all bits set => hash is useless */
2565 if (~(hashes[0] & hashes[1]) == 0)
2566 goto allmulti;
2567
2568setit:
2569 if (ifp->if_flags & IFF_ALLMULTI) {
2570 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */
2571 hashes[0] = hashes[1] = 0xffffffff;
2572 }
2573
2574 RTW_WRITE(regs, RTW_MAR0, hashes[0]);
2575 RTW_WRITE(regs, RTW_MAR1, hashes[1]);
2576 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
2577 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
2578
2579 DPRINTF(sc, RTW_DEBUG_PKTFILT,
2580 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n",
2581 ifp->if_xname, RTW_READ(regs, RTW_MAR0),
2582 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
2583}
2584
2585/* Must be called at splnet. */
2586static void
2587rtw_init(void *xsc)
2588{
2589 struct rtw_softc *sc = xsc;
2590 struct ieee80211com *ic = &sc->sc_ic;
2591 struct ifnet *ifp = &ic->ic_if;
2592 struct rtw_regs *regs = &sc->sc_regs;
2593 int rc = 0;
2594
2595 rc = rtw_enable(sc);
2596 if (rc)
2597 goto out;
2598
2599 /* Cancel pending I/O and reset. */
2600 rtw_stop(sc, 0);
2601
2602 DPRINTF(sc, RTW_DEBUG_TUNE,
2603 ("%s: channel %d freq %d flags 0x%04x\n", ifp->if_xname,
2604 ieee80211_chan2ieee(ic, ic->ic_curchan),
2605 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
2606
2607 rc = rtw_pwrstate(sc, RTW_OFF);
2608 if (rc)
2609 goto out;
2610
2611 rc = rtw_swring_setup(sc);
2612 if (rc)
2613 goto out;
2614
2615 rtw_transmit_config(regs);
2616
2617 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2618
2619 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
2620 RTW_WBW(regs, RTW_MSR, RTW_BRSR);
2621
2622 /* long PLCP header, 1Mb/2Mb basic rate */
2623 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS);
2624 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
2625
2626 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2627 rtw_set_access(sc, RTW_ACCESS_NONE);
2628
2629 /* XXX from reference sources */
2630 RTW_WRITE(regs, RTW_FEMR, 0xffff);
2631 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
2632
2633 rtw_set_rfprog(sc);
2634
2635 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
2636 /* from Linux driver */
2637 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
2638
2639 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
2640
2641 rtw_enable_interrupts(sc);
2642
2643 rtw_pktfilt_load(sc);
2644
2645 rtw_hwring_setup(sc);
2646
2647 rtw_wep_setkeys(sc);
2648
2649 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2650
2651 ifp->if_flags |= IFF_RUNNING;
2652 ic->ic_state = IEEE80211_S_INIT;
2653
2654 RTW_WRITE16(regs, RTW_BSSID16, 0x0);
2655 RTW_WRITE(regs, RTW_BSSID32, 0x0);
2656
2657 rtw_resume_ticks(sc);
2658
2659 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
2660
2661 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2662 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2663 else
2664 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2665
2666out:
2667 if (rc)
2668 if_printf(ifp, "interface not running\n");
2669}
2670
2671static void
2672rtw_led_init(struct rtw_softc *sc)
2673{
2674 struct rtw_regs *regs = &sc->sc_regs;
2675 uint8_t cfg0, cfg1;
2676
2677 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2678
2679 cfg0 = RTW_READ8(regs, RTW_CONFIG0);
2680 cfg0 |= RTW_CONFIG0_LEDGPOEN;
2681 RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
2682
2683 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2684 RTW_DPRINTF(RTW_DEBUG_LED,
2685 ("%s: read %02x from reg[CONFIG1]\n",
2686 sc->sc_ic.ic_if.if_xname, cfg1));
2687
2688 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2689 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2690 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
2691
2692 rtw_set_access(sc, RTW_ACCESS_NONE);
2693}
2694
2695/*
2696 * IEEE80211_S_INIT: LED1 off
2697 *
2698 * IEEE80211_S_AUTH,
2699 * IEEE80211_S_ASSOC,
2700 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx
2701 *
2702 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx
2703 */
2704static void
2705rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate)
2706{
2707 struct rtw_led_state *ls = &sc->sc_led_state;
2708
2709 switch (nstate) {
2710 case IEEE80211_S_INIT:
2711 rtw_led_init(sc);
2712 callout_stop(&ls->ls_slow_ch);
2713 callout_stop(&ls->ls_fast_ch);
2714 ls->ls_slowblink = 0;
2715 ls->ls_actblink = 0;
2716 ls->ls_default = 0;
2717 break;
2718 case IEEE80211_S_SCAN:
2719 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2720 rtw_led_slowblink, sc);
2721 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2722 rtw_led_fastblink, sc);
2723 /*FALLTHROUGH*/
2724 case IEEE80211_S_AUTH:
2725 case IEEE80211_S_ASSOC:
2726 ls->ls_default = RTW_LED1;
2727 ls->ls_actblink = RTW_LED1;
2728 ls->ls_slowblink = RTW_LED1;
2729 break;
2730 case IEEE80211_S_RUN:
2731 ls->ls_slowblink = 0;
2732 break;
2733 }
2734 rtw_led_set(sc);
2735}
2736
2737static void
2738rtw_led_set(struct rtw_softc *sc)
2739{
2740 struct rtw_led_state *ls = &sc->sc_led_state;
2741 struct rtw_regs *regs = &sc->sc_regs;
2742 uint8_t led_condition, mask, newval, val;
2743 bus_size_t ofs;
2744
2745 led_condition = ls->ls_default;
2746
2747 if (ls->ls_state & RTW_LED_S_SLOW)
2748 led_condition ^= ls->ls_slowblink;
2749 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX))
2750 led_condition ^= ls->ls_actblink;
2751
2752 RTW_DPRINTF(RTW_DEBUG_LED,
2753 ("%s: LED condition %02x\n", sc->sc_ic.ic_if.if_xname,
2754 led_condition));
2755
2756 switch (sc->sc_hwverid) {
2757 default:
2758 case 'F':
2759 ofs = RTW_PSR;
2760 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;
2761 if (led_condition & RTW_LED0)
2762 newval &= ~RTW_PSR_LEDGPO0;
2763 if (led_condition & RTW_LED1)
2764 newval &= ~RTW_PSR_LEDGPO1;
2765 break;
2766 case 'D':
2767 ofs = RTW_9346CR;
2768 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;
2769 newval = RTW_9346CR_EEM_PROGRAM;
2770 if (led_condition & RTW_LED0)
2771 newval |= RTW_9346CR_EEDI;
2772 if (led_condition & RTW_LED1)
2773 newval |= RTW_9346CR_EECS;
2774 break;
2775 }
2776 val = RTW_READ8(regs, ofs);
2777 RTW_DPRINTF(RTW_DEBUG_LED,
2778 ("%s: read %02x from reg[%02x]\n",
2779 sc->sc_ic.ic_if.if_xname, val, ofs));
2780 val &= ~mask;
2781 val |= newval;
2782 RTW_WRITE8(regs, ofs, val);
2783 RTW_DPRINTF(RTW_DEBUG_LED,
2784 ("%s: wrote %02x to reg[%02x]\n",
2785 sc->sc_ic.ic_if.if_xname, val, ofs));
2786 RTW_SYNC(regs, ofs, ofs);
2787}
2788
2789static void
2790rtw_led_fastblink(void *arg)
2791{
2792 struct rtw_softc *sc = arg;
2793 struct ifnet *ifp = &sc->sc_ic.ic_if;
2794 struct rtw_led_state *ls = &sc->sc_led_state;
2795 int ostate;
2796
2797 lwkt_serialize_enter(ifp->if_serializer);
2798
2799 ostate = ls->ls_state;
2800 ls->ls_state ^= ls->ls_event;
2801
2802 if ((ls->ls_event & RTW_LED_S_TX) == 0)
2803 ls->ls_state &= ~RTW_LED_S_TX;
2804
2805 if ((ls->ls_event & RTW_LED_S_RX) == 0)
2806 ls->ls_state &= ~RTW_LED_S_RX;
2807
2808 ls->ls_event = 0;
2809
2810 if (ostate != ls->ls_state)
2811 rtw_led_set(sc);
2812
2813 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2814 rtw_led_fastblink, sc);
2815
2816 lwkt_serialize_exit(ifp->if_serializer);
2817}
2818
2819static void
2820rtw_led_slowblink(void *arg)
2821{
2822 struct rtw_softc *sc = arg;
2823 struct ifnet *ifp = &sc->sc_ic.ic_if;
2824 struct rtw_led_state *ls = &sc->sc_led_state;
2825
2826 lwkt_serialize_enter(ifp->if_serializer);
2827
2828 ls->ls_state ^= RTW_LED_S_SLOW;
2829 rtw_led_set(sc);
2830 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2831 rtw_led_slowblink, sc);
2832
2833 lwkt_serialize_exit(ifp->if_serializer);
2834}
2835
2836static int
2837rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2838{
2839 struct rtw_softc *sc = ifp->if_softc;
2840 int rc = 0;
2841
2842 switch (cmd) {
2843 case SIOCSIFFLAGS:
2844 if (ifp->if_flags & IFF_UP) {
2845 if ((ifp->if_flags & IFF_RUNNING) == 0)
2846 rtw_init(sc);
2847 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2848 } else if (sc->sc_flags & RTW_F_ENABLED) {
2849 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2850 rtw_stop(sc, 1);
2851 }
2852 break;
2853 case SIOCADDMULTI:
2854 case SIOCDELMULTI:
2855 if (ifp->if_flags & IFF_RUNNING)
2856 rtw_pktfilt_load(sc);
2857 break;
2858 default:
2859 rc = ieee80211_ioctl(&sc->sc_ic, cmd, data, cr);
2860 if (rc == ENETRESET) {
2861 if (sc->sc_flags & RTW_F_ENABLED)
2862 rtw_init(sc);
2863 rc = 0;
2864 }
2865 break;
2866 }
2867 return rc;
2868}
2869
2870/*
2871 * Select a transmit ring with at least one h/w and s/w descriptor free.
2872 * Return 0 on success, -1 on failure.
2873 */
2874static __inline int
2875rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp,
2876 struct rtw_txdesc_blk **tdbp, int pri)
2877{
2878 struct rtw_txsoft_blk *tsb;
2879 struct rtw_txdesc_blk *tdb;
2880
2881 KKASSERT(pri >= 0 && pri < RTW_NTXPRI);
2882
2883 tsb = &sc->sc_txsoft_blk[pri];
2884 tdb = &sc->sc_txdesc_blk[pri];
2885
2886 if (STAILQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) {
2887 if (tsb->tsb_tx_timer == 0)
2888 tsb->tsb_tx_timer = 5;
2889 *tsbp = NULL;
2890 *tdbp = NULL;
2891 return -1;
2892 }
2893 *tsbp = tsb;
2894 *tdbp = tdb;
2895 return 0;
2896}
2897
2898static __inline struct mbuf *
2899rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri,
2900 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp,
2901 struct ieee80211_node **nip, int *if_flagsp)
2902{
2903 struct mbuf *m;
2904 struct ifnet *ifp = &sc->sc_if;
2905
2906 if (IF_QEMPTY(ifq))
2907 return NULL;
2908 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2909 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2910 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2911 *if_flagsp |= IFF_OACTIVE;
2912 ifp->if_timer = 1;
2913 return NULL;
2914 }
2915 IF_DEQUEUE(ifq, m);
2916 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2917 m->m_pkthdr.rcvif = NULL;
2918 KKASSERT(*nip != NULL);
2919 return m;
2920}
2921
2922/*
2923 * Point *mp at the next 802.11 frame to transmit. Point *tsbp
2924 * at the driver's selection of transmit control block for the packet.
2925 */
2926static int
2927rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp,
2928 struct rtw_txdesc_blk **tdbp, struct mbuf **mp,
2929 struct ieee80211_node **nip)
2930{
2931 struct rtw_softc *sc = ifp->if_softc;
2932 int *if_flagsp = &ifp->if_flags;
2933 struct ether_header *eh;
2934 struct mbuf *m0;
2935 int pri;
2936
2937 DPRINTF(sc, RTW_DEBUG_XMIT,
2938 ("%s: enter %s\n", ifp->if_xname, __func__));
2939
2940 if (sc->sc_ic.ic_state == IEEE80211_S_RUN &&
2941 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp,
2942 tdbp, nip, if_flagsp)) != NULL) {
2943 DPRINTF(sc, RTW_DEBUG_XMIT,
2944 ("%s: dequeue beacon frame\n", ifp->if_xname));
2945 return 0;
2946 }
2947
2948 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp,
2949 tdbp, nip, if_flagsp)) != NULL) {
2950 DPRINTF(sc, RTW_DEBUG_XMIT,
2951 ("%s: dequeue mgt frame\n", ifp->if_xname));
2952 return 0;
2953 }
2954
2955 *mp = NULL;
2956
2957 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) {
9db4b353 2958 ifq_purge(&ifp->if_snd);
44db266b
SZ
2959 DPRINTF(sc, RTW_DEBUG_XMIT,
2960 ("%s: not running\n", ifp->if_xname));
2961 return 0;
2962 }
2963
9db4b353 2964 m0 = ifq_dequeue(&ifp->if_snd, NULL);
44db266b
SZ
2965 if (m0 == NULL) {
2966 DPRINTF(sc, RTW_DEBUG_XMIT,
2967 ("%s: no frame ready\n", ifp->if_xname));
2968 return 0;
2969 }
9db4b353
SZ
2970 DPRINTF(sc, RTW_DEBUG_XMIT,
2971 ("%s: dequeue data frame\n", ifp->if_xname));
44db266b
SZ
2972
2973 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD;
2974
2975 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2976 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2977 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2978 *if_flagsp |= IFF_OACTIVE;
9db4b353 2979 ifq_prepend(&ifp->if_snd, m0);
44db266b
SZ
2980 sc->sc_if.if_timer = 1;
2981 return 0;
2982 }
2983
44db266b
SZ
2984 BPF_MTAP(ifp, m0);
2985
2986 eh = mtod(m0, struct ether_header *);
2987 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost);
2988 if (*nip == NULL) {
2989 /* NB: ieee80211_find_txnode does stat+msg */
2990 m_freem(m0);
2991 return -1;
2992 }
2993
2994 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) {
2995 DPRINTF(sc, RTW_DEBUG_XMIT,
2996 ("%s: encap error\n", ifp->if_xname));
2997 ieee80211_free_node(*nip);
2998 ifp->if_oerrors++;
2999 return -1;
3000 }
3001
3002 ifp->if_opackets++;
3003 DPRINTF(sc, RTW_DEBUG_XMIT,
3004 ("%s: leave %s\n", ifp->if_xname, __func__));
3005 *mp = m0;
3006 return 0;
3007}
3008
3009static __inline int
3010rtw_txsegs_too_short(struct rtw_txsegs *segs)
3011{
3012 int i;
3013
3014 for (i = 0; i < segs->nseg; i++) {
3015 if (segs->segs[i].ds_len < 4)
3016 return 1;
3017 }
3018 return 0;
3019}
3020
3021static __inline int
3022rtw_txsegs_too_long(struct rtw_txsegs *segs)
3023{
3024 int i;
3025
3026 for (i = 0; i < segs->nseg; i++) {
3027 if (segs->segs[i].ds_len > RTW_TXLEN_LENGTH_MASK)
3028 return 1;
3029 }
3030 return 0;
3031}
3032
3033static void
3034rtw_txbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
3035 bus_size_t mapsize, int error)
3036{
3037 struct rtw_txsegs *s = arg;
3038
3039 if (error)
3040 return;
3041
3042 KASSERT(nseg <= RTW_MAXPKTSEGS, ("too many tx mbuf seg\n"));
3043
3044 s->nseg = nseg;
3045 bcopy(seg, s->segs, sizeof(*seg) * nseg);
3046}
3047
3048static struct mbuf *
3049rtw_load_txbuf(struct rtw_softc *sc, struct rtw_txsoft *ts,
3050 struct rtw_txsegs *segs, int ndesc_free, struct mbuf *m)
3051{
3052 int unload = 0, error;
3053
3054 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap, m,
3055 rtw_txbuf_dma_map, segs, BUS_DMA_NOWAIT);
79bbf413 3056 if (error && error != EFBIG) {
44db266b
SZ
3057 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf1\n");
3058 goto back;
3059 }
3060
3061 if (error || segs->nseg > ndesc_free || rtw_txsegs_too_short(segs)) {
3062 struct mbuf *m_new;
3063
3064 if (error == 0)
3065 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3066
3067 m_new = m_defrag(m, MB_DONTWAIT);
3068 if (m_new == NULL) {
3069 if_printf(&sc->sc_ic.ic_if, "can't defrag tx mbuf\n");
3070 error = ENOBUFS;
3071 goto back;
3072 }
3073 m = m_new;
3074
3075 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap,
3076 m, rtw_txbuf_dma_map, segs,
3077 BUS_DMA_NOWAIT);
3078 if (error) {
3079 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf2\n");
3080 goto back;
3081 }
3082 unload = 1;
3083
79bbf413 3084 error = EFBIG;
44db266b
SZ
3085 if (segs->nseg > ndesc_free) {
3086 if_printf(&sc->sc_ic.ic_if, "not enough free txdesc\n");
3087 goto back;
3088 }
3089 if (rtw_txsegs_too_short(segs)) {
3090 if_printf(&sc->sc_ic.ic_if, "segment too short\n");
3091 goto back;
3092 }
3093 error = 0;
3094 }
3095
3096 if (rtw_txsegs_too_long(segs)) {
3097 if_printf(&sc->sc_ic.ic_if, "segment too long\n");
3098 unload = 1;
79bbf413 3099 error = EFBIG;
44db266b
SZ
3100 }
3101
3102back:
3103 if (error) {
3104 if (unload)
3105 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3106 m_freem(m);
3107 m = NULL;
3108 } else {
3109 bus_dmamap_sync(sc->sc_txsoft_dmat, ts->ts_dmamap,
3110 BUS_DMASYNC_PREWRITE);
3111 }
3112 return m;
3113}
3114
3115#ifdef RTW_DEBUG
3116static void
3117rtw_print_txdesc(struct rtw_softc *sc, const char *action,
3118 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc)
3119{
3120 struct rtw_txdesc *td = &tdb->tdb_desc[desc];
3121
3122 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
3123 ("%s: %p %s txdesc[%d] "
3124 "next %#08x buf %#08x "
3125 "ctl0 %#08x ctl1 %#08x len %#08x\n",
3126 sc->sc_ic.ic_if.if_xname, ts, action,
3127 desc, le32toh(td->td_buf), le32toh(td->td_next),
3128 le32toh(td->td_ctl0), le32toh(td->td_ctl1),
3129 le32toh(td->td_len)));
3130}
3131#endif /* RTW_DEBUG */
3132
3133static void
3134rtw_start(struct ifnet *ifp)
3135{
3136 struct rtw_softc *sc = ifp->if_softc;
3137 struct ieee80211com *ic = &sc->sc_ic;
3138 struct ieee80211_node *ni;
3139 struct rtw_txsoft *ts;
3140 struct mbuf *m0;
3141 uint32_t proto_ctl0;
3142
3143 DPRINTF(sc, RTW_DEBUG_XMIT,
3144 ("%s: enter %s\n", ifp->if_xname, __func__));
3145
3146 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3147 goto out;
3148
3149 /* XXX do real rate control */
3150 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS;
3151
3152 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3153 proto_ctl0 |= RTW_TXCTL0_SPLCP;
3154
3155 for (;;) {
3156 struct rtw_txsegs segs;
3157 struct rtw_duration *d0;
3158 struct ieee80211_frame_min *wh;
3159 struct rtw_txsoft_blk *tsb;
3160 struct rtw_txdesc_blk *tdb;
3161 struct rtw_txdesc *td;
3162 struct ieee80211_key *k;
3163 uint32_t ctl0, ctl1;
3164 uint8_t tppoll;
3165 int desc, i, lastdesc, npkt, rate, rateidx, ratectl;
3166
3167 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1)
3168 continue;
3169 if (m0 == NULL)
3170 break;
3171
3172 wh = mtod(m0, struct ieee80211_frame_min *);
3173
3174 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 &&
3175 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3176 ieee80211_free_node(ni);
3177 m_freem(m0);
3178 break;
3179 } else {
3180 k = NULL;
3181 }
3182
3183 ts = STAILQ_FIRST(&tsb->tsb_freeq);
3184
3185 m0 = rtw_load_txbuf(sc, ts, &segs, tdb->tdb_nfree, m0);
3186 if (m0 == NULL || segs.nseg == 0) {
3187 DPRINTF(sc, RTW_DEBUG_XMIT,
3188 ("%s: %s failed\n", ifp->if_xname, __func__));
3189 goto post_dequeue_err;
3190 }
3191
3192 /*
3193 * Note well: rtw_load_txbuf may have created a new chain,
3194 * so we must find the header once more.
3195 */
3196 wh = mtod(m0, struct ieee80211_frame_min *);
3197
3198 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3199 IEEE80211_FC0_TYPE_MGT) {
3200 rateidx = 0;
3201 rate = 2; /* 1Mbit/s */
3202 ratectl = 0;
3203 } else {
3204 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len,
3205 &rateidx, 1);
3206 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx);
3207 ratectl =1;
3208
3209 if (rate == 0) {
3210 if_printf(ifp, "incorrect rate\n");
3211 rateidx = 0;
3212 rate = 2; /* 1Mbit/s */
3213 ratectl = 0;
3214 }
3215 }
3216
3217#ifdef RTW_DEBUG
3218 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
3219 (IFF_DEBUG | IFF_LINK2)) {
3220 ieee80211_dump_pkt(mtod(m0, uint8_t *),
3221 (segs.nseg == 1) ? m0->m_pkthdr.len
3222 : sizeof(wh),
3223 rate, 0);
3224 }
3225#endif /* RTW_DEBUG */
3226 ctl0 = proto_ctl0 |
b5b6e4f4 3227 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
44db266b
SZ
3228
3229 switch (rate) {
3230 default:
3231 case 2:
3232 ctl0 |= RTW_TXCTL0_RATE_1MBPS;
3233 break;
3234 case 4:
3235 ctl0 |= RTW_TXCTL0_RATE_2MBPS;
3236 break;
3237 case 11:
3238 ctl0 |= RTW_TXCTL0_RATE_5MBPS;
3239 break;
3240 case 22:
3241 ctl0 |= RTW_TXCTL0_RATE_11MBPS;
3242 break;
3243 }
3244 /* XXX >= ? Compare after fragmentation? */
3245 if (m0->m_pkthdr.len > ic->ic_rtsthreshold)
3246 ctl0 |= RTW_TXCTL0_RTSEN;
3247
3248 /*
3249 * XXX Sometimes writes a bogus keyid; h/w doesn't
3250 * seem to care, since we don't activate h/w Tx
3251 * encryption.
3252 */
3253 if (k != NULL) {
b5b6e4f4 3254 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &
44db266b
SZ
3255 RTW_TXCTL0_KEYID_MASK;
3256 }
3257
3258 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3259 IEEE80211_FC0_TYPE_MGT) {
3260 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
3261 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3262 IEEE80211_FC0_SUBTYPE_BEACON)
3263 ctl0 |= RTW_TXCTL0_BEACON;
3264 }
3265
3266 if (rtw_compute_duration(wh, k, m0->m_pkthdr.len,
3267 ic->ic_flags, ic->ic_fragthreshold,
3268 rate, &ts->ts_d0, &ts->ts_dn, &npkt,
3269 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3270 (IFF_DEBUG|IFF_LINK2)) == -1) {
3271 DPRINTF(sc, RTW_DEBUG_XMIT,
3272 ("%s: fail compute duration\n", __func__));
3273 goto post_load_err;
3274 }
3275
3276 d0 = &ts->ts_d0;
3277
3278 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur);
3279
b5b6e4f4
SZ
3280 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
3281 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
44db266b
SZ
3282
3283 if (d0->d_residue)
3284 ctl1 |= RTW_TXCTL1_LENGEXT;
3285
3286 /* TBD fragmentation */
3287
3288 ts->ts_first = tdb->tdb_next;
3289 KKASSERT(ts->ts_first < tdb->tdb_ndesc);
3290
3291 if (ic->ic_rawbpf != NULL)
3292 bpf_mtap(ic->ic_rawbpf, m0);
3293
3294 if (sc->sc_radiobpf != NULL) {
3295 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
3296
3297 rt->rt_flags = 0;
3298 rt->rt_rate = rate;
3299
3300 bpf_ptap(sc->sc_radiobpf, m0, rt,
3301 sizeof(sc->sc_txtapu));
3302 }
3303
3304 for (i = 0, lastdesc = desc = ts->ts_first; i < segs.nseg;
3305 i++, desc = RTW_NEXT_IDX(tdb, desc)) {
3306 td = &tdb->tdb_desc[desc];
3307 td->td_ctl0 = htole32(ctl0);
3308 if (i != 0)
3309 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3310 td->td_ctl1 = htole32(ctl1);
3311 td->td_buf = htole32(segs.segs[i].ds_addr);
3312 td->td_len = htole32(segs.segs[i].ds_len);
3313 lastdesc = desc;
3314#ifdef RTW_DEBUG
3315 rtw_print_txdesc(sc, "load", ts, tdb, desc);
3316#endif /* RTW_DEBUG */
3317 }
3318
3319 KKASSERT(desc < tdb->tdb_ndesc);
3320
3321 ts->ts_ni = ni;
3322 KKASSERT(ni != NULL);
3323 ts->ts_mbuf = m0;
3324 ts->ts_rateidx = rateidx;
3325 ts->ts_ratectl = ratectl;
3326 ts->ts_last = lastdesc;
3327 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS);
3328 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_FS);
3329
3330#ifdef RTW_DEBUG
3331 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first);
3332 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last);
3333#endif /* RTW_DEBUG */
3334
3335 tdb->tdb_nfree -= segs.nseg;
3336 tdb->tdb_next = desc;
3337
3338 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3339
3340#ifdef RTW_DEBUG
3341 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first);
3342#endif /* RTW_DEBUG */
3343
3344 STAILQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q);
3345 STAILQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q);
3346
3347 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN])
3348 sc->sc_led_state.ls_event |= RTW_LED_S_TX;
3349 tsb->tsb_tx_timer = 5;
3350 ifp->if_timer = 1;
3351 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL);
3352 tppoll &= ~RTW_TPPOLL_SALL;
3353 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL;
3354 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll);
3355 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL);
3356
3357 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
3358 BUS_DMASYNC_PREWRITE);
3359 }
3360out:
3361 DPRINTF(sc, RTW_DEBUG_XMIT,
3362 ("%s: leave %s\n", ifp->if_xname, __func__));
3363 return;
3364
3365post_load_err:
3366 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3367 m_freem(m0);
3368post_dequeue_err:
3369 ieee80211_free_node(ni);
3370
3371 DPRINTF(sc, RTW_DEBUG_XMIT,
3372 ("%s: leave %s\n", ifp->if_xname, __func__));
3373}
3374
3375static void
3376rtw_idle(struct rtw_softc *sc)
3377{
3378 struct rtw_regs *regs = &sc->sc_regs;
3379 int active;
3380
3381 /* request stop DMA; wait for packets to stop transmitting. */
3382
3383 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
3384 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
3385
3386 for (active = 0;
3387 active < 300 &&
3388 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0;
3389 active++)
3390 DELAY(10);
3391 if_printf(&sc->sc_ic.ic_if, "transmit DMA idle in %dus\n", active * 10);
3392}
3393
3394static void
3395rtw_watchdog(struct ifnet *ifp)
3396{
3397 int pri, tx_timeouts = 0;
3398 struct rtw_softc *sc = ifp->if_softc;
3399
3400 ifp->if_timer = 0;
3401
3402 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
3403 return;
3404
3405 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3406 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
3407
3408 if (tsb->tsb_tx_timer == 0)
3409 continue;
3410 else if (--tsb->tsb_tx_timer == 0) {
3411 if (STAILQ_EMPTY(&tsb->tsb_dirtyq))
3412 continue;
3413 if_printf(ifp, "transmit timeout, priority %d\n", pri);
3414 ifp->if_oerrors++;
3415 tx_timeouts++;
3416 } else {
3417 ifp->if_timer = 1;
3418 }
3419 }
3420
3421 if (tx_timeouts > 0) {
3422 /*
3423 * Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr,
3424 * reset s/w tx-ring pointers, and start transmission.
3425 *
3426 * TBD Stop/restart just the broken rings?
3427 */
3428 rtw_idle(sc);
3429 rtw_io_enable(sc, RTW_CR_TE, 0);
3430 rtw_txdesc_blk_reset_all(sc);
3431 rtw_io_enable(sc, RTW_CR_TE, 1);
3432 rtw_txring_fixup(sc);
3433 rtw_start(ifp);
3434 }
3435 ieee80211_watchdog(&sc->sc_ic);
3436}
3437
3438static void
3439rtw_next_scan(void *arg)
3440{
3441 struct ieee80211com *ic = arg;
3442 struct ifnet *ifp = &ic->ic_if;
3443
3444 lwkt_serialize_enter(ifp->if_serializer);
3445
3446 /* don't call rtw_start w/o network interrupts blocked */
3447 if (ic->ic_state == IEEE80211_S_SCAN)
3448 ieee80211_next_scan(ic);
3449
3450 lwkt_serialize_exit(ifp->if_serializer);
3451}
3452
3453static void
3454rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0)
3455{
3456 uint16_t bcnitv, bintritv, intval;
3457 int i;
3458 struct rtw_regs *regs = &sc->sc_regs;
3459
3460 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3461 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
3462
3463 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
3464
3465 rtw_set_access(sc, RTW_ACCESS_CONFIG);
3466
b5b6e4f4 3467 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK));
44db266b
SZ
3468
3469 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
b5b6e4f4 3470 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);
44db266b
SZ
3471 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
3472 /* interrupt host 1ms before the TBTT */
3473 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
b5b6e4f4 3474 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV);
44db266b
SZ
3475 RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
3476 /* magic from Linux */
b5b6e4f4
SZ
3477 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND));
3478 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));
44db266b
SZ
3479 rtw_set_access(sc, RTW_ACCESS_NONE);
3480
3481 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3482}
3483
3484/* Synchronize the hardware state with the software state. */
3485static int
3486rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3487{
3488 struct ifnet *ifp = ic->ic_ifp;
3489 struct rtw_softc *sc = ifp->if_softc;
3490 enum ieee80211_state ostate;
3491 int error;
3492
3493 ostate = ic->ic_state;
3494
3495 ieee80211_ratectl_newstate(ic, nstate);
3496 rtw_led_newstate(sc, nstate);
3497
3498 if (nstate == IEEE80211_S_INIT) {
3499 callout_stop(&sc->sc_scan_ch);
3500 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
3501 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3502 }
3503
3504 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT)
3505 rtw_pwrstate(sc, RTW_ON);
3506
3507 error = rtw_tune(sc);
3508 if (error != 0)
3509 return error;
3510
3511 switch (nstate) {
3512 case IEEE80211_S_INIT:
3513 panic("%s: unexpected state IEEE80211_S_INIT\n", __func__);
3514 break;
3515 case IEEE80211_S_SCAN:
3516 if (ostate != IEEE80211_S_SCAN) {
3517 memset(ic->ic_bss->ni_bssid, 0, IEEE80211_ADDR_LEN);
3518 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3519 }
3520
3521 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000,
3522 rtw_next_scan, ic);
3523
3524 break;
3525 case IEEE80211_S_RUN:
3526 switch (ic->ic_opmode) {
3527 case IEEE80211_M_HOSTAP:
3528 case IEEE80211_M_IBSS:
3529 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3530 /*FALLTHROUGH*/
3531 case IEEE80211_M_AHDEMO:
3532 case IEEE80211_M_STA:
3533 rtw_join_bss(sc, ic->ic_bss->ni_bssid,
3534 ic->ic_bss->ni_intval);
3535 break;
3536 case IEEE80211_M_MONITOR:
3537 break;
3538 }
3539 rtw_set_nettype(sc, ic->ic_opmode);
3540 break;
3541 case IEEE80211_S_ASSOC:
3542 case IEEE80211_S_AUTH:
3543 break;
3544 }
3545
3546 if (nstate != IEEE80211_S_SCAN)
3547 callout_stop(&sc->sc_scan_ch);
3548
3549 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3550}
3551
3552/* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */
3553static uint64_t
3554rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp)
3555{
3556 uint32_t tsftl, tsfth;
3557
3558 tsfth = RTW_READ(regs, RTW_TSFTRH);
3559 tsftl = RTW_READ(regs, RTW_TSFTRL);
3560 if (tsftl < rstamp) /* Compensate for rollover. */
3561 tsfth--;
3562 return ((uint64_t)tsfth << 32) | rstamp;
3563}
3564
3565static void
3566rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
3567 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
3568{
3569 struct ifnet *ifp = &ic->ic_if;
3570 struct rtw_softc *sc = ifp->if_softc;
3571
3572 sc->sc_mtbl.mt_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
3573
3574 switch (subtype) {
3575 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3576 case IEEE80211_FC0_SUBTYPE_BEACON:
3577 if (ic->ic_opmode == IEEE80211_M_IBSS &&
3578 ic->ic_state == IEEE80211_S_RUN) {
3579 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp);
3580
3581 if (le64toh(ni->ni_tstamp.tsf) >= tsf)
3582 ieee80211_ibss_merge(ni);
3583 }
3584 break;
3585 default:
3586 break;
3587 }
3588}
3589
3590#ifdef foo
3591static struct ieee80211_node *
3592rtw_node_alloc(struct ieee80211_node_table *nt)
3593{
3594 struct ifnet *ifp = nt->nt_ic->ic_ifp;
3595 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3596 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt);
3597
3598 DPRINTF(sc, RTW_DEBUG_NODE,
3599 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
3600 return ni;
3601}
3602
3603static void
3604rtw_node_free(struct ieee80211_node *ni)
3605{
3606 struct ieee80211com *ic = ni->ni_ic;
3607 struct ifnet *ifp = ic->ic_ifp;
3608 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3609
3610 DPRINTF(sc, RTW_DEBUG_NODE,
3611 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
3612 ether_sprintf(ni->ni_bssid)));
3613 sc->sc_mtbl.mt_node_free(ni);
3614}
3615#endif
3616
3617static int
3618rtw_media_change(struct ifnet *ifp)
3619{
3620 int error;
3621
3622 error = ieee80211_media_change(ifp);
3623 if (error == ENETRESET) {
3624 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
3625 (IFF_RUNNING|IFF_UP))
3626 rtw_init(ifp); /* XXX lose error */
3627 error = 0;
3628 }
3629 return error;
3630}
3631
3632static void
3633rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
3634{
3635 struct rtw_softc *sc = ifp->if_softc;
3636
3637 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
3638 imr->ifm_active = IFM_IEEE80211 | IFM_NONE;
3639 imr->ifm_status = 0;
3640 return;
3641 }
3642 ieee80211_media_status(ifp, imr);
3643}
3644
3645static __inline void
3646rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic)
3647{
3648 mtbl->mt_newstate = ic->ic_newstate;
3649 ic->ic_newstate = rtw_newstate;
3650
3651 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt;
3652 ic->ic_recv_mgmt = rtw_recv_mgmt;
3653
3654#ifdef foo
3655 mtbl->mt_node_free = ic->ic_node_free;
3656 ic->ic_node_free = rtw_node_free;
3657
3658 mtbl->mt_node_alloc = ic->ic_node_alloc;
3659 ic->ic_node_alloc = rtw_node_alloc;
3660#endif
3661
3662 ic->ic_crypto.cs_key_delete = rtw_key_delete;
3663 ic->ic_crypto.cs_key_set = rtw_key_set;
3664 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin;
3665 ic->ic_crypto.cs_key_update_end = rtw_key_update_end;
3666}
3667
3668static __inline void
3669rtw_init_radiotap(struct rtw_softc *sc)
3670{
3671 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
3672 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT);
3673
3674 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
3675 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT);
3676}
3677
3678static struct rtw_rf *
3679rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy)
3680{
3681 rtw_rf_write_t rf_write;
3682 struct rtw_rf *rf;
3683
3684 switch (rfchipid) {
3685 default:
3686 rf_write = rtw_rf_hostwrite;
3687 break;
3688 case RTW_RFCHIPID_INTERSIL:
3689 case RTW_RFCHIPID_PHILIPS:
3690 case RTW_RFCHIPID_GCT: /* XXX a guess */
3691 case RTW_RFCHIPID_RFMD:
3692 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite;
3693 break;
3694 }
3695
3696 switch (rfchipid) {
3697 case RTW_RFCHIPID_GCT:
3698 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0);
3699 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
dcb7b49c 3700 sc->sc_getrssi = rtw_gct_getrssi;
44db266b
SZ
3701 break;
3702 case RTW_RFCHIPID_MAXIM:
3703 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0);
3704 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
dcb7b49c 3705 sc->sc_getrssi = rtw_maxim_getrssi;
44db266b
SZ
3706 break;
3707 case RTW_RFCHIPID_PHILIPS:
3708 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy);
3709 sc->sc_pwrstate_cb = rtw_philips_pwrstate;
dcb7b49c 3710 sc->sc_getrssi = rtw_philips_getrssi;
44db266b
SZ
3711 break;
3712 case RTW_RFCHIPID_RFMD:
3713 /* XXX RFMD has no RF constructor */
3714 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate;
3715 /*FALLTHROUGH*/
3716 default:
3717 return NULL;
3718 }
3719 rf->rf_continuous_tx_cb =
3720 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable;
3721 rf->rf_continuous_tx_arg = sc;
3722 return rf;
3723}
3724
3725/* Revision C and later use a different PHY delay setting than
3726 * revisions A and B.
3727 */
3728static uint8_t
3729rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr)
3730{
3731#define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV)
3732#define REVC (REVAB | RTW_RCR_RXFTH_WHOLE)
3733
b5b6e4f4 3734 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);
44db266b
SZ
3735
3736 RTW_WRITE(regs, RTW_RCR, REVAB);
3737 RTW_WBW(regs, RTW_RCR, RTW_RCR);
3738 RTW_WRITE(regs, RTW_RCR, REVC);
3739
3740 RTW_WBR(regs, RTW_RCR, RTW_RCR);
3741 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
3742 phydelay |= RTW_PHYDELAY_REVC_MAGIC;
3743
3744 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
3745 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
3746
3747 return phydelay;
3748#undef REVC
3749#undef REVAB
3750}
3751
3752int
3753rtw_attach(device_t dev)
3754{
3755 struct rtw_softc *sc = device_get_softc(dev);
3756 struct ieee80211com *ic = &sc->sc_ic;
3757 const struct ieee80211_cipher *wep_cipher;
3758 struct ifnet *ifp = &ic->ic_if;
3759 int rc;
3760
3761 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
3762 KKASSERT(wep_cipher != NULL);
3763
3764 memcpy(&rtw_cipher_wep, wep_cipher, sizeof(rtw_cipher_wep));
3765 rtw_cipher_wep.ic_decap = rtw_wep_decap;
3766
3767 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3768
3769 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
3770 case RTW_TCR_HWVERID_F:
3771 sc->sc_hwverid = 'F';
3772 break;
3773 case RTW_TCR_HWVERID_D:
3774 sc->sc_hwverid = 'D';
3775 break;
3776 default:
3777 sc->sc_hwverid = '?';
3778 break;
3779 }
3780
3781 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3782 &sc->sc_irq_rid,
3783 RF_ACTIVE | RF_SHAREABLE);
3784 if (sc->sc_irq_res == NULL) {
3785 device_printf(dev, "could not alloc irq res\n");
3786 return ENXIO;
3787 }
3788
3789 /* Allocate h/w desc blocks */
3790 rc = rtw_desc_blk_alloc(sc);
3791 if (rc)
3792 goto err;
3793
3794 /* Allocate s/w desc blocks */
3795 rc = rtw_soft_blk_alloc(sc);
3796 if (rc)
3797 goto err;
3798
3799 /* Reset the chip to a known state. */
3800 rc = rtw_reset(sc);
3801 if (rc) {
3802 device_printf(dev, "could not reset\n");
3803 goto err;
3804 }
3805
3806 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
3807
3808 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0)
3809 sc->sc_flags |= RTW_F_9356SROM;
3810
3811 rc = rtw_srom_read(sc);
3812 if (rc)
3813 goto err;
3814
3815 rc = rtw_srom_parse(sc);
3816 if (rc) {
3817 device_printf(dev, "malformed serial ROM\n");
3818 goto err;
3819 }
3820
3821 device_printf(dev, "%s PHY\n",
3822 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital"
3823 : "analog");
3824
3825 device_printf(dev, "CS threshold %u\n", sc->sc_csthr);
3826
3827 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid,
3828 sc->sc_flags & RTW_F_DIGPHY);
3829 if (sc->sc_rf == NULL) {
3830 device_printf(dev, "could not attach RF\n");
3831 rc = ENXIO;
3832 goto err;
3833 }
3834
3835 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr);
3836
3837 RTW_DPRINTF(RTW_DEBUG_ATTACH,
3838 ("%s: PHY delay %d\n", ifp->if_xname, sc->sc_phydelay));
3839
3840 if (sc->sc_locale == RTW_LOCALE_UNKNOWN)
3841 rtw_identify_country(sc);
3842
3843 rtw_init_channels(sc);
3844
3845 rc = rtw_identify_sta(sc);
3846 if (rc)
3847 goto err;
3848
3849 ifp->if_softc = sc;
3850 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
3851 ifp->if_init = rtw_init;
3852 ifp->if_ioctl = rtw_ioctl;
3853 ifp->if_start = rtw_start;
3854 ifp->if_watchdog = rtw_watchdog;
3855 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
3856 ifq_set_ready(&ifp->if_snd);
3857
3858 ic->ic_phytype = IEEE80211_T_DS;
3859 ic->ic_opmode = IEEE80211_M_STA;
3860 ic->ic_caps = IEEE80211_C_PMGT |
3861 IEEE80211_C_IBSS |
3862 IEEE80211_C_HOSTAP |
3863 IEEE80211_C_MONITOR;
3864 ic->ic_sup_rates[IEEE80211_MODE_11B] = rtw_rates_11b;
3865
3866 /* initialize led callout */
3867 callout_init(&sc->sc_led_state.ls_fast_ch);
3868 callout_init(&sc->sc_led_state.ls_slow_ch);
3869
21028056 3870 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
44db266b
SZ
3871 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
3872 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
21028056 3873 ic->ic_ratectl.rc_st_attach = rtw_ratectl_attach;
44db266b
SZ
3874
3875 /*
3876 * Call MI attach routines.
3877 */
3878 ieee80211_ifattach(&sc->sc_ic);
3879
3880 /* Override some ieee80211 methods */
3881 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic);
3882
3883 /*
3884 * possibly we should fill in our own sc_send_prresp, since
3885 * the RTL8180 is probably sending probe responses in ad hoc
3886 * mode.
3887 */
3888
3889 /* complete initialization */
3890 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status);
3891 callout_init(&sc->sc_scan_ch);
3892
3893 rtw_init_radiotap(sc);
3894
3895 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
3896 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
3897
3898 rc = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, rtw_intr, sc,
3899 &sc->sc_irq_handle, ifp->if_serializer);
3900 if (rc) {
3901 device_printf(dev, "can't set up interrupt\n");
3902 bpfdetach(ifp);
3903 ieee80211_ifdetach(ic);
3904 goto err;
3905 }
3906
9db4b353
SZ
3907 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
3908 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3909
44db266b
SZ
3910 device_printf(dev, "hardware version %c\n", sc->sc_hwverid);
3911 if (bootverbose)
3912 ieee80211_announce(ic);
3913 return 0;
3914err:
3915 rtw_detach(dev);
3916 return rc;
3917}
3918
3919int
3920rtw_detach(device_t dev)
3921{
3922 struct rtw_softc *sc = device_get_softc(dev);
3923 struct ifnet *ifp = &sc->sc_ic.ic_if;
3924
3925 if (device_is_attached(dev)) {
3926 lwkt_serialize_enter(ifp->if_serializer);
3927
3928 rtw_stop(sc, 1);
3929 sc->sc_flags |= RTW_F_INVALID;
3930
3931 callout_stop(&sc->sc_scan_ch);
3932 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
3933
3934 lwkt_serialize_exit(ifp->if_serializer);
3935
3936 ieee80211_ifdetach(&sc->sc_ic);
3937 }
3938
3939 if (sc->sc_rf != NULL)
3940 rtw_rf_destroy(sc->sc_rf);
3941
3942 if (sc->sc_srom.sr_content != NULL)
efda3bd0 3943 kfree(sc->sc_srom.sr_content, M_DEVBUF);
44db266b
SZ
3944
3945 if (sc->sc_irq_res != NULL) {
3946 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
3947 sc->sc_irq_res);
3948 }
3949
3950 rtw_soft_blk_free(sc);
3951 rtw_desc_blk_free(sc);
3952 return 0;
3953}
3954
3955static void
3956rtw_desc_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3957{
3958 if (error)
3959 return;
3960
3961 KASSERT(nseg == 1, ("too many desc segments\n"));
3962 *((uint32_t *)arg) = seg->ds_addr; /* XXX bus_addr_t */
3963}
3964
3965static int
3966rtw_dma_alloc(struct rtw_softc *sc, bus_dma_tag_t *dmat, int len,
3967 void **desc, uint32_t *phyaddr, bus_dmamap_t *dmamap)
3968{
3969 int error;
3970
3971 error = bus_dma_tag_create(NULL, RTW_DESC_ALIGNMENT, 0,
3972 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3973 NULL, NULL, len, 1, len, 0, dmat);
3974 if (error) {
3975 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA tag");
3976 return error;
3977 }
3978
3979 error = bus_dmamem_alloc(*dmat, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3980 dmamap);
3981 if (error) {
3982 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA mem");
3983 return error;
3984 }
3985
3986 error = bus_dmamap_load(*dmat, *dmamap, *desc, len,
3987 rtw_desc_dma_addr, phyaddr, BUS_DMA_WAITOK);
3988 if (error) {
3989 if_printf(&sc->sc_ic.ic_if, "could not load desc DMA mem");
3990 bus_dmamem_free(*dmat, *desc, *dmamap);
3991 *desc = NULL;
3992 return error;
3993 }
3994 return 0;
3995}
3996
3997static void
3998rtw_dma_free(struct rtw_softc *sc __unused, bus_dma_tag_t *dmat, void **desc,
3999 bus_dmamap_t *dmamap)
4000{
4001 if (*desc != NULL) {
4002 bus_dmamap_unload(*dmat, *dmamap);
4003 bus_dmamem_free(*dmat, *desc, *dmamap);
4004 *desc = NULL;
4005 }
4006
4007 if (*dmat != NULL) {
4008 bus_dma_tag_destroy(*dmat);
4009 *dmat = NULL;
4010 }
4011}
4012
4013static void
4014rtw_txdesc_blk_free(struct rtw_softc *sc, int q_no)
4015{
4016 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4017
4018 rtw_dma_free(sc, &tdb->tdb_dmat, (void **)&tdb->tdb_desc,
4019 &tdb->tdb_dmamap);
4020}
4021
4022static int
4023rtw_txdesc_blk_alloc(struct rtw_softc *sc, int q_len, int q_no,
4024 bus_size_t q_basereg)
4025{
4026 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4027 int i, error;
4028
4029 /*
4030 * Setup TX h/w desc
4031 */
4032 error = rtw_dma_alloc(sc, &tdb->tdb_dmat,
4033 q_len * sizeof(*tdb->tdb_desc),
4034 (void **)&tdb->tdb_desc, &tdb->tdb_base,
4035 &tdb->tdb_dmamap);
4036 if (error) {
e3869ec7 4037 kprintf("%dth tx\n", q_no);
44db266b
SZ
4038 return error;
4039 }
4040 tdb->tdb_basereg = q_basereg;
4041
4042 tdb->tdb_ndesc = q_len;
4043 for (i = 0; i < tdb->tdb_ndesc; ++i)
4044 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i));
4045
4046 return 0;
4047}
4048
4049static void
4050rtw_rxdesc_blk_free(struct rtw_softc *sc)
4051{
4052 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4053
4054 rtw_dma_free(sc, &rdb->rdb_dmat, (void **)&rdb->rdb_desc,
4055 &rdb->rdb_dmamap);
4056}
4057
4058static int
4059rtw_rxdesc_blk_alloc(struct rtw_softc *sc, int q_len)
4060{
4061 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4062 int error;
4063
4064 /*
4065 * Setup RX h/w desc
4066 */
4067 error = rtw_dma_alloc(sc, &rdb->rdb_dmat,
4068 q_len * sizeof(*rdb->rdb_desc),
4069 (void **)&rdb->rdb_desc, &rdb->rdb_base,
4070 &rdb->rdb_dmamap);
4071 if (error) {
e3869ec7 4072 kprintf("rx\n");
44db266b
SZ
4073 } else {
4074 rdb->rdb_ndesc = q_len;
4075 }
4076
4077 return error;
4078}
4079
4080static void
4081rtw_txsoft_blk_free(struct rtw_softc *sc, int n_sd, int q_no)
4082{
4083 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4084
4085 if (tsb->tsb_desc != NULL) {
4086 int i;
4087
4088 for (i = 0; i < n_sd; ++i) {
4089 bus_dmamap_destroy(sc->sc_txsoft_dmat,
4090 tsb->tsb_desc[i].ts_dmamap);
4091 }
efda3bd0 4092 kfree(tsb->tsb_desc, M_DEVBUF);
44db266b
SZ
4093 tsb->tsb_desc = NULL;
4094 }
4095}
4096
4097static int
4098rtw_txsoft_blk_alloc(struct rtw_softc *sc, int q_len, int q_no, uint8_t q_poll)
4099{
4100 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4101 int i, error;
4102
4103 STAILQ_INIT(&tsb->tsb_dirtyq);
4104 STAILQ_INIT(&tsb->tsb_freeq);
4105 tsb->tsb_ndesc = q_len;
efda3bd0 4106 tsb->tsb_desc = kmalloc(q_len * sizeof(*tsb->tsb_desc), M_DEVBUF,
44db266b
SZ
4107 M_WAITOK | M_ZERO);
4108 tsb->tsb_poll = q_poll;
4109
4110 for (i = 0; i < tsb->tsb_ndesc; ++i) {
4111 error = bus_dmamap_create(sc->sc_txsoft_dmat, 0,
4112 &tsb->tsb_desc[i].ts_dmamap);
4113 if (error) {
4114 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4115 "for soft tx desc\n");
4116 rtw_txsoft_blk_free(sc, i, q_no);
4117 return error;
4118 }
4119 }
4120 return 0;
4121}
4122
4123static void
4124rtw_rxsoft_blk_free(struct rtw_softc *sc, int n_sd)
4125{
4126 if (sc->sc_rxsoft_free) {
4127 int i;
4128
4129 for (i = 0; i < n_sd; ++i) {
4130 bus_dmamap_destroy(sc->sc_rxsoft_dmat,
4131 sc->sc_rxsoft[i].rs_dmamap);
4132 }
4133 sc->sc_rxsoft_free = 0;
4134 }
4135}
4136
4137static int
4138rtw_rxsoft_blk_alloc(struct rtw_softc *sc, int q_len)
4139{
4140 int i, error;
4141
4142 sc->sc_rxsoft_free = 1;
4143
4144 /*
4145 * Setup RX s/w desc
4146 */
4147 for (i = 0; i < q_len; ++i) {
4148 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0,
4149 &sc->sc_rxsoft[i].rs_dmamap);
4150 if (error) {
4151 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4152 "for soft rx desc\n");
4153 rtw_rxsoft_blk_free(sc, i);
4154 return error;
4155 }
4156 }
4157 return 0;
4158}
4159
4160#define TXQ_PARAM(q, poll, breg) \
4161 [RTW_TXPRI ## q] = { \
4162 .txq_len = RTW_TXQLEN ## q, \
4163 .txq_poll = poll, \
4164 .txq_basereg = breg \
4165 }
4166static const struct {
4167 int txq_len;
4168 uint8_t txq_poll;
4169 bus_size_t txq_basereg;
4170} txq_params[RTW_NTXPRI] = {
4171 TXQ_PARAM(LO, RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ, RTW_TLPDA),
4172 TXQ_PARAM(MD, RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ, RTW_TNPDA),
4173 TXQ_PARAM(HI, RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ, RTW_THPDA),
4174 TXQ_PARAM(BCN, RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ, RTW_TBDA)
4175};
4176</