network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / sf / if_sf.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
95893fe4 33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.33 2008/08/17 04:32:34 sephe Exp $
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34 */
35
36/*
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
40 *
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
44 */
45
46/*
47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
48 * controller designed with flexibility and reducing CPU load in mind.
49 * The Starfire offers high and low priority buffer queues, a
50 * producer/consumer index mechanism and several different buffer
51 * queue and completion queue descriptor types. Any one of a number
52 * of different driver designs can be used, depending on system and
53 * OS requirements. This driver makes use of type0 transmit frame
54 * descriptors (since BSD fragments packets across an mbuf chain)
55 * and two RX buffer queues prioritized on size (one queue for small
56 * frames that will fit into a single mbuf, another with full size
57 * mbuf clusters for everything else). The producer/consumer indexes
58 * and completion queues are also used.
59 *
60 * One downside to the Starfire has to do with alignment: buffer
61 * queues must be aligned on 256-byte boundaries, and receive buffers
62 * must be aligned on longword boundaries. The receive buffer alignment
63 * causes problems on the Alpha platform, where the packet payload
64 * should be longword aligned. There is no simple way around this.
65 *
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
68 *
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
73 *
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
81 */
82
83#include <sys/param.h>
84#include <sys/systm.h>
85#include <sys/sockio.h>
86#include <sys/mbuf.h>
87#include <sys/malloc.h>
88#include <sys/kernel.h>
9db4b353 89#include <sys/interrupt.h>
984263bc 90#include <sys/socket.h>
78195a76 91#include <sys/serialize.h>
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92#include <sys/bus.h>
93#include <sys/rman.h>
0966b280 94#include <sys/thread2.h>
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95
96#include <net/if.h>
c49a85fd 97#include <net/ifq_var.h>
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98#include <net/if_arp.h>
99#include <net/ethernet.h>
100#include <net/if_dl.h>
101#include <net/if_media.h>
102
103#include <net/bpf.h>
104
105#include <vm/vm.h> /* for vtophys */
106#include <vm/pmap.h> /* for vtophys */
1f7ab7c9 107
984263bc 108#include <machine/clock.h> /* for DELAY */
984263bc 109
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110#include "../mii_layer/mii.h"
111#include "../mii_layer/miivar.h"
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112
113/* "controller miibus0" required. See GENERIC if you get errors here. */
114#include "miibus_if.h"
115
c5f22b3e 116#include <bus/pci/pcidevs.h>
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117#include <bus/pci/pcireg.h>
118#include <bus/pci/pcivar.h>
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119
120#define SF_USEIOSPACE
121
1f2de5d4 122#include "if_sfreg.h"
984263bc 123
984263bc 124static struct sf_type sf_devs[] = {
c5f22b3e 125 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915,
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126 "Adaptec AIC-6915 10/100BaseTX" },
127 { 0, 0, NULL }
128};
129
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130static int sf_probe (device_t);
131static int sf_attach (device_t);
132static int sf_detach (device_t);
133static void sf_intr (void *);
134static void sf_stats_update (void *);
135static void sf_rxeof (struct sf_softc *);
136static void sf_txeof (struct sf_softc *);
137static int sf_encap (struct sf_softc *,
984263bc 138 struct sf_tx_bufdesc_type0 *,
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139 struct mbuf *);
140static void sf_start (struct ifnet *);
bd4539cc
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141static int sf_ioctl (struct ifnet *, u_long, caddr_t,
142 struct ucred *);
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143static void sf_init (void *);
144static void sf_stop (struct sf_softc *);
145static void sf_watchdog (struct ifnet *);
146static void sf_shutdown (device_t);
147static int sf_ifmedia_upd (struct ifnet *);
148static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
149static void sf_reset (struct sf_softc *);
150static int sf_init_rx_ring (struct sf_softc *);
151static void sf_init_tx_ring (struct sf_softc *);
152static int sf_newbuf (struct sf_softc *,
984263bc 153 struct sf_rx_bufdesc_type0 *,
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154 struct mbuf *);
155static void sf_setmulti (struct sf_softc *);
156static int sf_setperf (struct sf_softc *, int, caddr_t);
157static int sf_sethash (struct sf_softc *, caddr_t, int);
984263bc 158#ifdef notdef
b5101a88 159static int sf_setvlan (struct sf_softc *, int, u_int32_t);
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160#endif
161
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162static u_int8_t sf_read_eeprom (struct sf_softc *, int);
163static u_int32_t sf_calchash (caddr_t);
984263bc 164
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165static int sf_miibus_readreg (device_t, int, int);
166static int sf_miibus_writereg (device_t, int, int, int);
167static void sf_miibus_statchg (device_t);
984263bc 168
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169static u_int32_t csr_read_4 (struct sf_softc *, int);
170static void csr_write_4 (struct sf_softc *, int, u_int32_t);
171static void sf_txthresh_adjust (struct sf_softc *);
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172
173#ifdef SF_USEIOSPACE
174#define SF_RES SYS_RES_IOPORT
175#define SF_RID SF_PCI_LOIO
176#else
177#define SF_RES SYS_RES_MEMORY
178#define SF_RID SF_PCI_LOMEM
179#endif
180
181static device_method_t sf_methods[] = {
182 /* Device interface */
183 DEVMETHOD(device_probe, sf_probe),
184 DEVMETHOD(device_attach, sf_attach),
185 DEVMETHOD(device_detach, sf_detach),
186 DEVMETHOD(device_shutdown, sf_shutdown),
187
188 /* bus interface */
189 DEVMETHOD(bus_print_child, bus_generic_print_child),
190 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191
192 /* MII interface */
193 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
194 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
195 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
196
197 { 0, 0 }
198};
199
200static driver_t sf_driver = {
201 "sf",
202 sf_methods,
203 sizeof(struct sf_softc),
204};
205
206static devclass_t sf_devclass;
207
32832096 208DECLARE_DUMMY_MODULE(if_sf);
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209DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
210DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
211
212#define SF_SETBIT(sc, reg, x) \
213 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
214
215#define SF_CLRBIT(sc, reg, x) \
216 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
217
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218static u_int32_t
219csr_read_4(struct sf_softc *sc, int reg)
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220{
221 u_int32_t val;
222
223#ifdef SF_USEIOSPACE
224 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
225 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
226#else
227 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
228#endif
229
230 return(val);
231}
232
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233static u_int8_t
234sf_read_eeprom(struct sf_softc *sc, int reg)
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235{
236 u_int8_t val;
237
238 val = (csr_read_4(sc, SF_EEADDR_BASE +
239 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
240
241 return(val);
242}
243
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244static void
245csr_write_4(struct sf_softc *sc, int reg, u_int32_t val)
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246{
247#ifdef SF_USEIOSPACE
248 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
249 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
250#else
251 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
252#endif
253 return;
254}
255
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256static u_int32_t
257sf_calchash(caddr_t addr)
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258{
259 u_int32_t crc, carry;
260 int i, j;
261 u_int8_t c;
262
263 /* Compute CRC for the address value. */
264 crc = 0xFFFFFFFF; /* initial value */
265
266 for (i = 0; i < 6; i++) {
267 c = *(addr + i);
268 for (j = 0; j < 8; j++) {
269 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
270 crc <<= 1;
271 c >>= 1;
272 if (carry)
273 crc = (crc ^ 0x04c11db6) | carry;
274 }
275 }
276
277 /* return the filter bit position */
278 return(crc >> 23 & 0x1FF);
279}
280
281/*
282 * Copy the address 'mac' into the perfect RX filter entry at
283 * offset 'idx.' The perfect filter only has 16 entries so do
284 * some sanity tests.
285 */
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286static int
287sf_setperf(struct sf_softc *sc, int idx, caddr_t mac)
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288{
289 u_int16_t *p;
290
291 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
292 return(EINVAL);
293
294 if (mac == NULL)
295 return(EINVAL);
296
297 p = (u_int16_t *)mac;
298
299 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
300 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
301 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
302 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
303 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
304 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
305
306 return(0);
307}
308
309/*
310 * Set the bit in the 512-bit hash table that corresponds to the
311 * specified mac address 'mac.' If 'prio' is nonzero, update the
312 * priority hash table instead of the filter hash table.
313 */
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314static int
315sf_sethash(struct sf_softc *sc, caddr_t mac, int prio)
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316{
317 u_int32_t h = 0;
318
319 if (mac == NULL)
320 return(EINVAL);
321
322 h = sf_calchash(mac);
323
324 if (prio) {
325 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
326 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
327 } else {
328 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
329 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
330 }
331
332 return(0);
333}
334
335#ifdef notdef
336/*
337 * Set a VLAN tag in the receive filter.
338 */
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339static int
340sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan)
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341{
342 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
343 return(EINVAL);
344
345 csr_write_4(sc, SF_RXFILT_HASH_BASE +
346 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
347
348 return(0);
349}
350#endif
351
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352static int
353sf_miibus_readreg(device_t dev, int phy, int reg)
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354{
355 struct sf_softc *sc;
356 int i;
357 u_int32_t val = 0;
358
359 sc = device_get_softc(dev);
360
361 for (i = 0; i < SF_TIMEOUT; i++) {
362 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
363 if (val & SF_MII_DATAVALID)
364 break;
365 }
366
367 if (i == SF_TIMEOUT)
368 return(0);
369
370 if ((val & 0x0000FFFF) == 0xFFFF)
371 return(0);
372
373 return(val & 0x0000FFFF);
374}
375
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376static int
377sf_miibus_writereg(device_t dev, int phy, int reg, int val)
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378{
379 struct sf_softc *sc;
380 int i;
381 int busy;
382
383 sc = device_get_softc(dev);
384
385 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
386
387 for (i = 0; i < SF_TIMEOUT; i++) {
388 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
389 if (!(busy & SF_MII_BUSY))
390 break;
391 }
392
393 return(0);
394}
395
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396static void
397sf_miibus_statchg(device_t dev)
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398{
399 struct sf_softc *sc;
400 struct mii_data *mii;
401
402 sc = device_get_softc(dev);
403 mii = device_get_softc(sc->sf_miibus);
404
405 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
406 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
407 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
408 } else {
409 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
410 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
411 }
412
413 return;
414}
415
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416static void
417sf_setmulti(struct sf_softc *sc)
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418{
419 struct ifnet *ifp;
420 int i;
421 struct ifmultiaddr *ifma;
422 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
423
424 ifp = &sc->arpcom.ac_if;
425
426 /* First zot all the existing filters. */
427 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
428 sf_setperf(sc, i, (char *)&dummy);
429 for (i = SF_RXFILT_HASH_BASE;
430 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
431 csr_write_4(sc, i, 0);
432 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
433
434 /* Now program new ones. */
435 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
436 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
437 } else {
438 i = 1;
441d34b2 439 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
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440 if (ifma->ifma_addr->sa_family != AF_LINK)
441 continue;
442 /*
443 * Program the first 15 multicast groups
444 * into the perfect filter. For all others,
445 * use the hash table.
446 */
447 if (i < SF_RXFILT_PERFECT_CNT) {
448 sf_setperf(sc, i,
449 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
450 i++;
451 continue;
452 }
453
454 sf_sethash(sc,
455 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
456 }
457 }
458
459 return;
460}
461
462/*
463 * Set media options.
464 */
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465static int
466sf_ifmedia_upd(struct ifnet *ifp)
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467{
468 struct sf_softc *sc;
469 struct mii_data *mii;
470
471 sc = ifp->if_softc;
472 mii = device_get_softc(sc->sf_miibus);
473 sc->sf_link = 0;
474 if (mii->mii_instance) {
475 struct mii_softc *miisc;
476 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
477 miisc = LIST_NEXT(miisc, mii_list))
478 mii_phy_reset(miisc);
479 }
480 mii_mediachg(mii);
481
482 return(0);
483}
484
485/*
486 * Report current media status.
487 */
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488static void
489sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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490{
491 struct sf_softc *sc;
492 struct mii_data *mii;
493
494 sc = ifp->if_softc;
495 mii = device_get_softc(sc->sf_miibus);
496
497 mii_pollstat(mii);
498 ifmr->ifm_active = mii->mii_media_active;
499 ifmr->ifm_status = mii->mii_media_status;
500
501 return;
502}
503
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504static int
505sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
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506{
507 struct sf_softc *sc = ifp->if_softc;
508 struct ifreq *ifr = (struct ifreq *) data;
509 struct mii_data *mii;
0966b280 510 int error = 0;
984263bc 511
984263bc 512 switch(command) {
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513 case SIOCSIFFLAGS:
514 if (ifp->if_flags & IFF_UP) {
515 if (ifp->if_flags & IFF_RUNNING &&
516 ifp->if_flags & IFF_PROMISC &&
517 !(sc->sf_if_flags & IFF_PROMISC)) {
518 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
519 } else if (ifp->if_flags & IFF_RUNNING &&
520 !(ifp->if_flags & IFF_PROMISC) &&
521 sc->sf_if_flags & IFF_PROMISC) {
522 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
523 } else if (!(ifp->if_flags & IFF_RUNNING))
524 sf_init(sc);
525 } else {
526 if (ifp->if_flags & IFF_RUNNING)
527 sf_stop(sc);
528 }
529 sc->sf_if_flags = ifp->if_flags;
530 error = 0;
531 break;
532 case SIOCADDMULTI:
533 case SIOCDELMULTI:
534 sf_setmulti(sc);
535 error = 0;
536 break;
537 case SIOCGIFMEDIA:
538 case SIOCSIFMEDIA:
539 mii = device_get_softc(sc->sf_miibus);
540 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
541 break;
542 default:
4cde4dd5 543 error = ether_ioctl(ifp, command, data);
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544 break;
545 }
546
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547 return(error);
548}
549
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550static void
551sf_reset(struct sf_softc *sc)
984263bc 552{
6de3da81 553 int i;
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554
555 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
556 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
557 DELAY(1000);
558 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
559
560 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
561
562 for (i = 0; i < SF_TIMEOUT; i++) {
563 DELAY(10);
564 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
565 break;
566 }
567
568 if (i == SF_TIMEOUT)
e3869ec7 569 kprintf("sf%d: reset never completed!\n", sc->sf_unit);
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570
571 /* Wait a little while for the chip to get its brains in order. */
572 DELAY(1000);
573 return;
574}
575
576/*
577 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
578 * IDs against our list and return a device name if we find a match.
579 * We also check the subsystem ID so that we can identify exactly which
580 * NIC has been found, if possible.
581 */
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582static int
583sf_probe(device_t dev)
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584{
585 struct sf_type *t;
586
587 t = sf_devs;
588
589 while(t->sf_name != NULL) {
590 if ((pci_get_vendor(dev) == t->sf_vid) &&
591 (pci_get_device(dev) == t->sf_did)) {
592 switch((pci_read_config(dev,
593 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
594 case AD_SUBSYSID_62011_REV0:
595 case AD_SUBSYSID_62011_REV1:
596 device_set_desc(dev,
597 "Adaptec ANA-62011 10/100BaseTX");
598 return(0);
599 break;
600 case AD_SUBSYSID_62022:
601 device_set_desc(dev,
602 "Adaptec ANA-62022 10/100BaseTX");
603 return(0);
604 break;
605 case AD_SUBSYSID_62044_REV0:
606 case AD_SUBSYSID_62044_REV1:
607 device_set_desc(dev,
608 "Adaptec ANA-62044 10/100BaseTX");
609 return(0);
610 break;
611 case AD_SUBSYSID_62020:
612 device_set_desc(dev,
613 "Adaptec ANA-62020 10/100BaseFX");
614 return(0);
615 break;
616 case AD_SUBSYSID_69011:
617 device_set_desc(dev,
618 "Adaptec ANA-69011 10/100BaseTX");
619 return(0);
620 break;
621 default:
622 device_set_desc(dev, t->sf_name);
623 return(0);
624 break;
625 }
626 }
627 t++;
628 }
629
630 return(ENXIO);
631}
632
633/*
634 * Attach the interface. Allocate softc structures, do ifmedia
635 * setup and ethernet/BPF attach.
636 */
c436375a
SW
637static int
638sf_attach(device_t dev)
984263bc 639{
0966b280 640 int i;
984263bc
MD
641 u_int32_t command;
642 struct sf_softc *sc;
643 struct ifnet *ifp;
644 int unit, rid, error = 0;
645
984263bc
MD
646 sc = device_get_softc(dev);
647 unit = device_get_unit(dev);
984263bc
MD
648
649 /*
650 * Handle power management nonsense.
651 */
652 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
653 if (command == 0x01) {
654
655 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
656 if (command & SF_PSTATE_MASK) {
657 u_int32_t iobase, membase, irq;
658
659 /* Save important PCI config data. */
660 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
661 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
662 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
663
664 /* Reset the power state. */
e3869ec7 665 kprintf("sf%d: chip is in D%d power mode "
984263bc
MD
666 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
667 command &= 0xFFFFFFFC;
668 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
669
670 /* Restore PCI config data. */
671 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
672 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
673 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
674 }
675 }
676
677 /*
678 * Map control/status registers.
679 */
680 command = pci_read_config(dev, PCIR_COMMAND, 4);
681 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
682 pci_write_config(dev, PCIR_COMMAND, command, 4);
683 command = pci_read_config(dev, PCIR_COMMAND, 4);
684
685#ifdef SF_USEIOSPACE
686 if (!(command & PCIM_CMD_PORTEN)) {
e3869ec7 687 kprintf("sf%d: failed to enable I/O ports!\n", unit);
984263bc 688 error = ENXIO;
0966b280 689 return(error);
984263bc
MD
690 }
691#else
692 if (!(command & PCIM_CMD_MEMEN)) {
e3869ec7 693 kprintf("sf%d: failed to enable memory mapping!\n", unit);
984263bc 694 error = ENXIO;
0966b280 695 return(error);
984263bc
MD
696 }
697#endif
698
699 rid = SF_RID;
4e6d744d 700 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
984263bc
MD
701
702 if (sc->sf_res == NULL) {
e3869ec7 703 kprintf ("sf%d: couldn't map ports\n", unit);
984263bc 704 error = ENXIO;
0966b280 705 return(error);
984263bc
MD
706 }
707
708 sc->sf_btag = rman_get_bustag(sc->sf_res);
709 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
710
711 /* Allocate interrupt */
712 rid = 0;
4e6d744d 713 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
714 RF_SHAREABLE | RF_ACTIVE);
715
716 if (sc->sf_irq == NULL) {
e3869ec7 717 kprintf("sf%d: couldn't map interrupt\n", unit);
984263bc
MD
718 error = ENXIO;
719 goto fail;
720 }
721
007bf9bb 722 callout_init(&sc->sf_stat_timer);
984263bc
MD
723
724 /* Reset the adapter. */
725 sf_reset(sc);
726
727 /*
728 * Get station address from the EEPROM.
729 */
730 for (i = 0; i < ETHER_ADDR_LEN; i++)
731 sc->arpcom.ac_enaddr[i] =
732 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
733
984263bc
MD
734 sc->sf_unit = unit;
735
736 /* Allocate the descriptor queues. */
737 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
e7b4468c 738 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
739
740 if (sc->sf_ldata == NULL) {
e3869ec7 741 kprintf("sf%d: no memory for list buffers!\n", unit);
984263bc
MD
742 error = ENXIO;
743 goto fail;
744 }
745
984263bc
MD
746 /* Do MII setup. */
747 if (mii_phy_probe(dev, &sc->sf_miibus,
748 sf_ifmedia_upd, sf_ifmedia_sts)) {
e3869ec7 749 kprintf("sf%d: MII without any phy!\n", sc->sf_unit);
984263bc
MD
750 error = ENXIO;
751 goto fail;
752 }
753
754 ifp = &sc->arpcom.ac_if;
755 ifp->if_softc = sc;
cdb7d804 756 if_initname(ifp, "sf", unit);
984263bc
MD
757 ifp->if_mtu = ETHERMTU;
758 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
759 ifp->if_ioctl = sf_ioctl;
984263bc
MD
760 ifp->if_start = sf_start;
761 ifp->if_watchdog = sf_watchdog;
762 ifp->if_init = sf_init;
763 ifp->if_baudrate = 10000000;
c49a85fd
JS
764 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
765 ifq_set_ready(&ifp->if_snd);
984263bc
MD
766
767 /*
768 * Call MI attach routine.
769 */
78195a76 770 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
984263bc 771
95893fe4 772 error = bus_setup_intr(dev, sc->sf_irq, INTR_MPSAFE,
78195a76
MD
773 sf_intr, sc, &sc->sf_intrhand,
774 ifp->if_serializer);
0966b280
JS
775
776 if (error) {
777 ether_ifdetach(ifp);
778 device_printf(dev, "couldn't set up irq\n");
779 goto fail;
780 }
781
9db4b353
SZ
782 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sf_irq));
783 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
784
0966b280
JS
785 return(0);
786
984263bc 787fail:
0966b280 788 sf_detach(dev);
984263bc
MD
789 return(error);
790}
791
c436375a
SW
792static int
793sf_detach(device_t dev)
984263bc 794{
0966b280
JS
795 struct sf_softc *sc = device_get_softc(dev);
796 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 797
0966b280 798 if (device_is_attached(dev)) {
cdf89432 799 lwkt_serialize_enter(ifp->if_serializer);
0966b280 800 sf_stop(sc);
cdf89432
SZ
801 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
802 lwkt_serialize_exit(ifp->if_serializer);
803
804 ether_ifdetach(ifp);
0966b280 805 }
984263bc 806
bbb8ae95
JS
807 if (sc->sf_miibus)
808 device_delete_child(dev, sc->sf_miibus);
0966b280 809 bus_generic_detach(dev);
984263bc 810
0966b280
JS
811 if (sc->sf_irq)
812 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
813 if(sc->sf_res)
814 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
815
816 if (sc->sf_ldata) {
817 contigfree(sc->sf_ldata, sizeof(struct sf_list_data),
818 M_DEVBUF);
819 }
984263bc
MD
820
821 return(0);
822}
823
c436375a
SW
824static int
825sf_init_rx_ring(struct sf_softc *sc)
984263bc
MD
826{
827 struct sf_list_data *ld;
828 int i;
829
830 ld = sc->sf_ldata;
831
832 bzero((char *)ld->sf_rx_dlist_big,
833 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
834 bzero((char *)ld->sf_rx_clist,
835 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
836
837 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
838 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
839 return(ENOBUFS);
840 }
841
842 return(0);
843}
844
c436375a
SW
845static void
846sf_init_tx_ring(struct sf_softc *sc)
984263bc
MD
847{
848 struct sf_list_data *ld;
849 int i;
850
851 ld = sc->sf_ldata;
852
853 bzero((char *)ld->sf_tx_dlist,
854 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
855 bzero((char *)ld->sf_tx_clist,
856 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
857
858 for (i = 0; i < SF_TX_DLIST_CNT; i++)
859 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
860 for (i = 0; i < SF_TX_CLIST_CNT; i++)
861 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
862
863 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
864 sc->sf_tx_cnt = 0;
865
866 return;
867}
868
c436375a
SW
869static int
870sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c,
871 struct mbuf *m)
984263bc
MD
872{
873 struct mbuf *m_new = NULL;
874
875 if (m == NULL) {
74f1caca 876 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
877 if (m_new == NULL)
878 return(ENOBUFS);
879
74f1caca 880 MCLGET(m_new, MB_DONTWAIT);
984263bc
MD
881 if (!(m_new->m_flags & M_EXT)) {
882 m_freem(m_new);
883 return(ENOBUFS);
884 }
885 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
886 } else {
887 m_new = m;
888 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
889 m_new->m_data = m_new->m_ext.ext_buf;
890 }
891
892 m_adj(m_new, sizeof(u_int64_t));
893
894 c->sf_mbuf = m_new;
895 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
896 c->sf_valid = 1;
897
898 return(0);
899}
900
901/*
902 * The starfire is programmed to use 'normal' mode for packet reception,
903 * which means we use the consumer/producer model for both the buffer
904 * descriptor queue and the completion descriptor queue. The only problem
905 * with this is that it involves a lot of register accesses: we have to
906 * read the RX completion consumer and producer indexes and the RX buffer
907 * producer index, plus the RX completion consumer and RX buffer producer
908 * indexes have to be updated. It would have been easier if Adaptec had
909 * put each index in a separate register, especially given that the damn
910 * NIC has a 512K register space.
911 *
912 * In spite of all the lovely features that Adaptec crammed into the 6915,
913 * it is marred by one truly stupid design flaw, which is that receive
914 * buffer addresses must be aligned on a longword boundary. This forces
915 * the packet payload to be unaligned, which is suboptimal on the x86 and
916 * completely unuseable on the Alpha. Our only recourse is to copy received
917 * packets into properly aligned buffers before handing them off.
918 */
919
c436375a
SW
920static void
921sf_rxeof(struct sf_softc *sc)
984263bc 922{
984263bc
MD
923 struct mbuf *m;
924 struct ifnet *ifp;
925 struct sf_rx_bufdesc_type0 *desc;
926 struct sf_rx_cmpdesc_type3 *cur_rx;
927 u_int32_t rxcons, rxprod;
928 int cmpprodidx, cmpconsidx, bufprodidx;
929
930 ifp = &sc->arpcom.ac_if;
931
932 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
933 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
934 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
935 cmpconsidx = SF_IDX_LO(rxcons);
936 bufprodidx = SF_IDX_LO(rxprod);
937
938 while (cmpconsidx != cmpprodidx) {
939 struct mbuf *m0;
940
941 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
942 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
943 m = desc->sf_mbuf;
944 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
945 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
946
947 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
948 ifp->if_ierrors++;
949 sf_newbuf(sc, desc, m);
950 continue;
951 }
952
953 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
954 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
955 sf_newbuf(sc, desc, m);
956 if (m0 == NULL) {
957 ifp->if_ierrors++;
958 continue;
959 }
960 m_adj(m0, ETHER_ALIGN);
961 m = m0;
962
984263bc
MD
963 ifp->if_ipackets++;
964
78195a76 965 ifp->if_input(ifp, m);
984263bc
MD
966 }
967
968 csr_write_4(sc, SF_CQ_CONSIDX,
969 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
970 csr_write_4(sc, SF_RXDQ_PTR_Q1,
971 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
972
973 return;
974}
975
976/*
977 * Read the transmit status from the completion queue and release
978 * mbufs. Note that the buffer descriptor index in the completion
979 * descriptor is an offset from the start of the transmit buffer
980 * descriptor list in bytes. This is important because the manual
981 * gives the impression that it should match the producer/consumer
982 * index, which is the offset in 8 byte blocks.
983 */
c436375a
SW
984static void
985sf_txeof(struct sf_softc *sc)
984263bc
MD
986{
987 int txcons, cmpprodidx, cmpconsidx;
988 struct sf_tx_cmpdesc_type1 *cur_cmp;
989 struct sf_tx_bufdesc_type0 *cur_tx;
990 struct ifnet *ifp;
991
992 ifp = &sc->arpcom.ac_if;
993
994 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
995 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
996 cmpconsidx = SF_IDX_HI(txcons);
997
998 while (cmpconsidx != cmpprodidx) {
999 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1000 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1001
1002 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1003 ifp->if_opackets++;
1004 else {
1005 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1006 sf_txthresh_adjust(sc);
1007 ifp->if_oerrors++;
1008 }
1009
1010 sc->sf_tx_cnt--;
1011 if (cur_tx->sf_mbuf != NULL) {
1012 m_freem(cur_tx->sf_mbuf);
1013 cur_tx->sf_mbuf = NULL;
1014 } else
1015 break;
1016 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1017 }
1018
1019 ifp->if_timer = 0;
1020 ifp->if_flags &= ~IFF_OACTIVE;
1021
1022 csr_write_4(sc, SF_CQ_CONSIDX,
1023 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1024 ((cmpconsidx << 16) & 0xFFFF0000));
1025
1026 return;
1027}
1028
c436375a
SW
1029static void
1030sf_txthresh_adjust(struct sf_softc *sc)
984263bc
MD
1031{
1032 u_int32_t txfctl;
1033 u_int8_t txthresh;
1034
1035 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1036 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1037 if (txthresh < 0xFF) {
1038 txthresh++;
1039 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1040 txfctl |= txthresh;
1041#ifdef DIAGNOSTIC
e3869ec7 1042 kprintf("sf%d: tx underrun, increasing "
984263bc
MD
1043 "tx threshold to %d bytes\n",
1044 sc->sf_unit, txthresh * 4);
1045#endif
1046 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1047 }
1048
1049 return;
1050}
1051
c436375a
SW
1052static void
1053sf_intr(void *arg)
984263bc
MD
1054{
1055 struct sf_softc *sc;
1056 struct ifnet *ifp;
1057 u_int32_t status;
1058
1059 sc = arg;
1060 ifp = &sc->arpcom.ac_if;
1061
1062 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1063 return;
1064
1065 /* Disable interrupts. */
1066 csr_write_4(sc, SF_IMR, 0x00000000);
1067
1068 for (;;) {
1069 status = csr_read_4(sc, SF_ISR);
1070 if (status)
1071 csr_write_4(sc, SF_ISR, status);
1072
1073 if (!(status & SF_INTRS))
1074 break;
1075
1076 if (status & SF_ISR_RXDQ1_DMADONE)
1077 sf_rxeof(sc);
1078
1079 if (status & SF_ISR_TX_TXDONE ||
1080 status & SF_ISR_TX_DMADONE ||
1081 status & SF_ISR_TX_QUEUEDONE)
1082 sf_txeof(sc);
1083
1084 if (status & SF_ISR_TX_LOFIFO)
1085 sf_txthresh_adjust(sc);
1086
1087 if (status & SF_ISR_ABNORMALINTR) {
1088 if (status & SF_ISR_STATSOFLOW) {
007bf9bb 1089 callout_stop(&sc->sf_stat_timer);
984263bc
MD
1090 sf_stats_update(sc);
1091 } else
1092 sf_init(sc);
1093 }
1094 }
1095
1096 /* Re-enable interrupts. */
1097 csr_write_4(sc, SF_IMR, SF_INTRS);
1098
c49a85fd 1099 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1100 if_devstart(ifp);
984263bc
MD
1101}
1102
c436375a
SW
1103static void
1104sf_init(void *xsc)
984263bc 1105{
0966b280
JS
1106 struct sf_softc *sc = xsc;
1107 struct ifnet *ifp = &sc->arpcom.ac_if;
1108 int i;
984263bc 1109
984263bc
MD
1110 sf_stop(sc);
1111 sf_reset(sc);
1112
1113 /* Init all the receive filter registers */
1114 for (i = SF_RXFILT_PERFECT_BASE;
1115 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1116 csr_write_4(sc, i, 0);
1117
1118 /* Empty stats counter registers. */
1119 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1120 csr_write_4(sc, SF_STATS_BASE +
1121 (i + sizeof(u_int32_t)), 0);
1122
1123 /* Init our MAC address */
1124 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1125 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1126 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1127
1128 if (sf_init_rx_ring(sc) == ENOBUFS) {
e3869ec7 1129 kprintf("sf%d: initialization failed: no "
984263bc 1130 "memory for rx buffers\n", sc->sf_unit);
984263bc
MD
1131 return;
1132 }
1133
1134 sf_init_tx_ring(sc);
1135
1136 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1137
1138 /* If we want promiscuous mode, set the allframes bit. */
1139 if (ifp->if_flags & IFF_PROMISC) {
1140 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1141 } else {
1142 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1143 }
1144
1145 if (ifp->if_flags & IFF_BROADCAST) {
1146 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1147 } else {
1148 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1149 }
1150
1151 /*
1152 * Load the multicast filter.
1153 */
1154 sf_setmulti(sc);
1155
1156 /* Init the completion queue indexes */
1157 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1158 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1159
1160 /* Init the RX completion queue */
1161 csr_write_4(sc, SF_RXCQ_CTL_1,
1162 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1163 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1164
1165 /* Init RX DMA control. */
1166 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1167
1168 /* Init the RX buffer descriptor queue. */
1169 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1170 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1171 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1172 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1173
1174 /* Init the TX completion queue */
1175 csr_write_4(sc, SF_TXCQ_CTL,
1176 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1177
1178 /* Init the TX buffer descriptor queue. */
1179 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1180 vtophys(sc->sf_ldata->sf_tx_dlist));
1181 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1182 csr_write_4(sc, SF_TXDQ_CTL,
1183 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1184 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1185
1186 /* Enable autopadding of short TX frames. */
1187 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1188
1189 /* Enable interrupts. */
1190 csr_write_4(sc, SF_IMR, SF_INTRS);
1191 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1192
1193 /* Enable the RX and TX engines. */
1194 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1195 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1196
1197 /*mii_mediachg(mii);*/
1198 sf_ifmedia_upd(ifp);
1199
1200 ifp->if_flags |= IFF_RUNNING;
1201 ifp->if_flags &= ~IFF_OACTIVE;
1202
007bf9bb 1203 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
984263bc
MD
1204}
1205
c436375a
SW
1206static int
1207sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c,
1208 struct mbuf *m_head)
984263bc
MD
1209{
1210 int frag = 0;
1211 struct sf_frag *f = NULL;
1212 struct mbuf *m;
1213
9db4b353 1214 for (m = m_head; m != NULL; m = m->m_next) {
984263bc
MD
1215 if (m->m_len != 0) {
1216 if (frag == SF_MAXFRAGS)
1217 break;
1218 f = &c->sf_frags[frag];
1219 if (frag == 0)
1220 f->sf_pktlen = m_head->m_pkthdr.len;
1221 f->sf_fraglen = m->m_len;
1222 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1223 frag++;
1224 }
1225 }
9db4b353
SZ
1226 /* Caller should make sure that 'm_head' is not excessive fragmented */
1227 KASSERT(m == NULL, ("too many fragments\n"));
984263bc
MD
1228
1229 c->sf_mbuf = m_head;
1230 c->sf_id = SF_TX_BUFDESC_ID;
1231 c->sf_fragcnt = frag;
1232 c->sf_intr = 1;
1233 c->sf_caltcp = 0;
1234 c->sf_crcen = 1;
1235
1236 return(0);
1237}
1238
c436375a
SW
1239static void
1240sf_start(struct ifnet *ifp)
984263bc
MD
1241{
1242 struct sf_softc *sc;
1243 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
9db4b353
SZ
1244 struct mbuf *m_head = NULL, *m_defragged;
1245 int i, txprod, need_trans = 0;
984263bc
MD
1246
1247 sc = ifp->if_softc;
1248
9db4b353
SZ
1249 if (!sc->sf_link) {
1250 ifq_purge(&ifp->if_snd);
984263bc 1251 return;
9db4b353 1252 }
984263bc 1253
9db4b353 1254 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
984263bc
MD
1255 return;
1256
1257 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1258 i = SF_IDX_HI(txprod) >> 4;
1259
1260 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
e3869ec7 1261 kprintf("sf%d: TX ring full, resetting\n", sc->sf_unit);
984263bc
MD
1262 sf_init(sc);
1263 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1264 i = SF_IDX_HI(txprod) >> 4;
1265 }
1266
9db4b353
SZ
1267 while (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1268 struct mbuf *m;
1269 int frag;
1270
1271 /*
1272 * Don't get the TX DMA queue get too full.
1273 */
1274 if (sc->sf_tx_cnt > 64) {
1275 ifp->if_flags |= IFF_OACTIVE;
1276 break;
1277 }
1278#ifdef foo
984263bc
MD
1279 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1280 ifp->if_flags |= IFF_OACTIVE;
984263bc
MD
1281 break;
1282 }
9db4b353
SZ
1283#endif
1284
1285 m_defragged = NULL;
1286 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1287 if (m_head == NULL)
1288 break;
1289
9db4b353
SZ
1290again:
1291 frag = 0;
1292 for (m = m_head; m != NULL; m = m->m_next)
1293 ++frag;
1294 if (frag > SF_MAXFRAGS) {
1295 if (m_defragged != NULL) {
1296 /*
1297 * Even after defragmentation, there
1298 * are still too many fragments, so
1299 * drop this packet.
1300 */
1301 m_freem(m_head);
1302 continue;
1303 }
1304
1305 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1306 if (m_defragged == NULL) {
1307 m_freem(m_head);
1308 continue;
1309 }
1310 m_head = m_defragged;
1311
1312 /* Recount # of fragments */
1313 goto again;
984263bc 1314 }
9db4b353
SZ
1315
1316 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1317 sf_encap(sc, cur_tx, m_head);
c49a85fd 1318 BPF_MTAP(ifp, cur_tx->sf_mbuf);
984263bc
MD
1319
1320 SF_INC(i, SF_TX_DLIST_CNT);
1321 sc->sf_tx_cnt++;
9db4b353 1322 need_trans = 1;
984263bc
MD
1323 }
1324
9db4b353 1325 if (!need_trans)
984263bc
MD
1326 return;
1327
1328 /* Transmit */
1329 csr_write_4(sc, SF_TXDQ_PRODIDX,
1330 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1331 ((i << 20) & 0xFFFF0000));
1332
1333 ifp->if_timer = 5;
984263bc
MD
1334}
1335
c436375a
SW
1336static void
1337sf_stop(struct sf_softc *sc)
984263bc
MD
1338{
1339 int i;
1340 struct ifnet *ifp;
1341
1342 ifp = &sc->arpcom.ac_if;
1343
007bf9bb 1344 callout_stop(&sc->sf_stat_timer);
984263bc
MD
1345
1346 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1347 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1348 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1349 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1350 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1351 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1352 csr_write_4(sc, SF_TXCQ_CTL, 0);
1353 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1354 csr_write_4(sc, SF_TXDQ_CTL, 0);
1355 sf_reset(sc);
1356
1357 sc->sf_link = 0;
1358
1359 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1360 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1361 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1362 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1363 }
1364 }
1365
1366 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1367 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1368 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1369 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1370 }
1371 }
1372
1373 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1374
1375 return;
1376}
1377
1378/*
1379 * Note: it is important that this function not be interrupted. We
1380 * use a two-stage register access scheme: if we are interrupted in
1381 * between setting the indirect address register and reading from the
1382 * indirect data register, the contents of the address register could
1383 * be changed out from under us.
1384 */
c436375a
SW
1385static void
1386sf_stats_update(void *xsc)
984263bc 1387{
0966b280
JS
1388 struct sf_softc *sc = xsc;
1389 struct ifnet *ifp = &sc->arpcom.ac_if;
1390 struct mii_data *mii = device_get_softc(sc->sf_miibus);
984263bc
MD
1391 struct sf_stats stats;
1392 u_int32_t *ptr;
0966b280 1393 int i;
984263bc 1394
78195a76 1395 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
1396
1397 ptr = (u_int32_t *)&stats;
1398 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1399 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1400 (i + sizeof(u_int32_t)));
1401
1402 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1403 csr_write_4(sc, SF_STATS_BASE +
1404 (i + sizeof(u_int32_t)), 0);
1405
1406 ifp->if_collisions += stats.sf_tx_single_colls +
1407 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1408
1409 mii_tick(mii);
1410 if (!sc->sf_link) {
1411 mii_pollstat(mii);
1412 if (mii->mii_media_status & IFM_ACTIVE &&
9db4b353 1413 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
984263bc 1414 sc->sf_link++;
c49a85fd 1415 if (!ifq_is_empty(&ifp->if_snd))
9db4b353
SZ
1416 if_devstart(ifp);
1417 }
984263bc
MD
1418 }
1419
007bf9bb 1420 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
984263bc 1421
78195a76 1422 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1423}
1424
c436375a
SW
1425static void
1426sf_watchdog(struct ifnet *ifp)
984263bc
MD
1427{
1428 struct sf_softc *sc;
1429
1430 sc = ifp->if_softc;
1431
1432 ifp->if_oerrors++;
e3869ec7 1433 kprintf("sf%d: watchdog timeout\n", sc->sf_unit);
984263bc
MD
1434
1435 sf_stop(sc);
1436 sf_reset(sc);
1437 sf_init(sc);
1438
c49a85fd 1439 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1440 if_devstart(ifp);
984263bc
MD
1441}
1442
c436375a
SW
1443static void
1444sf_shutdown(device_t dev)
984263bc 1445{
78195a76
MD
1446 struct sf_softc *sc;
1447 struct ifnet *ifp;
984263bc
MD
1448
1449 sc = device_get_softc(dev);
78195a76
MD
1450 ifp = &sc->arpcom.ac_if;
1451 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1452 sf_stop(sc);
78195a76 1453 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1454
1455 return;
1456}