network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / sk / if_sk.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998, 1999, 2000
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
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32 * $OpenBSD: if_sk.c,v 1.129 2006/10/16 12:30:08 tom Exp $
33 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
9165dea4 34 * $DragonFly: src/sys/dev/netif/sk/if_sk.c,v 1.58 2008/10/12 11:17:08 sephe Exp $
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35 */
36
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37/*
38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
39 *
40 * Permission to use, copy, modify, and distribute this software for any
41 * purpose with or without fee is hereby granted, provided that the above
42 * copyright notice and this permission notice appear in all copies.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
51 */
52
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53/*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
ce17751a 58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
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59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
ce17751a 61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
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62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71
72/*
73 * The SysKonnect gigabit ethernet adapters consist of two main
74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
76 * components and a PHY while the GEnesis controller provides a PCI
77 * interface with DMA support. Each card may have between 512K and
78 * 2MB of SRAM on board depending on the configuration.
79 *
80 * The SysKonnect GEnesis controller can have either one or two XMAC
81 * chips connected to it, allowing single or dual port NIC configurations.
82 * SysKonnect has the distinction of being the only vendor on the market
83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
85 * XMAC registers. This driver takes advantage of these features to allow
86 * both XMACs to operate as independent interfaces.
87 */
88
89#include <sys/param.h>
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90#include <sys/bus.h>
91#include <sys/endian.h>
92#include <sys/in_cksum.h>
93#include <sys/kernel.h>
9db4b353 94#include <sys/interrupt.h>
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95#include <sys/mbuf.h>
96#include <sys/malloc.h>
984263bc 97#include <sys/queue.h>
1f7ab7c9 98#include <sys/rman.h>
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99#include <sys/serialize.h>
100#include <sys/socket.h>
101#include <sys/sockio.h>
dbe44a55 102#include <sys/sysctl.h>
984263bc 103
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104#include <net/bpf.h>
105#include <net/ethernet.h>
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106#include <net/if.h>
107#include <net/if_arp.h>
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108#include <net/if_dl.h>
109#include <net/if_media.h>
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110#include <net/ifq_var.h>
111#include <net/vlan/if_vlan_var.h>
984263bc 112
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113#include <netinet/ip.h>
114#include <netinet/udp.h>
984263bc 115
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116#include <dev/netif/mii_layer/mii.h>
117#include <dev/netif/mii_layer/miivar.h>
118#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 119
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120#include <bus/pci/pcireg.h>
121#include <bus/pci/pcivar.h>
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122#include <bus/pci/pcidevs.h>
123
124#include <dev/netif/sk/if_skreg.h>
125#include <dev/netif/sk/yukonreg.h>
126#include <dev/netif/sk/xmaciireg.h>
127#include <dev/netif/sk/if_skvar.h>
128
129#include "miibus_if.h"
984263bc 130
1fb1e4cd 131#if 0
ce17751a 132#define SK_DEBUG
1fb1e4cd 133#endif
984263bc 134
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135#if 0
136#define SK_RXCSUM
137#endif
984263bc 138
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139/* supported device vendors */
140static const struct skc_type {
141 uint16_t skc_vid;
142 uint16_t skc_did;
143 const char *skc_name;
144} skc_devs[] = {
145 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940,
146 "3Com 3C940" },
147 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B,
148 "3Com 3C940B" },
149
150 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD,
151 "CNet GigaCard" },
152
153 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1,
154 "D-Link DGE-530T A1" },
155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1,
156 "D-Link DGE-530T B1" },
157
158 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
159 "Linksys EG1032 v2" },
160 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064,
161 "Linksys EG1064" },
162
163 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON,
164 "Marvell Yukon 88E8001/8003/8010" },
165 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN,
166 "Belkin F5D5005" },
167
168 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE,
169 "SysKonnect SK-NET" },
170 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2,
171 "SysKonnect SK9821 v2" },
984263bc 172
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173 { 0, 0, NULL }
174};
175
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176static int skc_probe(device_t);
177static int skc_attach(device_t);
178static int skc_detach(device_t);
179static void skc_shutdown(device_t);
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180static int skc_sysctl_imtime(SYSCTL_HANDLER_ARGS);
181
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182static int sk_probe(device_t);
183static int sk_attach(device_t);
184static int sk_detach(device_t);
185static void sk_tick(void *);
ce17751a 186static void sk_yukon_tick(void *);
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187static void sk_intr(void *);
188static void sk_intr_bcom(struct sk_if_softc *);
189static void sk_intr_xmac(struct sk_if_softc *);
190static void sk_intr_yukon(struct sk_if_softc *);
191static void sk_rxeof(struct sk_if_softc *);
192static void sk_txeof(struct sk_if_softc *);
fcbf2fb6 193static int sk_encap(struct sk_if_softc *, struct mbuf **, uint32_t *);
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194static void sk_start(struct ifnet *);
195static int sk_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
196static void sk_init(void *);
197static void sk_init_xmac(struct sk_if_softc *);
198static void sk_init_yukon(struct sk_if_softc *);
199static void sk_stop(struct sk_if_softc *);
200static void sk_watchdog(struct ifnet *);
201static int sk_ifmedia_upd(struct ifnet *);
202static void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
203static void sk_reset(struct sk_softc *);
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204static int sk_newbuf_jumbo(struct sk_if_softc *, int, int);
205static int sk_newbuf_std(struct sk_if_softc *, int, int);
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206static int sk_jpool_alloc(device_t);
207static void sk_jpool_free(struct sk_if_softc *);
208static struct sk_jpool_entry
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209 *sk_jalloc(struct sk_if_softc *);
210static void sk_jfree(void *);
211static void sk_jref(void *);
c352b0ba 212static int sk_init_rx_ring(struct sk_if_softc *);
ce17751a 213static int sk_init_tx_ring(struct sk_if_softc *);
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214
215static int sk_miibus_readreg(device_t, int, int);
216static int sk_miibus_writereg(device_t, int, int, int);
217static void sk_miibus_statchg(device_t);
218
219static int sk_xmac_miibus_readreg(struct sk_if_softc *, int, int);
220static int sk_xmac_miibus_writereg(struct sk_if_softc *, int, int, int);
221static void sk_xmac_miibus_statchg(struct sk_if_softc *);
222
223static int sk_marv_miibus_readreg(struct sk_if_softc *, int, int);
224static int sk_marv_miibus_writereg(struct sk_if_softc *, int, int, int);
225static void sk_marv_miibus_statchg(struct sk_if_softc *);
226
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227static void sk_setfilt(struct sk_if_softc *, caddr_t, int);
228static void sk_setmulti(struct sk_if_softc *);
229static void sk_setpromisc(struct sk_if_softc *);
984263bc 230
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231#ifdef SK_RXCSUM
232static void sk_rxcsum(struct ifnet *, struct mbuf *, const uint16_t,
233 const uint16_t);
234#endif
235static int sk_dma_alloc(device_t);
236static void sk_dma_free(device_t);
237
ce17751a 238#ifdef SK_DEBUG
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239#define DPRINTF(x) if (skdebug) kprintf x
240#define DPRINTFN(n,x) if (skdebug >= (n)) kprintf x
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241static int skdebug = 2;
242
243static void sk_dump_txdesc(struct sk_tx_desc *, int);
244static void sk_dump_mbuf(struct mbuf *);
245static void sk_dump_bytes(const char *, int);
984263bc 246#else
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247#define DPRINTF(x)
248#define DPRINTFN(n,x)
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249#endif
250
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251/* Interrupt moderation time. */
252static int skc_imtime = SK_IMTIME_DEFAULT;
253TUNABLE_INT("hw.skc.imtime", &skc_imtime);
254
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255/*
256 * Note that we have newbus methods for both the GEnesis controller
257 * itself and the XMAC(s). The XMACs are children of the GEnesis, and
258 * the miibus code is a child of the XMACs. We need to do it this way
259 * so that the miibus drivers can access the PHY registers on the
260 * right PHY. It's not quite what I had in mind, but it's the only
261 * design that achieves the desired effect.
262 */
263static device_method_t skc_methods[] = {
264 /* Device interface */
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265 DEVMETHOD(device_probe, skc_probe),
266 DEVMETHOD(device_attach, skc_attach),
267 DEVMETHOD(device_detach, skc_detach),
268 DEVMETHOD(device_shutdown, skc_shutdown),
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269
270 /* bus interface */
271 DEVMETHOD(bus_print_child, bus_generic_print_child),
272 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
273
274 { 0, 0 }
275};
276
c352b0ba 277static DEFINE_CLASS_0(skc, skc_driver, skc_methods, sizeof(struct sk_softc));
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278static devclass_t skc_devclass;
279
280static device_method_t sk_methods[] = {
281 /* Device interface */
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282 DEVMETHOD(device_probe, sk_probe),
283 DEVMETHOD(device_attach, sk_attach),
284 DEVMETHOD(device_detach, sk_detach),
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285 DEVMETHOD(device_shutdown, bus_generic_shutdown),
286
287 /* bus interface */
288 DEVMETHOD(bus_print_child, bus_generic_print_child),
289 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
290
291 /* MII interface */
292 DEVMETHOD(miibus_readreg, sk_miibus_readreg),
293 DEVMETHOD(miibus_writereg, sk_miibus_writereg),
294 DEVMETHOD(miibus_statchg, sk_miibus_statchg),
295
296 { 0, 0 }
297};
298
c352b0ba 299static DEFINE_CLASS_0(sk, sk_driver, sk_methods, sizeof(struct sk_if_softc));
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300static devclass_t sk_devclass;
301
32832096 302DECLARE_DUMMY_MODULE(if_sk);
984263bc 303DRIVER_MODULE(if_sk, pci, skc_driver, skc_devclass, 0, 0);
32832096 304DRIVER_MODULE(if_sk, skc, sk_driver, sk_devclass, 0, 0);
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305DRIVER_MODULE(miibus, sk, miibus_driver, miibus_devclass, 0, 0);
306
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307static __inline uint32_t
308sk_win_read_4(struct sk_softc *sc, uint32_t reg)
984263bc 309{
ce17751a 310 return CSR_READ_4(sc, reg);
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311}
312
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313static __inline uint16_t
314sk_win_read_2(struct sk_softc *sc, uint32_t reg)
984263bc 315{
ce17751a 316 return CSR_READ_2(sc, reg);
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317}
318
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319static __inline uint8_t
320sk_win_read_1(struct sk_softc *sc, uint32_t reg)
984263bc 321{
ce17751a 322 return CSR_READ_1(sc, reg);
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323}
324
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325static __inline void
326sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
984263bc 327{
ce17751a 328 CSR_WRITE_4(sc, reg, x);
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329}
330
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331static __inline void
332sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
984263bc 333{
ce17751a 334 CSR_WRITE_2(sc, reg, x);
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335}
336
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337static __inline void
338sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
984263bc 339{
ce17751a 340 CSR_WRITE_1(sc, reg, x);
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341}
342
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343static __inline int
344sk_newbuf(struct sk_if_softc *sc_if, int idx, int wait)
345{
346 int ret;
347
348 if (sc_if->sk_use_jumbo)
349 ret = sk_newbuf_jumbo(sc_if, idx, wait);
350 else
351 ret = sk_newbuf_std(sc_if, idx, wait);
352 return ret;
353}
354
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355static int
356sk_miibus_readreg(device_t dev, int phy, int reg)
984263bc 357{
c352b0ba 358 struct sk_if_softc *sc_if = device_get_softc(dev);
984263bc 359
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360 if (SK_IS_GENESIS(sc_if->sk_softc))
361 return sk_xmac_miibus_readreg(sc_if, phy, reg);
362 else
363 return sk_marv_miibus_readreg(sc_if, phy, reg);
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364}
365
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366static int
367sk_miibus_writereg(device_t dev, int phy, int reg, int val)
1fb1e4cd 368{
c352b0ba 369 struct sk_if_softc *sc_if = device_get_softc(dev);
1fb1e4cd 370
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371 if (SK_IS_GENESIS(sc_if->sk_softc))
372 return sk_xmac_miibus_writereg(sc_if, phy, reg, val);
373 else
374 return sk_marv_miibus_writereg(sc_if, phy, reg, val);
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375}
376
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377static void
378sk_miibus_statchg(device_t dev)
1fb1e4cd 379{
c352b0ba 380 struct sk_if_softc *sc_if = device_get_softc(dev);
1fb1e4cd 381
ce17751a 382 if (SK_IS_GENESIS(sc_if->sk_softc))
1fb1e4cd 383 sk_xmac_miibus_statchg(sc_if);
ce17751a 384 else
1fb1e4cd 385 sk_marv_miibus_statchg(sc_if);
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386}
387
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388static int
389sk_xmac_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
1fb1e4cd 390{
c352b0ba 391 int i;
1fb1e4cd 392
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393 DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
394
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395 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
396 return(0);
397
398 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
399 SK_XM_READ_2(sc_if, XM_PHY_DATA);
400 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
401 for (i = 0; i < SK_TIMEOUT; i++) {
402 DELAY(1);
403 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
404 XM_MMUCMD_PHYDATARDY)
405 break;
406 }
407
408 if (i == SK_TIMEOUT) {
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409 if_printf(&sc_if->arpcom.ac_if,
410 "phy failed to come ready\n");
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411 return(0);
412 }
413 }
414 DELAY(1);
415 return(SK_XM_READ_2(sc_if, XM_PHY_DATA));
416}
417
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418static int
419sk_xmac_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
984263bc 420{
c352b0ba 421 int i;
984263bc 422
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423 DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
424
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425 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
426 for (i = 0; i < SK_TIMEOUT; i++) {
c352b0ba 427 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
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428 break;
429 }
430
431 if (i == SK_TIMEOUT) {
ce17751a 432 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
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433 return(ETIMEDOUT);
434 }
435
436 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
437 for (i = 0; i < SK_TIMEOUT; i++) {
438 DELAY(1);
c352b0ba 439 if ((SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY) == 0)
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440 break;
441 }
442
443 if (i == SK_TIMEOUT)
ce17751a 444 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
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445 return(0);
446}
447
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448static void
449sk_xmac_miibus_statchg(struct sk_if_softc *sc_if)
1fb1e4cd 450{
c352b0ba 451 struct mii_data *mii;
984263bc 452
984263bc 453 mii = device_get_softc(sc_if->sk_miibus);
ce17751a 454 DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
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455
456 /*
457 * If this is a GMII PHY, manually set the XMAC's
458 * duplex mode accordingly.
459 */
460 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
c352b0ba 461 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
984263bc 462 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
c352b0ba 463 else
984263bc 464 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
984263bc 465 }
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466}
467
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468static int
469sk_marv_miibus_readreg(struct sk_if_softc *sc_if, int phy, int reg)
1fb1e4cd 470{
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471 uint16_t val;
472 int i;
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473
474 if (phy != 0 ||
475 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
476 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
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477 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
478 phy, reg));
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479 return(0);
480 }
481
482 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
483 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
484
485 for (i = 0; i < SK_TIMEOUT; i++) {
486 DELAY(1);
487 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
488 if (val & YU_SMICR_READ_VALID)
489 break;
490 }
491
492 if (i == SK_TIMEOUT) {
ce17751a 493 if_printf(&sc_if->arpcom.ac_if, "phy failed to come ready\n");
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494 return(0);
495 }
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496
497 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
498 SK_TIMEOUT));
c352b0ba 499
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500 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
501
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502 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
503 phy, reg, val));
504
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505 return(val);
506}
507
c352b0ba
JS
508static int
509sk_marv_miibus_writereg(struct sk_if_softc *sc_if, int phy, int reg, int val)
1fb1e4cd 510{
c352b0ba 511 int i;
1fb1e4cd 512
ce17751a
SZ
513 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
514 phy, reg, val));
515
1fb1e4cd
MD
516 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
517 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
518 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
519
520 for (i = 0; i < SK_TIMEOUT; i++) {
521 DELAY(1);
522 if (SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY)
523 break;
524 }
525
ce17751a
SZ
526 if (i == SK_TIMEOUT)
527 if_printf(&sc_if->arpcom.ac_if, "phy write timed out\n");
528
1fb1e4cd
MD
529 return(0);
530}
531
c352b0ba
JS
532static void
533sk_marv_miibus_statchg(struct sk_if_softc *sc_if)
1fb1e4cd 534{
ce17751a
SZ
535 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
536 SK_YU_READ_2(sc_if, YUKON_GPCR)));
537}
538
539#define HASH_BITS 6
540
541static uint32_t
542sk_xmac_hash(caddr_t addr)
543{
544 uint32_t crc;
545
546 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
547 return (~crc & ((1 << HASH_BITS) - 1));
1fb1e4cd
MD
548}
549
ce17751a
SZ
550static uint32_t
551sk_yukon_hash(caddr_t addr)
552{
553 uint32_t crc;
554
555 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
556 return (crc & ((1 << HASH_BITS) - 1));
557}
984263bc 558
7b9f668c
SW
559static void
560sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
984263bc 561{
c352b0ba 562 int base;
984263bc
MD
563
564 base = XM_RXFILT_ENTRY(slot);
565
c352b0ba
JS
566 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
567 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
568 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
984263bc
MD
569}
570
c352b0ba
JS
571static void
572sk_setmulti(struct sk_if_softc *sc_if)
984263bc 573{
c352b0ba
JS
574 struct sk_softc *sc = sc_if->sk_softc;
575 struct ifnet *ifp = &sc_if->arpcom.ac_if;
576 uint32_t hashes[2] = { 0, 0 };
ce17751a 577 int h = 0, i;
c352b0ba
JS
578 struct ifmultiaddr *ifma;
579 uint8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
984263bc
MD
580
581 /* First, zot all the existing filters. */
1fb1e4cd
MD
582 switch(sc->sk_type) {
583 case SK_GENESIS:
584 for (i = 1; i < XM_RXFILT_MAX; i++)
585 sk_setfilt(sc_if, (caddr_t)&dummy, i);
586
587 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
588 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
589 break;
590 case SK_YUKON:
ce17751a
SZ
591 case SK_YUKON_LITE:
592 case SK_YUKON_LP:
1fb1e4cd
MD
593 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
594 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
595 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
596 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
597 break;
598 }
984263bc
MD
599
600 /* Now program new ones. */
601 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
602 hashes[0] = 0xFFFFFFFF;
603 hashes[1] = 0xFFFFFFFF;
604 } else {
605 i = 1;
606 /* First find the tail of the list. */
441d34b2
SW
607 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead,
608 ifma_link) {
ce17751a
SZ
609 caddr_t maddr;
610
984263bc
MD
611 if (ifma->ifma_addr->sa_family != AF_LINK)
612 continue;
ce17751a
SZ
613
614 maddr = LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
615
984263bc
MD
616 /*
617 * Program the first XM_RXFILT_MAX multicast groups
618 * into the perfect filter. For all others,
619 * use the hash table.
620 */
ce17751a
SZ
621 if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
622 sk_setfilt(sc_if, maddr, i);
984263bc
MD
623 i++;
624 continue;
625 }
626
ce17751a
SZ
627 switch(sc->sk_type) {
628 case SK_GENESIS:
629 h = sk_xmac_hash(maddr);
630 break;
631
632 case SK_YUKON:
633 case SK_YUKON_LITE:
634 case SK_YUKON_LP:
635 h = sk_yukon_hash(maddr);
636 break;
637 }
638 if (h < 32)
639 hashes[0] |= (1 << h);
640 else
641 hashes[1] |= (1 << (h - 32));
984263bc
MD
642 }
643 }
644
1fb1e4cd
MD
645 switch(sc->sk_type) {
646 case SK_GENESIS:
647 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
648 XM_MODE_RX_USE_PERFECT);
649 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
650 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
651 break;
652 case SK_YUKON:
ce17751a
SZ
653 case SK_YUKON_LITE:
654 case SK_YUKON_LP:
1fb1e4cd
MD
655 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
656 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
657 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
658 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
659 break;
660 }
984263bc
MD
661}
662
c352b0ba
JS
663static void
664sk_setpromisc(struct sk_if_softc *sc_if)
0d939d2c 665{
ce17751a 666 struct sk_softc *sc = sc_if->sk_softc;
c352b0ba 667 struct ifnet *ifp = &sc_if->arpcom.ac_if;
0d939d2c
MD
668
669 switch(sc->sk_type) {
670 case SK_GENESIS:
ce17751a 671 if (ifp->if_flags & IFF_PROMISC)
0d939d2c 672 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
ce17751a 673 else
0d939d2c 674 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
0d939d2c
MD
675 break;
676 case SK_YUKON:
ce17751a
SZ
677 case SK_YUKON_LITE:
678 case SK_YUKON_LP:
0d939d2c
MD
679 if (ifp->if_flags & IFF_PROMISC) {
680 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
681 YU_RCR_UFLEN | YU_RCR_MUFLEN);
682 } else {
683 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
684 YU_RCR_UFLEN | YU_RCR_MUFLEN);
685 }
686 break;
687 }
0d939d2c
MD
688}
689
c352b0ba
JS
690static int
691sk_init_rx_ring(struct sk_if_softc *sc_if)
984263bc 692{
c352b0ba 693 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d 694 struct sk_ring_data *rd = &sc_if->sk_rdata;
ff7f301d 695 int i, nexti, error;
984263bc 696
105b9b5d 697 bzero(rd->sk_rx_ring, SK_RX_RING_SIZE);
984263bc
MD
698
699 for (i = 0; i < SK_RX_RING_CNT; i++) {
105b9b5d
SZ
700 bus_addr_t paddr;
701
ce17751a
SZ
702 if (i == (SK_RX_RING_CNT - 1))
703 nexti = 0;
704 else
705 nexti = i + 1;
105b9b5d
SZ
706 paddr = rd->sk_rx_ring_paddr +
707 (nexti * sizeof(struct sk_rx_desc));
708
709 rd->sk_rx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
ce17751a
SZ
710 rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
711 rd->sk_rx_ring[i].sk_csum2_start =
712 htole16(ETHER_HDR_LEN + sizeof(struct ip));
713
ff7f301d
SZ
714 error = sk_newbuf(sc_if, i, 1);
715 if (error) {
ce17751a
SZ
716 if_printf(&sc_if->arpcom.ac_if,
717 "failed alloc of %dth mbuf\n", i);
ff7f301d 718 return error;
984263bc
MD
719 }
720 }
721
ce17751a
SZ
722 cd->sk_rx_prod = 0;
723 cd->sk_rx_cons = 0;
984263bc 724
ce17751a 725 return (0);
984263bc
MD
726}
727
ce17751a 728static int
c352b0ba 729sk_init_tx_ring(struct sk_if_softc *sc_if)
984263bc 730{
105b9b5d 731 struct sk_ring_data *rd = &sc_if->sk_rdata;
c352b0ba 732 int i, nexti;
984263bc 733
105b9b5d 734 bzero(rd->sk_tx_ring, SK_TX_RING_SIZE);
984263bc
MD
735
736 for (i = 0; i < SK_TX_RING_CNT; i++) {
105b9b5d
SZ
737 bus_addr_t paddr;
738
ce17751a
SZ
739 if (i == (SK_TX_RING_CNT - 1))
740 nexti = 0;
741 else
742 nexti = i + 1;
105b9b5d
SZ
743 paddr = rd->sk_tx_ring_paddr +
744 (nexti * sizeof(struct sk_tx_desc));
745
746 rd->sk_tx_ring[i].sk_next = htole32(SK_ADDR_LO(paddr));
984263bc
MD
747 }
748
749 sc_if->sk_cdata.sk_tx_prod = 0;
750 sc_if->sk_cdata.sk_tx_cons = 0;
751 sc_if->sk_cdata.sk_tx_cnt = 0;
ce17751a 752
ce17751a 753 return (0);
984263bc
MD
754}
755
c352b0ba 756static int
ff7f301d 757sk_newbuf_jumbo(struct sk_if_softc *sc_if, int idx, int wait)
984263bc 758{
ce17751a 759 struct sk_jpool_entry *entry;
c352b0ba
JS
760 struct mbuf *m_new = NULL;
761 struct sk_rx_desc *r;
105b9b5d 762 bus_addr_t paddr;
984263bc 763
ff7f301d 764 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
984263bc 765
ff7f301d
SZ
766 MGETHDR(m_new, wait ? MB_WAIT : MB_DONTWAIT, MT_DATA);
767 if (m_new == NULL)
768 return ENOBUFS;
143c4a06 769
ff7f301d
SZ
770 /* Allocate the jumbo buffer */
771 entry = sk_jalloc(sc_if);
772 if (entry == NULL) {
773 m_freem(m_new);
774 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
775 "dropped!\n", sc_if->arpcom.ac_if.if_xname));
776 return ENOBUFS;
984263bc 777 }
ff7f301d
SZ
778
779 m_new->m_ext.ext_arg = entry;
780 m_new->m_ext.ext_buf = entry->buf;
781 m_new->m_ext.ext_free = sk_jfree;
782 m_new->m_ext.ext_ref = sk_jref;
783 m_new->m_ext.ext_size = SK_JLEN;
784
785 m_new->m_flags |= M_EXT;
786
ce17751a
SZ
787 m_new->m_data = m_new->m_ext.ext_buf;
788 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc 789
105b9b5d
SZ
790 paddr = entry->paddr;
791
984263bc
MD
792 /*
793 * Adjust alignment so packet payload begins on a
794 * longword boundary. Mandatory for Alpha, useful on
795 * x86 too.
796 */
797 m_adj(m_new, ETHER_ALIGN);
105b9b5d 798 paddr += ETHER_ALIGN;
984263bc 799
ff7f301d 800 sc_if->sk_cdata.sk_rx_mbuf[idx] = m_new;
984263bc 801
105b9b5d
SZ
802 r = &sc_if->sk_rdata.sk_rx_ring[idx];
803 r->sk_data_lo = htole32(SK_ADDR_LO(paddr));
804 r->sk_data_hi = htole32(SK_ADDR_HI(paddr));
ff7f301d 805 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
ce17751a 806
ff7f301d
SZ
807 return 0;
808}
809
810static int
811sk_newbuf_std(struct sk_if_softc *sc_if, int idx, int wait)
812{
813 struct mbuf *m_new = NULL;
814 struct sk_chain_data *cd = &sc_if->sk_cdata;
815 struct sk_rx_desc *r;
ff7f301d
SZ
816 bus_dma_segment_t seg;
817 bus_dmamap_t map;
32aca3fc 818 int error, nseg;
ff7f301d
SZ
819
820 KKASSERT(idx < SK_RX_RING_CNT && idx >= 0);
821
822 m_new = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
823 if (m_new == NULL)
824 return ENOBUFS;
825
826 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
827
828 /*
829 * Adjust alignment so packet payload begins on a
830 * longword boundary. Mandatory for Alpha, useful on
831 * x86 too.
832 */
833 m_adj(m_new, ETHER_ALIGN);
834
32aca3fc
SZ
835 error = bus_dmamap_load_mbuf_segment(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp,
836 m_new, &seg, 1, &nseg, BUS_DMA_NOWAIT);
ff7f301d 837 if (error) {
ff7f301d 838 m_freem(m_new);
32aca3fc
SZ
839 if (wait) {
840 if_printf(&sc_if->arpcom.ac_if,
841 "could not map RX mbuf\n");
842 }
ff7f301d
SZ
843 return error;
844 }
845
846 /* Unload originally mapped mbuf */
32aca3fc
SZ
847 if (cd->sk_rx_mbuf[idx] != NULL) {
848 bus_dmamap_sync(cd->sk_rx_dtag, cd->sk_rx_dmap[idx],
849 BUS_DMASYNC_POSTREAD);
ff7f301d 850 bus_dmamap_unload(cd->sk_rx_dtag, cd->sk_rx_dmap[idx]);
32aca3fc 851 }
ff7f301d
SZ
852
853 /* Switch DMA map with tmp DMA map */
854 map = cd->sk_rx_dmap_tmp;
855 cd->sk_rx_dmap_tmp = cd->sk_rx_dmap[idx];
856 cd->sk_rx_dmap[idx] = map;
857
858 cd->sk_rx_mbuf[idx] = m_new;
859
105b9b5d
SZ
860 r = &sc_if->sk_rdata.sk_rx_ring[idx];
861 r->sk_data_lo = htole32(SK_ADDR_LO(seg.ds_addr));
862 r->sk_data_hi = htole32(SK_ADDR_HI(seg.ds_addr));
ff7f301d
SZ
863 r->sk_ctl = htole32(m_new->m_pkthdr.len | SK_RXSTAT);
864
865 return 0;
984263bc
MD
866}
867
868/*
ce17751a 869 * Allocate a jumbo buffer.
984263bc 870 */
ce17751a
SZ
871struct sk_jpool_entry *
872sk_jalloc(struct sk_if_softc *sc_if)
984263bc 873{
ce17751a
SZ
874 struct sk_chain_data *cd = &sc_if->sk_cdata;
875 struct sk_jpool_entry *entry;
984263bc 876
ce17751a 877 lwkt_serialize_enter(&cd->sk_jpool_serializer);
984263bc 878
ce17751a
SZ
879 entry = SLIST_FIRST(&cd->sk_jpool_free_ent);
880 if (entry != NULL) {
881 SLIST_REMOVE_HEAD(&cd->sk_jpool_free_ent, entry_next);
882 entry->inuse = 1;
883 } else {
ff7f301d 884 DPRINTF(("no free jumbo buffer\n"));
984263bc
MD
885 }
886
ce17751a
SZ
887 lwkt_serialize_exit(&cd->sk_jpool_serializer);
888 return entry;
984263bc
MD
889}
890
891/*
ce17751a 892 * Release a jumbo buffer.
984263bc 893 */
ce17751a
SZ
894void
895sk_jfree(void *arg)
984263bc 896{
ce17751a
SZ
897 struct sk_jpool_entry *entry = arg;
898 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
c352b0ba 899
ce17751a
SZ
900 if (&cd->sk_jpool_ent[entry->slot] != entry)
901 panic("%s: free wrong jumbo buffer\n", __func__);
902 else if (entry->inuse == 0)
903 panic("%s: jumbo buffer already freed\n", __func__);
904
905 lwkt_serialize_enter(&cd->sk_jpool_serializer);
906
907 atomic_subtract_int(&entry->inuse, 1);
908 if (entry->inuse == 0)
909 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
910
911 lwkt_serialize_exit(&cd->sk_jpool_serializer);
984263bc
MD
912}
913
c352b0ba 914static void
143c4a06 915sk_jref(void *arg)
984263bc 916{
ce17751a
SZ
917 struct sk_jpool_entry *entry = arg;
918 struct sk_chain_data *cd = &entry->sc_if->sk_cdata;
984263bc 919
ce17751a
SZ
920 if (&cd->sk_jpool_ent[entry->slot] != entry)
921 panic("%s: free wrong jumbo buffer\n", __func__);
922 else if (entry->inuse == 0)
923 panic("%s: jumbo buffer already freed\n", __func__);
924
925 atomic_add_int(&entry->inuse, 1);
984263bc
MD
926}
927
928/*
929 * Set media options.
930 */
c352b0ba
JS
931static int
932sk_ifmedia_upd(struct ifnet *ifp)
984263bc 933{
c352b0ba
JS
934 struct sk_if_softc *sc_if = ifp->if_softc;
935 struct mii_data *mii;
984263bc 936
984263bc
MD
937 mii = device_get_softc(sc_if->sk_miibus);
938 sk_init(sc_if);
939 mii_mediachg(mii);
940
941 return(0);
942}
943
944/*
945 * Report current media status.
946 */
c352b0ba
JS
947static void
948sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 949{
c352b0ba
JS
950 struct sk_if_softc *sc_if;
951 struct mii_data *mii;
984263bc
MD
952
953 sc_if = ifp->if_softc;
954 mii = device_get_softc(sc_if->sk_miibus);
955
956 mii_pollstat(mii);
957 ifmr->ifm_active = mii->mii_media_active;
958 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
959}
960
c352b0ba
JS
961static int
962sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 963{
c352b0ba
JS
964 struct sk_if_softc *sc_if = ifp->if_softc;
965 struct ifreq *ifr = (struct ifreq *)data;
966 struct mii_data *mii;
60b1a963 967 int error = 0;
984263bc 968
ce17751a 969 ASSERT_SERIALIZED(ifp->if_serializer);
984263bc
MD
970
971 switch(command) {
984263bc
MD
972 case SIOCSIFMTU:
973 if (ifr->ifr_mtu > SK_JUMBO_MTU)
974 error = EINVAL;
975 else {
976 ifp->if_mtu = ifr->ifr_mtu;
25c93c10 977 ifp->if_flags &= ~IFF_RUNNING;
984263bc
MD
978 sk_init(sc_if);
979 }
980 break;
981 case SIOCSIFFLAGS:
982 if (ifp->if_flags & IFF_UP) {
0d939d2c
MD
983 if (ifp->if_flags & IFF_RUNNING) {
984 if ((ifp->if_flags ^ sc_if->sk_if_flags)
985 & IFF_PROMISC) {
986 sk_setpromisc(sc_if);
987 sk_setmulti(sc_if);
1fb1e4cd 988 }
984263bc
MD
989 } else
990 sk_init(sc_if);
991 } else {
992 if (ifp->if_flags & IFF_RUNNING)
993 sk_stop(sc_if);
994 }
995 sc_if->sk_if_flags = ifp->if_flags;
984263bc
MD
996 break;
997 case SIOCADDMULTI:
998 case SIOCDELMULTI:
999 sk_setmulti(sc_if);
984263bc
MD
1000 break;
1001 case SIOCGIFMEDIA:
1002 case SIOCSIFMEDIA:
1003 mii = device_get_softc(sc_if->sk_miibus);
1004 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1005 break;
1006 default:
4cde4dd5 1007 error = ether_ioctl(ifp, command, data);
984263bc
MD
1008 break;
1009 }
1010
984263bc
MD
1011 return(error);
1012}
1013
1014/*
1015 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
1016 * IDs against our list and return a device name if we find a match.
1017 */
c352b0ba
JS
1018static int
1019skc_probe(device_t dev)
984263bc 1020{
ce17751a
SZ
1021 const struct skc_type *t;
1022 uint16_t vid, did;
984263bc 1023
ce17751a
SZ
1024 vid = pci_get_vendor(dev);
1025 did = pci_get_device(dev);
984263bc 1026
c0f707e2
SZ
1027 /*
1028 * Only attach to rev.2 of the Linksys EG1032 adapter.
1029 * Rev.3 is supported by re(4).
1030 */
ce17751a
SZ
1031 if (vid == PCI_VENDOR_LINKSYS &&
1032 did == PCI_PRODUCT_LINKSYS_EG1032 &&
fbd85e3e 1033 pci_get_subdevice(dev) != SUBDEVICEID_LINKSYS_EG1032_REV2)
ce17751a 1034 return ENXIO;
fbd85e3e 1035
ce17751a
SZ
1036 for (t = skc_devs; t->skc_name != NULL; t++) {
1037 if (vid == t->skc_vid && did == t->skc_did) {
1038 device_set_desc(dev, t->skc_name);
1039 return 0;
984263bc 1040 }
984263bc 1041 }
ce17751a 1042 return ENXIO;
984263bc
MD
1043}
1044
1045/*
1046 * Force the GEnesis into reset, then bring it out of reset.
1047 */
c352b0ba
JS
1048static void
1049sk_reset(struct sk_softc *sc)
984263bc 1050{
ce17751a
SZ
1051 DPRINTFN(2, ("sk_reset\n"));
1052
1fb1e4cd
MD
1053 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1054 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
ce17751a 1055 if (SK_IS_YUKON(sc))
1fb1e4cd 1056 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
984263bc 1057
1fb1e4cd
MD
1058 DELAY(1000);
1059 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1060 DELAY(2);
1061 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
ce17751a 1062 if (SK_IS_YUKON(sc))
1fb1e4cd
MD
1063 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1064
ce17751a
SZ
1065 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1066 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1067 CSR_READ_2(sc, SK_LINK_CTRL)));
1068
1069 if (SK_IS_GENESIS(sc)) {
1fb1e4cd
MD
1070 /* Configure packet arbiter */
1071 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1072 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1073 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1074 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1075 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1076 }
984263bc
MD
1077
1078 /* Enable RAM interface */
1079 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1080
1081 /*
ce17751a 1082 * Configure interrupt moderation. The moderation timer
984263bc
MD
1083 * defers interrupts specified in the interrupt moderation
1084 * timer mask based on the timeout specified in the interrupt
1085 * moderation timer init register. Each bit in the timer
ce17751a
SZ
1086 * register represents one tick, so to specify a timeout in
1087 * microseconds, we have to multiply by the correct number of
1088 * ticks-per-microsecond.
984263bc 1089 */
dbe44a55
SZ
1090 KKASSERT(sc->sk_imtimer_ticks != 0 && sc->sk_imtime != 0);
1091 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc, sc->sk_imtime));
ce17751a 1092 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
984263bc 1093 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
ce17751a 1094 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
984263bc
MD
1095}
1096
c352b0ba
JS
1097static int
1098sk_probe(device_t dev)
984263bc 1099{
c352b0ba 1100 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
ce17751a
SZ
1101 const char *revstr = "", *name = NULL;
1102 char devname[80];
1fb1e4cd 1103
1fb1e4cd
MD
1104 switch (sc->sk_type) {
1105 case SK_GENESIS:
ce17751a 1106 name = "SysKonnect GEnesis";
1fb1e4cd
MD
1107 break;
1108 case SK_YUKON:
ce17751a
SZ
1109 name = "Marvell Yukon";
1110 break;
1111 case SK_YUKON_LITE:
1112 name = "Marvell Yukon Lite";
1113 switch (sc->sk_rev) {
1114 case SK_YUKON_LITE_REV_A0:
1115 revstr = " rev.A0";
1116 break;
1117 case SK_YUKON_LITE_REV_A1:
1118 revstr = " rev.A1";
1119 break;
1120 case SK_YUKON_LITE_REV_A3:
1121 revstr = " rev.A3";
1122 break;
1123 }
1fb1e4cd 1124 break;
ce17751a
SZ
1125 case SK_YUKON_LP:
1126 name = "Marvell Yukon LP";
1127 break;
1128 default:
1129 return ENXIO;
1fb1e4cd 1130 }
984263bc 1131
f8c7a42d 1132 ksnprintf(devname, sizeof(devname), "%s%s (0x%x)",
ce17751a
SZ
1133 name, revstr, sc->sk_rev);
1134 device_set_desc_copy(dev, devname);
1135 return 0;
984263bc
MD
1136}
1137
1138/*
1139 * Each XMAC chip is attached as a separate logical IP interface.
1140 * Single port cards will have only one logical interface of course.
1141 */
c352b0ba
JS
1142static int
1143sk_attach(device_t dev)
984263bc 1144{
c352b0ba
JS
1145 struct sk_softc *sc = device_get_softc(device_get_parent(dev));
1146 struct sk_if_softc *sc_if = device_get_softc(dev);
ce17751a
SZ
1147 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1148 int i, error;
1149
1150 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1151
1152 sc_if->sk_port = *(int *)device_get_ivars(dev);
1153 KKASSERT(sc_if->sk_port == SK_PORT_A || sc_if->sk_port == SK_PORT_B);
1154
1155 sc_if->sk_softc = sc;
1156 sc->sk_if[sc_if->sk_port] = sc_if;
984263bc 1157
efda3bd0 1158 kfree(device_get_ivars(dev), M_DEVBUF);
984263bc 1159 device_set_ivars(dev, NULL);
984263bc 1160
ce17751a 1161 if (sc_if->sk_port == SK_PORT_A)
984263bc 1162 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
ce17751a 1163 if (sc_if->sk_port == SK_PORT_B)
984263bc 1164 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1fb1e4cd 1165
ce17751a
SZ
1166 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1167
984263bc
MD
1168 /*
1169 * Get station address for this interface. Note that
1170 * dual port cards actually come with three station
1171 * addresses: one for each port, plus an extra. The
1172 * extra one is used by the SysKonnect driver software
1173 * as a 'virtual' station address for when both ports
1174 * are operating in failover mode. Currently we don't
1175 * use this extra address.
1176 */
ce17751a
SZ
1177 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1178 /* XXX */
984263bc 1179 sc_if->arpcom.ac_enaddr[i] =
ce17751a
SZ
1180 sk_win_read_1(sc, SK_MAC0_0 + (sc_if->sk_port * 8) + i);
1181 }
984263bc 1182
984263bc
MD
1183 /*
1184 * Set up RAM buffer addresses. The NIC will have a certain
1185 * amount of SRAM on it, somewhere between 512K and 2MB. We
1186 * need to divide this up a) between the transmitter and
1187 * receiver and b) between the two XMACs, if this is a
ce17751a 1188 * dual port NIC. Our algorithm is to divide up the memory
984263bc
MD
1189 * evenly so that everyone gets a fair share.
1190 */
1191 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
c352b0ba 1192 uint32_t chunk, val;
984263bc
MD
1193
1194 chunk = sc->sk_ramsize / 2;
c352b0ba 1195 val = sc->sk_rboff / sizeof(uint64_t);
984263bc 1196 sc_if->sk_rx_ramstart = val;
c352b0ba 1197 val += (chunk / sizeof(uint64_t));
984263bc
MD
1198 sc_if->sk_rx_ramend = val - 1;
1199 sc_if->sk_tx_ramstart = val;
c352b0ba 1200 val += (chunk / sizeof(uint64_t));
984263bc
MD
1201 sc_if->sk_tx_ramend = val - 1;
1202 } else {
c352b0ba 1203 uint32_t chunk, val;
984263bc
MD
1204
1205 chunk = sc->sk_ramsize / 4;
1206 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
c352b0ba 1207 sizeof(uint64_t);
984263bc 1208 sc_if->sk_rx_ramstart = val;
c352b0ba 1209 val += (chunk / sizeof(uint64_t));
984263bc
MD
1210 sc_if->sk_rx_ramend = val - 1;
1211 sc_if->sk_tx_ramstart = val;
c352b0ba 1212 val += (chunk / sizeof(uint64_t));
984263bc
MD
1213 sc_if->sk_tx_ramend = val - 1;
1214 }
1215
ce17751a
SZ
1216 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1217 " tx_ramstart=%#x tx_ramend=%#x\n",
1218 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1219 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
984263bc 1220
ce17751a
SZ
1221 /* Read and save PHY type */
1222 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
984263bc 1223
ce17751a
SZ
1224 /* Set PHY address */
1225 if (SK_IS_GENESIS(sc)) {
1226 switch (sc_if->sk_phytype) {
1227 case SK_PHYTYPE_XMAC:
1228 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1229 break;
1230 case SK_PHYTYPE_BCOM:
1231 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1232 break;
1233 default:
1234 device_printf(dev, "unsupported PHY type: %d\n",
1235 sc_if->sk_phytype);
1236 error = ENXIO;
1237 goto fail;
1238 }
984263bc
MD
1239 }
1240
ce17751a
SZ
1241 if (SK_IS_YUKON(sc)) {
1242 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
1243 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
1244 /* not initialized, punt */
1245 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
1246 sc->sk_coppertype = 1;
1247 }
1248
1249 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
984263bc 1250
ce17751a
SZ
1251 if (!(sc->sk_coppertype))
1252 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
984263bc
MD
1253 }
1254
ce17751a
SZ
1255 error = sk_dma_alloc(dev);
1256 if (error)
1257 goto fail;
1258
984263bc 1259 ifp->if_softc = sc_if;
984263bc
MD
1260 ifp->if_mtu = ETHERMTU;
1261 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1262 ifp->if_ioctl = sk_ioctl;
984263bc
MD
1263 ifp->if_start = sk_start;
1264 ifp->if_watchdog = sk_watchdog;
1265 ifp->if_init = sk_init;
1266 ifp->if_baudrate = 1000000000;
6eb61075
JS
1267 ifq_set_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1268 ifq_set_ready(&ifp->if_snd);
984263bc 1269
ce17751a
SZ
1270 ifp->if_capabilities = IFCAP_VLAN_MTU;
1271
ff7f301d
SZ
1272 /* Don't use jumbo buffers by default */
1273 sc_if->sk_use_jumbo = 0;
1274
984263bc
MD
1275 /*
1276 * Do miibus setup.
1277 */
1fb1e4cd
MD
1278 switch (sc->sk_type) {
1279 case SK_GENESIS:
1280 sk_init_xmac(sc_if);
1281 break;
1282 case SK_YUKON:
ce17751a
SZ
1283 case SK_YUKON_LITE:
1284 case SK_YUKON_LP:
1fb1e4cd
MD
1285 sk_init_yukon(sc_if);
1286 break;
ce17751a
SZ
1287 default:
1288 device_printf(dev, "unknown device type %d\n", sc->sk_type);
1289 error = ENXIO;
1290 goto fail;
1fb1e4cd
MD
1291 }
1292
ce17751a
SZ
1293 DPRINTFN(2, ("sk_attach: 1\n"));
1294
1295 error = mii_phy_probe(dev, &sc_if->sk_miibus,
1296 sk_ifmedia_upd, sk_ifmedia_sts);
1297 if (error) {
1298 device_printf(dev, "no PHY found!\n");
1299 goto fail;
984263bc
MD
1300 }
1301
ce17751a
SZ
1302 callout_init(&sc_if->sk_tick_timer);
1303
984263bc 1304 /*
ce17751a 1305 * Call MI attach routines.
984263bc 1306 */
ce17751a 1307 ether_ifattach(ifp, sc_if->arpcom.ac_enaddr, &sc->sk_serializer);
984263bc 1308
ce17751a
SZ
1309 DPRINTFN(2, ("sk_attach: end\n"));
1310 return 0;
1311fail:
1312 sk_detach(dev);
1313 sc->sk_if[sc_if->sk_port] = NULL;
1314 return error;
984263bc
MD
1315}
1316
1317/*
1318 * Attach the interface. Allocate softc structures, do ifmedia
1319 * setup and ethernet/BPF attach.
1320 */
c352b0ba
JS
1321static int
1322skc_attach(device_t dev)
984263bc 1323{
ce17751a 1324 struct sk_softc *sc = device_get_softc(dev);
c352b0ba 1325 uint8_t skrs;
ce17751a 1326 int *port;
9db4b353 1327 int error, cpuid;
984263bc 1328
ce17751a 1329 DPRINTFN(2, ("begin skc_attach\n"));
984263bc 1330
720cce88 1331 sc->sk_dev = dev;
ce17751a 1332 lwkt_serialize_init(&sc->sk_serializer);
984263bc 1333
ce17751a 1334#ifndef BURN_BRIDGES
984263bc
MD
1335 /*
1336 * Handle power management nonsense.
1337 */
ce17751a
SZ
1338 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1339 uint32_t iobase, membase, irq;
1340
1341 /* Save important PCI config data. */
1342 iobase = pci_read_config(dev, SK_PCI_LOIO, 4);
1343 membase = pci_read_config(dev, SK_PCI_LOMEM, 4);
1344 irq = pci_read_config(dev, SK_PCI_INTLINE, 4);
1345
1346 /* Reset the power state. */
1347 device_printf(dev, "chip is in D%d power mode "
1348 "-- setting to D0\n", pci_get_powerstate(dev));
1349
1350 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1351
1352 /* Restore PCI config data. */
1353 pci_write_config(dev, SK_PCI_LOIO, iobase, 4);
1354 pci_write_config(dev, SK_PCI_LOMEM, membase, 4);
1355 pci_write_config(dev, SK_PCI_INTLINE, irq, 4);
984263bc 1356 }
ce17751a 1357#endif /* BURN_BRIDGES */
984263bc
MD
1358
1359 /*
1360 * Map control/status registers.
1361 */
ce17751a 1362 pci_enable_busmaster(dev);
984263bc 1363
ce17751a
SZ
1364 sc->sk_res_rid = SK_PCI_LOMEM;
1365 sc->sk_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1366 &sc->sk_res_rid, RF_ACTIVE);
984263bc 1367 if (sc->sk_res == NULL) {
ce17751a 1368 device_printf(dev, "couldn't map memory\n");
984263bc
MD
1369 error = ENXIO;
1370 goto fail;
1371 }
984263bc
MD
1372 sc->sk_btag = rman_get_bustag(sc->sk_res);
1373 sc->sk_bhandle = rman_get_bushandle(sc->sk_res);
1374
ce17751a
SZ
1375 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1376 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
984263bc 1377
ce17751a
SZ
1378 /* Bail out here if chip is not recognized */
1379 if (!SK_IS_GENESIS(sc) && !SK_IS_YUKON(sc)) {
1380 device_printf(dev, "unknown chip type: %d\n", sc->sk_type);
984263bc
MD
1381 error = ENXIO;
1382 goto fail;
1383 }
1384
ce17751a 1385 DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
984263bc 1386
ce17751a
SZ
1387 /* Allocate interrupt */
1388 sc->sk_irq_rid = 0;
1389 sc->sk_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sk_irq_rid,
1390 RF_SHAREABLE | RF_ACTIVE);
1391 if (sc->sk_irq == NULL) {
1392 device_printf(dev, "couldn't map interrupt\n");
1393 error = ENXIO;
984263bc
MD
1394 goto fail;
1395 }
1396
dbe44a55
SZ
1397 switch (sc->sk_type) {
1398 case SK_GENESIS:
1399 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1400 break;
1401 default:
1402 sc->sk_imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1403 break;
1404 }
1405 sc->sk_imtime = skc_imtime;
1406
984263bc
MD
1407 /* Reset the adapter. */
1408 sk_reset(sc);
1409
d34d2c96 1410 skrs = sk_win_read_1(sc, SK_EPROM0);
ce17751a 1411 if (SK_IS_GENESIS(sc)) {
1fb1e4cd 1412 /* Read and save RAM size and RAMbuffer offset */
d34d2c96 1413 switch(skrs) {
1fb1e4cd
MD
1414 case SK_RAMSIZE_512K_64:
1415 sc->sk_ramsize = 0x80000;
1416 sc->sk_rboff = SK_RBOFF_0;
1417 break;
1418 case SK_RAMSIZE_1024K_64:
1419 sc->sk_ramsize = 0x100000;
1420 sc->sk_rboff = SK_RBOFF_80000;
1421 break;
1422 case SK_RAMSIZE_1024K_128:
1423 sc->sk_ramsize = 0x100000;
1424 sc->sk_rboff = SK_RBOFF_0;
1425 break;
1426 case SK_RAMSIZE_2048K_128:
1427 sc->sk_ramsize = 0x200000;
1428 sc->sk_rboff = SK_RBOFF_0;
1429 break;
1430 default:
ce17751a 1431 device_printf(dev, "unknown ram size: %d\n", skrs);
1fb1e4cd
MD
1432 error = ENXIO;
1433 goto fail;
1fb1e4cd 1434 }
ce17751a
SZ
1435 } else {
1436 if (skrs == 0x00)
d34d2c96 1437 sc->sk_ramsize = 0x20000;
ce17751a 1438 else
d34d2c96 1439 sc->sk_ramsize = skrs * (1<<12);
984263bc 1440 sc->sk_rboff = SK_RBOFF_0;
984263bc
MD
1441 }
1442
ce17751a
SZ
1443 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1444 sc->sk_ramsize, sc->sk_ramsize / 1024,
1445 sc->sk_rboff));
1446
984263bc 1447 /* Read and save physical media type */
ce17751a
SZ
1448 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1449
1450 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1451 sc->sk_coppertype = 1;
1452 else
1453 sc->sk_coppertype = 0;
1454
1455 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1456 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1457 uint32_t flashaddr;
1458 uint8_t testbyte;
1459
1460 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1461
1462 /* Test Flash-Address Register */
1463 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1464 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1465
1466 if (testbyte != 0) {
1467 /* This is a Yukon Lite Rev A0 */
1468 sc->sk_type = SK_YUKON_LITE;
1469 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1470 /* Restore Flash-Address Register */
1471 sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1472 }
984263bc
MD
1473 }
1474
dbe44a55
SZ
1475 /*
1476 * Create sysctl nodes.
1477 */
1478 sysctl_ctx_init(&sc->sk_sysctl_ctx);
1479 sc->sk_sysctl_tree = SYSCTL_ADD_NODE(&sc->sk_sysctl_ctx,
1480 SYSCTL_STATIC_CHILDREN(_hw),
1481 OID_AUTO,
1482 device_get_nameunit(dev),
1483 CTLFLAG_RD, 0, "");
1484 if (sc->sk_sysctl_tree == NULL) {
1485 device_printf(dev, "can't add sysctl node\n");
1486 error = ENXIO;
1487 goto fail;
1488 }
1489 SYSCTL_ADD_PROC(&sc->sk_sysctl_ctx,
1490 SYSCTL_CHILDREN(sc->sk_sysctl_tree),
1491 OID_AUTO, "imtime", CTLTYPE_INT | CTLFLAG_RW,
1492 sc, 0, skc_sysctl_imtime, "I",
1493 "Interrupt moderation time (usec).");
1494
984263bc 1495 sc->sk_devs[SK_PORT_A] = device_add_child(dev, "sk", -1);
ce17751a 1496 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
984263bc
MD
1497 *port = SK_PORT_A;
1498 device_set_ivars(sc->sk_devs[SK_PORT_A], port);
1499
1500 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1501 sc->sk_devs[SK_PORT_B] = device_add_child(dev, "sk", -1);
ce17751a 1502 port = kmalloc(sizeof(*port), M_DEVBUF, M_WAITOK);
984263bc
MD
1503 *port = SK_PORT_B;
1504 device_set_ivars(sc->sk_devs[SK_PORT_B], port);
1505 }
1506
1507 /* Turn on the 'driver is loaded' LED. */
1508 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1509
1510 bus_generic_attach(dev);
1511
95893fe4 1512 error = bus_setup_intr(dev, sc->sk_irq, INTR_MPSAFE, sk_intr, sc,
ce17751a
SZ
1513 &sc->sk_intrhand, &sc->sk_serializer);
1514 if (error) {
1515 device_printf(dev, "couldn't set up irq\n");
1516 goto fail;
1517 }
9db4b353
SZ
1518
1519 cpuid = ithread_cpuid(rman_get_start(sc->sk_irq));
1520 KKASSERT(cpuid >= 0 && cpuid < ncpus);
1521
1522 if (sc->sk_if[0] != NULL)
1523 sc->sk_if[0]->arpcom.ac_if.if_cpuid = cpuid;
1524 if (sc->sk_if[1] != NULL)
1525 sc->sk_if[1]->arpcom.ac_if.if_cpuid = cpuid;
1526
ce17751a 1527 return 0;
984263bc 1528fail:
ce17751a
SZ
1529 skc_detach(dev);
1530 return error;
984263bc
MD
1531}
1532
c352b0ba
JS
1533static int
1534sk_detach(device_t dev)
984263bc 1535{
c352b0ba 1536 struct sk_if_softc *sc_if = device_get_softc(dev);
984263bc 1537
720cce88
SZ
1538 if (device_is_attached(dev)) {
1539 struct sk_softc *sc = sc_if->sk_softc;
1540 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1541
1542 lwkt_serialize_enter(ifp->if_serializer);
1543
1544 if (sc->sk_intrhand != NULL) {
1545 if (sc->sk_if[SK_PORT_A] != NULL)
1546 sk_stop(sc->sk_if[SK_PORT_A]);
1547 if (sc->sk_if[SK_PORT_B] != NULL)
1548 sk_stop(sc->sk_if[SK_PORT_B]);
1549
1550 bus_teardown_intr(sc->sk_dev, sc->sk_irq,
1551 sc->sk_intrhand);
1552 sc->sk_intrhand = NULL;
1553 }
1554
1555 lwkt_serialize_exit(ifp->if_serializer);
1556
ce17751a 1557 ether_ifdetach(ifp);
720cce88 1558 }
ce17751a 1559
984263bc
MD
1560 if (sc_if->sk_miibus != NULL)
1561 device_delete_child(dev, sc_if->sk_miibus);
984263bc 1562
ce17751a
SZ
1563 sk_dma_free(dev);
1564 return 0;
984263bc
MD
1565}
1566
c352b0ba
JS
1567static int
1568skc_detach(device_t dev)
984263bc 1569{
ce17751a
SZ
1570 struct sk_softc *sc = device_get_softc(dev);
1571 int *port;
984263bc 1572
720cce88 1573#ifdef INVARIANTS
ce17751a 1574 if (device_is_attached(dev)) {
720cce88
SZ
1575 KASSERT(sc->sk_intrhand == NULL,
1576 ("intr has not been torn down yet"));
ce17751a 1577 }
720cce88 1578#endif
cdf89432 1579
ce17751a
SZ
1580 if (sc->sk_devs[SK_PORT_A] != NULL) {
1581 port = device_get_ivars(sc->sk_devs[SK_PORT_A]);
1582 if (port != NULL) {
1583 kfree(port, M_DEVBUF);
1584 device_set_ivars(sc->sk_devs[SK_PORT_A], NULL);
1585 }
984263bc 1586 device_delete_child(dev, sc->sk_devs[SK_PORT_A]);
ce17751a
SZ
1587 }
1588 if (sc->sk_devs[SK_PORT_B] != NULL) {
1589 port = device_get_ivars(sc->sk_devs[SK_PORT_B]);
1590 if (port != NULL) {
1591 kfree(port, M_DEVBUF);
1592 device_set_ivars(sc->sk_devs[SK_PORT_B], NULL);
1593 }
984263bc 1594 device_delete_child(dev, sc->sk_devs[SK_PORT_B]);
ce17751a 1595 }
984263bc 1596
ce17751a
SZ
1597 if (sc->sk_irq != NULL) {
1598 bus_release_resource(dev, SYS_RES_IRQ, sc->sk_irq_rid,
1599 sc->sk_irq);
1600 }
1601 if (sc->sk_res != NULL) {
1602 bus_release_resource(dev, SYS_RES_MEMORY, sc->sk_res_rid,
1603 sc->sk_res);
1604 }
984263bc 1605
dbe44a55
SZ
1606 if (sc->sk_sysctl_tree != NULL)
1607 sysctl_ctx_free(&sc->sk_sysctl_ctx);
1608
ce17751a 1609 return 0;
984263bc
MD
1610}
1611
c352b0ba 1612static int
fcbf2fb6 1613sk_encap(struct sk_if_softc *sc_if, struct mbuf **m_head0, uint32_t *txidx)
984263bc 1614{
ce17751a 1615 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d 1616 struct sk_ring_data *rd = &sc_if->sk_rdata;
c352b0ba 1617 struct sk_tx_desc *f = NULL;
ce17751a 1618 uint32_t frag, cur, sk_ctl;
ce17751a
SZ
1619 bus_dma_segment_t segs[SK_NTXSEG];
1620 bus_dmamap_t map;
cd1d88d9 1621 int i, error, maxsegs, nsegs;
ce17751a
SZ
1622
1623 DPRINTFN(2, ("sk_encap\n"));
984263bc 1624
fcbf2fb6
SZ
1625 maxsegs = SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - SK_NDESC_RESERVE;
1626 KASSERT(maxsegs >= SK_NDESC_SPARE, ("not enough spare TX desc\n"));
1627 if (maxsegs > SK_NTXSEG)
1628 maxsegs = SK_NTXSEG;
1629
984263bc
MD
1630 cur = frag = *txidx;
1631
ce17751a
SZ
1632#ifdef SK_DEBUG
1633 if (skdebug >= 2)
cd1d88d9 1634 sk_dump_mbuf(*m_head0);
ce17751a
SZ
1635#endif
1636
1637 map = cd->sk_tx_dmap[*txidx];
1638
cd1d88d9
SZ
1639 error = bus_dmamap_load_mbuf_defrag(cd->sk_tx_dtag, map, m_head0,
1640 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
ce17751a 1641 if (error) {
cd1d88d9
SZ
1642 m_freem(*m_head0);
1643 *m_head0 = NULL;
1644 return error;
984263bc
MD
1645 }
1646
cd1d88d9 1647 DPRINTFN(2, ("sk_encap: nsegs=%d\n", nsegs));
ce17751a
SZ
1648
1649 /* Sync the DMA map. */
1650 bus_dmamap_sync(cd->sk_tx_dtag, map, BUS_DMASYNC_PREWRITE);
1651
cd1d88d9 1652 for (i = 0; i < nsegs; i++) {
ce17751a 1653 f = &rd->sk_tx_ring[frag];
105b9b5d
SZ
1654 f->sk_data_lo = htole32(SK_ADDR_LO(segs[i].ds_addr));
1655 f->sk_data_hi = htole32(SK_ADDR_HI(segs[i].ds_addr));
ce17751a
SZ
1656 sk_ctl = segs[i].ds_len | SK_OPCODE_DEFAULT;
1657 if (i == 0)
1658 sk_ctl |= SK_TXCTL_FIRSTFRAG;
1659 else
1660 sk_ctl |= SK_TXCTL_OWN;
1661 f->sk_ctl = htole32(sk_ctl);
1662 cur = frag;
1663 SK_INC(frag, SK_TX_RING_CNT);
1664 }
1665
cd1d88d9 1666 cd->sk_tx_mbuf[cur] = *m_head0;
ce17751a
SZ
1667 /* Switch DMA map */
1668 cd->sk_tx_dmap[*txidx] = cd->sk_tx_dmap[cur];
1669 cd->sk_tx_dmap[cur] = map;
1670
1671 rd->sk_tx_ring[cur].sk_ctl |=
1672 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1673 rd->sk_tx_ring[*txidx].sk_ctl |= htole32(SK_TXCTL_OWN);
1674
cd1d88d9 1675 sc_if->sk_cdata.sk_tx_cnt += nsegs;
ce17751a
SZ
1676
1677#ifdef SK_DEBUG
1678 if (skdebug >= 2) {
1679 struct sk_tx_desc *desc;
1680 uint32_t idx;
1681
1682 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1683 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1684 sk_dump_txdesc(desc, idx);
1685 }
1686 }
1687#endif
984263bc
MD
1688
1689 *txidx = frag;
1690
ce17751a
SZ
1691 DPRINTFN(2, ("sk_encap: completed successfully\n"));
1692
1693 return (0);
984263bc
MD
1694}
1695
c352b0ba
JS
1696static void
1697sk_start(struct ifnet *ifp)
984263bc 1698{
fcbf2fb6
SZ
1699 struct sk_if_softc *sc_if = ifp->if_softc;
1700 struct sk_softc *sc = sc_if->sk_softc;
ce17751a 1701 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
fcbf2fb6 1702 int trans = 0;
984263bc 1703
ce17751a 1704 DPRINTFN(2, ("sk_start\n"));
984263bc 1705
9db4b353
SZ
1706 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1707 return;
1708
ff7f301d 1709 while (sc_if->sk_cdata.sk_tx_mbuf[idx] == NULL) {
fcbf2fb6
SZ
1710 struct mbuf *m_head;
1711
1712 if (SK_IS_OACTIVE(sc_if)) {
9db4b353
SZ
1713 ifp->if_flags |= IFF_OACTIVE;
1714 break;
1715 }
1716
1717 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1718 if (m_head == NULL)
1719 break;
1720
1721 /*
1722 * Pack the data into the transmit ring. If we
1723 * don't have room, set the OACTIVE flag and wait
1724 * for the NIC to drain the ring.
1725 */
fcbf2fb6 1726 if (sk_encap(sc_if, &m_head, &idx)) {
cd1d88d9
SZ
1727 if (sc_if->sk_cdata.sk_tx_cnt == 0) {
1728 continue;
1729 } else {
1730 ifp->if_flags |= IFF_OACTIVE;
1731 break;
1732 }
984263bc 1733 }
ce17751a 1734
fcbf2fb6 1735 trans = 1;
7600679e 1736 BPF_MTAP(ifp, m_head);
984263bc 1737 }
fcbf2fb6 1738 if (!trans)
2f54d1d2
SZ
1739 return;
1740
984263bc 1741 /* Transmit */
ce17751a
SZ
1742 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1743 sc_if->sk_cdata.sk_tx_prod = idx;
1744 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
984263bc 1745
ce17751a
SZ
1746 /* Set a timeout in case the chip goes out to lunch. */
1747 ifp->if_timer = 5;
1748 }
984263bc
MD
1749}
1750
c352b0ba
JS
1751static void
1752sk_watchdog(struct ifnet *ifp)
984263bc 1753{
ce17751a 1754 struct sk_if_softc *sc_if = ifp->if_softc;
2f54d1d2 1755
ce17751a
SZ
1756 ASSERT_SERIALIZED(ifp->if_serializer);
1757 /*
1758 * Reclaim first as there is a possibility of losing Tx completion
1759 * interrupts.
1760 */
1761 sk_txeof(sc_if);
1762 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1763 if_printf(&sc_if->arpcom.ac_if, "watchdog timeout\n");
1764 ifp->if_oerrors++;
1765 ifp->if_flags &= ~IFF_RUNNING;
1766 sk_init(sc_if);
1767 }
984263bc
MD
1768}
1769
c352b0ba
JS
1770static void
1771skc_shutdown(device_t dev)
984263bc 1772{
c352b0ba 1773 struct sk_softc *sc = device_get_softc(dev);
984263bc 1774
ce17751a
SZ
1775 DPRINTFN(2, ("sk_shutdown\n"));
1776
1777 lwkt_serialize_enter(&sc->sk_serializer);
78195a76 1778
984263bc
MD
1779 /* Turn off the 'driver is loaded' LED. */
1780 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
1781
1782 /*
1783 * Reset the GEnesis controller. Doing this should also
1784 * assert the resets on the attached XMAC(s).
1785 */
1786 sk_reset(sc);
ce17751a
SZ
1787
1788 lwkt_serialize_exit(&sc->sk_serializer);
1789}
1790
1791static __inline int
1792sk_rxvalid(struct sk_softc *sc, uint32_t stat, uint32_t len)
1793{
1794 if (sc->sk_type == SK_GENESIS) {
1795 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1796 XM_RXSTAT_BYTES(stat) != len)
1797 return (0);
1798 } else {
1799 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1800 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1801 YU_RXSTAT_JABBER)) != 0 ||
1802 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1803 YU_RXSTAT_BYTES(stat) != len)
1804 return (0);
1805 }
1806
1807 return (1);
984263bc
MD
1808}
1809
c352b0ba
JS
1810static void
1811sk_rxeof(struct sk_if_softc *sc_if)
984263bc 1812{
ce17751a 1813 struct sk_softc *sc = sc_if->sk_softc;
c352b0ba 1814 struct ifnet *ifp = &sc_if->arpcom.ac_if;
ce17751a 1815 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d 1816 struct sk_ring_data *rd = &sc_if->sk_rdata;
ff7f301d 1817 int i, reap, max_frmlen;
ce17751a
SZ
1818
1819 DPRINTFN(2, ("sk_rxeof\n"));
984263bc 1820
ce17751a 1821 i = cd->sk_rx_prod;
984263bc 1822
32aca3fc 1823 if (sc_if->sk_use_jumbo)
ff7f301d 1824 max_frmlen = SK_JUMBO_FRAMELEN;
32aca3fc 1825 else
ff7f301d 1826 max_frmlen = ETHER_MAX_LEN;
ce17751a
SZ
1827
1828 reap = 0;
1829 for (;;) {
ce17751a
SZ
1830 struct sk_rx_desc *cur_desc;
1831 uint32_t rxstat, sk_ctl;
ff7f301d 1832#ifdef SK_RXCSUM
ce17751a 1833 uint16_t csum1, csum2;
ff7f301d 1834#endif
ce17751a
SZ
1835 int cur, total_len;
1836 struct mbuf *m;
1837
1838 cur = i;
ff7f301d 1839 cur_desc = &rd->sk_rx_ring[cur];
ce17751a 1840
ff7f301d
SZ
1841 sk_ctl = le32toh(cur_desc->sk_ctl);
1842 if (sk_ctl & SK_RXCTL_OWN) {
ce17751a 1843 /* Invalidate the descriptor -- it's not ready yet */
ff7f301d 1844 cd->sk_rx_prod = cur;
ce17751a
SZ
1845 break;
1846 }
1847
ce17751a 1848 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
ce17751a
SZ
1849 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
1850
ff7f301d
SZ
1851#ifdef SK_RXCSUM
1852 csum1 = le16toh(cur_desc->sk_csum1);
1853 csum2 = le16toh(cur_desc->sk_csum2);
1854#endif
1855
1856 m = cd->sk_rx_mbuf[cur];
ce17751a 1857
ff7f301d
SZ
1858 /*
1859 * Bump 'i' here, so we can keep going, even if the current
1860 * RX descriptor reaping fails later. 'i' shoult NOT be used
1861 * in the following processing any more.
1862 */
984263bc 1863 SK_INC(i, SK_RX_RING_CNT);
ff7f301d 1864 reap = 1;
984263bc 1865
ce17751a
SZ
1866 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1867 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1868 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
ff7f301d 1869 total_len < SK_MIN_FRAMELEN || total_len > max_frmlen ||
ce17751a 1870 sk_rxvalid(sc, rxstat, total_len) == 0) {
984263bc 1871 ifp->if_ierrors++;
ff7f301d 1872 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
984263bc
MD
1873 continue;
1874 }
1875
1876 /*
ff7f301d
SZ
1877 * Try to allocate a new RX buffer. If that fails,
1878 * copy the packet to mbufs and put the RX buffer
1879 * back in the ring so it can be re-used. If
1880 * allocating mbufs fails, then we have to drop
1881 * the packet.
984263bc 1882 */
ff7f301d 1883 if (sk_newbuf(sc_if, cur, 0)) {
32aca3fc 1884 ifp->if_ierrors++;
9165dea4 1885 cur_desc->sk_ctl = htole32(m->m_pkthdr.len | SK_RXSTAT);
32aca3fc 1886 continue;
984263bc
MD
1887 } else {
1888 m->m_pkthdr.rcvif = ifp;
1889 m->m_pkthdr.len = m->m_len = total_len;
1890 }
1891
ce17751a
SZ
1892#ifdef SK_RXCSUM
1893 sk_rxcsum(ifp, m, csum1, csum2);
1894#endif
1895
984263bc 1896 ifp->if_ipackets++;
78195a76 1897 ifp->if_input(ifp, m);
984263bc 1898 }
984263bc
MD
1899}
1900
ce17751a
SZ
1901#ifdef SK_RXCSUM
1902static void
1903sk_rxcsum(struct ifnet *ifp, struct mbuf *m,
1904 const uint16_t csum1, const uint16_t csum2)
1905{
1906 struct ether_header *eh;
1907 struct ip *ip;
1908 uint8_t *pp;
1909 int hlen, len, plen;
1910 uint16_t iph_csum, ipo_csum, ipd_csum, csum;
1911
1912 pp = mtod(m, uint8_t *);
1913 plen = m->m_pkthdr.len;
1914 if (plen < sizeof(*eh))
1915 return;
1916 eh = (struct ether_header *)pp;
1917 iph_csum = in_addword(csum1, (~csum2 & 0xffff));
1918
1919 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1920 uint16_t *xp = (uint16_t *)pp;
1921
1922 xp = (uint16_t *)pp;
1923 if (xp[1] != htons(ETHERTYPE_IP))
1924 return;
1925 iph_csum = in_addword(iph_csum, (~xp[0] & 0xffff));
1926 iph_csum = in_addword(iph_csum, (~xp[1] & 0xffff));
1927 xp = (uint16_t *)(pp + sizeof(struct ip));
1928 iph_csum = in_addword(iph_csum, xp[0]);
1929 iph_csum = in_addword(iph_csum, xp[1]);
1930 pp += EVL_ENCAPLEN;
1931 } else if (eh->ether_type != htons(ETHERTYPE_IP)) {
1932 return;
1933 }
1934
1935 pp += sizeof(*eh);
1936 plen -= sizeof(*eh);
1937
1938 ip = (struct ip *)pp;
1939
1940 if (ip->ip_v != IPVERSION)
1941 return;
1942
1943 hlen = ip->ip_hl << 2;
1944 if (hlen < sizeof(struct ip))
1945 return;
1946 if (hlen > ntohs(ip->ip_len))
1947 return;
1948
1949 /* Don't deal with truncated or padded packets. */
1950 if (plen != ntohs(ip->ip_len))
1951 return;
1952
1953 len = hlen - sizeof(struct ip);
1954 if (len > 0) {
1955 uint16_t *p;
1956
1957 p = (uint16_t *)(ip + 1);
1958 ipo_csum = 0;
1959 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
1960 ipo_csum = in_addword(ipo_csum, *p);
1961 iph_csum = in_addword(iph_csum, ipo_csum);
1962 ipd_csum = in_addword(csum2, (~ipo_csum & 0xffff));
1963 } else {
1964 ipd_csum = csum2;
1965 }
1966
1967 if (iph_csum != 0xffff)
1968 return;
1969 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID;
1970
1971 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
1972 return; /* ip frag, we're done for now */
1973
1974 pp += hlen;
1975
1976 /* Only know checksum protocol for udp/tcp */
1977 if (ip->ip_p == IPPROTO_UDP) {
1978 struct udphdr *uh = (struct udphdr *)pp;
1979
1980 if (uh->uh_sum == 0) /* udp with no checksum */
1981 return;
1982 } else if (ip->ip_p != IPPROTO_TCP) {
1983 return;
1984 }
1985
1986 csum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1987 htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
1988 if (csum == 0xffff) {
1989 m->m_pkthdr.csum_data = csum;
1990 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1991 }
1992}
1993#endif
1994
c352b0ba
JS
1995static void
1996sk_txeof(struct sk_if_softc *sc_if)
984263bc 1997{
ce17751a 1998 struct sk_chain_data *cd = &sc_if->sk_cdata;
c352b0ba 1999 struct ifnet *ifp = &sc_if->arpcom.ac_if;
c352b0ba 2000 uint32_t idx;
ce17751a
SZ
2001 int reap = 0;
2002
2003 DPRINTFN(2, ("sk_txeof\n"));
2004
984263bc
MD
2005 /*
2006 * Go through our tx ring and free mbufs for those
2007 * frames that have been sent.
2008 */
ce17751a
SZ
2009 idx = cd->sk_tx_cons;
2010 while (idx != cd->sk_tx_prod) {
2011 struct sk_tx_desc *cur_tx;
2012 uint32_t sk_ctl;
2013
105b9b5d 2014 cur_tx = &sc_if->sk_rdata.sk_tx_ring[idx];
ce17751a
SZ
2015 sk_ctl = le32toh(cur_tx->sk_ctl);
2016#ifdef SK_DEBUG
2017 if (skdebug >= 2)
2018 sk_dump_txdesc(cur_tx, idx);
2019#endif
2020 if (sk_ctl & SK_TXCTL_OWN)
984263bc 2021 break;
ce17751a 2022 if (sk_ctl & SK_TXCTL_LASTFRAG)
984263bc 2023 ifp->if_opackets++;
ff7f301d 2024 if (cd->sk_tx_mbuf[idx] != NULL) {
ce17751a 2025 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[idx]);
ff7f301d
SZ
2026 m_freem(cd->sk_tx_mbuf[idx]);
2027 cd->sk_tx_mbuf[idx] = NULL;
984263bc
MD
2028 }
2029 sc_if->sk_cdata.sk_tx_cnt--;
ce17751a 2030 reap = 1;
984263bc 2031 SK_INC(idx, SK_TX_RING_CNT);
984263bc 2032 }
ce17751a 2033
fcbf2fb6 2034 if (!SK_IS_OACTIVE(sc_if))
ce17751a 2035 ifp->if_flags &= ~IFF_OACTIVE;
984263bc 2036
fcbf2fb6
SZ
2037 if (sc_if->sk_cdata.sk_tx_cnt == 0)
2038 ifp->if_timer = 0;
2039
984263bc 2040 sc_if->sk_cdata.sk_tx_cons = idx;
984263bc
MD
2041}
2042
c352b0ba
JS
2043static void
2044sk_tick(void *xsc_if)
984263bc 2045{
c352b0ba
JS
2046 struct sk_if_softc *sc_if = xsc_if;
2047 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2048 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2049 int i;
984263bc 2050
ce17751a
SZ
2051 DPRINTFN(2, ("sk_tick\n"));
2052
2053 lwkt_serialize_enter(ifp->if_serializer);
78195a76
MD
2054
2055 if ((ifp->if_flags & IFF_UP) == 0) {
ce17751a 2056 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2057 return;
78195a76 2058 }
984263bc
MD
2059
2060 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2061 sk_intr_bcom(sc_if);
ce17751a 2062 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2063 return;
2064 }
2065
2066 /*
2067 * According to SysKonnect, the correct way to verify that
2068 * the link has come back up is to poll bit 0 of the GPIO
2069 * register three times. This pin has the signal from the
ce17751a 2070 * link sync pin connected to it; if we read the same link
984263bc
MD
2071 * state 3 times in a row, we know the link is up.
2072 */
2073 for (i = 0; i < 3; i++) {
2074 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2075 break;
2076 }
2077
2078 if (i != 3) {
664739a3 2079 callout_reset(&sc_if->sk_tick_timer, hz, sk_tick, sc_if);
ce17751a 2080 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2081 return;
2082 }
2083
2084 /* Turn the GP0 interrupt back on. */
2085 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2086 SK_XM_READ_2(sc_if, XM_ISR);
2087 mii_tick(mii);
664739a3 2088 callout_stop(&sc_if->sk_tick_timer);
ce17751a 2089 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2090}
2091
c352b0ba 2092static void
ce17751a 2093sk_yukon_tick(void *xsc_if)
984263bc 2094{
ce17751a 2095 struct sk_if_softc *sc_if = xsc_if;
c352b0ba
JS
2096 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2097 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
ce17751a
SZ
2098
2099 lwkt_serialize_enter(ifp->if_serializer);
2100 mii_tick(mii);
2101 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
2102 lwkt_serialize_exit(ifp->if_serializer);
2103}
2104
2105static void
2106sk_intr_bcom(struct sk_if_softc *sc_if)
2107{
2108 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
2109 struct ifnet *ifp = &sc_if->arpcom.ac_if;
c352b0ba 2110 int status;
984263bc 2111
ce17751a
SZ
2112 DPRINTFN(2, ("sk_intr_bcom\n"));
2113
984263bc
MD
2114 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2115
2116 /*
2117 * Read the PHY interrupt register to make sure
2118 * we clear any pending interrupts.
2119 */
1fb1e4cd 2120 status = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
984263bc 2121
c352b0ba 2122 if ((ifp->if_flags & IFF_RUNNING) == 0) {
984263bc
MD
2123 sk_init_xmac(sc_if);
2124 return;
2125 }
2126
2127 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
c352b0ba 2128 int lstat;
ce17751a 2129
1fb1e4cd
MD
2130 lstat = sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM,
2131 BRGPHY_MII_AUXSTS);
984263bc
MD
2132
2133 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2134 mii_mediachg(mii);
2135 /* Turn off the link LED. */
2136 SK_IF_WRITE_1(sc_if, 0,
2137 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2138 sc_if->sk_link = 0;
2139 } else if (status & BRGPHY_ISR_LNK_CHG) {
1fb1e4cd 2140 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
ce17751a 2141 BRGPHY_MII_IMR, 0xFF00);
984263bc
MD
2142 mii_tick(mii);
2143 sc_if->sk_link = 1;
2144 /* Turn on the link LED. */
2145 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2146 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
2147 SK_LINKLED_BLINK_OFF);
984263bc
MD
2148 } else {
2149 mii_tick(mii);
664739a3
JS
2150 callout_reset(&sc_if->sk_tick_timer, hz,
2151 sk_tick, sc_if);
984263bc
MD
2152 }
2153 }
2154
2155 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
984263bc
MD
2156}
2157
c352b0ba
JS
2158static void
2159sk_intr_xmac(struct sk_if_softc *sc_if)
984263bc 2160{
c352b0ba 2161 uint16_t status;
984263bc 2162
984263bc 2163 status = SK_XM_READ_2(sc_if, XM_ISR);
ce17751a 2164 DPRINTFN(2, ("sk_intr_xmac\n"));
984263bc 2165
ce17751a
SZ
2166 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC &&
2167 (status & (XM_ISR_GP0_SET | XM_ISR_AUTONEG_DONE))) {
2168 if (status & XM_ISR_GP0_SET)
984263bc 2169 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
984263bc 2170
ce17751a
SZ
2171 callout_reset(&sc_if->sk_tick_timer, hz,
2172 sk_tick, sc_if);
984263bc
MD
2173 }
2174
2175 if (status & XM_IMR_TX_UNDERRUN)
2176 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2177
2178 if (status & XM_IMR_RX_OVERRUN)
2179 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
984263bc
MD
2180}
2181
c352b0ba
JS
2182static void
2183sk_intr_yukon(struct sk_if_softc *sc_if)
1fb1e4cd 2184{
ce17751a
SZ
2185 uint8_t status;
2186
2187 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
2188 /* RX overrun */
2189 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
2190 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2191 SK_RFCTL_RX_FIFO_OVER);
2192 }
2193 /* TX underrun */
2194 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
2195 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
2196 SK_TFCTL_TX_FIFO_UNDER);
2197 }
1fb1e4cd 2198
ce17751a 2199 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
1fb1e4cd
MD
2200}
2201
c352b0ba
JS
2202static void
2203sk_intr(void *xsc)
984263bc 2204{
c352b0ba
JS
2205 struct sk_softc *sc = xsc;
2206 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
ce17751a 2207 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
c352b0ba
JS
2208 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2209 uint32_t status;
984263bc 2210
ce17751a
SZ
2211 ASSERT_SERIALIZED(&sc->sk_serializer);
2212
2213 status = CSR_READ_4(sc, SK_ISSR);
2214 if (status == 0 || status == 0xffffffff)
2215 return;
2216
984263bc
MD
2217 if (sc_if0 != NULL)
2218 ifp0 = &sc_if0->arpcom.ac_if;
2219 if (sc_if1 != NULL)
2220 ifp1 = &sc_if1->arpcom.ac_if;
2221
ce17751a 2222 for (; (status &= sc->sk_intrmask) != 0;) {
984263bc 2223 /* Handle receive interrupts first. */
ce17751a 2224 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
984263bc
MD
2225 sk_rxeof(sc_if0);
2226 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2227 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2228 }
ce17751a 2229 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
984263bc
MD
2230 sk_rxeof(sc_if1);
2231 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2232 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
2233 }
2234
2235 /* Then transmit interrupts. */
ce17751a 2236 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
984263bc
MD
2237 sk_txeof(sc_if0);
2238 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2239 SK_TXBMU_CLR_IRQ_EOF);
2240 }
ce17751a 2241 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
984263bc
MD
2242 sk_txeof(sc_if1);
2243 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2244 SK_TXBMU_CLR_IRQ_EOF);
2245 }
2246
2247 /* Then MAC interrupts. */
ce17751a
SZ
2248 if (sc_if0 && (status & SK_ISR_MAC1) &&
2249 (ifp0->if_flags & IFF_RUNNING)) {
2250 if (SK_IS_GENESIS(sc))
1fb1e4cd
MD
2251 sk_intr_xmac(sc_if0);
2252 else
2253 sk_intr_yukon(sc_if0);
2254 }
984263bc 2255
ce17751a
SZ
2256 if (sc_if1 && (status & SK_ISR_MAC2) &&
2257 (ifp1->if_flags & IFF_RUNNING)) {
2258 if (SK_IS_GENESIS(sc))
1fb1e4cd
MD
2259 sk_intr_xmac(sc_if1);
2260 else
ce17751a 2261 sk_intr_yukon(sc_if1);
1fb1e4cd 2262 }
984263bc
MD
2263
2264 if (status & SK_ISR_EXTERNAL_REG) {
ce17751a 2265 if (sc_if0 != NULL &&
1fb1e4cd 2266 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
984263bc 2267 sk_intr_bcom(sc_if0);
ce17751a
SZ
2268
2269 if (sc_if1 != NULL &&
1fb1e4cd 2270 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
984263bc
MD
2271 sk_intr_bcom(sc_if1);
2272 }
ce17751a 2273 status = CSR_READ_4(sc, SK_ISSR);
984263bc
MD
2274 }
2275
2276 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2277
6eb61075 2278 if (ifp0 != NULL && !ifq_is_empty(&ifp0->if_snd))
9db4b353 2279 if_devstart(ifp0);
ce17751a 2280 if (ifp1 != NULL && !ifq_is_empty(&ifp1->if_snd))
9db4b353 2281 if_devstart(ifp1);
984263bc
MD
2282}
2283
c352b0ba 2284static void
ce17751a 2285sk_init_xmac(struct sk_if_softc *sc_if)
984263bc 2286{
c352b0ba
JS
2287 struct sk_softc *sc = sc_if->sk_softc;
2288 struct ifnet *ifp = &sc_if->arpcom.ac_if;
ce17751a 2289 static const struct sk_bcom_hack bhack[] = {
984263bc
MD
2290 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2291 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2292 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2293 { 0, 0 } };
2294
ce17751a
SZ
2295 DPRINTFN(2, ("sk_init_xmac\n"));
2296
984263bc
MD
2297 /* Unreset the XMAC. */
2298 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2299 DELAY(1000);
2300
2301 /* Reset the XMAC's internal state. */
2302 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2303
2304 /* Save the XMAC II revision */
2305 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2306
2307 /*
2308 * Perform additional initialization for external PHYs,
9bbc5585 2309 * namely for the 1000baseT cards that use the XMAC's
984263bc
MD
2310 * GMII mode.
2311 */
2312 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
c352b0ba
JS
2313 int i = 0;
2314 uint32_t val;
984263bc
MD
2315
2316 /* Take PHY out of reset. */
2317 val = sk_win_read_4(sc, SK_GPIO);
2318 if (sc_if->sk_port == SK_PORT_A)
2319 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
2320 else
2321 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
2322 sk_win_write_4(sc, SK_GPIO, val);
2323
2324 /* Enable GMII mode on the XMAC. */
2325 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2326
1fb1e4cd 2327 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
984263bc
MD
2328 BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
2329 DELAY(10000);
1fb1e4cd 2330 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
984263bc
MD
2331 BRGPHY_MII_IMR, 0xFFF0);
2332
2333 /*
2334 * Early versions of the BCM5400 apparently have
2335 * a bug that requires them to have their reserved
2336 * registers initialized to some magic values. I don't
2337 * know what the numbers do, I'm just the messenger.
2338 */
1fb1e4cd
MD
2339 if (sk_xmac_miibus_readreg(sc_if, SK_PHYADDR_BCOM, 0x03)
2340 == 0x6041) {
984263bc 2341 while(bhack[i].reg) {
1fb1e4cd
MD
2342 sk_xmac_miibus_writereg(sc_if, SK_PHYADDR_BCOM,
2343 bhack[i].reg, bhack[i].val);
984263bc
MD
2344 i++;
2345 }
2346 }
2347 }
2348
2349 /* Set station address */
2350 SK_XM_WRITE_2(sc_if, XM_PAR0,
c352b0ba 2351 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[0]));
984263bc 2352 SK_XM_WRITE_2(sc_if, XM_PAR1,
c352b0ba 2353 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[2]));
984263bc 2354 SK_XM_WRITE_2(sc_if, XM_PAR2,
c352b0ba 2355 *(uint16_t *)(&sc_if->arpcom.ac_enaddr[4]));
984263bc
MD
2356 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2357
c352b0ba 2358 if (ifp->if_flags & IFF_BROADCAST)
984263bc 2359 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
c352b0ba 2360 else
984263bc 2361 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
984263bc
MD
2362
2363 /* We don't need the FCS appended to the packet. */
2364 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2365
2366 /* We want short frames padded to 60 bytes. */
2367 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2368
2369 /*
ce17751a 2370 * Enable the reception of all error frames. This is
984263bc
MD
2371 * a necessary evil due to the design of the XMAC. The
2372 * XMAC's receive FIFO is only 8K in size, however jumbo
2373 * frames can be up to 9000 bytes in length. When bad
2374 * frame filtering is enabled, the XMAC's RX FIFO operates
2375 * in 'store and forward' mode. For this to work, the
2376 * entire frame has to fit into the FIFO, but that means
2377 * that jumbo frames larger than 8192 bytes will be
2378 * truncated. Disabling all bad frame filtering causes
2379 * the RX FIFO to operate in streaming mode, in which
2380 * case the XMAC will start transfering frames out of the
2381 * RX FIFO as soon as the FIFO threshold is reached.
2382 */
ff7f301d
SZ
2383 if (sc_if->sk_use_jumbo) {
2384 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2385 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2386 XM_MODE_RX_INRANGELEN);
2387 }
984263bc 2388
ce17751a 2389 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
984263bc
MD
2390
2391 /*
2392 * Bump up the transmit threshold. This helps hold off transmit
2393 * underruns when we're blasting traffic from both ports at once.
2394 */
2395 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2396
0d939d2c
MD
2397 /* Set promiscuous mode */
2398 sk_setpromisc(sc_if);
2399
984263bc
MD
2400 /* Set multicast filter */
2401 sk_setmulti(sc_if);
2402
2403 /* Clear and enable interrupts */
2404 SK_XM_READ_2(sc_if, XM_ISR);
2405 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2406 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2407 else
2408 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2409
2410 /* Configure MAC arbiter */
2411 switch(sc_if->sk_xmac_rev) {
2412 case XM_XMAC_REV_B2:
2413 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2414 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2415 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2416 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2417 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2418 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2419 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2420 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2421 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2422 break;
2423 case XM_XMAC_REV_C1:
2424 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2425 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2426 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2427 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2428 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2429 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2430 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2431 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2432 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2433 break;
2434 default:
2435 break;
2436 }
2437 sk_win_write_2(sc, SK_MACARB_CTL,
2438 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2439
2440 sc_if->sk_link = 1;
984263bc
MD
2441}
2442
c352b0ba
JS
2443static void
2444sk_init_yukon(struct sk_if_softc *sc_if)
1fb1e4cd 2445{
ce17751a 2446 uint32_t phy, v;
c352b0ba 2447 uint16_t reg;
ce17751a 2448 struct sk_softc *sc;
c352b0ba 2449 int i;
7fafc0f4 2450
ce17751a
SZ
2451 sc = sc_if->sk_softc;
2452
2453 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2454 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2455
2456 if (sc->sk_type == SK_YUKON_LITE &&
2457 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2458 /*
2459 * Workaround code for COMA mode, set PHY reset.
2460 * Otherwise it will not correctly take chip out of
2461 * powerdown (coma)
2462 */
2463 v = sk_win_read_4(sc, SK_GPIO);
2464 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2465 sk_win_write_4(sc, SK_GPIO, v);
2466 }
2467
2468 DPRINTFN(6, ("sk_init_yukon: 1\n"));
2469
1fb1e4cd
MD
2470 /* GMAC and GPHY Reset */
2471 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2472 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2473 DELAY(1000);
ce17751a
SZ
2474
2475 DPRINTFN(6, ("sk_init_yukon: 2\n"));
2476
2477 if (sc->sk_type == SK_YUKON_LITE &&
2478 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2479 /*
2480 * Workaround code for COMA mode, clear PHY reset
2481 */
2482 v = sk_win_read_4(sc, SK_GPIO);
2483 v |= SK_GPIO_DIR9;
2484 v &= ~SK_GPIO_DAT9;
2485 sk_win_write_4(sc, SK_GPIO, v);
2486 }
1fb1e4cd
MD
2487
2488 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2489 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2490
ce17751a
SZ
2491 if (sc->sk_coppertype)
2492 phy |= SK_GPHY_COPPER;
2493 else
1fb1e4cd 2494 phy |= SK_GPHY_FIBER;
1fb1e4cd 2495
ce17751a 2496 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
1fb1e4cd
MD
2497
2498 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2499 DELAY(1000);
2500 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2501 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2502 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2503
ce17751a
SZ
2504 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2505 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2506
2507 DPRINTFN(6, ("sk_init_yukon: 3\n"));
2508
1fb1e4cd 2509 /* unused read of the interrupt source register */
ce17751a 2510 DPRINTFN(6, ("sk_init_yukon: 4\n"));
1fb1e4cd
MD
2511 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2512
ce17751a 2513 DPRINTFN(6, ("sk_init_yukon: 4a\n"));
1fb1e4cd 2514 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
ce17751a 2515 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
1fb1e4cd
MD
2516
2517 /* MIB Counter Clear Mode set */
2518 reg |= YU_PAR_MIB_CLR;
ce17751a
SZ
2519 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2520 DPRINTFN(6, ("sk_init_yukon: 4b\n"));
1fb1e4cd
MD
2521 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2522
2523 /* MIB Counter Clear Mode clear */
ce17751a 2524 DPRINTFN(6, ("sk_init_yukon: 5\n"));
1fb1e4cd
MD
2525 reg &= ~YU_PAR_MIB_CLR;
2526 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2527
2528 /* receive control reg */
ce17751a 2529 DPRINTFN(6, ("sk_init_yukon: 7\n"));
0d939d2c 2530 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
1fb1e4cd
MD
2531
2532 /* transmit parameter register */
ce17751a 2533 DPRINTFN(6, ("sk_init_yukon: 8\n"));
1fb1e4cd
MD
2534 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2535 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2536
2537 /* serial mode register */
ce17751a 2538 DPRINTFN(6, ("sk_init_yukon: 9\n"));
ff7f301d
SZ
2539 reg = YU_SMR_DATA_BLIND(0x1c) | YU_SMR_MFL_VLAN | YU_SMR_IPG_DATA(0x1e);
2540 if (sc_if->sk_use_jumbo)
2541 reg |= YU_SMR_MFL_JUMBO;
2542 SK_YU_WRITE_2(sc_if, YUKON_SMR, reg);
1fb1e4cd 2543
ce17751a 2544 DPRINTFN(6, ("sk_init_yukon: 10\n"));
1fb1e4cd
MD
2545 /* Setup Yukon's address */
2546 for (i = 0; i < 3; i++) {
2547 /* Write Source Address 1 (unicast filter) */
2548 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2549 sc_if->arpcom.ac_enaddr[i * 2] |
2550 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2551 }
2552
2553 for (i = 0; i < 3; i++) {
2554 reg = sk_win_read_2(sc_if->sk_softc,
2555 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2556 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2557 }
2558
0d939d2c
MD
2559 /* Set promiscuous mode */
2560 sk_setpromisc(sc_if);
2561
2562 /* Set multicast filter */
ce17751a 2563 DPRINTFN(6, ("sk_init_yukon: 11\n"));
0d939d2c 2564 sk_setmulti(sc_if);
1fb1e4cd
MD
2565
2566 /* enable interrupt mask for counter overflows */
ce17751a 2567 DPRINTFN(6, ("sk_init_yukon: 12\n"));
1fb1e4cd
MD
2568 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2569 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2570 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2571
ce17751a
SZ
2572 /* Configure RX MAC FIFO Flush Mask */
2573 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2574 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2575 YU_RXSTAT_JABBER;
2576 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2577
2578 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2579 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2580 v = SK_TFCTL_OPERATION_ON;
2581 else
2582 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
1fb1e4cd
MD
2583 /* Configure RX MAC FIFO */
2584 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
ce17751a
SZ
2585 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2586
2587 /* Increase flush threshould to 64 bytes */
2588 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2589 SK_RFCTL_FIFO_THRESHOLD + 1);
1fb1e4cd
MD
2590
2591 /* Configure TX MAC FIFO */
2592 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
ce17751a
SZ
2593 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2594
2595 DPRINTFN(6, ("sk_init_yukon: end\n"));
1fb1e4cd
MD
2596}
2597
984263bc
MD
2598/*
2599 * Note that to properly initialize any part of the GEnesis chip,
2600 * you first have to take it out of reset mode.
2601 */
c352b0ba 2602static void
ce17751a 2603sk_init(void *xsc_if)
984263bc 2604{
ce17751a 2605 struct sk_if_softc *sc_if = xsc_if;
c352b0ba
JS
2606 struct sk_softc *sc = sc_if->sk_softc;
2607 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2608 struct mii_data *mii = device_get_softc(sc_if->sk_miibus);
984263bc 2609
ce17751a
SZ
2610 DPRINTFN(2, ("sk_init\n"));
2611
2612 ASSERT_SERIALIZED(ifp->if_serializer);
984263bc 2613
ce17751a 2614 if (ifp->if_flags & IFF_RUNNING)
25c93c10 2615 return;
25c93c10 2616
984263bc
MD
2617 /* Cancel pending I/O and free all RX/TX buffers. */
2618 sk_stop(sc_if);
2619
ff7f301d
SZ
2620 /*
2621 * NOTE: Change sk_use_jumbo after sk_stop(),
2622 * but before real initialization.
2623 */
2624 if (ifp->if_mtu > ETHER_MAX_LEN)
2625 sc_if->sk_use_jumbo = 1;
2626 else
2627 sc_if->sk_use_jumbo = 0;
2628 DPRINTF(("use jumbo buffer: %s\n", sc_if->sk_use_jumbo ? "YES" : "NO"));
2629
ce17751a 2630 if (SK_IS_GENESIS(sc)) {
1fb1e4cd
MD
2631 /* Configure LINK_SYNC LED */
2632 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2633 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2634 SK_LINKLED_LINKSYNC_ON);
984263bc 2635
1fb1e4cd 2636 /* Configure RX LED */
ce17751a 2637 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
1fb1e4cd 2638 SK_RXLEDCTL_COUNTER_START);
ce17751a 2639
1fb1e4cd
MD
2640 /* Configure TX LED */
2641 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2642 SK_TXLEDCTL_COUNTER_START);
2643 }
984263bc 2644
ce17751a
SZ
2645 /*
2646 * Configure descriptor poll timer
2647 *
2648 * SK-NET GENESIS data sheet says that possibility of losing Start
2649 * transmit command due to CPU/cache related interim storage problems
2650 * under certain conditions. The document recommends a polling
2651 * mechanism to send a Start transmit command to initiate transfer
2652 * of ready descriptors regulary. To cope with this issue sk(4) now
2653 * enables descriptor poll timer to initiate descriptor processing
2654 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2655 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2656 * command instead of waiting for next descriptor polling time.
2657 * The same rule may apply to Rx side too but it seems that is not
2658 * needed at the moment.
2659 * Since sk(4) uses descriptor polling as a last resort there is no
2660 * need to set smaller polling time than maximum allowable one.
2661 */
2662 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2663
984263bc
MD
2664 /* Configure I2C registers */
2665
2666 /* Configure XMAC(s) */
1fb1e4cd
MD
2667 switch (sc->sk_type) {
2668 case SK_GENESIS:
2669 sk_init_xmac(sc_if);
2670 break;
2671 case SK_YUKON:
ce17751a
SZ
2672 case SK_YUKON_LITE:
2673 case SK_YUKON_LP:
1fb1e4cd
MD
2674 sk_init_yukon(sc_if);
2675 break;
2676 }
984263bc
MD
2677 mii_mediachg(mii);
2678
ce17751a 2679 if (SK_IS_GENESIS(sc)) {
1fb1e4cd
MD
2680 /* Configure MAC FIFOs */
2681 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2682 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2683 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
984263bc 2684
1fb1e4cd
MD
2685 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2686 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2687 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2688 }
984263bc
MD
2689
2690 /* Configure transmit arbiter(s) */
2691 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
c352b0ba 2692 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
984263bc
MD
2693
2694 /* Configure RAMbuffers */
2695 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2696 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2697 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2698 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2699 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2700 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2701
2702 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2703 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2704 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2705 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2706 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2707 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2708 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2709
2710 /* Configure BMUs */
2711 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2712 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
105b9b5d
SZ
2713 SK_ADDR_LO(sc_if->sk_rdata.sk_rx_ring_paddr));
2714 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI,
2715 SK_ADDR_HI(sc_if->sk_rdata.sk_rx_ring_paddr));
984263bc
MD
2716
2717 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2718 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
105b9b5d
SZ
2719 SK_ADDR_LO(sc_if->sk_rdata.sk_tx_ring_paddr));
2720 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI,
2721 SK_ADDR_HI(sc_if->sk_rdata.sk_tx_ring_paddr));
984263bc
MD
2722
2723 /* Init descriptors */
2724 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
ce17751a
SZ
2725 if_printf(ifp, "initialization failed: "
2726 "no memory for rx buffers\n");
2727 sk_stop(sc_if);
2728 return;
2729 }
2730
2731 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2732 if_printf(ifp, "initialization failed: "
2733 "no memory for tx buffers\n");
984263bc 2734 sk_stop(sc_if);
984263bc
MD
2735 return;
2736 }
984263bc
MD
2737
2738 /* Configure interrupt handling */
2739 CSR_READ_4(sc, SK_ISSR);
2740 if (sc_if->sk_port == SK_PORT_A)
2741 sc->sk_intrmask |= SK_INTRS1;
2742 else
2743 sc->sk_intrmask |= SK_INTRS2;
2744
2745 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2746
2747 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2748
2749 /* Start BMUs. */
2750 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2751
ce17751a 2752 if (SK_IS_GENESIS(sc)) {
1fb1e4cd
MD
2753 /* Enable XMACs TX and RX state machines */
2754 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
c352b0ba 2755 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
ce17751a
SZ
2756 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2757 }
2758
2759 if (SK_IS_YUKON(sc)) {
2760 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
1fb1e4cd 2761 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
ce17751a
SZ
2762#if 0
2763 /* XXX disable 100Mbps and full duplex mode? */
2764 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_DIS);
2765#endif
1fb1e4cd
MD
2766 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2767 }
984263bc 2768
ce17751a
SZ
2769 /* Activate descriptor polling timer */
2770 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2771 /* Start transfer of Tx descriptors */
2772 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2773
984263bc
MD
2774 ifp->if_flags |= IFF_RUNNING;
2775 ifp->if_flags &= ~IFF_OACTIVE;
2776
ce17751a
SZ
2777 if (SK_IS_YUKON(sc))
2778 callout_reset(&sc_if->sk_tick_timer, hz, sk_yukon_tick, sc_if);
984263bc
MD
2779}
2780
c352b0ba
JS
2781static void
2782sk_stop(struct sk_if_softc *sc_if)
984263bc 2783{
c352b0ba
JS
2784 struct sk_softc *sc = sc_if->sk_softc;
2785 struct ifnet *ifp = &sc_if->arpcom.ac_if;
ce17751a
SZ
2786 struct sk_chain_data *cd = &sc_if->sk_cdata;
2787 uint32_t val;
2788 int i;
2789
2790 ASSERT_SERIALIZED(ifp->if_serializer);
2791
2792 DPRINTFN(2, ("sk_stop\n"));
984263bc 2793
664739a3 2794 callout_stop(&sc_if->sk_tick_timer);
984263bc 2795
ce17751a
SZ
2796 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
2797
2798 /* Stop Tx descriptor polling timer */
2799 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2800
2801 /* Stop transfer of Tx descriptors */
2802 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2803 for (i = 0; i < SK_TIMEOUT; i++) {
2804 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2805 if (!(val & SK_TXBMU_TX_STOP))
2806 break;
2807 DELAY(1);
2808 }
2809 if (i == SK_TIMEOUT)
2810 if_printf(ifp, "cannot stop transfer of Tx descriptors\n");
2811
2812 /* Stop transfer of Rx descriptors */
2813 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2814 for (i = 0; i < SK_TIMEOUT; i++) {
2815 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2816 if (!(val & SK_RXBMU_RX_STOP))
2817 break;
2818 DELAY(1);
2819 }
2820 if (i == SK_TIMEOUT)
2821 if_printf(ifp, "cannot stop transfer of Rx descriptors\n");
984263bc 2822
ce17751a 2823 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
984263bc
MD
2824 /* Put PHY back into reset. */
2825 val = sk_win_read_4(sc, SK_GPIO);
2826 if (sc_if->sk_port == SK_PORT_A) {
2827 val |= SK_GPIO_DIR0;
2828 val &= ~SK_GPIO_DAT0;
2829 } else {
2830 val |= SK_GPIO_DIR2;
2831 val &= ~SK_GPIO_DAT2;
2832 }
2833 sk_win_write_4(sc, SK_GPIO, val);
2834 }
2835
2836 /* Turn off various components of this interface. */
2837 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
1fb1e4cd
MD
2838 switch (sc->sk_type) {
2839 case SK_GENESIS:
2840 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_RESET);
2841 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2842 break;
2843 case SK_YUKON:
ce17751a
SZ
2844 case SK_YUKON_LITE:
2845 case SK_YUKON_LP:
1fb1e4cd
MD
2846 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2847 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2848 break;
2849 }
984263bc 2850 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
c352b0ba 2851 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET | SK_RBCTL_OFF);
984263bc 2852 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
c352b0ba
JS
2853 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST,
2854 SK_RBCTL_RESET | SK_RBCTL_OFF);
984263bc
MD
2855 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2856 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2857 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2858 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2859 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2860
2861 /* Disable interrupts */
2862 if (sc_if->sk_port == SK_PORT_A)
2863 sc->sk_intrmask &= ~SK_INTRS1;
2864 else
2865 sc->sk_intrmask &= ~SK_INTRS2;
2866 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2867
2868 SK_XM_READ_2(sc_if, XM_ISR);
2869 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2870
2871 /* Free RX and TX mbufs still in the queues. */
2872 for (i = 0; i < SK_RX_RING_CNT; i++) {
ff7f301d
SZ
2873 if (cd->sk_rx_mbuf[i] != NULL) {
2874 if (!sc_if->sk_use_jumbo) {
2875 bus_dmamap_unload(cd->sk_rx_dtag,
2876 cd->sk_rx_dmap[i]);
2877 }
2878 m_freem(cd->sk_rx_mbuf[i]);
2879 cd->sk_rx_mbuf[i] = NULL;
984263bc
MD
2880 }
2881 }
ce17751a 2882 for (i = 0; i < SK_TX_RING_CNT; i++) {
ff7f301d 2883 if (cd->sk_tx_mbuf[i] != NULL) {
ce17751a 2884 bus_dmamap_unload(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
ff7f301d
SZ
2885 m_freem(cd->sk_tx_mbuf[i]);
2886 cd->sk_tx_mbuf[i] = NULL;
ce17751a
SZ
2887 }
2888 }
2889}
2890
2891#ifdef SK_DEBUG
2892static void
2893sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2894{
2895#define DESC_PRINT(X) \
2896 if (X) \
e3869ec7 2897 kprintf("txdesc[%d]." #X "=%#x\n", \
ce17751a
SZ
2898 idx, X);
2899
2900 DESC_PRINT(le32toh(desc->sk_ctl));
2901 DESC_PRINT(le32toh(desc->sk_next));
2902 DESC_PRINT(le32toh(desc->sk_data_lo));
2903 DESC_PRINT(le32toh(desc->sk_data_hi));
2904 DESC_PRINT(le32toh(desc->sk_xmac_txstat));
2905 DESC_PRINT(le16toh(desc->sk_rsvd0));
2906 DESC_PRINT(le16toh(desc->sk_csum_startval));
2907 DESC_PRINT(le16toh(desc->sk_csum_startpos));
2908 DESC_PRINT(le16toh(desc->sk_csum_writepos));
2909 DESC_PRINT(le16toh(desc->sk_rsvd1));
2910#undef PRINT
2911}
2912
2913static void
2914sk_dump_bytes(const char *data, int len)
2915{
2916 int c, i, j;
2917
2918 for (i = 0; i < len; i += 16) {
e3869ec7 2919 kprintf("%08x ", i);
ce17751a
SZ
2920 c = len - i;
2921 if (c > 16) c = 16;
2922
2923 for (j = 0; j < c; j++) {
e3869ec7 2924 kprintf("%02x ", data[i + j] & 0xff);
ce17751a 2925 if ((j & 0xf) == 7 && j > 0)
e3869ec7 2926 kprintf(" ");
ce17751a
SZ
2927 }
2928
2929 for (; j < 16; j++)
e3869ec7
SW
2930 kprintf(" ");
2931 kprintf(" ");
ce17751a
SZ
2932
2933 for (j = 0; j < c; j++) {
2934 int ch = data[i + j] & 0xff;
e3869ec7 2935 kprintf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
ce17751a
SZ
2936 }
2937
e3869ec7 2938 kprintf("\n");
ce17751a
SZ
2939
2940 if (c < 16)
2941 break;
2942 }
2943}
2944
2945static void
2946sk_dump_mbuf(struct mbuf *m)
2947{
2948 int count = m->m_pkthdr.len;
2949
e3869ec7 2950 kprintf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
ce17751a
SZ
2951
2952 while (count > 0 && m) {
e3869ec7 2953 kprintf("m=%p, m->m_data=%p, m->m_len=%d\n",
ce17751a
SZ
2954 m, m->m_data, m->m_len);
2955 sk_dump_bytes(mtod(m, char *), m->m_len);
2956
2957 count -= m->m_len;
2958 m = m->m_next;
2959 }
2960}
2961#endif
2962
2963/*
2964 * Allocate jumbo buffer storage. The SysKonnect adapters support
2965 * "jumbograms" (9K frames), although SysKonnect doesn't currently
2966 * use them in their drivers. In order for us to use them, we need
2967 * large 9K receive buffers, however standard mbuf clusters are only
2968 * 2048 bytes in size. Consequently, we need to allocate and manage
2969 * our own jumbo buffer pool. Fortunately, this does not require an
2970 * excessive amount of additional code.
2971 */
2972static int
2973sk_jpool_alloc(device_t dev)
2974{
2975 struct sk_if_softc *sc_if = device_get_softc(dev);
2976 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d 2977 bus_dmamem_t dmem;
ce17751a
SZ
2978 bus_addr_t paddr;
2979 caddr_t buf;
2980 int error, i;
2981
2982 lwkt_serialize_init(&cd->sk_jpool_serializer);
2983
105b9b5d
SZ
2984 error = bus_dmamem_coherent(cd->sk_buf_dtag, PAGE_SIZE /* XXX */, 0,
2985 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2986 SK_JMEM, BUS_DMA_WAITOK, &dmem);
ce17751a 2987 if (error) {
105b9b5d 2988 device_printf(dev, "can't allocate jumbo frame pool\n");
ce17751a
SZ
2989 return error;
2990 }
105b9b5d
SZ
2991 cd->sk_jpool_dtag = dmem.dmem_tag;
2992 cd->sk_jpool_dmap = dmem.dmem_map;
2993 cd->sk_jpool = dmem.dmem_addr;
2994 paddr = dmem.dmem_busaddr;
ce17751a
SZ
2995
2996 SLIST_INIT(&cd->sk_jpool_free_ent);
2997 buf = cd->sk_jpool;
2998
2999 /*
3000 * Now divide it up into SK_JLEN pieces.
3001 */
3002 for (i = 0; i < SK_JSLOTS; i++) {
3003 struct sk_jpool_entry *entry = &cd->sk_jpool_ent[i];
3004
3005 entry->sc_if = sc_if;
3006 entry->inuse = 0;
3007 entry->slot = i;
3008 entry->buf = buf;
3009 entry->paddr = paddr;
3010
3011 SLIST_INSERT_HEAD(&cd->sk_jpool_free_ent, entry, entry_next);
3012
3013 buf += SK_JLEN;
3014 paddr += SK_JLEN;
3015 }
3016 return 0;
3017}
3018
3019static void
3020sk_jpool_free(struct sk_if_softc *sc_if)
3021{
3022 struct sk_chain_data *cd = &sc_if->sk_cdata;
3023
3024 if (cd->sk_jpool_dtag != NULL) {
3025 bus_dmamap_unload(cd->sk_jpool_dtag, cd->sk_jpool_dmap);
3026 bus_dmamem_free(cd->sk_jpool_dtag, cd->sk_jpool,
3027 cd->sk_jpool_dmap);
3028 bus_dma_tag_destroy(cd->sk_jpool_dtag);
3029 cd->sk_jpool_dtag = NULL;
3030 }
3031}
3032
3033static int
3034sk_dma_alloc(device_t dev)
3035{
3036 struct sk_if_softc *sc_if = device_get_softc(dev);
3037 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d
SZ
3038 struct sk_ring_data *rd = &sc_if->sk_rdata;
3039 bus_dmamem_t dmem;
ce17751a
SZ
3040 int i, j, error;
3041
105b9b5d
SZ
3042 /* Create parent DMA tag */
3043 error = bus_dma_tag_create(NULL, 1, 0,
3044 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3045 NULL, NULL,
3046 BUS_SPACE_MAXSIZE_32BIT, 0,
3047 BUS_SPACE_MAXSIZE_32BIT,
3048 0, &sc_if->sk_parent_dtag);
3049 if (error) {
3050 device_printf(dev, "can't create parent DMA tag\n");
3051 return error;
3052 }
3053
3054 /* Create top level ring DMA tag */
3055 error = bus_dma_tag_create(sc_if->sk_parent_dtag,
3056 1, SK_RING_BOUNDARY,
3057 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3058 NULL, NULL,
3059 BUS_SPACE_MAXSIZE_32BIT, 0,
3060 BUS_SPACE_MAXSIZE_32BIT,
3061 0, &rd->sk_ring_dtag);
3062 if (error) {
3063 device_printf(dev, "can't create ring DMA tag\n");
3064 return error;
3065 }
3066
3067 /* Create top level buffer DMA tag */
3068 error = bus_dma_tag_create(sc_if->sk_parent_dtag, 1, 0,
3069 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ce17751a 3070 NULL, NULL,
105b9b5d
SZ
3071 BUS_SPACE_MAXSIZE_32BIT, 0,
3072 BUS_SPACE_MAXSIZE_32BIT,
3073 0, &cd->sk_buf_dtag);
ce17751a 3074 if (error) {
105b9b5d 3075 device_printf(dev, "can't create buf DMA tag\n");
ce17751a
SZ
3076 return error;
3077 }
3078
105b9b5d
SZ
3079 /* Allocate the TX descriptor queue. */
3080 error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3081 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3082 SK_TX_RING_SIZE,
3083 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
ce17751a 3084 if (error) {
105b9b5d 3085 device_printf(dev, "can't allocate TX ring\n");
ce17751a
SZ
3086 return error;
3087 }
105b9b5d
SZ
3088 rd->sk_tx_ring_dtag = dmem.dmem_tag;
3089 rd->sk_tx_ring_dmap = dmem.dmem_map;
3090 rd->sk_tx_ring = dmem.dmem_addr;
3091 rd->sk_tx_ring_paddr = dmem.dmem_busaddr;
ce17751a 3092
105b9b5d
SZ
3093 /* Allocate the RX descriptor queue. */
3094 error = bus_dmamem_coherent(rd->sk_ring_dtag, SK_RING_ALIGN, 0,
3095 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3096 SK_RX_RING_SIZE,
3097 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
ce17751a 3098 if (error) {
105b9b5d 3099 device_printf(dev, "can't allocate TX ring\n");
ce17751a
SZ
3100 return error;
3101 }
105b9b5d
SZ
3102 rd->sk_rx_ring_dtag = dmem.dmem_tag;
3103 rd->sk_rx_ring_dmap = dmem.dmem_map;
3104 rd->sk_rx_ring = dmem.dmem_addr;
3105 rd->sk_rx_ring_paddr = dmem.dmem_busaddr;
ce17751a
SZ
3106
3107 /* Try to allocate memory for jumbo buffers. */
3108 error = sk_jpool_alloc(dev);
3109 if (error) {
3110 device_printf(dev, "jumbo buffer allocation failed\n");
3111 return error;
3112 }
3113
3114 /* Create DMA tag for TX. */
105b9b5d
SZ
3115 error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3116 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
ce17751a
SZ
3117 NULL, NULL,
3118 SK_JLEN, SK_NTXSEG, SK_JLEN,
105b9b5d
SZ
3119 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3120 BUS_DMA_ONEBPAGE,
3121 &cd->sk_tx_dtag);
ce17751a
SZ
3122 if (error) {
3123 device_printf(dev, "can't create TX DMA tag\n");
3124 return error;
3125 }
3126
3127 /* Create DMA maps for TX. */
984263bc 3128 for (i = 0; i < SK_TX_RING_CNT; i++) {
105b9b5d
SZ
3129 error = bus_dmamap_create(cd->sk_tx_dtag,
3130 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
ce17751a
SZ
3131 &cd->sk_tx_dmap[i]);
3132 if (error) {
3133 device_printf(dev, "can't create %dth TX DMA map\n", i);
ff7f301d
SZ
3134
3135 for (j = 0; j < i; ++j) {
3136 bus_dmamap_destroy(cd->sk_tx_dtag,
3137 cd->sk_tx_dmap[i]);
3138 }
3139 bus_dma_tag_destroy(cd->sk_tx_dtag);
3140 cd->sk_tx_dtag = NULL;
3141 return error;
3142 }
3143 }
3144
3145 /* Create DMA tag for RX. */
105b9b5d
SZ
3146 error = bus_dma_tag_create(cd->sk_buf_dtag, 1, 0,
3147 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3148 NULL, NULL,
3149 MCLBYTES, 1, MCLBYTES,
3150 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3151 &cd->sk_rx_dtag);
ff7f301d
SZ
3152 if (error) {
3153 device_printf(dev, "can't create RX DMA tag\n");
3154 return error;
3155 }
3156
3157 /* Create a spare RX DMA map. */
105b9b5d
SZ
3158 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
3159 &cd->sk_rx_dmap_tmp);
ff7f301d
SZ
3160 if (error) {
3161 device_printf(dev, "can't create spare RX DMA map\n");
3162 bus_dma_tag_destroy(cd->sk_rx_dtag);
3163 cd->sk_rx_dtag = NULL;
3164 return error;
3165 }
3166
3167 /* Create DMA maps for RX. */
3168 for (i = 0; i < SK_RX_RING_CNT; ++i) {
105b9b5d 3169 error = bus_dmamap_create(cd->sk_rx_dtag, BUS_DMA_WAITOK,
ff7f301d
SZ
3170 &cd->sk_rx_dmap[i]);
3171 if (error) {
3172 device_printf(dev, "can't create %dth RX DMA map\n", i);
3173
3174 for (j = 0; j < i; ++j) {
3175 bus_dmamap_destroy(cd->sk_rx_dtag,
3176 cd->sk_rx_dmap[i]);
3177 }
3178 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3179 bus_dma_tag_destroy(cd->sk_rx_dtag);
3180 cd->sk_rx_dtag = NULL;
3181 return error;
984263bc
MD
3182 }
3183 }
ce17751a 3184 return 0;
ce17751a 3185}
984263bc 3186
ce17751a
SZ
3187static void
3188sk_dma_free(device_t dev)
3189{
3190 struct sk_if_softc *sc_if = device_get_softc(dev);
3191 struct sk_chain_data *cd = &sc_if->sk_cdata;
105b9b5d 3192 struct sk_ring_data *rd = &sc_if->sk_rdata;
ff7f301d 3193 int i;
ce17751a
SZ
3194
3195 if (cd->sk_tx_dtag != NULL) {
ce17751a 3196 for (i = 0; i < SK_TX_RING_CNT; ++i) {
ff7f301d
SZ
3197 KASSERT(cd->sk_tx_mbuf[i] == NULL,
3198 ("sk_stop() is not called before %s()",
3199 __func__));
ce17751a
SZ
3200 bus_dmamap_destroy(cd->sk_tx_dtag, cd->sk_tx_dmap[i]);
3201 }
3202 bus_dma_tag_destroy(cd->sk_tx_dtag);
ce17751a
SZ
3203 }
3204
ff7f301d
SZ
3205 if (cd->sk_rx_dtag != NULL) {
3206 for (i = 0; i < SK_RX_RING_CNT; ++i) {
3207 KASSERT(cd->sk_rx_mbuf[i] == NULL,
3208 ("sk_stop() is not called before %s()",
3209 __func__));
3210 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap[i]);
3211 }
3212 bus_dmamap_destroy(cd->sk_rx_dtag, cd->sk_rx_dmap_tmp);
3213 bus_dma_tag_destroy(cd->sk_rx_dtag);
ff7f301d
SZ
3214 }
3215
ce17751a
SZ
3216 sk_jpool_free(sc_if);
3217
105b9b5d
SZ
3218 if (rd->sk_rx_ring_dtag != NULL) {
3219 bus_dmamap_unload(rd->sk_rx_ring_dtag, rd->sk_rx_ring_dmap);
3220 bus_dmamem_free(rd->sk_rx_ring_dtag, rd->sk_rx_ring,
3221 rd->sk_rx_ring_dmap);
3222 bus_dma_tag_destroy(rd->sk_rx_ring_dtag);
ce17751a 3223 }
105b9b5d
SZ
3224
3225 if (rd->sk_tx_ring_dtag != NULL) {
3226 bus_dmamap_unload(rd->sk_tx_ring_dtag, rd->sk_tx_ring_dmap);
3227 bus_dmamem_free(rd->sk_tx_ring_dtag, rd->sk_tx_ring,
3228 rd->sk_tx_ring_dmap);
3229 bus_dma_tag_destroy(rd->sk_tx_ring_dtag);
3230 }
3231
3232 if (rd->sk_ring_dtag != NULL)
3233 bus_dma_tag_destroy(rd->sk_ring_dtag);
3234 if (cd->sk_buf_dtag != NULL)
3235 bus_dma_tag_destroy(cd->sk_buf_dtag);
3236 if (sc_if->sk_parent_dtag != NULL)
3237 bus_dma_tag_destroy(sc_if->sk_parent_dtag);
ce17751a
SZ
3238}
3239
dbe44a55
SZ
3240static int
3241skc_sysctl_imtime(SYSCTL_HANDLER_ARGS)
3242{
3243 struct sk_softc *sc = arg1;
3244 struct lwkt_serialize *slize = &sc->sk_serializer;
3245 int error = 0, v;
3246
3247 lwkt_serialize_enter(slize);
3248
3249 v = sc->sk_imtime;
3250 error = sysctl_handle_int(oidp, &v, 0, req);
3251 if (error || req->newptr == NULL)
3252 goto back;
3253 if (v <= 0) {
3254 error = EINVAL;
3255 goto back;
3256 }
3257
3258 if (sc->sk_imtime != v) {
3259 sc->sk_imtime = v;
3260 sk_win_write_4(sc, SK_IMTIMERINIT,
3261 SK_IM_USECS(sc, sc->sk_imtime));
3262
3263 /*
3264 * Force interrupt moderation timer to
3265 * reload new value.
3266 */
3267 sk_win_write_4(sc, SK_IMTIMER, 0);
3268 }
3269back:
3270 lwkt_serialize_exit(slize);
3271 return error;
3272}