network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / tl / if_tl.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_tl.c,v 1.51.2.5 2001/12/16 15:46:08 luigi Exp $
95893fe4 33 * $DragonFly: src/sys/dev/netif/tl/if_tl.c,v 1.40 2008/08/17 04:32:34 sephe Exp $
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34 */
35
36/*
37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x.
38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller,
39 * the National Semiconductor DP83840A physical interface and the
40 * Microchip Technology 24Cxx series serial EEPROM.
41 *
42 * Written using the following four documents:
43 *
44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com)
45 * National Semiconductor DP83840A data sheet (www.national.com)
46 * Microchip Technology 24C02C data sheet (www.microchip.com)
47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com)
48 *
49 * Written by Bill Paul <wpaul@ctr.columbia.edu>
50 * Electrical Engineering Department
51 * Columbia University, New York City
52 */
53
54/*
55 * Some notes about the ThunderLAN:
56 *
57 * The ThunderLAN controller is a single chip containing PCI controller
58 * logic, approximately 3K of on-board SRAM, a LAN controller, and media
59 * independent interface (MII) bus. The MII allows the ThunderLAN chip to
60 * control up to 32 different physical interfaces (PHYs). The ThunderLAN
61 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller
62 * to act as a complete ethernet interface.
63 *
64 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards
65 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec
66 * in full or half duplex. Some of the Compaq Deskpro machines use a
67 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters
68 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in
69 * concert with the ThunderLAN's internal PHY to provide full 10/100
70 * support. This is cheaper than using a standalone external PHY for both
71 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste.
72 * A serial EEPROM is also attached to the ThunderLAN chip to provide
73 * power-up default register settings and for storing the adapter's
74 * station address. Although not supported by this driver, the ThunderLAN
75 * chip can also be connected to token ring PHYs.
76 *
77 * The ThunderLAN has a set of registers which can be used to issue
78 * commands, acknowledge interrupts, and to manipulate other internal
79 * registers on its DIO bus. The primary registers can be accessed
80 * using either programmed I/O (inb/outb) or via PCI memory mapping,
81 * depending on how the card is configured during the PCI probing
82 * phase. It is even possible to have both PIO and memory mapped
83 * access turned on at the same time.
84 *
85 * Frame reception and transmission with the ThunderLAN chip is done
86 * using frame 'lists.' A list structure looks more or less like this:
87 *
88 * struct tl_frag {
89 * u_int32_t fragment_address;
90 * u_int32_t fragment_size;
91 * };
92 * struct tl_list {
93 * u_int32_t forward_pointer;
94 * u_int16_t cstat;
95 * u_int16_t frame_size;
96 * struct tl_frag fragments[10];
97 * };
98 *
99 * The forward pointer in the list header can be either a 0 or the address
100 * of another list, which allows several lists to be linked together. Each
101 * list contains up to 10 fragment descriptors. This means the chip allows
102 * ethernet frames to be broken up into up to 10 chunks for transfer to
103 * and from the SRAM. Note that the forward pointer and fragment buffer
104 * addresses are physical memory addresses, not virtual. Note also that
105 * a single ethernet frame can not span lists: if the host wants to
106 * transmit a frame and the frame data is split up over more than 10
107 * buffers, the frame has to collapsed before it can be transmitted.
108 *
109 * To receive frames, the driver sets up a number of lists and populates
110 * the fragment descriptors, then it sends an RX GO command to the chip.
111 * When a frame is received, the chip will DMA it into the memory regions
112 * specified by the fragment descriptors and then trigger an RX 'end of
113 * frame interrupt' when done. The driver may choose to use only one
114 * fragment per list; this may result is slighltly less efficient use
115 * of memory in exchange for improving performance.
116 *
117 * To transmit frames, the driver again sets up lists and fragment
118 * descriptors, only this time the buffers contain frame data that
119 * is to be DMA'ed into the chip instead of out of it. Once the chip
120 * has transfered the data into its on-board SRAM, it will trigger a
121 * TX 'end of frame' interrupt. It will also generate an 'end of channel'
122 * interrupt when it reaches the end of the list.
123 */
124
125/*
126 * Some notes about this driver:
127 *
128 * The ThunderLAN chip provides a couple of different ways to organize
129 * reception, transmission and interrupt handling. The simplest approach
130 * is to use one list each for transmission and reception. In this mode,
131 * the ThunderLAN will generate two interrupts for every received frame
132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one
133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts
134 * performance to have to handle so many interrupts.
135 *
136 * Initially I wanted to create a circular list of receive buffers so
137 * that the ThunderLAN chip would think there was an infinitely long
138 * receive channel and never deliver an RXEOC interrupt. However this
139 * doesn't work correctly under heavy load: while the manual says the
140 * chip will trigger an RXEOF interrupt each time a frame is copied into
141 * memory, you can't count on the chip waiting around for you to acknowledge
142 * the interrupt before it starts trying to DMA the next frame. The result
143 * is that the chip might traverse the entire circular list and then wrap
144 * around before you have a chance to do anything about it. Consequently,
145 * the receive list is terminated (with a 0 in the forward pointer in the
146 * last element). Each time an RXEOF interrupt arrives, the used list
147 * is shifted to the end of the list. This gives the appearance of an
148 * infinitely large RX chain so long as the driver doesn't fall behind
149 * the chip and allow all of the lists to be filled up.
150 *
151 * If all the lists are filled, the adapter will deliver an RX 'end of
152 * channel' interrupt when it hits the 0 forward pointer at the end of
153 * the chain. The RXEOC handler then cleans out the RX chain and resets
154 * the list head pointer in the ch_parm register and restarts the receiver.
155 *
156 * For frame transmission, it is possible to program the ThunderLAN's
157 * transmit interrupt threshold so that the chip can acknowledge multiple
158 * lists with only a single TX EOF interrupt. This allows the driver to
159 * queue several frames in one shot, and only have to handle a total
160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames
161 * are transmitted. Frame transmission is done directly out of the
162 * mbufs passed to the tl_start() routine via the interface send queue.
163 * The driver simply sets up the fragment descriptors in the transmit
164 * lists to point to the mbuf data regions and sends a TX GO command.
165 *
166 * Note that since the RX and TX lists themselves are always used
167 * only by the driver, the are malloc()ed once at driver initialization
168 * time and never free()ed.
169 *
170 * Also, in order to remain as platform independent as possible, this
171 * driver uses memory mapped register access to manipulate the card
172 * as opposed to programmed I/O. This avoids the use of the inb/outb
173 * (and related) instructions which are specific to the i386 platform.
174 *
175 * Using these techniques, this driver achieves very high performance
176 * by minimizing the amount of interrupts generated during large
177 * transfers and by completely avoiding buffer copies. Frame transfer
178 * to and from the ThunderLAN chip is performed entirely by the chip
179 * itself thereby reducing the load on the host CPU.
180 */
181
182#include <sys/param.h>
183#include <sys/systm.h>
184#include <sys/sockio.h>
185#include <sys/mbuf.h>
186#include <sys/malloc.h>
187#include <sys/kernel.h>
188#include <sys/socket.h>
78195a76 189#include <sys/serialize.h>
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190#include <sys/bus.h>
191#include <sys/rman.h>
9228feed 192#include <sys/thread2.h>
9db4b353 193#include <sys/interrupt.h>
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194
195#include <net/if.h>
ee9af5ee 196#include <net/ifq_var.h>
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197#include <net/if_arp.h>
198#include <net/ethernet.h>
199#include <net/if_dl.h>
200#include <net/if_media.h>
201
202#include <net/bpf.h>
203
204#include <vm/vm.h> /* for vtophys */
205#include <vm/pmap.h> /* for vtophys */
984263bc 206
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207#include "../mii_layer/mii.h"
208#include "../mii_layer/miivar.h"
984263bc 209
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210#include <bus/pci/pcireg.h>
211#include <bus/pci/pcivar.h>
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212
213/*
214 * Default to using PIO register access mode to pacify certain
215 * laptop docking stations with built-in ThunderLAN chips that
216 * don't seem to handle memory mapped mode properly.
217 */
218#define TL_USEIOSPACE
219
1f2de5d4 220#include "if_tlreg.h"
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221
222/* "controller miibus0" required. See GENERIC if you get errors here. */
223#include "miibus_if.h"
224
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225/*
226 * Various supported device vendors/types and their names.
227 */
228
229static struct tl_type tl_devs[] = {
230 { TI_VENDORID, TI_DEVICEID_THUNDERLAN,
231 "Texas Instruments ThunderLAN" },
232 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10,
233 "Compaq Netelligent 10" },
234 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100,
235 "Compaq Netelligent 10/100" },
236 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT,
237 "Compaq Netelligent 10/100 Proliant" },
238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL,
239 "Compaq Netelligent 10/100 Dual Port" },
240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED,
241 "Compaq NetFlex-3/P Integrated" },
242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P,
243 "Compaq NetFlex-3/P" },
244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC,
245 "Compaq NetFlex 3/P w/ BNC" },
246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED,
247 "Compaq Netelligent 10/100 TX Embedded UTP" },
248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX,
249 "Compaq Netelligent 10 T/2 PCI UTP/Coax" },
250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP,
251 "Compaq Netelligent 10/100 TX UTP" },
252 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183,
253 "Olicom OC-2183/2185" },
254 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325,
255 "Olicom OC-2325" },
256 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326,
257 "Olicom OC-2326 10/100 TX UTP" },
258 { 0, 0, NULL }
259};
260
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261static int tl_probe (device_t);
262static int tl_attach (device_t);
263static int tl_detach (device_t);
264static int tl_intvec_rxeoc (void *, u_int32_t);
265static int tl_intvec_txeoc (void *, u_int32_t);
266static int tl_intvec_txeof (void *, u_int32_t);
267static int tl_intvec_rxeof (void *, u_int32_t);
268static int tl_intvec_adchk (void *, u_int32_t);
269static int tl_intvec_netsts (void *, u_int32_t);
984263bc 270
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271static int tl_newbuf (struct tl_softc *,
272 struct tl_chain_onefrag *);
273static void tl_stats_update (void *);
78195a76 274static void tl_stats_update_serialized(void *);
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275static int tl_encap (struct tl_softc *, struct tl_chain *,
276 struct mbuf *);
984263bc 277
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278static void tl_intr (void *);
279static void tl_start (struct ifnet *);
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280static int tl_ioctl (struct ifnet *, u_long, caddr_t,
281 struct ucred *);
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282static void tl_init (void *);
283static void tl_stop (struct tl_softc *);
284static void tl_watchdog (struct ifnet *);
285static void tl_shutdown (device_t);
286static int tl_ifmedia_upd (struct ifnet *);
287static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
984263bc 288
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289static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int);
290static u_int8_t tl_eeprom_getbyte (struct tl_softc *,
291 int, u_int8_t *);
292static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int);
984263bc 293
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294static void tl_mii_sync (struct tl_softc *);
295static void tl_mii_send (struct tl_softc *, u_int32_t, int);
296static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *);
297static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *);
298static int tl_miibus_readreg (device_t, int, int);
299static int tl_miibus_writereg (device_t, int, int, int);
300static void tl_miibus_statchg (device_t);
984263bc 301
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302static void tl_setmode (struct tl_softc *, int);
303static int tl_calchash (caddr_t);
304static void tl_setmulti (struct tl_softc *);
305static void tl_setfilt (struct tl_softc *, caddr_t, int);
306static void tl_softreset (struct tl_softc *, int);
307static void tl_hardreset (device_t);
308static int tl_list_rx_init (struct tl_softc *);
309static int tl_list_tx_init (struct tl_softc *);
984263bc 310
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311static u_int8_t tl_dio_read8 (struct tl_softc *, int);
312static u_int16_t tl_dio_read16 (struct tl_softc *, int);
313static u_int32_t tl_dio_read32 (struct tl_softc *, int);
314static void tl_dio_write8 (struct tl_softc *, int, int);
315static void tl_dio_write16 (struct tl_softc *, int, int);
316static void tl_dio_write32 (struct tl_softc *, int, int);
317static void tl_dio_setbit (struct tl_softc *, int, int);
318static void tl_dio_clrbit (struct tl_softc *, int, int);
319static void tl_dio_setbit16 (struct tl_softc *, int, int);
320static void tl_dio_clrbit16 (struct tl_softc *, int, int);
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321
322#ifdef TL_USEIOSPACE
323#define TL_RES SYS_RES_IOPORT
324#define TL_RID TL_PCI_LOIO
325#else
326#define TL_RES SYS_RES_MEMORY
327#define TL_RID TL_PCI_LOMEM
328#endif
329
330static device_method_t tl_methods[] = {
331 /* Device interface */
332 DEVMETHOD(device_probe, tl_probe),
333 DEVMETHOD(device_attach, tl_attach),
334 DEVMETHOD(device_detach, tl_detach),
335 DEVMETHOD(device_shutdown, tl_shutdown),
336
337 /* bus interface */
338 DEVMETHOD(bus_print_child, bus_generic_print_child),
339 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
340
341 /* MII interface */
342 DEVMETHOD(miibus_readreg, tl_miibus_readreg),
343 DEVMETHOD(miibus_writereg, tl_miibus_writereg),
344 DEVMETHOD(miibus_statchg, tl_miibus_statchg),
345
346 { 0, 0 }
347};
348
349static driver_t tl_driver = {
350 "tl",
351 tl_methods,
352 sizeof(struct tl_softc)
353};
354
355static devclass_t tl_devclass;
356
32832096 357DECLARE_DUMMY_MODULE(if_tl);
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358DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0);
359DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0);
360
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361static u_int8_t
362tl_dio_read8(struct tl_softc *sc, int reg)
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363{
364 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
365 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)));
366}
367
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368static u_int16_t
369tl_dio_read16(struct tl_softc *sc, int reg)
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370{
371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
372 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
373}
374
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375static u_int32_t
376tl_dio_read32(struct tl_softc *sc, int reg)
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377{
378 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
379 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));
380}
381
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382static void
383tl_dio_write8(struct tl_softc *sc, int reg, int val)
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384{
385 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
386 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val);
387 return;
388}
389
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390static void
391tl_dio_write16(struct tl_softc *sc, int reg, int val)
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392{
393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
394 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
395 return;
396}
397
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398static void
399tl_dio_write32(struct tl_softc *sc, int reg, int val)
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400{
401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
402 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val);
403 return;
404}
405
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406static void
407tl_dio_setbit(struct tl_softc *sc, int reg, int bit)
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408{
409 u_int8_t f;
410
411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
412 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
413 f |= bit;
414 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
415
416 return;
417}
418
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419static void
420tl_dio_clrbit(struct tl_softc *sc, int reg, int bit)
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421{
422 u_int8_t f;
423
424 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
425 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3));
426 f &= ~bit;
427 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f);
428
429 return;
430}
431
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432static void
433tl_dio_setbit16(struct tl_softc *sc, int reg, int bit)
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434{
435 u_int16_t f;
436
437 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
438 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
439 f |= bit;
440 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
441
442 return;
443}
444
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445static void
446tl_dio_clrbit16(struct tl_softc *sc, int reg, int bit)
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447{
448 u_int16_t f;
449
450 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
451 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
452 f &= ~bit;
453 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f);
454
455 return;
456}
457
458/*
459 * Send an instruction or address to the EEPROM, check for ACK.
460 */
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461static u_int8_t
462tl_eeprom_putbyte(struct tl_softc *sc, int byte)
984263bc 463{
3d0f5f54 464 int i, ack = 0;
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465
466 /*
467 * Make sure we're in TX mode.
468 */
469 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN);
470
471 /*
472 * Feed in each bit and stobe the clock.
473 */
474 for (i = 0x80; i; i >>= 1) {
475 if (byte & i) {
476 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA);
477 } else {
478 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA);
479 }
480 DELAY(1);
481 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
482 DELAY(1);
483 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
484 }
485
486 /*
487 * Turn off TX mode.
488 */
489 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
490
491 /*
492 * Check for ack.
493 */
494 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
495 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA;
496 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
497
498 return(ack);
499}
500
501/*
502 * Read a byte of data stored in the EEPROM at address 'addr.'
503 */
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504static u_int8_t
505tl_eeprom_getbyte(struct tl_softc *sc, int addr, u_int8_t *dest)
984263bc 506{
3d0f5f54 507 int i;
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508 u_int8_t byte = 0;
509
510 tl_dio_write8(sc, TL_NETSIO, 0);
511
512 EEPROM_START;
513
514 /*
515 * Send write control code to EEPROM.
516 */
517 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
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518 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
519 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
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520 return(1);
521 }
522
523 /*
524 * Send address of byte we want to read.
525 */
526 if (tl_eeprom_putbyte(sc, addr)) {
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527 if_printf(&sc->arpcom.ac_if, "failed to send address, "
528 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
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529 return(1);
530 }
531
532 EEPROM_STOP;
533 EEPROM_START;
534 /*
535 * Send read control code to EEPROM.
536 */
537 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
962412c1
JS
538 if_printf(&sc->arpcom.ac_if, "failed to send write command, "
539 "status: %x\n", tl_dio_read8(sc, TL_NETSIO));
984263bc
MD
540 return(1);
541 }
542
543 /*
544 * Start reading bits from EEPROM.
545 */
546 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN);
547 for (i = 0x80; i; i >>= 1) {
548 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK);
549 DELAY(1);
550 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA)
551 byte |= i;
552 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK);
553 DELAY(1);
554 }
555
556 EEPROM_STOP;
557
558 /*
559 * No ACK generated for read, so just return byte.
560 */
561
562 *dest = byte;
563
564 return(0);
565}
566
567/*
568 * Read a sequence of bytes from the EEPROM.
569 */
c436375a
SW
570static int
571tl_read_eeprom(struct tl_softc *sc, caddr_t dest, int off, int cnt)
984263bc
MD
572{
573 int err = 0, i;
574 u_int8_t byte = 0;
575
576 for (i = 0; i < cnt; i++) {
577 err = tl_eeprom_getbyte(sc, off + i, &byte);
578 if (err)
579 break;
580 *(dest + i) = byte;
581 }
582
583 return(err ? 1 : 0);
584}
585
c436375a
SW
586static void
587tl_mii_sync(struct tl_softc *sc)
984263bc 588{
3d0f5f54 589 int i;
984263bc
MD
590
591 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
592
593 for (i = 0; i < 32; i++) {
594 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
595 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
596 }
597
598 return;
599}
600
c436375a
SW
601static void
602tl_mii_send(struct tl_softc *sc, u_int32_t bits, int cnt)
984263bc
MD
603{
604 int i;
605
606 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
607 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
608 if (bits & i) {
609 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA);
610 } else {
611 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA);
612 }
613 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
614 }
615}
616
c436375a
SW
617static int
618tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame)
984263bc 619{
9228feed 620 int i, ack;
984263bc
MD
621 int minten = 0;
622
984263bc
MD
623 tl_mii_sync(sc);
624
625 /*
626 * Set up frame for RX.
627 */
628 frame->mii_stdelim = TL_MII_STARTDELIM;
629 frame->mii_opcode = TL_MII_READOP;
630 frame->mii_turnaround = 0;
631 frame->mii_data = 0;
632
633 /*
634 * Turn off MII interrupt by forcing MINTEN low.
635 */
636 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
637 if (minten) {
638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
639 }
640
641 /*
642 * Turn on data xmit.
643 */
644 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
645
646 /*
647 * Send command/address info.
648 */
649 tl_mii_send(sc, frame->mii_stdelim, 2);
650 tl_mii_send(sc, frame->mii_opcode, 2);
651 tl_mii_send(sc, frame->mii_phyaddr, 5);
652 tl_mii_send(sc, frame->mii_regaddr, 5);
653
654 /*
655 * Turn off xmit.
656 */
657 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
658
659 /* Idle bit */
660 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
661 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
662
663 /* Check for ack */
664 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
665 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA;
666
667 /* Complete the cycle */
668 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
669
670 /*
671 * Now try reading data bits. If the ack failed, we still
672 * need to clock through 16 cycles to keep the PHYs in sync.
673 */
674 if (ack) {
675 for(i = 0; i < 16; i++) {
676 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
677 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
678 }
679 goto fail;
680 }
681
682 for (i = 0x8000; i; i >>= 1) {
683 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
684 if (!ack) {
685 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA)
686 frame->mii_data |= i;
687 }
688 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
689 }
690
691fail:
692
693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
695
696 /* Reenable interrupts */
697 if (minten) {
698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
699 }
700
984263bc
MD
701 if (ack)
702 return(1);
703 return(0);
704}
705
c436375a
SW
706static int
707tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame)
984263bc 708{
984263bc
MD
709 int minten;
710
711 tl_mii_sync(sc);
712
984263bc
MD
713 /*
714 * Set up frame for TX.
715 */
716
717 frame->mii_stdelim = TL_MII_STARTDELIM;
718 frame->mii_opcode = TL_MII_WRITEOP;
719 frame->mii_turnaround = TL_MII_TURNAROUND;
720
721 /*
722 * Turn off MII interrupt by forcing MINTEN low.
723 */
724 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN;
725 if (minten) {
726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN);
727 }
728
729 /*
730 * Turn on data output.
731 */
732 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN);
733
734 tl_mii_send(sc, frame->mii_stdelim, 2);
735 tl_mii_send(sc, frame->mii_opcode, 2);
736 tl_mii_send(sc, frame->mii_phyaddr, 5);
737 tl_mii_send(sc, frame->mii_regaddr, 5);
738 tl_mii_send(sc, frame->mii_turnaround, 2);
739 tl_mii_send(sc, frame->mii_data, 16);
740
741 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK);
742 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK);
743
744 /*
745 * Turn off xmit.
746 */
747 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN);
748
749 /* Reenable interrupts */
750 if (minten)
751 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN);
752
984263bc
MD
753 return(0);
754}
755
c436375a
SW
756static int
757tl_miibus_readreg(device_t dev, int phy, int reg)
984263bc
MD
758{
759 struct tl_softc *sc;
760 struct tl_mii_frame frame;
761
762 sc = device_get_softc(dev);
763 bzero((char *)&frame, sizeof(frame));
764
765 frame.mii_phyaddr = phy;
766 frame.mii_regaddr = reg;
767 tl_mii_readreg(sc, &frame);
768
769 return(frame.mii_data);
770}
771
c436375a
SW
772static int
773tl_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc
MD
774{
775 struct tl_softc *sc;
776 struct tl_mii_frame frame;
777
778 sc = device_get_softc(dev);
779 bzero((char *)&frame, sizeof(frame));
780
781 frame.mii_phyaddr = phy;
782 frame.mii_regaddr = reg;
783 frame.mii_data = data;
784
785 tl_mii_writereg(sc, &frame);
786
787 return(0);
788}
789
c436375a
SW
790static void
791tl_miibus_statchg(device_t dev)
984263bc
MD
792{
793 struct tl_softc *sc;
794 struct mii_data *mii;
795
796 sc = device_get_softc(dev);
797 mii = device_get_softc(sc->tl_miibus);
798
799 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
800 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
801 } else {
802 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
803 }
804
805 return;
806}
807
808/*
809 * Set modes for bitrate devices.
810 */
c436375a
SW
811static void
812tl_setmode(struct tl_softc *sc, int media)
984263bc
MD
813{
814 if (IFM_SUBTYPE(media) == IFM_10_5)
815 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
816 if (IFM_SUBTYPE(media) == IFM_10_T) {
817 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1);
818 if ((media & IFM_GMASK) == IFM_FDX) {
819 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
820 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
821 } else {
822 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3);
823 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX);
824 }
825 }
826
827 return;
828}
829
830/*
831 * Calculate the hash of a MAC address for programming the multicast hash
832 * table. This hash is simply the address split into 6-bit chunks
833 * XOR'd, e.g.
834 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555
835 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210
836 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then
837 * the folded 24-bit value is split into 6-bit portions and XOR'd.
838 */
c436375a
SW
839static int
840tl_calchash(caddr_t addr)
984263bc
MD
841{
842 int t;
843
844 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 |
845 (addr[2] ^ addr[5]);
846 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f;
847}
848
849/*
850 * The ThunderLAN has a perfect MAC address filter in addition to
851 * the multicast hash filter. The perfect filter can be programmed
852 * with up to four MAC addresses. The first one is always used to
853 * hold the station address, which leaves us free to use the other
854 * three for multicast addresses.
855 */
c436375a
SW
856static void
857tl_setfilt(struct tl_softc *sc, caddr_t addr, int slot)
984263bc
MD
858{
859 int i;
860 u_int16_t regaddr;
861
862 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN);
863
864 for (i = 0; i < ETHER_ADDR_LEN; i++)
865 tl_dio_write8(sc, regaddr + i, *(addr + i));
866
867 return;
868}
869
870/*
871 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly
872 * linked list. This is fine, except addresses are added from the head
873 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts")
874 * group to always be in the perfect filter, but as more groups are added,
875 * the 224.0.0.1 entry (which is always added first) gets pushed down
876 * the list and ends up at the tail. So after 3 or 4 multicast groups
877 * are added, the all-hosts entry gets pushed out of the perfect filter
878 * and into the hash table.
879 *
880 * Because the multicast list is a doubly-linked list as opposed to a
881 * circular queue, we don't have the ability to just grab the tail of
882 * the list and traverse it backwards. Instead, we have to traverse
883 * the list once to find the tail, then traverse it again backwards to
884 * update the multicast filter.
885 */
c436375a
SW
886static void
887tl_setmulti(struct tl_softc *sc)
984263bc
MD
888{
889 struct ifnet *ifp;
890 u_int32_t hashes[2] = { 0, 0 };
891 int h, i;
892 struct ifmultiaddr *ifma;
893 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
894 ifp = &sc->arpcom.ac_if;
895
896 /* First, zot all the existing filters. */
897 for (i = 1; i < 4; i++)
898 tl_setfilt(sc, (caddr_t)&dummy, i);
899 tl_dio_write32(sc, TL_HASH1, 0);
900 tl_dio_write32(sc, TL_HASH2, 0);
901
902 /* Now program new ones. */
903 if (ifp->if_flags & IFF_ALLMULTI) {
904 hashes[0] = 0xFFFFFFFF;
905 hashes[1] = 0xFFFFFFFF;
906 } else {
907 i = 1;
441d34b2 908 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
984263bc
MD
909 if (ifma->ifma_addr->sa_family != AF_LINK)
910 continue;
911 /*
912 * Program the first three multicast groups
913 * into the perfect filter. For all others,
914 * use the hash table.
915 */
916 if (i < 4) {
917 tl_setfilt(sc,
918 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i);
919 i++;
920 continue;
921 }
922
923 h = tl_calchash(
924 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
925 if (h < 32)
926 hashes[0] |= (1 << h);
927 else
928 hashes[1] |= (1 << (h - 32));
929 }
930 }
931
932 tl_dio_write32(sc, TL_HASH1, hashes[0]);
933 tl_dio_write32(sc, TL_HASH2, hashes[1]);
934
935 return;
936}
937
938/*
939 * This routine is recommended by the ThunderLAN manual to insure that
940 * the internal PHY is powered up correctly. It also recommends a one
941 * second pause at the end to 'wait for the clocks to start' but in my
942 * experience this isn't necessary.
943 */
c436375a
SW
944static void
945tl_hardreset(device_t dev)
984263bc
MD
946{
947 struct tl_softc *sc;
948 int i;
949 u_int16_t flags;
950
951 sc = device_get_softc(dev);
952
953 tl_mii_sync(sc);
954
955 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN;
956
957 for (i = 0; i < MII_NPHY; i++)
958 tl_miibus_writereg(dev, i, MII_BMCR, flags);
959
960 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO);
961 DELAY(50000);
962 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO);
963 tl_mii_sync(sc);
964 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET);
965
966 DELAY(50000);
967 return;
968}
969
c436375a
SW
970static void
971tl_softreset(struct tl_softc *sc, int internal)
984263bc
MD
972{
973 u_int32_t cmd, dummy, i;
974
975 /* Assert the adapter reset bit. */
976 CMD_SET(sc, TL_CMD_ADRST);
977
978 /* Turn off interrupts */
979 CMD_SET(sc, TL_CMD_INTSOFF);
980
981 /* First, clear the stats registers. */
982 for (i = 0; i < 5; i++)
983 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES);
984
985 /* Clear Areg and Hash registers */
986 for (i = 0; i < 8; i++)
987 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000);
988
989 /*
990 * Set up Netconfig register. Enable one channel and
991 * one fragment mode.
992 */
993 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG);
994 if (internal && !sc->tl_bitrate) {
995 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
996 } else {
997 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN);
998 }
999
1000 /* Handle cards with bitrate devices. */
1001 if (sc->tl_bitrate)
1002 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE);
1003
1004 /*
1005 * Load adapter irq pacing timer and tx threshold.
1006 * We make the transmit threshold 1 initially but we may
1007 * change that later.
1008 */
1009 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1010 cmd |= TL_CMD_NES;
1011 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK);
1012 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR));
1013 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003));
1014
1015 /* Unreset the MII */
1016 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST);
1017
1018 /* Take the adapter out of reset */
1019 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP);
1020
1021 /* Wait for things to settle down a little. */
1022 DELAY(500);
1023
1024 return;
1025}
1026
1027/*
1028 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs
1029 * against our list and return its name if we find a match.
1030 */
c436375a
SW
1031static int
1032tl_probe(device_t dev)
984263bc
MD
1033{
1034 struct tl_type *t;
1035
1036 t = tl_devs;
1037
1038 while(t->tl_name != NULL) {
1039 if ((pci_get_vendor(dev) == t->tl_vid) &&
1040 (pci_get_device(dev) == t->tl_did)) {
1041 device_set_desc(dev, t->tl_name);
1042 return(0);
1043 }
1044 t++;
1045 }
1046
1047 return(ENXIO);
1048}
1049
c436375a
SW
1050static int
1051tl_attach(device_t dev)
984263bc 1052{
9228feed 1053 int i;
984263bc
MD
1054 u_int16_t did, vid;
1055 struct tl_type *t;
1056 struct ifnet *ifp;
1057 struct tl_softc *sc;
962412c1 1058 int error = 0, rid;
e09b2784 1059 uint8_t eaddr[ETHER_ADDR_LEN];
984263bc 1060
984263bc
MD
1061 vid = pci_get_vendor(dev);
1062 did = pci_get_device(dev);
1063 sc = device_get_softc(dev);
984263bc
MD
1064
1065 t = tl_devs;
1066 while(t->tl_name != NULL) {
1067 if (vid == t->tl_vid && did == t->tl_did)
1068 break;
1069 t++;
1070 }
1071
e23464eb 1072 KKASSERT(t->tl_name != NULL);
984263bc 1073
92a5c122 1074 pci_enable_busmaster(dev);
984263bc
MD
1075
1076#ifdef TL_USEIOSPACE
984263bc 1077 rid = TL_PCI_LOIO;
4e6d744d
JS
1078 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1079 RF_ACTIVE);
984263bc
MD
1080
1081 /*
1082 * Some cards have the I/O and memory mapped address registers
1083 * reversed. Try both combinations before giving up.
1084 */
1085 if (sc->tl_res == NULL) {
1086 rid = TL_PCI_LOMEM;
4e6d744d
JS
1087 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1088 RF_ACTIVE);
984263bc
MD
1089 }
1090#else
984263bc 1091 rid = TL_PCI_LOMEM;
4e6d744d
JS
1092 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1093 RF_ACTIVE);
984263bc
MD
1094 if (sc->tl_res == NULL) {
1095 rid = TL_PCI_LOIO;
4e6d744d
JS
1096 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1097 RF_ACTIVE);
984263bc
MD
1098 }
1099#endif
1100
1101 if (sc->tl_res == NULL) {
962412c1 1102 device_printf(dev, "couldn't map ports/memory\n");
984263bc 1103 error = ENXIO;
d9961f1f 1104 return(error);
984263bc
MD
1105 }
1106
1107 sc->tl_btag = rman_get_bustag(sc->tl_res);
1108 sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
1109
1110#ifdef notdef
1111 /*
1112 * The ThunderLAN manual suggests jacking the PCI latency
1113 * timer all the way up to its maximum value. I'm not sure
1114 * if this is really necessary, but what the manual wants,
1115 * the manual gets.
1116 */
1117 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4);
1118 command |= 0x0000FF00;
1119 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4);
1120#endif
1121
1122 /* Allocate interrupt */
1123 rid = 0;
4e6d744d 1124 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
1125 RF_SHAREABLE | RF_ACTIVE);
1126
1127 if (sc->tl_irq == NULL) {
962412c1 1128 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
1129 error = ENXIO;
1130 goto fail;
1131 }
1132
984263bc
MD
1133 /*
1134 * Now allocate memory for the TX and RX lists.
1135 */
1136 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF,
e7b4468c 1137 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
1138
1139 if (sc->tl_ldata == NULL) {
962412c1 1140 device_printf(dev, "no memory for list buffers!\n");
984263bc
MD
1141 error = ENXIO;
1142 goto fail;
1143 }
1144
984263bc
MD
1145 sc->tl_dinfo = t;
1146 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID)
1147 sc->tl_eeaddr = TL_EEPROM_EADDR;
1148 if (t->tl_vid == OLICOM_VENDORID)
1149 sc->tl_eeaddr = TL_EEPROM_EADDR_OC;
1150
1151 /* Reset the adapter. */
1152 tl_softreset(sc, 1);
1153 tl_hardreset(dev);
1154 tl_softreset(sc, 1);
1155
962412c1
JS
1156 ifp = &sc->arpcom.ac_if;
1157 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1158
984263bc
MD
1159 /*
1160 * Get station address from the EEPROM.
1161 */
e09b2784 1162 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) {
962412c1 1163 device_printf(dev, "failed to read station address\n");
984263bc
MD
1164 error = ENXIO;
1165 goto fail;
1166 }
1167
1168 /*
1169 * XXX Olicom, in its desire to be different from the
1170 * rest of the world, has done strange things with the
1171 * encoding of the station address in the EEPROM. First
1172 * of all, they store the address at offset 0xF8 rather
1173 * than at 0x83 like the ThunderLAN manual suggests.
1174 * Second, they store the address in three 16-bit words in
1175 * network byte order, as opposed to storing it sequentially
1176 * like all the other ThunderLAN cards. In order to get
1177 * the station address in a form that matches what the Olicom
1178 * diagnostic utility specifies, we have to byte-swap each
1179 * word. To make things even more confusing, neither 00:00:28
1180 * nor 00:00:24 appear in the IEEE OUI database.
1181 */
1182 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) {
1183 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
1184 u_int16_t *p;
e09b2784 1185 p = (u_int16_t *)&eaddr[i];
984263bc
MD
1186 *p = ntohs(*p);
1187 }
1188 }
1189
984263bc 1190 ifp->if_softc = sc;
984263bc
MD
1191 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1192 ifp->if_ioctl = tl_ioctl;
984263bc
MD
1193 ifp->if_start = tl_start;
1194 ifp->if_watchdog = tl_watchdog;
1195 ifp->if_init = tl_init;
1196 ifp->if_mtu = ETHERMTU;
ee9af5ee
JS
1197 ifq_set_maxlen(&ifp->if_snd, TL_TX_LIST_CNT - 1);
1198 ifq_set_ready(&ifp->if_snd);
5abe9a2d 1199 callout_init(&sc->tl_stat_timer);
984263bc
MD
1200
1201 /* Reset the adapter again. */
1202 tl_softreset(sc, 1);
1203 tl_hardreset(dev);
1204 tl_softreset(sc, 1);
1205
1206 /*
1207 * Do MII setup. If no PHYs are found, then this is a
1208 * bitrate ThunderLAN chip that only supports 10baseT
1209 * and AUI/BNC.
1210 */
1211 if (mii_phy_probe(dev, &sc->tl_miibus,
1212 tl_ifmedia_upd, tl_ifmedia_sts)) {
1213 struct ifmedia *ifm;
1214 sc->tl_bitrate = 1;
1215 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts);
1216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1219 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1220 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T);
1221 /* Reset again, this time setting bitrate mode. */
1222 tl_softreset(sc, 1);
1223 ifm = &sc->ifmedia;
1224 ifm->ifm_media = ifm->ifm_cur->ifm_media;
1225 tl_ifmedia_upd(ifp);
1226 }
1227
1228 /*
1229 * Call MI attach routine.
1230 */
78195a76 1231 ether_ifattach(ifp, eaddr, NULL);
984263bc 1232
95893fe4 1233 error = bus_setup_intr(dev, sc->tl_irq, INTR_MPSAFE,
78195a76
MD
1234 tl_intr, sc, &sc->tl_intrhand,
1235 ifp->if_serializer);
d9961f1f
JS
1236
1237 if (error) {
1238 ether_ifdetach(ifp);
962412c1 1239 device_printf(dev, "couldn't set up irq\n");
d9961f1f
JS
1240 goto fail;
1241 }
1242
9db4b353
SZ
1243 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->tl_irq));
1244 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1245
d9961f1f
JS
1246 return(0);
1247
984263bc 1248fail:
d9961f1f 1249 tl_detach(dev);
984263bc
MD
1250 return(error);
1251}
1252
c436375a
SW
1253static int
1254tl_detach(device_t dev)
984263bc 1255{
d9961f1f
JS
1256 struct tl_softc *sc = device_get_softc(dev);
1257 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1258
d9961f1f 1259 if (device_is_attached(dev)) {
cdf89432 1260 lwkt_serialize_enter(ifp->if_serializer);
d9961f1f 1261 tl_stop(sc);
cdf89432
SZ
1262 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand);
1263 lwkt_serialize_exit(ifp->if_serializer);
1264
d9961f1f
JS
1265 ether_ifdetach(ifp);
1266 }
984263bc 1267
d9961f1f
JS
1268 if (sc->tl_miibus)
1269 device_delete_child(dev, sc->tl_miibus);
984263bc 1270 bus_generic_detach(dev);
984263bc 1271
d9961f1f
JS
1272 if (sc->tl_ldata)
1273 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF);
984263bc
MD
1274 if (sc->tl_bitrate)
1275 ifmedia_removeall(&sc->ifmedia);
d9961f1f
JS
1276 if (sc->tl_irq)
1277 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq);
1278 if (sc->tl_res)
1279 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res);
984263bc
MD
1280
1281 return(0);
1282}
1283
1284/*
1285 * Initialize the transmit lists.
1286 */
c436375a
SW
1287static int
1288tl_list_tx_init(struct tl_softc *sc)
984263bc
MD
1289{
1290 struct tl_chain_data *cd;
1291 struct tl_list_data *ld;
1292 int i;
1293
1294 cd = &sc->tl_cdata;
1295 ld = sc->tl_ldata;
1296 for (i = 0; i < TL_TX_LIST_CNT; i++) {
1297 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i];
1298 if (i == (TL_TX_LIST_CNT - 1))
1299 cd->tl_tx_chain[i].tl_next = NULL;
1300 else
1301 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1];
1302 }
1303
1304 cd->tl_tx_free = &cd->tl_tx_chain[0];
1305 cd->tl_tx_tail = cd->tl_tx_head = NULL;
1306 sc->tl_txeoc = 1;
1307
1308 return(0);
1309}
1310
1311/*
1312 * Initialize the RX lists and allocate mbufs for them.
1313 */
c436375a
SW
1314static int
1315tl_list_rx_init(struct tl_softc *sc)
984263bc
MD
1316{
1317 struct tl_chain_data *cd;
1318 struct tl_list_data *ld;
1319 int i;
1320
1321 cd = &sc->tl_cdata;
1322 ld = sc->tl_ldata;
1323
1324 for (i = 0; i < TL_RX_LIST_CNT; i++) {
1325 cd->tl_rx_chain[i].tl_ptr =
1326 (struct tl_list_onefrag *)&ld->tl_rx_list[i];
1327 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS)
1328 return(ENOBUFS);
1329 if (i == (TL_RX_LIST_CNT - 1)) {
1330 cd->tl_rx_chain[i].tl_next = NULL;
1331 ld->tl_rx_list[i].tlist_fptr = 0;
1332 } else {
1333 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1];
1334 ld->tl_rx_list[i].tlist_fptr =
1335 vtophys(&ld->tl_rx_list[i + 1]);
1336 }
1337 }
1338
1339 cd->tl_rx_head = &cd->tl_rx_chain[0];
1340 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1341
1342 return(0);
1343}
1344
c436375a
SW
1345static int
1346tl_newbuf(struct tl_softc *sc, struct tl_chain_onefrag *c)
984263bc 1347{
17b71a59 1348 struct mbuf *m_new;
984263bc 1349
17b71a59 1350 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc 1351 if (m_new == NULL)
17b71a59 1352 return (ENOBUFS);
984263bc 1353
984263bc
MD
1354 c->tl_mbuf = m_new;
1355 c->tl_next = NULL;
1356 c->tl_ptr->tlist_frsize = MCLBYTES;
1357 c->tl_ptr->tlist_fptr = 0;
1358 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t));
1359 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1360 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1361
1362 return(0);
1363}
c436375a 1364
984263bc
MD
1365/*
1366 * Interrupt handler for RX 'end of frame' condition (EOF). This
1367 * tells us that a full ethernet frame has been captured and we need
1368 * to handle it.
1369 *
1370 * Reception is done using 'lists' which consist of a header and a
1371 * series of 10 data count/data address pairs that point to buffers.
1372 * Initially you're supposed to create a list, populate it with pointers
1373 * to buffers, then load the physical address of the list into the
1374 * ch_parm register. The adapter is then supposed to DMA the received
1375 * frame into the buffers for you.
1376 *
1377 * To make things as fast as possible, we have the chip DMA directly
1378 * into mbufs. This saves us from having to do a buffer copy: we can
1379 * just hand the mbufs directly to ether_input(). Once the frame has
1380 * been sent on its way, the 'list' structure is assigned a new buffer
1381 * and moved to the end of the RX chain. As long we we stay ahead of
1382 * the chip, it will always think it has an endless receive channel.
1383 *
1384 * If we happen to fall behind and the chip manages to fill up all of
1385 * the buffers, it will generate an end of channel interrupt and wait
1386 * for us to empty the chain and restart the receiver.
1387 */
c436375a
SW
1388static int
1389tl_intvec_rxeof(void *xsc, u_int32_t type)
984263bc
MD
1390{
1391 struct tl_softc *sc;
1392 int r = 0, total_len = 0;
1393 struct ether_header *eh;
1394 struct mbuf *m;
1395 struct ifnet *ifp;
1396 struct tl_chain_onefrag *cur_rx;
1397
1398 sc = xsc;
1399 ifp = &sc->arpcom.ac_if;
1400
1401 while(sc->tl_cdata.tl_rx_head != NULL) {
1402 cur_rx = sc->tl_cdata.tl_rx_head;
1403 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1404 break;
1405 r++;
1406 sc->tl_cdata.tl_rx_head = cur_rx->tl_next;
1407 m = cur_rx->tl_mbuf;
1408 total_len = cur_rx->tl_ptr->tlist_frsize;
1409
1410 if (tl_newbuf(sc, cur_rx) == ENOBUFS) {
1411 ifp->if_ierrors++;
1412 cur_rx->tl_ptr->tlist_frsize = MCLBYTES;
1413 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1414 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES;
1415 continue;
1416 }
1417
1418 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr =
1419 vtophys(cur_rx->tl_ptr);
1420 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx;
1421 sc->tl_cdata.tl_rx_tail = cur_rx;
1422
1423 eh = mtod(m, struct ether_header *);
1424 m->m_pkthdr.rcvif = ifp;
fe80ae4a 1425 m->m_pkthdr.len = m->m_len = total_len;
984263bc
MD
1426
1427 /*
1428 * Note: when the ThunderLAN chip is in 'capture all
1429 * frames' mode, it will receive its own transmissions.
1430 * We drop don't need to process our own transmissions,
1431 * so we drop them here and continue.
1432 */
1433 /*if (ifp->if_flags & IFF_PROMISC && */
1434 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr,
1435 ETHER_ADDR_LEN)) {
1436 m_freem(m);
1437 continue;
1438 }
1439
78195a76 1440 ifp->if_input(ifp, m);
984263bc
MD
1441 }
1442
1443 return(r);
1444}
1445
1446/*
1447 * The RX-EOC condition hits when the ch_parm address hasn't been
1448 * initialized or the adapter reached a list with a forward pointer
1449 * of 0 (which indicates the end of the chain). In our case, this means
1450 * the card has hit the end of the receive buffer chain and we need to
1451 * empty out the buffers and shift the pointer back to the beginning again.
1452 */
c436375a
SW
1453static int
1454tl_intvec_rxeoc(void *xsc, u_int32_t type)
984263bc
MD
1455{
1456 struct tl_softc *sc;
1457 int r;
1458 struct tl_chain_data *cd;
1459
1460
1461 sc = xsc;
1462 cd = &sc->tl_cdata;
1463
1464 /* Flush out the receive queue and ack RXEOF interrupts. */
1465 r = tl_intvec_rxeof(xsc, type);
1466 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000)));
1467 r = 1;
1468 cd->tl_rx_head = &cd->tl_rx_chain[0];
1469 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1];
1470 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr));
1471 r |= (TL_CMD_GO|TL_CMD_RT);
1472 return(r);
1473}
1474
c436375a
SW
1475static int
1476tl_intvec_txeof(void *xsc, u_int32_t type)
984263bc
MD
1477{
1478 struct tl_softc *sc;
1479 int r = 0;
1480 struct tl_chain *cur_tx;
1481
1482 sc = xsc;
1483
1484 /*
1485 * Go through our tx list and free mbufs for those
1486 * frames that have been sent.
1487 */
1488 while (sc->tl_cdata.tl_tx_head != NULL) {
1489 cur_tx = sc->tl_cdata.tl_tx_head;
1490 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP))
1491 break;
1492 sc->tl_cdata.tl_tx_head = cur_tx->tl_next;
1493
1494 r++;
1495 m_freem(cur_tx->tl_mbuf);
1496 cur_tx->tl_mbuf = NULL;
1497
1498 cur_tx->tl_next = sc->tl_cdata.tl_tx_free;
1499 sc->tl_cdata.tl_tx_free = cur_tx;
1500 if (!cur_tx->tl_ptr->tlist_fptr)
1501 break;
1502 }
1503
1504 return(r);
1505}
1506
1507/*
1508 * The transmit end of channel interrupt. The adapter triggers this
1509 * interrupt to tell us it hit the end of the current transmit list.
1510 *
1511 * A note about this: it's possible for a condition to arise where
1512 * tl_start() may try to send frames between TXEOF and TXEOC interrupts.
1513 * You have to avoid this since the chip expects things to go in a
1514 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC.
1515 * When the TXEOF handler is called, it will free all of the transmitted
1516 * frames and reset the tx_head pointer to NULL. However, a TXEOC
1517 * interrupt should be received and acknowledged before any more frames
1518 * are queued for transmission. If tl_statrt() is called after TXEOF
1519 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives,
1520 * it could attempt to issue a transmit command prematurely.
1521 *
1522 * To guard against this, tl_start() will only issue transmit commands
1523 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler
1524 * can set this flag once tl_start() has cleared it.
1525 */
c436375a
SW
1526static int
1527tl_intvec_txeoc(void *xsc, u_int32_t type)
984263bc
MD
1528{
1529 struct tl_softc *sc;
1530 struct ifnet *ifp;
1531 u_int32_t cmd;
1532
1533 sc = xsc;
1534 ifp = &sc->arpcom.ac_if;
1535
1536 /* Clear the timeout timer. */
1537 ifp->if_timer = 0;
1538
1539 if (sc->tl_cdata.tl_tx_head == NULL) {
1540 ifp->if_flags &= ~IFF_OACTIVE;
1541 sc->tl_cdata.tl_tx_tail = NULL;
1542 sc->tl_txeoc = 1;
1543 } else {
1544 sc->tl_txeoc = 0;
1545 /* First we have to ack the EOC interrupt. */
1546 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type);
1547 /* Then load the address of the next TX list. */
1548 CSR_WRITE_4(sc, TL_CH_PARM,
1549 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr));
1550 /* Restart TX channel. */
1551 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1552 cmd &= ~TL_CMD_RT;
1553 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1554 CMD_PUT(sc, cmd);
1555 return(0);
1556 }
1557
1558 return(1);
1559}
1560
c436375a
SW
1561static int
1562tl_intvec_adchk(void *xsc, u_int32_t type)
984263bc
MD
1563{
1564 struct tl_softc *sc;
1565
1566 sc = xsc;
1567
962412c1
JS
1568 if (type) {
1569 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n",
1570 (unsigned int)CSR_READ_4(sc, TL_CH_PARM));
1571 }
984263bc
MD
1572
1573 tl_softreset(sc, 1);
1574 tl_stop(sc);
1575 tl_init(sc);
1576 CMD_SET(sc, TL_CMD_INTSON);
1577
1578 return(0);
1579}
1580
c436375a
SW
1581static int
1582tl_intvec_netsts(void *xsc, u_int32_t type)
984263bc
MD
1583{
1584 struct tl_softc *sc;
1585 u_int16_t netsts;
1586
1587 sc = xsc;
1588
1589 netsts = tl_dio_read16(sc, TL_NETSTS);
1590 tl_dio_write16(sc, TL_NETSTS, netsts);
1591
962412c1 1592 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts);
984263bc
MD
1593
1594 return(1);
1595}
1596
c436375a
SW
1597static void
1598tl_intr(void *xsc)
984263bc
MD
1599{
1600 struct tl_softc *sc;
1601 struct ifnet *ifp;
1602 int r = 0;
1603 u_int32_t type = 0;
1604 u_int16_t ints = 0;
1605 u_int8_t ivec = 0;
1606
1607 sc = xsc;
1608
1609 /* Disable interrupts */
1610 ints = CSR_READ_2(sc, TL_HOST_INT);
1611 CSR_WRITE_2(sc, TL_HOST_INT, ints);
1612 type = (ints << 16) & 0xFFFF0000;
1613 ivec = (ints & TL_VEC_MASK) >> 5;
1614 ints = (ints & TL_INT_MASK) >> 2;
1615
1616 ifp = &sc->arpcom.ac_if;
1617
1618 switch(ints) {
1619 case (TL_INTR_INVALID):
1620#ifdef DIAGNOSTIC
962412c1 1621 if_printf(ifp, "got an invalid interrupt!\n");
984263bc
MD
1622#endif
1623 /* Re-enable interrupts but don't ack this one. */
1624 CMD_PUT(sc, type);
1625 r = 0;
1626 break;
1627 case (TL_INTR_TXEOF):
1628 r = tl_intvec_txeof((void *)sc, type);
1629 break;
1630 case (TL_INTR_TXEOC):
1631 r = tl_intvec_txeoc((void *)sc, type);
1632 break;
1633 case (TL_INTR_STATOFLOW):
78195a76 1634 tl_stats_update_serialized(sc);
984263bc
MD
1635 r = 1;
1636 break;
1637 case (TL_INTR_RXEOF):
1638 r = tl_intvec_rxeof((void *)sc, type);
1639 break;
1640 case (TL_INTR_DUMMY):
962412c1 1641 if_printf(ifp, "got a dummy interrupt\n");
984263bc
MD
1642 r = 1;
1643 break;
1644 case (TL_INTR_ADCHK):
1645 if (ivec)
1646 r = tl_intvec_adchk((void *)sc, type);
1647 else
1648 r = tl_intvec_netsts((void *)sc, type);
1649 break;
1650 case (TL_INTR_RXEOC):
1651 r = tl_intvec_rxeoc((void *)sc, type);
1652 break;
1653 default:
962412c1 1654 if_printf(ifp, "bogus interrupt type\n");
984263bc
MD
1655 break;
1656 }
1657
1658 /* Re-enable interrupts */
1659 if (r) {
1660 CMD_PUT(sc, TL_CMD_ACK | r | type);
1661 }
1662
ee9af5ee 1663 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1664 if_devstart(ifp);
984263bc
MD
1665}
1666
78195a76
MD
1667static
1668void
1669tl_stats_update(void *xsc)
1670{
1671 struct tl_softc *sc = xsc;
1672 struct ifnet *ifp = &sc->arpcom.ac_if;
1673
1674 lwkt_serialize_enter(ifp->if_serializer);
1675 tl_stats_update_serialized(xsc);
1676 lwkt_serialize_exit(ifp->if_serializer);
1677}
1678
1679static
1680void
1681tl_stats_update_serialized(void *xsc)
984263bc
MD
1682{
1683 struct tl_softc *sc;
1684 struct ifnet *ifp;
1685 struct tl_stats tl_stats;
1686 struct mii_data *mii;
1687 u_int32_t *p;
984263bc 1688
984263bc
MD
1689 bzero((char *)&tl_stats, sizeof(struct tl_stats));
1690
1691 sc = xsc;
1692 ifp = &sc->arpcom.ac_if;
1693
1694 p = (u_int32_t *)&tl_stats;
1695
1696 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC);
1697 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1698 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1699 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1700 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1701 *p++ = CSR_READ_4(sc, TL_DIO_DATA);
1702
1703 ifp->if_opackets += tl_tx_goodframes(tl_stats);
1704 ifp->if_collisions += tl_stats.tl_tx_single_collision +
1705 tl_stats.tl_tx_multi_collision;
1706 ifp->if_ipackets += tl_rx_goodframes(tl_stats);
1707 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors +
1708 tl_rx_overrun(tl_stats);
1709 ifp->if_oerrors += tl_tx_underrun(tl_stats);
1710
1711 if (tl_tx_underrun(tl_stats)) {
1712 u_int8_t tx_thresh;
1713 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH;
1714 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) {
1715 tx_thresh >>= 4;
1716 tx_thresh++;
962412c1
JS
1717 if_printf(ifp, "tx underrun -- increasing "
1718 "tx threshold to %d bytes\n",
1719 (64 * (tx_thresh * 4)));
984263bc
MD
1720 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1721 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4);
1722 }
1723 }
1724
5abe9a2d 1725 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
984263bc
MD
1726
1727 if (!sc->tl_bitrate) {
1728 mii = device_get_softc(sc->tl_miibus);
1729 mii_tick(mii);
1730 }
984263bc
MD
1731}
1732
1733/*
1734 * Encapsulate an mbuf chain in a list by coupling the mbuf data
1735 * pointers to the fragment pointers.
1736 */
c436375a
SW
1737static int
1738tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head)
984263bc
MD
1739{
1740 int frag = 0;
1741 struct tl_frag *f = NULL;
1742 int total_len;
1743 struct mbuf *m;
1744
1745 /*
1746 * Start packing the mbufs in this chain into
1747 * the fragment pointers. Stop when we run out
1748 * of fragments or hit the end of the mbuf chain.
1749 */
1750 m = m_head;
1751 total_len = 0;
1752
1753 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1754 if (m->m_len != 0) {
1755 if (frag == TL_MAXFRAGS)
1756 break;
1757 total_len+= m->m_len;
1758 c->tl_ptr->tl_frag[frag].tlist_dadr =
1759 vtophys(mtod(m, vm_offset_t));
1760 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len;
1761 frag++;
1762 }
1763 }
1764
1765 /*
1766 * Handle special cases.
1767 * Special case #1: we used up all 10 fragments, but
1768 * we have more mbufs left in the chain. Copy the
1769 * data into an mbuf cluster. Note that we don't
1770 * bother clearing the values in the other fragment
1771 * pointers/counters; it wouldn't gain us anything,
1772 * and would waste cycles.
1773 */
1774 if (m != NULL) {
17b71a59 1775 struct mbuf *m_new;
984263bc 1776
17b71a59
JH
1777 m_new = m_getl(m_head->m_pkthdr.len, MB_DONTWAIT, MT_DATA,
1778 M_PKTHDR, NULL);
984263bc 1779 if (m_new == NULL) {
962412c1 1780 if_printf(&sc->arpcom.ac_if, "no memory for tx list\n");
17b71a59 1781 return (1);
984263bc
MD
1782 }
1783 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1784 mtod(m_new, caddr_t));
1785 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1786 m_freem(m_head);
1787 m_head = m_new;
1788 f = &c->tl_ptr->tl_frag[0];
1789 f->tlist_dadr = vtophys(mtod(m_new, caddr_t));
1790 f->tlist_dcnt = total_len = m_new->m_len;
1791 frag = 1;
1792 }
1793
1794 /*
1795 * Special case #2: the frame is smaller than the minimum
1796 * frame size. We have to pad it to make the chip happy.
1797 */
1798 if (total_len < TL_MIN_FRAMELEN) {
962412c1
JS
1799 if (frag == TL_MAXFRAGS) {
1800 if_printf(&sc->arpcom.ac_if, "all frags filled but "
1801 "frame still to small!\n");
1802 }
984263bc
MD
1803 f = &c->tl_ptr->tl_frag[frag];
1804 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len;
1805 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad);
1806 total_len += f->tlist_dcnt;
1807 frag++;
1808 }
1809
1810 c->tl_mbuf = m_head;
1811 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG;
1812 c->tl_ptr->tlist_frsize = total_len;
1813 c->tl_ptr->tlist_cstat = TL_CSTAT_READY;
1814 c->tl_ptr->tlist_fptr = 0;
1815
1816 return(0);
1817}
1818
1819/*
1820 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1821 * to the mbuf data regions directly in the transmit lists. We also save a
1822 * copy of the pointers since the transmit list fragment pointers are
1823 * physical addresses.
1824 */
c436375a
SW
1825static void
1826tl_start(struct ifnet *ifp)
984263bc
MD
1827{
1828 struct tl_softc *sc;
1829 struct mbuf *m_head = NULL;
1830 u_int32_t cmd;
1831 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
1832
1833 sc = ifp->if_softc;
1834
1835 /*
1836 * Check for an available queue slot. If there are none,
1837 * punt.
1838 */
1839 if (sc->tl_cdata.tl_tx_free == NULL) {
1840 ifp->if_flags |= IFF_OACTIVE;
1841 return;
1842 }
1843
1844 start_tx = sc->tl_cdata.tl_tx_free;
1845
1846 while(sc->tl_cdata.tl_tx_free != NULL) {
d2c71fa0 1847 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1848 if (m_head == NULL)
1849 break;
1850
1851 /* Pick a chain member off the free list. */
1852 cur_tx = sc->tl_cdata.tl_tx_free;
1853 sc->tl_cdata.tl_tx_free = cur_tx->tl_next;
1854
1855 cur_tx->tl_next = NULL;
1856
1857 /* Pack the data into the list. */
1858 tl_encap(sc, cur_tx, m_head);
1859
1860 /* Chain it together */
1861 if (prev != NULL) {
1862 prev->tl_next = cur_tx;
1863 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr);
1864 }
1865 prev = cur_tx;
1866
7600679e 1867 BPF_MTAP(ifp, cur_tx->tl_mbuf);
984263bc
MD
1868 }
1869
1870 /*
1871 * If there are no packets queued, bail.
1872 */
1873 if (cur_tx == NULL)
1874 return;
1875
1876 /*
1877 * That's all we can stands, we can't stands no more.
1878 * If there are no other transfers pending, then issue the
1879 * TX GO command to the adapter to start things moving.
1880 * Otherwise, just leave the data in the queue and let
1881 * the EOF/EOC interrupt handler send.
1882 */
1883 if (sc->tl_cdata.tl_tx_head == NULL) {
1884 sc->tl_cdata.tl_tx_head = start_tx;
1885 sc->tl_cdata.tl_tx_tail = cur_tx;
1886
1887 if (sc->tl_txeoc) {
1888 sc->tl_txeoc = 0;
1889 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr));
1890 cmd = CSR_READ_4(sc, TL_HOSTCMD);
1891 cmd &= ~TL_CMD_RT;
1892 cmd |= TL_CMD_GO|TL_CMD_INTSON;
1893 CMD_PUT(sc, cmd);
1894 }
1895 } else {
1896 sc->tl_cdata.tl_tx_tail->tl_next = start_tx;
1897 sc->tl_cdata.tl_tx_tail = cur_tx;
1898 }
1899
1900 /*
1901 * Set a timeout in case the chip goes out to lunch.
1902 */
1903 ifp->if_timer = 5;
1904
1905 return;
1906}
1907
c436375a
SW
1908static void
1909tl_init(void *xsc)
984263bc
MD
1910{
1911 struct tl_softc *sc = xsc;
1912 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1913 struct mii_data *mii;
1914
984263bc
MD
1915 /*
1916 * Cancel pending I/O.
1917 */
1918 tl_stop(sc);
1919
1920 /* Initialize TX FIFO threshold */
1921 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH);
1922 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG);
1923
1924 /* Set PCI burst size */
1925 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG);
1926
1927 /*
1928 * Set 'capture all frames' bit for promiscuous mode.
1929 */
1930 if (ifp->if_flags & IFF_PROMISC)
1931 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
1932 else
1933 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
1934
1935 /*
1936 * Set capture broadcast bit to capture broadcast frames.
1937 */
1938 if (ifp->if_flags & IFF_BROADCAST)
1939 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1940 else
1941 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX);
1942
1943 tl_dio_write16(sc, TL_MAXRX, MCLBYTES);
1944
1945 /* Init our MAC address */
1946 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0);
1947
1948 /* Init multicast filter, if needed. */
1949 tl_setmulti(sc);
1950
1951 /* Init circular RX list. */
1952 if (tl_list_rx_init(sc) == ENOBUFS) {
962412c1
JS
1953 if_printf(ifp, "initialization failed: no "
1954 "memory for rx buffers\n");
984263bc
MD
1955 tl_stop(sc);
1956 return;
1957 }
1958
1959 /* Init TX pointers. */
1960 tl_list_tx_init(sc);
1961
1962 /* Enable PCI interrupts. */
1963 CMD_SET(sc, TL_CMD_INTSON);
1964
1965 /* Load the address of the rx list */
1966 CMD_SET(sc, TL_CMD_RT);
1967 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0]));
1968
1969 if (!sc->tl_bitrate) {
1970 if (sc->tl_miibus != NULL) {
1971 mii = device_get_softc(sc->tl_miibus);
1972 mii_mediachg(mii);
1973 }
1974 }
1975
1976 /* Send the RX go command */
1977 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT);
1978
1979 ifp->if_flags |= IFF_RUNNING;
1980 ifp->if_flags &= ~IFF_OACTIVE;
1981
984263bc 1982 /* Start the stats update counter */
5abe9a2d 1983 callout_reset(&sc->tl_stat_timer, hz, tl_stats_update, sc);
984263bc
MD
1984}
1985
1986/*
1987 * Set media options.
1988 */
c436375a
SW
1989static int
1990tl_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
1991{
1992 struct tl_softc *sc;
1993 struct mii_data *mii = NULL;
1994
1995 sc = ifp->if_softc;
1996
1997 if (sc->tl_bitrate)
1998 tl_setmode(sc, sc->ifmedia.ifm_media);
1999 else {
2000 mii = device_get_softc(sc->tl_miibus);
2001 mii_mediachg(mii);
2002 }
2003
2004 return(0);
2005}
2006
2007/*
2008 * Report current media status.
2009 */
c436375a
SW
2010static void
2011tl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
2012{
2013 struct tl_softc *sc;
2014 struct mii_data *mii;
2015
2016 sc = ifp->if_softc;
2017
2018 ifmr->ifm_active = IFM_ETHER;
2019
2020 if (sc->tl_bitrate) {
2021 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1)
2022 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2023 else
2024 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2025 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3)
2026 ifmr->ifm_active |= IFM_HDX;
2027 else
2028 ifmr->ifm_active |= IFM_FDX;
2029 return;
2030 } else {
2031 mii = device_get_softc(sc->tl_miibus);
2032 mii_pollstat(mii);
2033 ifmr->ifm_active = mii->mii_media_active;
2034 ifmr->ifm_status = mii->mii_media_status;
2035 }
2036
2037 return;
2038}
2039
c436375a
SW
2040static int
2041tl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
2042{
2043 struct tl_softc *sc = ifp->if_softc;
2044 struct ifreq *ifr = (struct ifreq *) data;
9228feed 2045 int error = 0;
984263bc 2046
984263bc 2047 switch(command) {
984263bc
MD
2048 case SIOCSIFFLAGS:
2049 if (ifp->if_flags & IFF_UP) {
2050 if (ifp->if_flags & IFF_RUNNING &&
2051 ifp->if_flags & IFF_PROMISC &&
2052 !(sc->tl_if_flags & IFF_PROMISC)) {
2053 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF);
2054 tl_setmulti(sc);
2055 } else if (ifp->if_flags & IFF_RUNNING &&
2056 !(ifp->if_flags & IFF_PROMISC) &&
2057 sc->tl_if_flags & IFF_PROMISC) {
2058 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF);
2059 tl_setmulti(sc);
2060 } else
2061 tl_init(sc);
2062 } else {
2063 if (ifp->if_flags & IFF_RUNNING) {
2064 tl_stop(sc);
2065 }
2066 }
2067 sc->tl_if_flags = ifp->if_flags;
2068 error = 0;
2069 break;
2070 case SIOCADDMULTI:
2071 case SIOCDELMULTI:
2072 tl_setmulti(sc);
2073 error = 0;
2074 break;
2075 case SIOCSIFMEDIA:
2076 case SIOCGIFMEDIA:
2077 if (sc->tl_bitrate)
2078 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2079 else {
2080 struct mii_data *mii;
2081 mii = device_get_softc(sc->tl_miibus);
2082 error = ifmedia_ioctl(ifp, ifr,
2083 &mii->mii_media, command);
2084 }
2085 break;
2086 default:
4cde4dd5 2087 error = ether_ioctl(ifp, command, data);
984263bc
MD
2088 break;
2089 }
984263bc
MD
2090 return(error);
2091}
2092
c436375a
SW
2093static void
2094tl_watchdog(struct ifnet *ifp)
984263bc
MD
2095{
2096 struct tl_softc *sc;
2097
2098 sc = ifp->if_softc;
2099
962412c1 2100 if_printf(ifp, "device timeout\n");
984263bc
MD
2101
2102 ifp->if_oerrors++;
2103
2104 tl_softreset(sc, 1);
2105 tl_init(sc);
2106
2107 return;
2108}
2109
2110/*
2111 * Stop the adapter and free any mbufs allocated to the
2112 * RX and TX lists.
2113 */
c436375a
SW
2114static void
2115tl_stop(struct tl_softc *sc)
984263bc 2116{
3d0f5f54 2117 int i;
984263bc
MD
2118 struct ifnet *ifp;
2119
2120 ifp = &sc->arpcom.ac_if;
2121
2122 /* Stop the stats updater. */
5abe9a2d 2123 callout_stop(&sc->tl_stat_timer);
984263bc
MD
2124
2125 /* Stop the transmitter */
2126 CMD_CLR(sc, TL_CMD_RT);
2127 CMD_SET(sc, TL_CMD_STOP);
2128 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2129
2130 /* Stop the receiver */
2131 CMD_SET(sc, TL_CMD_RT);
2132 CMD_SET(sc, TL_CMD_STOP);
2133 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2134
2135 /*
2136 * Disable host interrupts.
2137 */
2138 CMD_SET(sc, TL_CMD_INTSOFF);
2139
2140 /*
2141 * Clear list pointer.
2142 */
2143 CSR_WRITE_4(sc, TL_CH_PARM, 0);
2144
2145 /*
2146 * Free the RX lists.
2147 */
2148 for (i = 0; i < TL_RX_LIST_CNT; i++) {
2149 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) {
2150 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf);
2151 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL;
2152 }
2153 }
2154 bzero((char *)&sc->tl_ldata->tl_rx_list,
2155 sizeof(sc->tl_ldata->tl_rx_list));
2156
2157 /*
2158 * Free the TX list buffers.
2159 */
2160 for (i = 0; i < TL_TX_LIST_CNT; i++) {
2161 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) {
2162 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf);
2163 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL;
2164 }
2165 }
2166 bzero((char *)&sc->tl_ldata->tl_tx_list,
2167 sizeof(sc->tl_ldata->tl_tx_list));
2168
2169 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2170
2171 return;
2172}
2173
2174/*
2175 * Stop all chip I/O so that the kernel's probe routines don't
2176 * get confused by errant DMAs when rebooting.
2177 */
c436375a
SW
2178static void
2179tl_shutdown(device_t dev)
984263bc
MD
2180{
2181 struct tl_softc *sc;
2182
2183 sc = device_get_softc(dev);
2184
2185 tl_stop(sc);
2186
2187 return;
2188}