network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / tx / if_tx.c
CommitLineData
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1/*-
2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
95893fe4 27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.43 2008/08/17 04:32:35 sephe Exp $
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28 */
29
30/*
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
32 *
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
38 *
39 * Thanks are going to Steve Bauer and Jason Wright.
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/sockio.h>
45#include <sys/mbuf.h>
46#include <sys/malloc.h>
47#include <sys/kernel.h>
48#include <sys/socket.h>
49#include <sys/queue.h>
78195a76 50#include <sys/serialize.h>
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51#include <sys/bus.h>
52#include <sys/rman.h>
9228feed 53#include <sys/thread2.h>
9db4b353 54#include <sys/interrupt.h>
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55
56#include <net/if.h>
882ec277 57#include <net/ifq_var.h>
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58#include <net/if_arp.h>
59#include <net/ethernet.h>
60#include <net/if_dl.h>
61#include <net/if_media.h>
62
63#include <net/bpf.h>
64
1f2de5d4 65#include <net/vlan/if_vlan_var.h>
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66
67#include <vm/vm.h> /* for vtophys */
68#include <vm/pmap.h> /* for vtophys */
984263bc 69
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70#include <bus/pci/pcireg.h>
71#include <bus/pci/pcivar.h>
f668be28 72#include <bus/pci/pcidevs.h>
984263bc 73
f668be28
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74#include <dev/netif/mii_layer/mii.h>
75#include <dev/netif/mii_layer/miivar.h>
76#include <dev/netif/mii_layer/miidevs.h>
77#include <dev/netif/mii_layer/lxtphyreg.h>
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78
79#include "miibus_if.h"
80
f668be28
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81#include <dev/netif/tx/if_txreg.h>
82#include <dev/netif/tx/if_txvar.h>
984263bc 83
bd4539cc 84static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
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85static void epic_intr(void *);
86static void epic_tx_underrun(epic_softc_t *);
87static int epic_common_attach(epic_softc_t *);
88static void epic_ifstart(struct ifnet *);
89static void epic_ifwatchdog(struct ifnet *);
9e6fd080 90static void epic_stats_update(void *);
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91static int epic_init(epic_softc_t *);
92static void epic_stop(epic_softc_t *);
93static void epic_rx_done(epic_softc_t *);
94static void epic_tx_done(epic_softc_t *);
95static int epic_init_rings(epic_softc_t *);
96static void epic_free_rings(epic_softc_t *);
97static void epic_stop_activity(epic_softc_t *);
98static int epic_queue_last_packet(epic_softc_t *);
99static void epic_start_activity(epic_softc_t *);
100static void epic_set_rx_mode(epic_softc_t *);
101static void epic_set_tx_mode(epic_softc_t *);
102static void epic_set_mc_table(epic_softc_t *);
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103static int epic_read_eeprom(epic_softc_t *,u_int16_t);
104static void epic_output_eepromw(epic_softc_t *, u_int16_t);
105static u_int16_t epic_input_eepromw(epic_softc_t *);
106static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
107static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
108static u_int8_t epic_read_eepromreg(epic_softc_t *);
109
110static int epic_read_phy_reg(epic_softc_t *, int, int);
111static void epic_write_phy_reg(epic_softc_t *, int, int, int);
112
113static int epic_miibus_readreg(device_t, int, int);
114static int epic_miibus_writereg(device_t, int, int, int);
115static void epic_miibus_statchg(device_t);
116static void epic_miibus_mediainit(device_t);
117
118static int epic_ifmedia_upd(struct ifnet *);
119static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
120
121static int epic_probe(device_t);
122static int epic_attach(device_t);
123static void epic_shutdown(device_t);
124static int epic_detach(device_t);
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125
126static device_method_t epic_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, epic_probe),
129 DEVMETHOD(device_attach, epic_attach),
130 DEVMETHOD(device_detach, epic_detach),
131 DEVMETHOD(device_shutdown, epic_shutdown),
132
133 /* MII interface */
134 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
135 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
136 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
137 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
138
139 { 0, 0 }
140};
141
142static driver_t epic_driver = {
143 "tx",
144 epic_methods,
145 sizeof(epic_softc_t)
146};
147
148static devclass_t epic_devclass;
149
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150DECLARE_DUMMY_MODULE(if_tx);
151MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
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152DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
153DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
154
155static struct epic_type epic_devs[] = {
f668be28 156 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
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157 "SMC EtherPower II 10/100" },
158 { 0, 0, NULL }
159};
160
161static int
2b272d21 162epic_probe(device_t dev)
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163{
164 struct epic_type *t;
f668be28
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165 uint16_t vid, did;
166
167 vid = pci_get_vendor(dev);
168 did = pci_get_device(dev);
169 for (t = epic_devs; t->name != NULL; ++t) {
170 if (vid == t->ven_id && did == t->dev_id) {
171 device_set_desc(dev, t->name);
172 return 0;
984263bc 173 }
984263bc 174 }
f668be28 175 return ENXIO;
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176}
177
178#if defined(EPIC_USEIOSPACE)
179#define EPIC_RES SYS_RES_IOPORT
f668be28 180#define EPIC_RID PCIR_BAR(0)
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181#else
182#define EPIC_RES SYS_RES_MEMORY
f668be28 183#define EPIC_RID PCIR_BAR(1)
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184#endif
185
186/*
187 * Attach routine: map registers, allocate softc, rings and descriptors.
188 * Reset to known state.
189 */
190static int
2b272d21 191epic_attach(device_t dev)
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192{
193 struct ifnet *ifp;
194 epic_softc_t *sc;
c8e12de8 195 int error;
9228feed 196 int i, rid, tmp;
984263bc 197
984263bc 198 sc = device_get_softc(dev);
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199
200 /* Preinitialize softc structure */
984263bc 201 sc->dev = dev;
9e6fd080 202 callout_init(&sc->tx_stat_timer);
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203
204 /* Fill ifnet structure */
205 ifp = &sc->sc_if;
c8e12de8 206 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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207 ifp->if_softc = sc;
208 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
209 ifp->if_ioctl = epic_ifioctl;
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210 ifp->if_start = epic_ifstart;
211 ifp->if_watchdog = epic_ifwatchdog;
212 ifp->if_init = (if_init_f_t*)epic_init;
213 ifp->if_timer = 0;
214 ifp->if_baudrate = 10000000;
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215 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
216 ifq_set_ready(&ifp->if_snd);
984263bc 217
38e96c87 218 pci_enable_busmaster(dev);
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219
220 rid = EPIC_RID;
4e6d744d 221 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
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222
223 if (sc->res == NULL) {
224 device_printf(dev, "couldn't map ports/memory\n");
225 error = ENXIO;
226 goto fail;
227 }
228
229 sc->sc_st = rman_get_bustag(sc->res);
230 sc->sc_sh = rman_get_bushandle(sc->res);
231
232 /* Allocate interrupt */
233 rid = 0;
4e6d744d 234 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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235 RF_SHAREABLE | RF_ACTIVE);
236
237 if (sc->irq == NULL) {
238 device_printf(dev, "couldn't map interrupt\n");
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239 error = ENXIO;
240 goto fail;
241 }
242
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243 /* Do OS independent part, including chip wakeup and reset */
244 error = epic_common_attach(sc);
245 if (error) {
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246 error = ENXIO;
247 goto fail;
248 }
249
250 /* Do ifmedia setup */
251 if (mii_phy_probe(dev, &sc->miibus,
252 epic_ifmedia_upd, epic_ifmedia_sts)) {
253 device_printf(dev, "ERROR! MII without any PHY!?\n");
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254 error = ENXIO;
255 goto fail;
256 }
257
984263bc 258 /* board type and ... */
e3869ec7 259 kprintf(" type ");
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260 for(i=0x2c;i<0x32;i++) {
261 tmp = epic_read_eeprom(sc, i);
262 if (' ' == (u_int8_t)tmp) break;
e3869ec7 263 kprintf("%c", (u_int8_t)tmp);
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264 tmp >>= 8;
265 if (' ' == (u_int8_t)tmp) break;
e3869ec7 266 kprintf("%c", (u_int8_t)tmp);
984263bc 267 }
e3869ec7 268 kprintf("\n");
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269
270 /* Attach to OS's managers */
78195a76 271 ether_ifattach(ifp, sc->sc_macaddr, NULL);
984263bc 272 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
984263bc 273
95893fe4 274 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
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275 epic_intr, sc, &sc->sc_ih,
276 ifp->if_serializer);
984263bc 277
8359def6
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278 if (error) {
279 device_printf(dev, "couldn't set up irq\n");
280 ether_ifdetach(ifp);
281 goto fail;
282 }
283
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284 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq));
285 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
286
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287 return(0);
288
289fail:
290 epic_detach(dev);
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291 return(error);
292}
293
294/*
295 * Detach driver and free resources
296 */
297static int
2b272d21 298epic_detach(device_t dev)
984263bc 299{
cdf89432
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300 epic_softc_t *sc = device_get_softc(dev);
301 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 302
8359def6 303 if (device_is_attached(dev)) {
cdf89432 304 lwkt_serialize_enter(ifp->if_serializer);
8359def6 305 epic_stop(sc);
cdf89432
SZ
306 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
307 lwkt_serialize_exit(ifp->if_serializer);
308
309 ether_ifdetach(ifp);
8359def6 310 }
984263bc 311
8359def6
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312 if (sc->miibus)
313 device_delete_child(dev, sc->miibus);
984263bc 314 bus_generic_detach(dev);
984263bc 315
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316 if (sc->irq)
317 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
318 if (sc->res)
319 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
320
321 if (sc->tx_flist)
efda3bd0 322 kfree(sc->tx_flist, M_DEVBUF);
8359def6 323 if (sc->tx_desc)
efda3bd0 324 kfree(sc->tx_desc, M_DEVBUF);
8359def6 325 if (sc->rx_desc)
efda3bd0 326 kfree(sc->rx_desc, M_DEVBUF);
8359def6 327
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328 return(0);
329}
330
331#undef EPIC_RES
332#undef EPIC_RID
333
334/*
335 * Stop all chip I/O so that the kernel's probe routines don't
336 * get confused by errant DMAs when rebooting.
337 */
338static void
2b272d21 339epic_shutdown(device_t dev)
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340{
341 epic_softc_t *sc;
78195a76 342 struct ifnet *ifp;
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343
344 sc = device_get_softc(dev);
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345 ifp = &sc->arpcom.ac_if;
346 lwkt_serialize_enter(ifp->if_serializer);
984263bc 347 epic_stop(sc);
78195a76 348 lwkt_serialize_exit(ifp->if_serializer);
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349}
350
351/*
352 * This is if_ioctl handler.
353 */
354static int
2b272d21 355epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
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356{
357 epic_softc_t *sc = ifp->if_softc;
358 struct mii_data *mii;
359 struct ifreq *ifr = (struct ifreq *) data;
9228feed 360 int error = 0;
984263bc 361
984263bc 362 switch (command) {
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363 case SIOCSIFMTU:
364 if (ifp->if_mtu == ifr->ifr_mtu)
365 break;
366
367 /* XXX Though the datasheet doesn't imply any
368 * limitations on RX and TX sizes beside max 64Kb
369 * DMA transfer, seems we can't send more then 1600
370 * data bytes per ethernet packet. (Transmitter hangs
371 * up if more data is sent)
372 */
373 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
374 ifp->if_mtu = ifr->ifr_mtu;
375 epic_stop(sc);
376 epic_init(sc);
377 } else
378 error = EINVAL;
379 break;
380
381 case SIOCSIFFLAGS:
382 /*
383 * If the interface is marked up and stopped, then start it.
384 * If it is marked down and running, then stop it.
385 */
386 if (ifp->if_flags & IFF_UP) {
387 if ((ifp->if_flags & IFF_RUNNING) == 0) {
388 epic_init(sc);
389 break;
390 }
391 } else {
392 if (ifp->if_flags & IFF_RUNNING) {
393 epic_stop(sc);
394 break;
395 }
396 }
397
398 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
399 epic_stop_activity(sc);
400 epic_set_mc_table(sc);
401 epic_set_rx_mode(sc);
402 epic_start_activity(sc);
403 break;
404
405 case SIOCADDMULTI:
406 case SIOCDELMULTI:
407 epic_set_mc_table(sc);
408 error = 0;
409 break;
410
411 case SIOCSIFMEDIA:
412 case SIOCGIFMEDIA:
413 mii = device_get_softc(sc->miibus);
414 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
415 break;
416
417 default:
4cde4dd5
JS
418 error = ether_ioctl(ifp, command, data);
419 break;
984263bc 420 }
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421 return error;
422}
423
424/*
425 * OS-independed part of attach process. allocate memory for descriptors
426 * and frag lists, wake up chip, read MAC address and PHY identyfier.
427 * Return -1 on failure.
428 */
429static int
2b272d21 430epic_common_attach(epic_softc_t *sc)
984263bc 431{
f668be28 432 uint16_t sub_vid;
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433 int i;
434
77652cad 435 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
c5541aee 436 M_DEVBUF, M_WAITOK | M_ZERO);
77652cad 437 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
c5541aee 438 M_DEVBUF, M_WAITOK | M_ZERO);
77652cad 439 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
c5541aee 440 M_DEVBUF, M_WAITOK | M_ZERO);
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441
442 /* Bring the chip out of low-power mode. */
443 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
444 DELAY(500);
445
446 /* Workaround for Application Note 7-15 */
447 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
448
449 /* Read mac address from EEPROM */
450 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
451 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
452
453 /* Set Non-Volatile Control Register from EEPROM */
454 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
455
456 /* Set defaults */
457 sc->tx_threshold = TRANSMIT_THRESHOLD;
458 sc->txcon = TXCON_DEFAULT;
459 sc->miicfg = MIICFG_SMI_ENABLE;
460 sc->phyid = EPIC_UNKN_PHY;
461 sc->serinst = -1;
462
463 /* Fetch card id */
f668be28 464 sub_vid = pci_get_subvendor(sc->dev);
38e96c87 465 sc->cardid = pci_get_subdevice(sc->dev);
984263bc 466
f668be28
SZ
467 if (sub_vid != PCI_VENDOR_SMC)
468 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
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469
470 return 0;
471}
472
473/*
474 * This is if_start handler. It takes mbufs from if_snd queue
475 * and queue them for transmit, one by one, until TX ring become full
476 * or queue become empty.
477 */
478static void
2b272d21 479epic_ifstart(struct ifnet *ifp)
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480{
481 epic_softc_t *sc = ifp->if_softc;
482 struct epic_tx_buffer *buf;
483 struct epic_tx_desc *desc;
484 struct epic_frag_list *flist;
485 struct mbuf *m0;
f96d6c88
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486 struct mbuf *m;
487 int i;
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488
489 while (sc->pending_txs < TX_RING_SIZE) {
490 buf = sc->tx_buffer + sc->cur_tx;
491 desc = sc->tx_desc + sc->cur_tx;
492 flist = sc->tx_flist + sc->cur_tx;
493
494 /* Get next packet to send */
d2c71fa0 495 m0 = ifq_dequeue(&ifp->if_snd, NULL);
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496
497 /* If nothing to send, return */
882ec277
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498 if (m0 == NULL)
499 return;
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500
501 /* Fill fragments list */
502 for (m = m0, i = 0;
503 (NULL != m) && (i < EPIC_MAX_FRAGS);
504 m = m->m_next, i++) {
505 flist->frag[i].fraglen = m->m_len;
506 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
507 }
508 flist->numfrags = i;
509
510 /* If packet was more than EPIC_MAX_FRAGS parts, */
511 /* recopy packet to new allocated mbuf cluster */
512 if (NULL != m) {
290d24ac 513 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
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514 if (NULL == m) {
515 m_freem(m0);
516 ifp->if_oerrors++;
517 continue;
518 }
519
520 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
521 flist->frag[0].fraglen =
522 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
523 m->m_pkthdr.rcvif = ifp;
524
525 flist->numfrags = 1;
526 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
527 m_freem(m0);
528 m0 = m;
529 }
530
531 buf->mbuf = m0;
532 sc->pending_txs++;
533 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
534 desc->control = 0x01;
535 desc->txlength =
536 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
537 desc->status = 0x8000;
538 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
539
540 /* Set watchdog timer */
541 ifp->if_timer = 8;
542
7600679e 543 BPF_MTAP(ifp, m0);
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544 }
545
546 ifp->if_flags |= IFF_OACTIVE;
547
548 return;
549
550}
551
552/*
553 * Synopsis: Finish all received frames.
554 */
555static void
2b272d21 556epic_rx_done(epic_softc_t *sc)
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557{
558 u_int16_t len;
3013ac0e 559 struct ifnet *ifp = &sc->sc_if;
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560 struct epic_rx_buffer *buf;
561 struct epic_rx_desc *desc;
562 struct mbuf *m;
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563
564 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
565 buf = sc->rx_buffer + sc->cur_rx;
566 desc = sc->rx_desc + sc->cur_rx;
567
568 /* Switch to next descriptor */
569 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
570
571 /*
572 * Check for RX errors. This should only happen if
573 * SAVE_ERRORED_PACKETS is set. RX errors generate
574 * RXE interrupt usually.
575 */
576 if ((desc->status & 1) == 0) {
577 sc->sc_if.if_ierrors++;
578 desc->status = 0x8000;
579 continue;
580 }
581
582 /* Save packet length and mbuf contained packet */
583 len = desc->rxlength - ETHER_CRC_LEN;
584 m = buf->mbuf;
585
586 /* Try to get mbuf cluster */
290d24ac 587 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
588 if (NULL == buf->mbuf) {
589 buf->mbuf = m;
590 desc->status = 0x8000;
3013ac0e 591 ifp->if_ierrors++;
984263bc
MD
592 continue;
593 }
594
595 /* Point to new mbuf, and give descriptor to chip */
596 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
597 desc->status = 0x8000;
598
599 /* First mbuf in packet holds the ethernet and packet headers */
3013ac0e 600 m->m_pkthdr.rcvif = ifp;
984263bc
MD
601 m->m_pkthdr.len = m->m_len = len;
602
984263bc 603 /* Give mbuf to OS */
78195a76 604 ifp->if_input(ifp, m);
984263bc
MD
605
606 /* Successfuly received frame */
3013ac0e 607 ifp->if_ipackets++;
984263bc
MD
608 }
609
610 return;
611}
612
613/*
614 * Synopsis: Do last phase of transmission. I.e. if desc is
615 * transmitted, decrease pending_txs counter, free mbuf contained
616 * packet, switch to next descriptor and repeat until no packets
617 * are pending or descriptor is not transmitted yet.
618 */
619static void
2b272d21 620epic_tx_done(epic_softc_t *sc)
984263bc
MD
621{
622 struct epic_tx_buffer *buf;
623 struct epic_tx_desc *desc;
624 u_int16_t status;
625
626 while (sc->pending_txs > 0) {
627 buf = sc->tx_buffer + sc->dirty_tx;
628 desc = sc->tx_desc + sc->dirty_tx;
629 status = desc->status;
630
631 /* If packet is not transmitted, thou followed */
632 /* packets are not transmitted too */
633 if (status & 0x8000) break;
634
635 /* Packet is transmitted. Switch to next and */
636 /* free mbuf */
637 sc->pending_txs--;
638 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
639 m_freem(buf->mbuf);
640 buf->mbuf = NULL;
641
642 /* Check for errors and collisions */
643 if (status & 0x0001) sc->sc_if.if_opackets++;
644 else sc->sc_if.if_oerrors++;
645 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
646#if defined(EPIC_DIAG)
c8e12de8
JS
647 if ((status & 0x1001) == 0x1001) {
648 if_printf(&sc->sc_if,
649 "Tx ERROR: excessive coll. number\n");
650 }
984263bc
MD
651#endif
652 }
653
654 if (sc->pending_txs < TX_RING_SIZE)
655 sc->sc_if.if_flags &= ~IFF_OACTIVE;
656}
657
658/*
659 * Interrupt function
660 */
661static void
2b272d21 662epic_intr(void *arg)
984263bc
MD
663{
664 epic_softc_t * sc = (epic_softc_t *) arg;
665 int status, i = 4;
666
667 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
668 CSR_WRITE_4(sc, INTSTAT, status);
669
670 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
671 epic_rx_done(sc);
672 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
673#if defined(EPIC_DIAG)
674 if (status & INTSTAT_OVW)
c8e12de8 675 if_printf(&sc->sc_if, "RX buffer overflow\n");
984263bc 676 if (status & INTSTAT_RQE)
c8e12de8 677 if_printf(&sc->sc_if, "RX FIFO overflow\n");
984263bc
MD
678#endif
679 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
680 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
681 sc->sc_if.if_ierrors++;
682 }
683 }
684
685 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
686 epic_tx_done(sc);
882ec277 687 if (!ifq_is_empty(&sc->sc_if.if_snd))
9db4b353 688 if_devstart(&sc->sc_if);
984263bc
MD
689 }
690
691 /* Check for rare errors */
692 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
693 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
694 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
695 INTSTAT_APE|INTSTAT_DPE)) {
3f625015 696 if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n",
984263bc
MD
697 (status&INTSTAT_PMA)?"PMA ":"",
698 (status&INTSTAT_PTA)?"PTA ":"",
699 (status&INTSTAT_APE)?"APE ":"",
700 (status&INTSTAT_DPE)?"DPE":""
701 );
702
703 epic_stop(sc);
704 epic_init(sc);
705
706 break;
707 }
708
709 if (status & INTSTAT_RXE) {
710#if defined(EPIC_DIAG)
c8e12de8 711 if_printf(sc->sc_if, "CRC/Alignment error\n");
984263bc
MD
712#endif
713 sc->sc_if.if_ierrors++;
714 }
715
716 if (status & INTSTAT_TXU) {
717 epic_tx_underrun(sc);
718 sc->sc_if.if_oerrors++;
719 }
720 }
721 }
722
723 /* If no packets are pending, then no timeouts */
724 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
725
726 return;
727}
728
729/*
730 * Handle the TX underrun error: increase the TX threshold
731 * and restart the transmitter.
732 */
733static void
2b272d21 734epic_tx_underrun(epic_softc_t *sc)
984263bc
MD
735{
736 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
737 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
738#if defined(EPIC_DIAG)
c8e12de8 739 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
984263bc
MD
740#endif
741 } else {
742 sc->tx_threshold += 0x40;
743#if defined(EPIC_DIAG)
c8e12de8
JS
744 if_printf(&sc->sc_if, "Tx UNDERRUN: "
745 "TX threshold increased to %d\n", sc->tx_threshold);
984263bc
MD
746#endif
747 }
748
749 /* We must set TXUGO to reset the stuck transmitter */
750 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
751
752 /* Update the TX threshold */
753 epic_stop_activity(sc);
754 epic_set_tx_mode(sc);
755 epic_start_activity(sc);
756
757 return;
758}
759
760/*
761 * Synopsis: This one is called if packets wasn't transmitted
762 * during timeout. Try to deallocate transmitted packets, and
763 * if success continue to work.
764 */
765static void
2b272d21 766epic_ifwatchdog(struct ifnet *ifp)
984263bc
MD
767{
768 epic_softc_t *sc = ifp->if_softc;
984263bc 769
c8e12de8 770 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
984263bc
MD
771
772 /* Try to finish queued packets */
773 epic_tx_done(sc);
774
775 /* If not successful */
776 if (sc->pending_txs > 0) {
777
778 ifp->if_oerrors+=sc->pending_txs;
779
780 /* Reinitialize board */
c8e12de8 781 if_printf(ifp, "reinitialization\n");
984263bc
MD
782 epic_stop(sc);
783 epic_init(sc);
784
785 } else
3f5e28f4 786 if_printf(ifp, "seems we can continue normally\n");
984263bc
MD
787
788 /* Start output */
882ec277 789 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 790 if_devstart(ifp);
984263bc
MD
791}
792
793/*
794 * Despite the name of this function, it doesn't update statistics, it only
795 * helps in autonegotiation process.
796 */
797static void
9e6fd080 798epic_stats_update(void *xsc)
984263bc 799{
9e6fd080 800 epic_softc_t *sc = xsc;
78195a76 801 struct ifnet *ifp = &sc->sc_if;
984263bc 802 struct mii_data * mii;
984263bc 803
78195a76 804 lwkt_serialize_enter(ifp->if_serializer);
984263bc
MD
805
806 mii = device_get_softc(sc->miibus);
807 mii_tick(mii);
808
9e6fd080 809 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
984263bc 810
78195a76 811 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
812}
813
814/*
815 * Set media options.
816 */
817static int
2b272d21 818epic_ifmedia_upd(struct ifnet *ifp)
984263bc
MD
819{
820 epic_softc_t *sc;
821 struct mii_data *mii;
822 struct ifmedia *ifm;
823 struct mii_softc *miisc;
824 int cfg, media;
825
826 sc = ifp->if_softc;
827 mii = device_get_softc(sc->miibus);
828 ifm = &mii->mii_media;
829 media = ifm->ifm_cur->ifm_media;
830
831 /* Do not do anything if interface is not up */
832 if ((ifp->if_flags & IFF_UP) == 0)
833 return (0);
834
835 /*
836 * Lookup current selected PHY
837 */
838 if (IFM_INST(media) == sc->serinst) {
839 sc->phyid = EPIC_SERIAL;
840 sc->physc = NULL;
841 } else {
842 /* If we're not selecting serial interface, select MII mode */
843 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
844 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
845
846 /* Default to unknown PHY */
847 sc->phyid = EPIC_UNKN_PHY;
848
849 /* Lookup selected PHY */
850 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
851 miisc = LIST_NEXT(miisc, mii_list)) {
852 if (IFM_INST(media) == miisc->mii_inst) {
853 sc->physc = miisc;
854 break;
855 }
856 }
857
858 /* Identify selected PHY */
859 if (sc->physc) {
860 int id1, id2, model, oui;
861
862 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
863 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
864
865 oui = MII_OUI(id1, id2);
866 model = MII_MODEL(id2);
867 switch (oui) {
868 case MII_OUI_QUALSEMI:
869 if (model == MII_MODEL_QUALSEMI_QS6612)
870 sc->phyid = EPIC_QS6612_PHY;
871 break;
872 case MII_OUI_xxALTIMA:
873 if (model == MII_MODEL_xxALTIMA_AC101)
874 sc->phyid = EPIC_AC101_PHY;
875 break;
876 case MII_OUI_xxLEVEL1:
877 if (model == MII_MODEL_xxLEVEL1_LXT970)
878 sc->phyid = EPIC_LXT970_PHY;
879 break;
880 }
881 }
882 }
883
884 /*
885 * Do PHY specific card setup
886 */
887
888 /* Call this, to isolate all not selected PHYs and
889 * set up selected
890 */
891 mii_mediachg(mii);
892
893 /* Do our own setup */
894 switch (sc->phyid) {
895 case EPIC_QS6612_PHY:
896 break;
897 case EPIC_AC101_PHY:
898 /* We have to powerup fiber tranceivers */
899 if (IFM_SUBTYPE(media) == IFM_100_FX)
900 sc->miicfg |= MIICFG_694_ENABLE;
901 else
902 sc->miicfg &= ~MIICFG_694_ENABLE;
903 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
904
905 break;
906 case EPIC_LXT970_PHY:
907 /* We have to powerup fiber tranceivers */
908 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
909 if (IFM_SUBTYPE(media) == IFM_100_FX)
910 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
911 else
912 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
913 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
914
915 break;
916 case EPIC_SERIAL:
917 /* Select serial PHY, (10base2/BNC usually) */
918 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
919 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
920
921 /* There is no driver to fill this */
922 mii->mii_media_active = media;
923 mii->mii_media_status = 0;
924
925 /* We need to call this manualy as i wasn't called
926 * in mii_mediachg()
927 */
928 epic_miibus_statchg(sc->dev);
929
930 break;
931 default:
c8e12de8 932 if_printf(ifp, "ERROR! Unknown PHY selected\n");
984263bc
MD
933 return (EINVAL);
934 }
935
936 return(0);
937}
938
939/*
940 * Report current media status.
941 */
942static void
2b272d21 943epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc
MD
944{
945 epic_softc_t *sc;
946 struct mii_data *mii;
947 struct ifmedia *ifm;
948
949 sc = ifp->if_softc;
950 mii = device_get_softc(sc->miibus);
951 ifm = &mii->mii_media;
952
953 /* Nothing should be selected if interface is down */
954 if ((ifp->if_flags & IFF_UP) == 0) {
955 ifmr->ifm_active = IFM_NONE;
956 ifmr->ifm_status = 0;
957
958 return;
959 }
960
961 /* Call underlying pollstat, if not serial PHY */
962 if (sc->phyid != EPIC_SERIAL)
963 mii_pollstat(mii);
964
965 /* Simply copy media info */
966 ifmr->ifm_active = mii->mii_media_active;
967 ifmr->ifm_status = mii->mii_media_status;
968
969 return;
970}
971
972/*
973 * Callback routine, called on media change.
974 */
975static void
2b272d21 976epic_miibus_statchg(device_t dev)
984263bc
MD
977{
978 epic_softc_t *sc;
979 struct mii_data *mii;
980 int media;
981
982 sc = device_get_softc(dev);
983 mii = device_get_softc(sc->miibus);
984 media = mii->mii_media_active;
985
986 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
987
988 /* If we are in full-duplex mode or loopback operation,
989 * we need to decouple receiver and transmitter.
990 */
991 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
992 sc->txcon |= TXCON_FULL_DUPLEX;
993
994 /* On some cards we need manualy set fullduplex led */
995 if (sc->cardid == SMC9432FTX ||
996 sc->cardid == SMC9432FTX_SC) {
997 if (IFM_OPTIONS(media) & IFM_FDX)
998 sc->miicfg |= MIICFG_694_ENABLE;
999 else
1000 sc->miicfg &= ~MIICFG_694_ENABLE;
1001
1002 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1003 }
1004
1005 /* Update baudrate */
1006 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1007 IFM_SUBTYPE(media) == IFM_100_FX)
1008 sc->sc_if.if_baudrate = 100000000;
1009 else
1010 sc->sc_if.if_baudrate = 10000000;
1011
1012 epic_stop_activity(sc);
1013 epic_set_tx_mode(sc);
1014 epic_start_activity(sc);
1015
1016 return;
1017}
1018
1019static void
2b272d21 1020epic_miibus_mediainit(device_t dev)
984263bc
MD
1021{
1022 epic_softc_t *sc;
1023 struct mii_data *mii;
1024 struct ifmedia *ifm;
1025 int media;
1026
1027 sc = device_get_softc(dev);
1028 mii = device_get_softc(sc->miibus);
1029 ifm = &mii->mii_media;
1030
1031 /* Add Serial Media Interface if present, this applies to
1032 * SMC9432BTX serie
1033 */
1034 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1035 /* Store its instance */
1036 sc->serinst = mii->mii_instance++;
1037
1038 /* Add as 10base2/BNC media */
1039 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1040 ifmedia_add(ifm, media, 0, NULL);
1041
1042 /* Report to user */
c8e12de8 1043 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
984263bc
MD
1044 }
1045
1046 return;
1047}
1048
1049/*
1050 * Reset chip, allocate rings, and update media.
1051 */
1052static int
2b272d21 1053epic_init(epic_softc_t *sc)
984263bc
MD
1054{
1055 struct ifnet *ifp = &sc->sc_if;
9228feed 1056 int i;
984263bc 1057
984263bc
MD
1058 /* If interface is already running, then we need not do anything */
1059 if (ifp->if_flags & IFF_RUNNING) {
984263bc
MD
1060 return 0;
1061 }
1062
1063 /* Soft reset the chip (we have to power up card before) */
1064 CSR_WRITE_4(sc, GENCTL, 0);
1065 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1066
1067 /*
1068 * Reset takes 15 pci ticks which depends on PCI bus speed.
1069 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1070 */
1071 DELAY(500);
1072
1073 /* Wake up */
1074 CSR_WRITE_4(sc, GENCTL, 0);
1075
1076 /* Workaround for Application Note 7-15 */
1077 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1078
1079 /* Initialize rings */
1080 if (epic_init_rings(sc)) {
c8e12de8 1081 if_printf(ifp, "failed to init rings\n");
984263bc
MD
1082 return -1;
1083 }
1084
1085 /* Give rings to EPIC */
1086 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1087 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1088
1089 /* Put node address to EPIC */
1090 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1091 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1092 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1093
1094 /* Set tx mode, includeing transmit threshold */
1095 epic_set_tx_mode(sc);
1096
1097 /* Compute and set RXCON. */
1098 epic_set_rx_mode(sc);
1099
1100 /* Set multicast table */
1101 epic_set_mc_table(sc);
1102
1103 /* Enable interrupts by setting the interrupt mask. */
1104 CSR_WRITE_4(sc, INTMASK,
1105 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1106 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1107 INTSTAT_FATAL);
1108
1109 /* Acknowledge all pending interrupts */
1110 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1111
1112 /* Enable interrupts, set for PCI read multiple and etc */
1113 CSR_WRITE_4(sc, GENCTL,
1114 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1115 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1116
1117 /* Mark interface running ... */
1118 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1119 else ifp->if_flags &= ~IFF_RUNNING;
1120
1121 /* ... and free */
1122 ifp->if_flags &= ~IFF_OACTIVE;
1123
1124 /* Start Rx process */
1125 epic_start_activity(sc);
1126
1127 /* Set appropriate media */
1128 epic_ifmedia_upd(ifp);
1129
9e6fd080 1130 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
984263bc 1131
984263bc
MD
1132 return 0;
1133}
1134
1135/*
1136 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1137 * access RXCON.
1138 */
1139static void
2b272d21 1140epic_set_rx_mode(epic_softc_t *sc)
984263bc
MD
1141{
1142 u_int32_t flags = sc->sc_if.if_flags;
1143 u_int32_t rxcon = RXCON_DEFAULT;
1144
1145#if defined(EPIC_EARLY_RX)
1146 rxcon |= RXCON_EARLY_RX;
1147#endif
1148
1149 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1150
1151 CSR_WRITE_4(sc, RXCON, rxcon);
1152
1153 return;
1154}
1155
1156/*
1157 * Synopsis: Set transmit control register. Chip must be in idle state to
1158 * access TXCON.
1159 */
1160static void
2b272d21 1161epic_set_tx_mode(epic_softc_t *sc)
984263bc
MD
1162{
1163 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1164 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1165
1166 CSR_WRITE_4(sc, TXCON, sc->txcon);
1167}
1168
1169/*
1170 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1171 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1172 * individual frames, multicast filter must be manually programmed)
1173 *
1174 * Note: EPIC must be in idle state.
1175 */
1176static void
2b272d21 1177epic_set_mc_table(epic_softc_t *sc)
984263bc
MD
1178{
1179 struct ifnet *ifp = &sc->sc_if;
1180 struct ifmultiaddr *ifma;
1181 u_int16_t filter[4];
1182 u_int8_t h;
1183
1184 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1185 CSR_WRITE_4(sc, MC0, 0xFFFF);
1186 CSR_WRITE_4(sc, MC1, 0xFFFF);
1187 CSR_WRITE_4(sc, MC2, 0xFFFF);
1188 CSR_WRITE_4(sc, MC3, 0xFFFF);
1189
1190 return;
1191 }
1192
1193 filter[0] = 0;
1194 filter[1] = 0;
1195 filter[2] = 0;
1196 filter[3] = 0;
1197
441d34b2 1198 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1199 if (ifma->ifma_addr->sa_family != AF_LINK)
1200 continue;
7cf92e2d
JS
1201 h = (ether_crc32_be(
1202 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1203 ETHER_ADDR_LEN) >> 26) & 0x3f;
984263bc
MD
1204 filter[h >> 4] |= 1 << (h & 0xF);
1205 }
1206
1207 CSR_WRITE_4(sc, MC0, filter[0]);
1208 CSR_WRITE_4(sc, MC1, filter[1]);
1209 CSR_WRITE_4(sc, MC2, filter[2]);
1210 CSR_WRITE_4(sc, MC3, filter[3]);
1211
1212 return;
1213}
1214
984263bc
MD
1215/*
1216 * Synopsis: Start receive process and transmit one, if they need.
1217 */
1218static void
2b272d21 1219epic_start_activity(epic_softc_t *sc)
984263bc
MD
1220{
1221 /* Start rx process */
1222 CSR_WRITE_4(sc, COMMAND,
1223 COMMAND_RXQUEUED | COMMAND_START_RX |
1224 (sc->pending_txs?COMMAND_TXQUEUED:0));
1225}
1226
1227/*
1228 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1229 * packet needs to be queued to stop Tx DMA.
1230 */
1231static void
2b272d21 1232epic_stop_activity(epic_softc_t *sc)
984263bc
MD
1233{
1234 int status, i;
1235
1236 /* Stop Tx and Rx DMA */
1237 CSR_WRITE_4(sc, COMMAND,
1238 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1239
1240 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1241 for (i=0; i<0x1000; i++) {
1242 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1243 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1244 break;
1245 DELAY(1);
1246 }
1247
1248 /* Catch all finished packets */
1249 epic_rx_done(sc);
1250 epic_tx_done(sc);
1251
1252 status = CSR_READ_4(sc, INTSTAT);
1253
1254 if ((status & INTSTAT_RXIDLE) == 0)
c8e12de8 1255 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
984263bc
MD
1256
1257 if ((status & INTSTAT_TXIDLE) == 0)
c8e12de8 1258 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
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1259
1260 /*
1261 * May need to queue one more packet if TQE, this is rare
1262 * but existing case.
1263 */
1264 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
7b9f668c 1265 epic_queue_last_packet(sc);
984263bc
MD
1266
1267}
1268
1269/*
1270 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1271 * a packet from current descriptor will be copied to internal RAM. We
1272 * compose a dummy packet here and queue it for transmission.
1273 *
1274 * XXX the packet will then be actually sent over network...
1275 */
1276static int
2b272d21 1277epic_queue_last_packet(epic_softc_t *sc)
984263bc
MD
1278{
1279 struct epic_tx_desc *desc;
1280 struct epic_frag_list *flist;
1281 struct epic_tx_buffer *buf;
1282 struct mbuf *m0;
1283 int i;
1284
c8e12de8 1285 if_printf(&sc->sc_if, "queue last packet\n");
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MD
1286
1287 desc = sc->tx_desc + sc->cur_tx;
1288 flist = sc->tx_flist + sc->cur_tx;
1289 buf = sc->tx_buffer + sc->cur_tx;
1290
1291 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1292 return (EBUSY);
1293
74f1caca 1294 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
984263bc
MD
1295 if (NULL == m0)
1296 return (ENOBUFS);
1297
1298 /* Prepare mbuf */
1299 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1300 flist->frag[0].fraglen = m0->m_len;
1301 m0->m_pkthdr.len = m0->m_len;
1302 m0->m_pkthdr.rcvif = &sc->sc_if;
1303 bzero(mtod(m0,caddr_t), m0->m_len);
1304
1305 /* Fill fragments list */
1306 flist->frag[0].fraglen = m0->m_len;
1307 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1308 flist->numfrags = 1;
1309
1310 /* Fill in descriptor */
1311 buf->mbuf = m0;
1312 sc->pending_txs++;
1313 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1314 desc->control = 0x01;
1315 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1316 desc->status = 0x8000;
1317
1318 /* Launch transmition */
1319 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1320
1321 /* Wait Tx DMA to stop (for how long??? XXX) */
1322 for (i=0; i<1000; i++) {
1323 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1324 break;
1325 DELAY(1);
1326 }
1327
1328 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
c8e12de8 1329 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
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MD
1330 else
1331 epic_tx_done(sc);
1332
1333 return 0;
1334}
1335
1336/*
1337 * Synopsis: Shut down board and deallocates rings.
1338 */
1339static void
2b272d21 1340epic_stop(epic_softc_t *sc)
984263bc 1341{
984263bc
MD
1342 sc->sc_if.if_timer = 0;
1343
9e6fd080 1344 callout_stop(&sc->tx_stat_timer);
984263bc
MD
1345
1346 /* Disable interrupts */
1347 CSR_WRITE_4(sc, INTMASK, 0);
1348 CSR_WRITE_4(sc, GENCTL, 0);
1349
1350 /* Try to stop Rx and TX processes */
1351 epic_stop_activity(sc);
1352
1353 /* Reset chip */
1354 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1355 DELAY(1000);
1356
1357 /* Make chip go to bed */
1358 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1359
1360 /* Free memory allocated for rings */
1361 epic_free_rings(sc);
1362
1363 /* Mark as stoped */
1364 sc->sc_if.if_flags &= ~IFF_RUNNING;
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MD
1365}
1366
1367/*
1368 * Synopsis: This function should free all memory allocated for rings.
1369 */
1370static void
2b272d21 1371epic_free_rings(epic_softc_t *sc)
984263bc
MD
1372{
1373 int i;
1374
1375 for (i=0; i<RX_RING_SIZE; i++) {
1376 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1377 struct epic_rx_desc *desc = sc->rx_desc + i;
1378
1379 desc->status = 0;
1380 desc->buflength = 0;
1381 desc->bufaddr = 0;
1382
1383 if (buf->mbuf) m_freem(buf->mbuf);
1384 buf->mbuf = NULL;
1385 }
1386
1387 for (i=0; i<TX_RING_SIZE; i++) {
1388 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1389 struct epic_tx_desc *desc = sc->tx_desc + i;
1390
1391 desc->status = 0;
1392 desc->buflength = 0;
1393 desc->bufaddr = 0;
1394
1395 if (buf->mbuf) m_freem(buf->mbuf);
1396 buf->mbuf = NULL;
1397 }
1398}
1399
1400/*
1401 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1402 * Point Tx descs to fragment lists. Check that all descs and fraglists
1403 * are bounded and aligned properly.
1404 */
1405static int
2b272d21 1406epic_init_rings(epic_softc_t *sc)
984263bc
MD
1407{
1408 int i;
1409
1410 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1411
1412 for (i = 0; i < RX_RING_SIZE; i++) {
1413 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1414 struct epic_rx_desc *desc = sc->rx_desc + i;
1415
1416 desc->status = 0; /* Owned by driver */
1417 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1418
1419 if ((desc->next & 3) ||
1420 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1421 epic_free_rings(sc);
1422 return EFAULT;
1423 }
1424
290d24ac 1425 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
984263bc
MD
1426 if (NULL == buf->mbuf) {
1427 epic_free_rings(sc);
1428 return ENOBUFS;
1429 }
1430 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1431
1432 desc->buflength = MCLBYTES; /* Max RX buffer length */
1433 desc->status = 0x8000; /* Set owner bit to NIC */
1434 }
1435
1436 for (i = 0; i < TX_RING_SIZE; i++) {
1437 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1438 struct epic_tx_desc *desc = sc->tx_desc + i;
1439
1440 desc->status = 0;
1441 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1442
1443 if ((desc->next & 3) ||
1444 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1445 epic_free_rings(sc);
1446 return EFAULT;
1447 }
1448
1449 buf->mbuf = NULL;
1450 desc->bufaddr = vtophys(sc->tx_flist + i);
1451
1452 if ((desc->bufaddr & 3) ||
1453 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1454 epic_free_rings(sc);
1455 return EFAULT;
1456 }
1457 }
1458
1459 return 0;
1460}
1461
1462/*
1463 * EEPROM operation functions
1464 */
1465static void
2b272d21 1466epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
984263bc
MD
1467{
1468 u_int16_t i;
1469
1470 CSR_WRITE_1(sc, EECTL, val);
1471
1472 for (i=0; i<0xFF; i++)
1473 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1474
1475 return;
1476}
1477
1478static u_int8_t
2b272d21 1479epic_read_eepromreg(epic_softc_t *sc)
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MD
1480{
1481 return CSR_READ_1(sc, EECTL);
1482}
1483
1484static u_int8_t
2b272d21 1485epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
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MD
1486{
1487 epic_write_eepromreg(sc, val);
1488 epic_write_eepromreg(sc, (val | 0x4));
1489 epic_write_eepromreg(sc, val);
1490
1491 return epic_read_eepromreg(sc);
1492}
1493
1494static void
2b272d21 1495epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
984263bc
MD
1496{
1497 int i;
1498
1499 for (i = 0xF; i >= 0; i--) {
1500 if (val & (1 << i))
1501 epic_eeprom_clock(sc, 0x0B);
1502 else
1503 epic_eeprom_clock(sc, 0x03);
1504 }
1505}
1506
1507static u_int16_t
2b272d21 1508epic_input_eepromw(epic_softc_t *sc)
984263bc
MD
1509{
1510 u_int16_t retval = 0;
1511 int i;
1512
1513 for (i = 0xF; i >= 0; i--) {
1514 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1515 retval |= (1 << i);
1516 }
1517
1518 return retval;
1519}
1520
1521static int
2b272d21 1522epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
984263bc
MD
1523{
1524 u_int16_t dataval;
1525 u_int16_t read_cmd;
1526
1527 epic_write_eepromreg(sc, 3);
1528
1529 if (epic_read_eepromreg(sc) & 0x40)
1530 read_cmd = (loc & 0x3F) | 0x180;
1531 else
1532 read_cmd = (loc & 0xFF) | 0x600;
1533
1534 epic_output_eepromw(sc, read_cmd);
1535
1536 dataval = epic_input_eepromw(sc);
1537
1538 epic_write_eepromreg(sc, 1);
1539
1540 return dataval;
1541}
1542
1543/*
1544 * Here goes MII read/write routines
1545 */
1546static int
2b272d21 1547epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
984263bc
MD
1548{
1549 int i;
1550
1551 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1552
1553 for (i = 0; i < 0x100; i++) {
1554 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1555 DELAY(1);
1556 }
1557
1558 return (CSR_READ_4(sc, MIIDATA));
1559}
1560
1561static void
2b272d21 1562epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
984263bc
MD
1563{
1564 int i;
1565
1566 CSR_WRITE_4(sc, MIIDATA, val);
1567 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1568
1569 for(i=0;i<0x100;i++) {
1570 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1571 DELAY(1);
1572 }
1573
1574 return;
1575}
1576
1577static int
2b272d21 1578epic_miibus_readreg(device_t dev, int phy, int reg)
984263bc
MD
1579{
1580 epic_softc_t *sc;
1581
1582 sc = device_get_softc(dev);
1583
1584 return (PHY_READ_2(sc, phy, reg));
1585}
1586
1587static int
2b272d21 1588epic_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc
MD
1589{
1590 epic_softc_t *sc;
1591
1592 sc = device_get_softc(dev);
1593
1594 PHY_WRITE_2(sc, phy, reg, data);
1595
1596 return (0);
1597}