network code: Convert if_multiaddrs from LIST to TAILQ.
[dragonfly.git] / sys / dev / netif / wb / if_wb.c
CommitLineData
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1/*
2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26.2.6 2003/03/05 18:42:34 njl Exp $
95893fe4 33 * $DragonFly: src/sys/dev/netif/wb/if_wb.c,v 1.42 2008/08/17 04:32:35 sephe Exp $
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34 */
35
36/*
37 * Winbond fast ethernet PCI NIC driver
38 *
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
42 *
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
46 */
47
48/*
49 * The Winbond W89C840F chip is a bus master; in some ways it resembles
50 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
51 * one major difference which is that while the registers do many of
52 * the same things as a tulip adapter, the offsets are different: where
53 * tulip registers are typically spaced 8 bytes apart, the Winbond
54 * registers are spaced 4 bytes apart. The receiver filter is also
55 * programmed differently.
56 *
57 * Like the tulip, the Winbond chip uses small descriptors containing
58 * a status word, a control word and 32-bit areas that can either be used
59 * to point to two external data blocks, or to point to a single block
60 * and another descriptor in a linked list. Descriptors can be grouped
61 * together in blocks to form fixed length rings or can be chained
62 * together in linked lists. A single packet may be spread out over
63 * several descriptors if necessary.
64 *
65 * For the receive ring, this driver uses a linked list of descriptors,
66 * each pointing to a single mbuf cluster buffer, which us large enough
67 * to hold an entire packet. The link list is looped back to created a
68 * closed ring.
69 *
70 * For transmission, the driver creates a linked list of 'super descriptors'
71 * which each contain several individual descriptors linked toghether.
72 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
73 * abuse as fragment pointers. This allows us to use a buffer managment
74 * scheme very similar to that used in the ThunderLAN and Etherlink XL
75 * drivers.
76 *
77 * Autonegotiation is performed using the external PHY via the MII bus.
78 * The sample boards I have all use a Davicom PHY.
79 *
80 * Note: the author of the Linux driver for the Winbond chip alludes
81 * to some sort of flaw in the chip's design that seems to mandate some
82 * drastic workaround which signigicantly impairs transmit performance.
83 * I have no idea what he's on about: transmit performance with all
84 * three of my test boards seems fine.
85 */
86
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87#include <sys/param.h>
88#include <sys/systm.h>
89#include <sys/sockio.h>
90#include <sys/mbuf.h>
91#include <sys/malloc.h>
92#include <sys/kernel.h>
93#include <sys/socket.h>
94#include <sys/queue.h>
78195a76 95#include <sys/serialize.h>
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96#include <sys/bus.h>
97#include <sys/rman.h>
9228feed 98#include <sys/thread2.h>
9db4b353 99#include <sys/interrupt.h>
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100
101#include <net/if.h>
0536a950 102#include <net/ifq_var.h>
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103#include <net/if_arp.h>
104#include <net/ethernet.h>
105#include <net/if_dl.h>
106#include <net/if_media.h>
107
108#include <net/bpf.h>
109
110#include <vm/vm.h> /* for vtophys */
111#include <vm/pmap.h> /* for vtophys */
984263bc 112
243b8210 113#include <bus/pci/pcidevs.h>
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114#include <bus/pci/pcireg.h>
115#include <bus/pci/pcivar.h>
984263bc 116
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117#include <dev/netif/mii_layer/mii.h>
118#include <dev/netif/mii_layer/miivar.h>
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119
120/* "controller miibus0" required. See GENERIC if you get errors here. */
121#include "miibus_if.h"
122
123#define WB_USEIOSPACE
124
1f2de5d4 125#include "if_wbreg.h"
984263bc 126
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127/*
128 * Various supported device vendors/types and their names.
129 */
130static struct wb_type wb_devs[] = {
243b8210 131 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F,
984263bc 132 "Winbond W89C840F 10/100BaseTX" },
243b8210 133 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX,
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134 "Compex RL100-ATX 10/100baseTX" },
135 { 0, 0, NULL }
136};
137
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138static int wb_probe(device_t);
139static int wb_attach(device_t);
140static int wb_detach(device_t);
141
1f36295c 142static void wb_bfree(void *);
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143static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
144 struct mbuf *);
145static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
146
147static void wb_rxeof(struct wb_softc *);
148static void wb_rxeoc(struct wb_softc *);
149static void wb_txeof(struct wb_softc *);
150static void wb_txeoc(struct wb_softc *);
151static void wb_intr(void *);
152static void wb_tick(void *);
153static void wb_start(struct ifnet *);
154static int wb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
155static void wb_init(void *);
156static void wb_stop(struct wb_softc *);
157static void wb_watchdog(struct ifnet *);
158static void wb_shutdown(device_t);
159static int wb_ifmedia_upd(struct ifnet *);
160static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
161
162static void wb_eeprom_putbyte(struct wb_softc *, int);
163static void wb_eeprom_getword(struct wb_softc *, int, uint16_t *);
164static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int);
165static void wb_mii_sync(struct wb_softc *);
166static void wb_mii_send(struct wb_softc *, uint32_t, int);
167static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
168static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
169
170static void wb_setcfg(struct wb_softc *, uint32_t);
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171static void wb_setmulti(struct wb_softc *);
172static void wb_reset(struct wb_softc *);
173static void wb_fixmedia(struct wb_softc *);
174static int wb_list_rx_init(struct wb_softc *);
175static int wb_list_tx_init(struct wb_softc *);
176
177static int wb_miibus_readreg(device_t, int, int);
178static int wb_miibus_writereg(device_t, int, int, int);
179static void wb_miibus_statchg(device_t);
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180
181#ifdef WB_USEIOSPACE
182#define WB_RES SYS_RES_IOPORT
183#define WB_RID WB_PCI_LOIO
184#else
185#define WB_RES SYS_RES_MEMORY
186#define WB_RID WB_PCI_LOMEM
187#endif
188
189static device_method_t wb_methods[] = {
190 /* Device interface */
191 DEVMETHOD(device_probe, wb_probe),
192 DEVMETHOD(device_attach, wb_attach),
193 DEVMETHOD(device_detach, wb_detach),
194 DEVMETHOD(device_shutdown, wb_shutdown),
195
196 /* bus interface, for miibus */
197 DEVMETHOD(bus_print_child, bus_generic_print_child),
198 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
199
200 /* MII interface */
201 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
202 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
203 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
204 { 0, 0 }
205};
206
5f700c02 207static DEFINE_CLASS_0(wb, wb_driver, wb_methods, sizeof(struct wb_softc));
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208static devclass_t wb_devclass;
209
32832096 210DECLARE_DUMMY_MODULE(if_wb);
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211DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0);
212DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
213
214#define WB_SETBIT(sc, reg, x) \
5f700c02 215 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
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216
217#define WB_CLRBIT(sc, reg, x) \
5f700c02 218 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
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219
220#define SIO_SET(x) \
5f700c02 221 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))
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222
223#define SIO_CLR(x) \
5f700c02 224 CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))
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225
226/*
227 * Send a read command and address to the EEPROM, check for ACK.
228 */
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229static void
230wb_eeprom_putbyte(struct wb_softc *sc, int addr)
984263bc 231{
5f700c02 232 int d, i;
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233
234 d = addr | WB_EECMD_READ;
235
236 /*
237 * Feed in each bit and stobe the clock.
238 */
239 for (i = 0x400; i; i >>= 1) {
5f700c02 240 if (d & i)
984263bc 241 SIO_SET(WB_SIO_EE_DATAIN);
5f700c02 242 else
984263bc 243 SIO_CLR(WB_SIO_EE_DATAIN);
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244 DELAY(100);
245 SIO_SET(WB_SIO_EE_CLK);
246 DELAY(150);
247 SIO_CLR(WB_SIO_EE_CLK);
248 DELAY(100);
249 }
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250}
251
252/*
253 * Read a word of data stored in the EEPROM at address 'addr.'
254 */
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255static void
256wb_eeprom_getword(struct wb_softc *sc, int addr, uint16_t *dest)
984263bc 257{
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258 int i;
259 uint16_t word = 0;
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260
261 /* Enter EEPROM access mode. */
262 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
263
264 /*
265 * Send address of word we want to read.
266 */
267 wb_eeprom_putbyte(sc, addr);
268
269 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
270
271 /*
272 * Start reading bits from EEPROM.
273 */
274 for (i = 0x8000; i; i >>= 1) {
275 SIO_SET(WB_SIO_EE_CLK);
276 DELAY(100);
277 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
278 word |= i;
279 SIO_CLR(WB_SIO_EE_CLK);
280 DELAY(100);
281 }
282
283 /* Turn off EEPROM access mode. */
284 CSR_WRITE_4(sc, WB_SIO, 0);
285
286 *dest = word;
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287}
288
289/*
290 * Read a sequence of words from the EEPROM.
291 */
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292static void
293wb_read_eeprom(struct wb_softc *sc, caddr_t dest, int off, int cnt)
984263bc 294{
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295 int i;
296 uint16_t word = 0, *ptr;
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297
298 for (i = 0; i < cnt; i++) {
299 wb_eeprom_getword(sc, off + i, &word);
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300 ptr = (uint16_t *)(dest + (i * 2));
301 *ptr = word;
984263bc 302 }
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303}
304
305/*
306 * Sync the PHYs by setting data bit and strobing the clock 32 times.
307 */
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308static void
309wb_mii_sync(struct wb_softc *sc)
984263bc 310{
5f700c02 311 int i;
984263bc 312
5f700c02 313 SIO_SET(WB_SIO_MII_DIR | WB_SIO_MII_DATAIN);
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314
315 for (i = 0; i < 32; i++) {
316 SIO_SET(WB_SIO_MII_CLK);
317 DELAY(1);
318 SIO_CLR(WB_SIO_MII_CLK);
319 DELAY(1);
320 }
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321}
322
323/*
324 * Clock a series of bits through the MII.
325 */
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326static void
327wb_mii_send(struct wb_softc *sc, uint32_t bits, int cnt)
984263bc 328{
5f700c02 329 int i;
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330
331 SIO_CLR(WB_SIO_MII_CLK);
332
333 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
5f700c02 334 if (bits & i)
984263bc 335 SIO_SET(WB_SIO_MII_DATAIN);
5f700c02 336 else
984263bc 337 SIO_CLR(WB_SIO_MII_DATAIN);
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338 DELAY(1);
339 SIO_CLR(WB_SIO_MII_CLK);
340 DELAY(1);
341 SIO_SET(WB_SIO_MII_CLK);
342 }
343}
344
345/*
346 * Read an PHY register through the MII.
347 */
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348static int
349wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame)
984263bc 350{
9228feed 351 int ack, i;
984263bc 352
9228feed 353 crit_enter();
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354
355 /*
356 * Set up frame for RX.
357 */
358 frame->mii_stdelim = WB_MII_STARTDELIM;
359 frame->mii_opcode = WB_MII_READOP;
360 frame->mii_turnaround = 0;
361 frame->mii_data = 0;
5f700c02 362
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363 CSR_WRITE_4(sc, WB_SIO, 0);
364
365 /*
366 * Turn on data xmit.
367 */
368 SIO_SET(WB_SIO_MII_DIR);
369
370 wb_mii_sync(sc);
371
372 /*
373 * Send command/address info.
374 */
375 wb_mii_send(sc, frame->mii_stdelim, 2);
376 wb_mii_send(sc, frame->mii_opcode, 2);
377 wb_mii_send(sc, frame->mii_phyaddr, 5);
378 wb_mii_send(sc, frame->mii_regaddr, 5);
379
380 /* Idle bit */
5f700c02 381 SIO_CLR((WB_SIO_MII_CLK | WB_SIO_MII_DATAIN));
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382 DELAY(1);
383 SIO_SET(WB_SIO_MII_CLK);
384 DELAY(1);
385
386 /* Turn off xmit. */
387 SIO_CLR(WB_SIO_MII_DIR);
388 /* Check for ack */
389 SIO_CLR(WB_SIO_MII_CLK);
390 DELAY(1);
391 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
392 SIO_SET(WB_SIO_MII_CLK);
393 DELAY(1);
394 SIO_CLR(WB_SIO_MII_CLK);
395 DELAY(1);
396 SIO_SET(WB_SIO_MII_CLK);
397 DELAY(1);
398
399 /*
400 * Now try reading data bits. If the ack failed, we still
401 * need to clock through 16 cycles to keep the PHY(s) in sync.
402 */
403 if (ack) {
404 for(i = 0; i < 16; i++) {
405 SIO_CLR(WB_SIO_MII_CLK);
406 DELAY(1);
407 SIO_SET(WB_SIO_MII_CLK);
408 DELAY(1);
409 }
410 goto fail;
411 }
412
413 for (i = 0x8000; i; i >>= 1) {
414 SIO_CLR(WB_SIO_MII_CLK);
415 DELAY(1);
416 if (!ack) {
417 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
418 frame->mii_data |= i;
419 DELAY(1);
420 }
421 SIO_SET(WB_SIO_MII_CLK);
422 DELAY(1);
423 }
424
425fail:
426
427 SIO_CLR(WB_SIO_MII_CLK);
428 DELAY(1);
429 SIO_SET(WB_SIO_MII_CLK);
430 DELAY(1);
431
9228feed 432 crit_exit();
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433
434 if (ack)
435 return(1);
436 return(0);
437}
438
439/*
440 * Write to a PHY register through the MII.
441 */
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442static int
443wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame)
984263bc 444{
984263bc 445
9228feed 446 crit_enter();
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447 /*
448 * Set up frame for TX.
449 */
450
451 frame->mii_stdelim = WB_MII_STARTDELIM;
452 frame->mii_opcode = WB_MII_WRITEOP;
453 frame->mii_turnaround = WB_MII_TURNAROUND;
454
455 /*
456 * Turn on data output.
457 */
458 SIO_SET(WB_SIO_MII_DIR);
459
460 wb_mii_sync(sc);
461
462 wb_mii_send(sc, frame->mii_stdelim, 2);
463 wb_mii_send(sc, frame->mii_opcode, 2);
464 wb_mii_send(sc, frame->mii_phyaddr, 5);
465 wb_mii_send(sc, frame->mii_regaddr, 5);
466 wb_mii_send(sc, frame->mii_turnaround, 2);
467 wb_mii_send(sc, frame->mii_data, 16);
468
469 /* Idle bit. */
470 SIO_SET(WB_SIO_MII_CLK);
471 DELAY(1);
472 SIO_CLR(WB_SIO_MII_CLK);
473 DELAY(1);
474
475 /*
476 * Turn off xmit.
477 */
478 SIO_CLR(WB_SIO_MII_DIR);
479
9228feed 480 crit_exit();
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481
482 return(0);
483}
484
5f700c02
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485static int
486wb_miibus_readreg(device_t dev, int phy, int reg)
984263bc 487{
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488 struct wb_softc *sc = device_get_softc(dev);
489 struct wb_mii_frame frame;
984263bc 490
5f700c02 491 bzero(&frame, sizeof(frame));
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492
493 frame.mii_phyaddr = phy;
494 frame.mii_regaddr = reg;
495 wb_mii_readreg(sc, &frame);
496
497 return(frame.mii_data);
498}
499
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500static int
501wb_miibus_writereg(device_t dev, int phy, int reg, int data)
984263bc 502{
5f700c02
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503 struct wb_softc *sc = device_get_softc(dev);
504 struct wb_mii_frame frame;
984263bc 505
5f700c02 506 bzero(&frame, sizeof(frame));
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507
508 frame.mii_phyaddr = phy;
509 frame.mii_regaddr = reg;
510 frame.mii_data = data;
511
512 wb_mii_writereg(sc, &frame);
513
514 return(0);
515}
516
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517static void
518wb_miibus_statchg(device_t dev)
984263bc 519{
5f700c02
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520 struct wb_softc *sc = device_get_softc(dev);
521 struct mii_data *mii;
984263bc 522
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523 mii = device_get_softc(sc->wb_miibus);
524 wb_setcfg(sc, mii->mii_media_active);
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525}
526
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527/*
528 * Program the 64-bit multicast hash filter.
529 */
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530static void
531wb_setmulti(struct wb_softc *sc)
984263bc 532{
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533 struct ifnet *ifp = &sc->arpcom.ac_if;
534 int h = 0, mcnt = 0;
535 uint32_t hashes[2] = { 0, 0 };
536 struct ifmultiaddr *ifma;
537 uint32_t rxfilt;
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538
539 rxfilt = CSR_READ_4(sc, WB_NETCFG);
540
541 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
542 rxfilt |= WB_NETCFG_RX_MULTI;
543 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
544 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
545 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
546 return;
547 }
548
549 /* first, zot all the existing hash bits */
550 CSR_WRITE_4(sc, WB_MAR0, 0);
551 CSR_WRITE_4(sc, WB_MAR1, 0);
552
553 /* now program new ones */
441d34b2 554 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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555 if (ifma->ifma_addr->sa_family != AF_LINK)
556 continue;
a10e77b6
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557 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
558 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
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559 if (h < 32)
560 hashes[0] |= (1 << h);
561 else
562 hashes[1] |= (1 << (h - 32));
563 mcnt++;
564 }
565
566 if (mcnt)
567 rxfilt |= WB_NETCFG_RX_MULTI;
568 else
569 rxfilt &= ~WB_NETCFG_RX_MULTI;
570
571 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
572 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
573 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
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574}
575
576/*
577 * The Winbond manual states that in order to fiddle with the
578 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
579 * first have to put the transmit and/or receive logic in the idle state.
580 */
5f700c02
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581static void
582wb_setcfg(struct wb_softc *sc, uint32_t media)
984263bc 583{
5f700c02 584 int i, restart = 0;
984263bc 585
5f700c02 586 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {
984263bc 587 restart = 1;
5f700c02 588 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON));
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589
590 for (i = 0; i < WB_TIMEOUT; i++) {
591 DELAY(10);
592 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
593 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
594 break;
595 }
596
5b73a04e
JS
597 if (i == WB_TIMEOUT) {
598 if_printf(&sc->arpcom.ac_if, "failed to force tx and "
599 "rx to idle state\n");
600 }
984263bc
MD
601 }
602
603 if (IFM_SUBTYPE(media) == IFM_10_T)
604 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
605 else
606 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
607
608 if ((media & IFM_GMASK) == IFM_FDX)
609 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
610 else
611 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
612
613 if (restart)
5f700c02 614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON | WB_NETCFG_RX_ON);
984263bc
MD
615}
616
5f700c02
JS
617static void
618wb_reset(struct wb_softc *sc)
984263bc 619{
5f700c02
JS
620 int i;
621 struct mii_data *mii;
984263bc
MD
622
623 CSR_WRITE_4(sc, WB_NETCFG, 0);
624 CSR_WRITE_4(sc, WB_BUSCTL, 0);
625 CSR_WRITE_4(sc, WB_TXADDR, 0);
626 CSR_WRITE_4(sc, WB_RXADDR, 0);
627
628 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
629 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
630
631 for (i = 0; i < WB_TIMEOUT; i++) {
632 DELAY(10);
5f700c02 633 if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)
984263bc
MD
634 break;
635 }
636 if (i == WB_TIMEOUT)
5b73a04e 637 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
984263bc
MD
638
639 /* Wait a little while for the chip to get its brains in order. */
640 DELAY(1000);
641
642 if (sc->wb_miibus == NULL)
643 return;
644
645 mii = device_get_softc(sc->wb_miibus);
646 if (mii == NULL)
647 return;
648
649 if (mii->mii_instance) {
5f700c02
JS
650 struct mii_softc *miisc;
651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
984263bc
MD
652 mii_phy_reset(miisc);
653 }
984263bc
MD
654}
655
5f700c02
JS
656static void
657wb_fixmedia(struct wb_softc *sc)
984263bc 658{
5f700c02
JS
659 struct mii_data *mii;
660 uint32_t media;
984263bc
MD
661
662 if (sc->wb_miibus == NULL)
663 return;
664
665 mii = device_get_softc(sc->wb_miibus);
984263bc
MD
666
667 mii_pollstat(mii);
668 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
669 media = mii->mii_media_active & ~IFM_10_T;
670 media |= IFM_100_TX;
671 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
672 media = mii->mii_media_active & ~IFM_100_TX;
673 media |= IFM_10_T;
674 } else
675 return;
676
677 ifmedia_set(&mii->mii_media, media);
984263bc
MD
678}
679
680/*
681 * Probe for a Winbond chip. Check the PCI vendor and device
682 * IDs against our list and return a device name if we find a match.
683 */
7b9f668c
SW
684static int
685wb_probe(device_t dev)
984263bc 686{
5f700c02
JS
687 struct wb_type *t;
688 uint16_t vendor, product;
984263bc 689
5f700c02
JS
690 vendor = pci_get_vendor(dev);
691 product = pci_get_device(dev);
984263bc 692
5f700c02
JS
693 for (t = wb_devs; t->wb_name != NULL; t++) {
694 if (vendor == t->wb_vid && product == t->wb_did) {
984263bc
MD
695 device_set_desc(dev, t->wb_name);
696 return(0);
697 }
984263bc
MD
698 }
699
700 return(ENXIO);
701}
702
703/*
704 * Attach the interface. Allocate softc structures, do ifmedia
705 * setup and ethernet/BPF attach.
706 */
5f700c02
JS
707static int
708wb_attach(device_t dev)
984263bc 709{
5f700c02 710 u_char eaddr[ETHER_ADDR_LEN];
5f700c02
JS
711 struct wb_softc *sc;
712 struct ifnet *ifp;
5b73a04e 713 int error = 0, rid;
984263bc 714
984263bc 715 sc = device_get_softc(dev);
ef203de8 716 callout_init(&sc->wb_stat_timer);
984263bc
MD
717
718 /*
719 * Handle power management nonsense.
720 */
a4229cc8
JS
721 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
722 uint32_t iobase, membase, irq;
723
724 /* Save important PCI config data. */
725 iobase = pci_read_config(dev, WB_PCI_LOIO, 4);
726 membase = pci_read_config(dev, WB_PCI_LOMEM, 4);
727 irq = pci_read_config(dev, WB_PCI_INTLINE, 4);
728
729 /* Reset the power state. */
730 device_printf(dev, "chip is in D%d power mode "
731 "-- setting to D0\n", pci_get_powerstate(dev));
732 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
733
734 /* Restore PCI config data. */
735 pci_write_config(dev, WB_PCI_LOIO, iobase, 4);
736 pci_write_config(dev, WB_PCI_LOMEM, membase, 4);
737 pci_write_config(dev, WB_PCI_INTLINE, irq, 4);
984263bc
MD
738 }
739
a4229cc8 740 pci_enable_busmaster(dev);
984263bc
MD
741
742 rid = WB_RID;
4e6d744d 743 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
984263bc
MD
744
745 if (sc->wb_res == NULL) {
f1a5487f 746 device_printf(dev, "couldn't map ports/memory\n");
984263bc
MD
747 error = ENXIO;
748 goto fail;
749 }
750
751 sc->wb_btag = rman_get_bustag(sc->wb_res);
752 sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
753
754 /* Allocate interrupt */
755 rid = 0;
4e6d744d 756 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
984263bc
MD
757 RF_SHAREABLE | RF_ACTIVE);
758
759 if (sc->wb_irq == NULL) {
f1a5487f 760 device_printf(dev, "couldn't map interrupt\n");
984263bc
MD
761 error = ENXIO;
762 goto fail;
763 }
764
984263bc
MD
765 /* Save the cache line size. */
766 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
767
5b73a04e
JS
768 ifp = &sc->arpcom.ac_if;
769 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
770
984263bc
MD
771 /* Reset the adapter. */
772 wb_reset(sc);
773
774 /*
775 * Get station address from the EEPROM.
776 */
5f700c02 777 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3);
984263bc 778
984263bc 779 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
e7b4468c 780 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
984263bc
MD
781
782 if (sc->wb_ldata == NULL) {
f1a5487f 783 device_printf(dev, "no memory for list buffers!\n");
984263bc
MD
784 error = ENXIO;
785 goto fail;
786 }
787
984263bc 788 ifp->if_softc = sc;
984263bc
MD
789 ifp->if_mtu = ETHERMTU;
790 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
791 ifp->if_ioctl = wb_ioctl;
984263bc
MD
792 ifp->if_start = wb_start;
793 ifp->if_watchdog = wb_watchdog;
794 ifp->if_init = wb_init;
795 ifp->if_baudrate = 10000000;
0536a950
JS
796 ifq_set_maxlen(&ifp->if_snd, WB_TX_LIST_CNT - 1);
797 ifq_set_ready(&ifp->if_snd);
984263bc
MD
798
799 /*
800 * Do MII setup.
801 */
802 if (mii_phy_probe(dev, &sc->wb_miibus,
803 wb_ifmedia_upd, wb_ifmedia_sts)) {
984263bc
MD
804 error = ENXIO;
805 goto fail;
806 }
807
808 /*
809 * Call MI attach routine.
810 */
78195a76 811 ether_ifattach(ifp, eaddr, NULL);
984263bc 812
95893fe4 813 error = bus_setup_intr(dev, sc->wb_irq, INTR_MPSAFE,
78195a76
MD
814 wb_intr, sc, &sc->wb_intrhand,
815 ifp->if_serializer);
984263bc 816
f1a5487f
JS
817 if (error) {
818 device_printf(dev, "couldn't set up irq\n");
9ed0a178 819 ether_ifdetach(ifp);
f1a5487f
JS
820 goto fail;
821 }
822
9db4b353
SZ
823 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->wb_irq));
824 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
825
f1a5487f
JS
826 return(0);
827
828fail:
829 wb_detach(dev);
984263bc
MD
830 return(error);
831}
832
5f700c02
JS
833static int
834wb_detach(device_t dev)
984263bc 835{
5f700c02
JS
836 struct wb_softc *sc = device_get_softc(dev);
837 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 838
984263bc 839
f1a5487f 840 if (device_is_attached(dev)) {
cdf89432
SZ
841 lwkt_serialize_enter(ifp->if_serializer);
842 wb_stop(sc);
843 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
844 lwkt_serialize_exit(ifp->if_serializer);
845
f1a5487f 846 ether_ifdetach(ifp);
f1a5487f 847 }
984263bc 848
9ed0a178
JS
849 if (sc->wb_miibus)
850 device_delete_child(dev, sc->wb_miibus);
851 bus_generic_detach(dev);
852
6d089972 853 if (sc->wb_irq)
f1a5487f
JS
854 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
855 if (sc->wb_res)
856 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
857 if (sc->wb_ldata_ptr) {
858 contigfree(sc->wb_ldata_ptr, sizeof(struct wb_list_data) + 8,
859 M_DEVBUF);
860 }
984263bc
MD
861
862 return(0);
863}
864
865/*
866 * Initialize the transmit descriptors.
867 */
5f700c02
JS
868static int
869wb_list_tx_init(struct wb_softc *sc)
984263bc 870{
5f700c02
JS
871 struct wb_chain_data *cd;
872 struct wb_list_data *ld;
873 int i, nexti;
984263bc
MD
874
875 cd = &sc->wb_cdata;
876 ld = sc->wb_ldata;
877
878 for (i = 0; i < WB_TX_LIST_CNT; i++) {
5f700c02 879 nexti = (i == WB_TX_LIST_CNT - 1) ? 0 : i + 1;
984263bc 880 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
5f700c02 881 cd->wb_tx_chain[i].wb_nextdesc = &cd->wb_tx_chain[nexti];
984263bc
MD
882 }
883
884 cd->wb_tx_free = &cd->wb_tx_chain[0];
885 cd->wb_tx_tail = cd->wb_tx_head = NULL;
886
887 return(0);
888}
889
984263bc
MD
890/*
891 * Initialize the RX descriptors and allocate mbufs for them. Note that
892 * we arrange the descriptors in a closed ring, so that the last descriptor
893 * points back to the first.
894 */
5f700c02
JS
895static int
896wb_list_rx_init(struct wb_softc *sc)
984263bc 897{
5f700c02
JS
898 struct wb_chain_data *cd;
899 struct wb_list_data *ld;
900 int i, nexti;
984263bc
MD
901
902 cd = &sc->wb_cdata;
903 ld = sc->wb_ldata;
904
905 for (i = 0; i < WB_RX_LIST_CNT; i++) {
5f700c02
JS
906 cd->wb_rx_chain[i].wb_ptr = &ld->wb_rx_list[i];
907 cd->wb_rx_chain[i].wb_buf = &ld->wb_rxbufs[i];
984263bc
MD
908 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
909 return(ENOBUFS);
5f700c02
JS
910 nexti = (WB_RX_LIST_CNT - 1) ? 0 : i + 1;
911 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[nexti];
912 ld->wb_rx_list[i].wb_next = vtophys(&ld->wb_rx_list[nexti]);
984263bc
MD
913 }
914
915 cd->wb_rx_head = &cd->wb_rx_chain[0];
916
917 return(0);
918}
919
5f700c02 920static void
1f36295c 921wb_bfree(void *arg)
984263bc 922{
984263bc
MD
923}
924
925/*
926 * Initialize an RX descriptor and attach an MBUF cluster.
927 */
5f700c02
JS
928static int
929wb_newbuf(struct wb_softc *sc, struct wb_chain_onefrag *c, struct mbuf *m)
984263bc 930{
5f700c02 931 struct mbuf *m_new = NULL;
984263bc
MD
932
933 if (m == NULL) {
74f1caca 934 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
935 if (m_new == NULL)
936 return(ENOBUFS);
937
938 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
b542cd49 939 m_new->m_flags |= M_EXT;
984263bc
MD
940 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
941 m_new->m_len = WB_BUFBYTES;
b542cd49
JS
942 m_new->m_ext.ext_free = wb_bfree;
943 m_new->m_ext.ext_ref = wb_bfree;
984263bc
MD
944 } else {
945 m_new = m;
946 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
947 m_new->m_data = m_new->m_ext.ext_buf;
948 }
949
5f700c02 950 m_adj(m_new, sizeof(uint64_t));
984263bc
MD
951
952 c->wb_mbuf = m_new;
953 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
954 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
955 c->wb_ptr->wb_status = WB_RXSTAT;
956
957 return(0);
958}
959
960/*
961 * A frame has been uploaded: pass the resulting mbuf chain up to
962 * the higher level protocols.
963 */
5f700c02
JS
964static void
965wb_rxeof(struct wb_softc *sc)
984263bc 966{
5f700c02
JS
967 struct ifnet *ifp = &sc->arpcom.ac_if;
968 struct mbuf *m, *m0;
969 struct wb_chain_onefrag *cur_rx;
970 int total_len = 0;
971 uint32_t rxstat;
984263bc 972
5f700c02
JS
973 for (;;) {
974 rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status;
975 if ((rxstat & WB_RXSTAT_OWN) == 0)
976 break;
984263bc
MD
977
978 cur_rx = sc->wb_cdata.wb_rx_head;
979 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
980
981 m = cur_rx->wb_mbuf;
982
983 if ((rxstat & WB_RXSTAT_MIIERR) ||
984 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
985 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
5f700c02
JS
986 (rxstat & WB_RXSTAT_LASTFRAG) == 0||
987 (rxstat & WB_RXSTAT_RXCMP) == 0) {
984263bc
MD
988 ifp->if_ierrors++;
989 wb_newbuf(sc, cur_rx, m);
5b73a04e
JS
990 if_printf(ifp, "receiver babbling: possible chip "
991 "bug, forcing reset\n");
984263bc
MD
992 wb_fixmedia(sc);
993 wb_reset(sc);
994 wb_init(sc);
995 return;
996 }
997
998 if (rxstat & WB_RXSTAT_RXERR) {
999 ifp->if_ierrors++;
1000 wb_newbuf(sc, cur_rx, m);
1001 break;
1002 }
1003
1004 /* No errors; receive the packet. */
1005 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1006
1007 /*
1008 * XXX The Winbond chip includes the CRC with every
1009 * received frame, and there's no way to turn this
1010 * behavior off (at least, I can't find anything in
1011 * the manual that explains how to do it) so we have
1012 * to trim off the CRC manually.
1013 */
1014 total_len -= ETHER_CRC_LEN;
1015
1016 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1017 total_len + ETHER_ALIGN, 0, ifp, NULL);
1018 wb_newbuf(sc, cur_rx, m);
1019 if (m0 == NULL) {
1020 ifp->if_ierrors++;
1021 break;
1022 }
1023 m_adj(m0, ETHER_ALIGN);
1024 m = m0;
1025
1026 ifp->if_ipackets++;
78195a76 1027 ifp->if_input(ifp, m);
984263bc
MD
1028 }
1029}
1030
5f700c02
JS
1031static void
1032wb_rxeoc(struct wb_softc *sc)
984263bc
MD
1033{
1034 wb_rxeof(sc);
1035
1036 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1037 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1038 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1039 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1040 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
984263bc
MD
1041}
1042
1043/*
1044 * A frame was downloaded to the chip. It's safe for us to clean up
1045 * the list buffers.
1046 */
5f700c02
JS
1047static void
1048wb_txeof(struct wb_softc *sc)
984263bc 1049{
5f700c02
JS
1050 struct ifnet *ifp = &sc->arpcom.ac_if;
1051 struct wb_chain *cur_tx;
984263bc
MD
1052
1053 /* Clear the timeout timer. */
1054 ifp->if_timer = 0;
1055
1056 if (sc->wb_cdata.wb_tx_head == NULL)
1057 return;
1058
1059 /*
1060 * Go through our tx list and free mbufs for those
1061 * frames that have been transmitted.
1062 */
1063 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
5f700c02 1064 uint32_t txstat;
984263bc
MD
1065
1066 cur_tx = sc->wb_cdata.wb_tx_head;
1067 txstat = WB_TXSTATUS(cur_tx);
1068
1069 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1070 break;
1071
1072 if (txstat & WB_TXSTAT_TXERR) {
1073 ifp->if_oerrors++;
1074 if (txstat & WB_TXSTAT_ABORT)
1075 ifp->if_collisions++;
1076 if (txstat & WB_TXSTAT_LATECOLL)
1077 ifp->if_collisions++;
1078 }
1079
1080 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1081
1082 ifp->if_opackets++;
1083 m_freem(cur_tx->wb_mbuf);
1084 cur_tx->wb_mbuf = NULL;
1085
1086 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1087 sc->wb_cdata.wb_tx_head = NULL;
1088 sc->wb_cdata.wb_tx_tail = NULL;
1089 break;
1090 }
1091
1092 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1093 }
984263bc
MD
1094}
1095
1096/*
1097 * TX 'end of channel' interrupt handler.
1098 */
5f700c02
JS
1099static void
1100wb_txeoc(struct wb_softc *sc)
984263bc 1101{
5f700c02 1102 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc
MD
1103
1104 ifp->if_timer = 0;
1105
1106 if (sc->wb_cdata.wb_tx_head == NULL) {
1107 ifp->if_flags &= ~IFF_OACTIVE;
1108 sc->wb_cdata.wb_tx_tail = NULL;
5f700c02
JS
1109 } else if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1110 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1111 ifp->if_timer = 5;
1112 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
984263bc 1113 }
984263bc
MD
1114}
1115
5f700c02
JS
1116static void
1117wb_intr(void *arg)
984263bc 1118{
5f700c02
JS
1119 struct wb_softc *sc = arg;
1120 struct ifnet *ifp = &sc->arpcom.ac_if;
1121 uint32_t status;
984263bc 1122
5f700c02 1123 if ((ifp->if_flags & IFF_UP) == 0)
984263bc
MD
1124 return;
1125
1126 /* Disable interrupts. */
1127 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1128
1129 for (;;) {
984263bc
MD
1130 status = CSR_READ_4(sc, WB_ISR);
1131 if (status)
1132 CSR_WRITE_4(sc, WB_ISR, status);
1133
1134 if ((status & WB_INTRS) == 0)
1135 break;
1136
1137 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1138 ifp->if_ierrors++;
1139 wb_reset(sc);
1140 if (status & WB_ISR_RX_ERR)
1141 wb_fixmedia(sc);
1142 wb_init(sc);
1143 continue;
1144 }
1145
1146 if (status & WB_ISR_RX_OK)
1147 wb_rxeof(sc);
1148
1149 if (status & WB_ISR_RX_IDLE)
1150 wb_rxeoc(sc);
1151
1152 if (status & WB_ISR_TX_OK)
1153 wb_txeof(sc);
1154
1155 if (status & WB_ISR_TX_NOBUF)
1156 wb_txeoc(sc);
1157
1158 if (status & WB_ISR_TX_IDLE) {
1159 wb_txeof(sc);
1160 if (sc->wb_cdata.wb_tx_head != NULL) {
1161 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1162 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1163 }
1164 }
1165
1166 if (status & WB_ISR_TX_UNDERRUN) {
1167 ifp->if_oerrors++;
1168 wb_txeof(sc);
1169 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1170 /* Jack up TX threshold */
1171 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1172 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1173 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1174 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1175 }
1176
1177 if (status & WB_ISR_BUS_ERR) {
1178 wb_reset(sc);
1179 wb_init(sc);
1180 }
984263bc
MD
1181 }
1182
1183 /* Re-enable interrupts. */
1184 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1185
5f700c02 1186 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1187 if_devstart(ifp);
984263bc
MD
1188}
1189
5f700c02
JS
1190static void
1191wb_tick(void *xsc)
984263bc 1192{
5f700c02 1193 struct wb_softc *sc = xsc;
78195a76 1194 struct ifnet *ifp = &sc->arpcom.ac_if;
5f700c02 1195 struct mii_data *mii = device_get_softc(sc->wb_miibus);
984263bc 1196
78195a76 1197 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1198 mii_tick(mii);
ef203de8 1199 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
78195a76 1200 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
1201}
1202
1203/*
1204 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1205 * pointers to the fragment pointers.
1206 */
5f700c02
JS
1207static int
1208wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head)
984263bc 1209{
5f700c02
JS
1210 struct wb_desc *f = NULL;
1211 struct mbuf *m;
1212 int frag, total_len;
984263bc
MD
1213
1214 /*
1215 * Start packing the mbufs in this chain into
1216 * the fragment pointers. Stop when we run out
1217 * of fragments or hit the end of the mbuf chain.
1218 */
984263bc
MD
1219 total_len = 0;
1220
1221 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1222 if (m->m_len != 0) {
1223 if (frag == WB_MAXFRAGS)
1224 break;
1225 total_len += m->m_len;
1226 f = &c->wb_ptr->wb_frag[frag];
1227 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1228 if (frag == 0) {
1229 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1230 f->wb_status = 0;
5f700c02 1231 } else {
984263bc 1232 f->wb_status = WB_TXSTAT_OWN;
5f700c02 1233 }
984263bc
MD
1234 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1235 f->wb_data = vtophys(mtod(m, vm_offset_t));
1236 frag++;
1237 }
1238 }
1239
1240 /*
1241 * Handle special case: we used up all 16 fragments,
1242 * but we have more mbufs left in the chain. Copy the
1243 * data into an mbuf cluster. Note that we don't
1244 * bother clearing the values in the other fragment
1245 * pointers/counters; it wouldn't gain us anything,
1246 * and would waste cycles.
1247 */
1248 if (m != NULL) {
5f700c02 1249 struct mbuf *m_new = NULL;
984263bc 1250
74f1caca 1251 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
984263bc
MD
1252 if (m_new == NULL)
1253 return(1);
1254 if (m_head->m_pkthdr.len > MHLEN) {
74f1caca 1255 MCLGET(m_new, MB_DONTWAIT);
5f700c02 1256 if ((m_new->m_flags & M_EXT) == 0) {
984263bc
MD
1257 m_freem(m_new);
1258 return(1);
1259 }
1260 }
5f700c02
JS
1261 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1262 mtod(m_new, caddr_t));
984263bc
MD
1263 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1264 m_freem(m_head);
1265 m_head = m_new;
1266 f = &c->wb_ptr->wb_frag[0];
1267 f->wb_status = 0;
1268 f->wb_data = vtophys(mtod(m_new, caddr_t));
1269 f->wb_ctl = total_len = m_new->m_len;
1270 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1271 frag = 1;
1272 }
1273
1274 if (total_len < WB_MIN_FRAMELEN) {
1275 f = &c->wb_ptr->wb_frag[frag];
1276 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1277 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1278 f->wb_ctl |= WB_TXCTL_TLINK;
1279 f->wb_status = WB_TXSTAT_OWN;
1280 frag++;
1281 }
1282
1283 c->wb_mbuf = m_head;
1284 c->wb_lastdesc = frag - 1;
1285 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1286 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1287
1288 return(0);
1289}
1290
1291/*
1292 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1293 * to the mbuf data regions directly in the transmit lists. We also save a
1294 * copy of the pointers since the transmit list fragment pointers are
1295 * physical addresses.
1296 */
5f700c02
JS
1297static void
1298wb_start(struct ifnet *ifp)
984263bc 1299{
5f700c02
JS
1300 struct wb_softc *sc = ifp->if_softc;
1301 struct mbuf *m_head = NULL;
1302 struct wb_chain *cur_tx = NULL, *start_tx;
984263bc
MD
1303
1304 /*
1305 * Check for an available queue slot. If there are none,
1306 * punt.
1307 */
1308 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1309 ifp->if_flags |= IFF_OACTIVE;
1310 return;
1311 }
1312
1313 start_tx = sc->wb_cdata.wb_tx_free;
1314
5f700c02 1315 while (sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
d2c71fa0 1316 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
1317 if (m_head == NULL)
1318 break;
1319
1320 /* Pick a descriptor off the free list. */
1321 cur_tx = sc->wb_cdata.wb_tx_free;
1322 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1323
1324 /* Pack the data into the descriptor. */
1325 wb_encap(sc, cur_tx, m_head);
1326
1327 if (cur_tx != start_tx)
1328 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1329
7600679e 1330 BPF_MTAP(ifp, cur_tx->wb_mbuf);
984263bc
MD
1331 }
1332
1333 /*
1334 * If there are no packets queued, bail.
1335 */
1336 if (cur_tx == NULL)
1337 return;
1338
1339 /*
1340 * Place the request for the upload interrupt
1341 * in the last descriptor in the chain. This way, if
1342 * we're chaining several packets at once, we'll only
1343 * get an interupt once for the whole chain rather than
1344 * once for each packet.
1345 */
1346 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1347 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1348 sc->wb_cdata.wb_tx_tail = cur_tx;
1349
1350 if (sc->wb_cdata.wb_tx_head == NULL) {
1351 sc->wb_cdata.wb_tx_head = start_tx;
1352 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1353 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1354 } else {
1355 /*
1356 * We need to distinguish between the case where
1357 * the own bit is clear because the chip cleared it
1358 * and where the own bit is clear because we haven't
1359 * set it yet. The magic value WB_UNSET is just some
1360 * ramdomly chosen number which doesn't have the own
1361 * bit set. When we actually transmit the frame, the
1362 * status word will have _only_ the own bit set, so
1363 * the txeoc handler will be able to tell if it needs
1364 * to initiate another transmission to flush out pending
1365 * frames.
1366 */
1367 WB_TXOWN(start_tx) = WB_UNSENT;
1368 }
1369
1370 /*
1371 * Set a timeout in case the chip goes out to lunch.
1372 */
1373 ifp->if_timer = 5;
984263bc
MD
1374}
1375
5f700c02
JS
1376static void
1377wb_init(void *xsc)
984263bc 1378{
5f700c02
JS
1379 struct wb_softc *sc = xsc;
1380 struct ifnet *ifp = &sc->arpcom.ac_if;
9228feed 1381 int i;
5f700c02 1382 struct mii_data *mii;
984263bc 1383
9228feed 1384 crit_enter();
984263bc
MD
1385
1386 mii = device_get_softc(sc->wb_miibus);
1387
1388 /*
1389 * Cancel pending I/O and free all RX/TX buffers.
1390 */
1391 wb_stop(sc);
1392 wb_reset(sc);
1393
1394 sc->wb_txthresh = WB_TXTHRESH_INIT;
1395
1396 /*
1397 * Set cache alignment and burst length.
1398 */
1399#ifdef foo
1400 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1401 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1402 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1403#endif
1404
5f700c02 1405 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE | WB_BUSCTL_ARBITRATION);
984263bc
MD
1406 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1407 switch(sc->wb_cachesize) {
1408 case 32:
1409 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1410 break;
1411 case 16:
1412 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1413 break;
1414 case 8:
1415 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1416 break;
1417 case 0:
1418 default:
1419 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1420 break;
1421 }
1422
1423 /* This doesn't tend to work too well at 100Mbps. */
1424 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1425
1426 /* Init our MAC address */
5f700c02 1427 for (i = 0; i < ETHER_ADDR_LEN; i++)
984263bc 1428 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
984263bc
MD
1429
1430 /* Init circular RX list. */
1431 if (wb_list_rx_init(sc) == ENOBUFS) {
5b73a04e
JS
1432 if_printf(ifp, "initialization failed: no "
1433 "memory for rx buffers\n");
984263bc 1434 wb_stop(sc);
9228feed 1435 crit_exit();
984263bc
MD
1436 return;
1437 }
1438
1439 /* Init TX descriptors. */
1440 wb_list_tx_init(sc);
1441
1442 /* If we want promiscuous mode, set the allframes bit. */
5f700c02 1443 if (ifp->if_flags & IFF_PROMISC)
984263bc 1444 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
5f700c02 1445 else
984263bc 1446 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
984263bc
MD
1447
1448 /*
1449 * Set capture broadcast bit to capture broadcast frames.
1450 */
5f700c02 1451 if (ifp->if_flags & IFF_BROADCAST)
984263bc 1452 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
5f700c02 1453 else
984263bc 1454 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
984263bc
MD
1455
1456 /*
1457 * Program the multicast filter, if necessary.
1458 */
1459 wb_setmulti(sc);
1460
1461 /*
1462 * Load the address of the RX list.
1463 */
1464 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1465 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1466
1467 /*
1468 * Enable interrupts.
1469 */
1470 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1471 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1472
1473 /* Enable receiver and transmitter. */
1474 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1475 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1476
1477 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1478 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1479 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1480
1481 mii_mediachg(mii);
1482
1483 ifp->if_flags |= IFF_RUNNING;
1484 ifp->if_flags &= ~IFF_OACTIVE;
1485
9228feed 1486 crit_exit();
984263bc 1487
ef203de8 1488 callout_reset(&sc->wb_stat_timer, hz, wb_tick, sc);
984263bc
MD
1489}
1490
1491/*
1492 * Set media options.
1493 */
5f700c02
JS
1494static int
1495wb_ifmedia_upd(struct ifnet *ifp)
984263bc 1496{
5f700c02 1497 struct wb_softc *sc = ifp->if_softc;
984263bc
MD
1498
1499 if (ifp->if_flags & IFF_UP)
1500 wb_init(sc);
1501
1502 return(0);
1503}
1504
1505/*
1506 * Report current media status.
1507 */
5f700c02
JS
1508static void
1509wb_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 1510{
5f700c02
JS
1511 struct wb_softc *sc = ifp->if_softc;
1512 struct mii_data *mii = device_get_softc(sc->wb_miibus);
984263bc
MD
1513
1514 mii_pollstat(mii);
1515 ifmr->ifm_active = mii->mii_media_active;
1516 ifmr->ifm_status = mii->mii_media_status;
984263bc
MD
1517}
1518
5f700c02
JS
1519static int
1520wb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc 1521{
5f700c02
JS
1522 struct wb_softc *sc = ifp->if_softc;
1523 struct mii_data *mii;
1524 struct ifreq *ifr = (struct ifreq *) data;
9228feed 1525 int error = 0;
984263bc 1526
9228feed 1527 crit_enter();
984263bc
MD
1528
1529 switch(command) {
984263bc 1530 case SIOCSIFFLAGS:
5f700c02 1531 if (ifp->if_flags & IFF_UP)
984263bc 1532 wb_init(sc);
5f700c02
JS
1533 else if (ifp->if_flags & IFF_RUNNING)
1534 wb_stop(sc);
984263bc
MD
1535 error = 0;
1536 break;
1537 case SIOCADDMULTI:
1538 case SIOCDELMULTI:
1539 wb_setmulti(sc);
1540 error = 0;
1541 break;
1542 case SIOCGIFMEDIA:
1543 case SIOCSIFMEDIA:
1544 mii = device_get_softc(sc->wb_miibus);
1545 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1546 break;
1547 default:
4cde4dd5 1548 error = ether_ioctl(ifp, command, data);
984263bc
MD
1549 break;
1550 }
1551
9228feed 1552 crit_exit();
984263bc
MD
1553
1554 return(error);
1555}
1556
5f700c02
JS
1557static void
1558wb_watchdog(struct ifnet *ifp)
984263bc 1559{
5f700c02 1560 struct wb_softc *sc = ifp->if_softc;
984263bc
MD
1561
1562 ifp->if_oerrors++;
5b73a04e 1563 if_printf(ifp, "watchdog timeout\n");
984263bc 1564#ifdef foo
5f700c02 1565 if ((wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) == 0)
5b73a04e 1566 if_printf(ifp, "no carrier - transceiver cable problem?\n");
984263bc
MD
1567#endif
1568 wb_stop(sc);
1569 wb_reset(sc);
1570 wb_init(sc);
1571
0536a950 1572 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 1573 if_devstart(ifp);
984263bc
MD
1574}
1575
1576/*
1577 * Stop the adapter and free any mbufs allocated to the
1578 * RX and TX lists.
1579 */
5f700c02
JS
1580static void
1581wb_stop(struct wb_softc *sc)
984263bc 1582{
5f700c02
JS
1583 struct ifnet *ifp = &sc->arpcom.ac_if;
1584 int i;
984263bc 1585
984263bc
MD
1586 ifp->if_timer = 0;
1587
ef203de8 1588 callout_stop(&sc->wb_stat_timer);
984263bc 1589
5f700c02 1590 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON | WB_NETCFG_TX_ON));
984263bc
MD
1591 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1592 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1593 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1594
1595 /*
1596 * Free data in the RX lists.
1597 */
1598 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1599 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1600 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1601 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1602 }
1603 }
5f700c02 1604 bzero(&sc->wb_ldata->wb_rx_list, sizeof(sc->wb_ldata->wb_rx_list));
984263bc
MD
1605
1606 /*
1607 * Free the TX list buffers.
1608 */
1609 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1610 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1611 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1612 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1613 }
1614 }
1615
5f700c02 1616 bzero(&sc->wb_ldata->wb_tx_list, sizeof(sc->wb_ldata->wb_tx_list));
984263bc
MD
1617
1618 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
984263bc
MD
1619}
1620
1621/*
1622 * Stop all chip I/O so that the kernel's probe routines don't
1623 * get confused by errant DMAs when rebooting.
1624 */
5f700c02
JS
1625static void
1626wb_shutdown(device_t dev)
984263bc 1627{
5f700c02 1628 struct wb_softc *sc = device_get_softc(dev);
78195a76 1629 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 1630
78195a76 1631 lwkt_serialize_enter(ifp->if_serializer);
984263bc 1632 wb_stop(sc);
78195a76 1633 lwkt_serialize_exit(ifp->if_serializer);
984263bc 1634}
78195a76 1635