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kernel - Major signal path adjustments to fix races, tsleep race fixes, +more
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
984263bc
MD		 1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
39 */
40
1f2de5d4
MD		 41#include "use_npx.h"
42#include "use_isa.h"
984263bc
MD		 43#include "opt_compat.h"
44#include "opt_cpu.h"
45#include "opt_ddb.h"
46#include "opt_directio.h"
47#include "opt_inet.h"
48#include "opt_ipx.h"
49#include "opt_maxmem.h"
50#include "opt_msgbuf.h"
51#include "opt_perfmon.h"
52#include "opt_swap.h"
984263bc
MD		 53#include "opt_userconfig.h"
54
55#include <sys/param.h>
56#include <sys/systm.h>
57#include <sys/sysproto.h>
58#include <sys/signalvar.h>
59#include <sys/kernel.h>
60#include <sys/linker.h>
61#include <sys/malloc.h>
62#include <sys/proc.h>
895c1f85 63#include <sys/priv.h>
984263bc
MD		 64#include <sys/buf.h>
65#include <sys/reboot.h>
984263bc
MD		 66#include <sys/mbuf.h>
67#include <sys/msgbuf.h>
68#include <sys/sysent.h>
69#include <sys/sysctl.h>
70#include <sys/vmmeter.h>
71#include <sys/bus.h>
a722be49 72#include <sys/upcall.h>
cb7f4ab1 73#include <sys/usched.h>
527fddf7 74#include <sys/reg.h>
984263bc
MD		 75
76#include <vm/vm.h>
77#include <vm/vm_param.h>
78#include <sys/lock.h>
79#include <vm/vm_kern.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_map.h>
83#include <vm/vm_pager.h>
84#include <vm/vm_extern.h>
85
4b5f931b 86#include <sys/thread2.h>
684a93c4 87#include <sys/mplock2.h>
320c681e 88#include <sys/mutex2.h>
4b5f931b 89
984263bc
MD		 90#include <sys/user.h>
91#include <sys/exec.h>
92#include <sys/cons.h>
93
94#include <ddb/ddb.h>
95
984263bc 96#include <machine/cpu.h>
984263bc
MD		 97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
984263bc
MD		 100#include <machine/md_var.h>
101#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 102#include <machine/globaldata.h> /* CPU_prvspace */
984263bc 103#include <machine/smp.h>
984263bc
MD		 104#ifdef PERFMON
105#include <machine/perfmon.h>
106#endif
107#include <machine/cputypes.h>
87cf6827 108#include <machine/intr_machdep.h>
984263bc
MD		 109
110#ifdef OLD_BUS_ARCH
21ce0dfa 111#include <bus/isa/isa_device.h>
984263bc 112#endif
87cf6827 113#include <machine_base/isa/isa_intr.h>
1f2de5d4 114#include <bus/isa/rtc.h>
984263bc
MD		 115#include <machine/vm86.h>
116#include <sys/random.h>
117#include <sys/ptrace.h>
118#include <machine/sigframe.h>
119
30c5f287 120#include <sys/machintr.h>
9284cddf 121#include <machine_base/icu/icu_abi.h>
7265a4fe 122#include <machine_base/icu/elcr_var.h>
1d6d7089 123#include <machine_base/apic/lapic.h>
ed4d621d 124#include <machine_base/apic/ioapic.h>
a3dd9120 125#include <machine_base/apic/ioapic_abi.h>
d904d4d9 126#include <machine/mptable.h>
30c5f287 127
ff1a75a1
MD		 128#define PHYSMAP_ENTRIES 10
129
d678dc17
MN		 130extern void init386(int first);
131extern void dblfault_handler(void);
984263bc
MD		 132
133extern void printcpuinfo(void); /* XXX header file */
134extern void finishidentcpu(void);
135extern void panicifcpuunsupported(void);
136extern void initializecpu(void);
137
d678dc17 138static void cpu_startup(void *);
d883128f
SZ		 139static void pic_finish(void *);
140static void cpu_finish(void *);
642a6e88 141#ifndef CPU_DISABLE_SSE
d678dc17
MN		 142static void set_fpregs_xmm(struct save87 *, struct savexmm *);
143static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
642a6e88 144#endif /* CPU_DISABLE_SSE */
984263bc
MD		 145#ifdef DIRECTIO
146extern void ffs_rawread_setup(void);
147#endif /* DIRECTIO */
8a8d5d85 148static void init_locks(void);
984263bc 149
7c006a9e 150SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
d883128f
SZ		 151SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
152SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
984263bc 153
984263bc
MD		 154int _udatasel, _ucodesel;
155u_int atdevbase;
c2751817
MD		 156#ifdef SMP
157int64_t tsc_offsets[MAXCPU];
158#else
159int64_t tsc_offsets[1];
160#endif
984263bc
MD		 161
162#if defined(SWTCH_OPTIM_STATS)
163extern int swtch_optim_stats;
164SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
165 CTLFLAG_RD, &swtch_optim_stats, 0, "");
166SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
167 CTLFLAG_RD, &tlb_flush_count, 0, "");
168#endif
169
39d69dae 170long physmem = 0;
984263bc 171
1876681a
SZ		 172u_long ebda_addr = 0;
173
1d903de5
SZ		 174int imcr_present = 0;
175
2abaa030 176int naps = 0; /* # of Applications processors */
320c681e 177struct mtx dt_lock; /* lock for GDT and LDT */
2abaa030 178
ed721f0f
SZ		 179u_int base_memory;
180
984263bc
MD		 181static int
182sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
183{
39d69dae
AH		 184 u_long pmem = ctob(physmem);
185
186 int error = sysctl_handle_long(oidp, &pmem, 0, req);
984263bc
MD		 187 return (error);
188}
189
39d69dae 190SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 191 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
984263bc
MD		 192
193static int
194sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
195{
196 int error = sysctl_handle_int(oidp, 0,
12e4aaff 197 ctob(physmem - vmstats.v_wire_count), req);
984263bc
MD		 198 return (error);
199}
200
201SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
202 0, 0, sysctl_hw_usermem, "IU", "");
203
204static int
205sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
206{
207 int error = sysctl_handle_int(oidp, 0,
208 i386_btop(avail_end - avail_start), req);
209 return (error);
210}
211
212SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
213 0, 0, sysctl_hw_availpages, "I", "");
214
1bda0d3d
MD		 215vm_paddr_t Maxmem;
216vm_paddr_t Realmem;
984263bc 217
ff1a75a1 218vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
b24cd69c
AH		 219vm_paddr_t dump_avail[PHYSMAP_ENTRIES*2+2];
220
984263bc
MD		 221
222static vm_offset_t buffer_sva, buffer_eva;
223vm_offset_t clean_sva, clean_eva;
224static vm_offset_t pager_sva, pager_eva;
225static struct trapframe proc0_tf;
226
227static void
f123d5a1 228cpu_startup(void *dummy)
984263bc 229{
c9faf524 230 caddr_t v;
984263bc 231 vm_size_t size = 0;
e4846942 232 vm_offset_t firstaddr;
984263bc 233
984263bc
MD		 234 /*
235 * Good {morning,afternoon,evening,night}.
236 */
26be20a0 237 kprintf("%s", version);
984263bc
MD		 238 startrtclock();
239 printcpuinfo();
240 panicifcpuunsupported();
241#ifdef PERFMON
242 perfmon_init();
243#endif
15dc6550 244 kprintf("real memory = %ju (%ju MB)\n",
1bda0d3d
MD		 245 (intmax_t)Realmem,
246 (intmax_t)Realmem / 1024 / 1024);
984263bc
MD		 247 /*
248 * Display any holes after the first chunk of extended memory.
249 */
250 if (bootverbose) {
251 int indx;
252
26be20a0 253 kprintf("Physical memory chunk(s):\n");
984263bc 254 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 255 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 256
26be20a0 257 kprintf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
984263bc
MD		 258 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
259 size1 / PAGE_SIZE);
260 }
261 }
262
263 /*
984263bc
MD		 264 * Allocate space for system data structures.
265 * The first available kernel virtual address is in "v".
266 * As pages of kernel virtual memory are allocated, "v" is incremented.
267 * As pages of memory are allocated and cleared,
268 * "firstaddr" is incremented.
269 * An index into the kernel page table corresponding to the
270 * virtual memory address maintained in "v" is kept in "mapaddr".
271 */
272
273 /*
274 * Make two passes. The first pass calculates how much memory is
275 * needed and allocates it. The second pass assigns virtual
276 * addresses to the various data structures.
277 */
278 firstaddr = 0;
279again:
280 v = (caddr_t)firstaddr;
281
282#define valloc(name, type, num) \
283 (name) = (type *)v; v = (caddr_t)((name)+(num))
284#define valloclim(name, type, num, lim) \
285 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
286
984263bc
MD		 287 /*
288 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
289 * For the first 64MB of ram nominally allocate sufficient buffers to
290 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
291 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
292 * the buffer cache we limit the eventual kva reservation to
293 * maxbcache bytes.
294 *
295 * factor represents the 1/4 x ram conversion.
296 */
297 if (nbuf == 0) {
298 int factor = 4 * BKVASIZE / 1024;
299 int kbytes = physmem * (PAGE_SIZE / 1024);
300
301 nbuf = 50;
302 if (kbytes > 4096)
303 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
304 if (kbytes > 65536)
305 nbuf += (kbytes - 65536) * 2 / (factor * 5);
306 if (maxbcache && nbuf > maxbcache / BKVASIZE)
307 nbuf = maxbcache / BKVASIZE;
308 }
309
310 /*
311 * Do not allow the buffer_map to be more then 1/2 the size of the
312 * kernel_map.
313 */
e4846942
MD		 314 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
315 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
26be20a0 316 kprintf("Warning: nbufs capped at %d\n", nbuf);
984263bc
MD		 317 }
318
948209ce
MD		 319 /* limit to 128 on i386 */
320 nswbuf = max(min(nbuf/4, 128), 16);
984263bc
MD		 321#ifdef NSWBUF_MIN
322 if (nswbuf < NSWBUF_MIN)
323 nswbuf = NSWBUF_MIN;
324#endif
325#ifdef DIRECTIO
326 ffs_rawread_setup();
327#endif
328
329 valloc(swbuf, struct buf, nswbuf);
330 valloc(buf, struct buf, nbuf);
984263bc
MD		 331
332 /*
333 * End of first pass, size has been calculated so allocate memory
334 */
335 if (firstaddr == 0) {
336 size = (vm_size_t)(v - firstaddr);
e4846942 337 firstaddr = kmem_alloc(&kernel_map, round_page(size));
984263bc
MD		 338 if (firstaddr == 0)
339 panic("startup: no room for tables");
340 goto again;
341 }
342
343 /*
344 * End of second pass, addresses have been assigned
345 */
346 if ((vm_size_t)(v - firstaddr) != size)
347 panic("startup: table size inconsistency");
348
e4846942
MD		 349 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
350 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
351 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
352 (nbuf*BKVASIZE));
353 buffer_map.system_map = 1;
354 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
355 (nswbuf*MAXPHYS) + pager_map_size);
356 pager_map.system_map = 1;
984263bc 357
984263bc
MD		 358#if defined(USERCONFIG)
359 userconfig();
360 cninit(); /* the preferred console may have changed */
361#endif
362
15dc6550 363 kprintf("avail memory = %ju (%ju MB)\n",
f9ab53b8 364 (intmax_t)ptoa(vmstats.v_free_count),
15dc6550 365 (intmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
984263bc
MD		 366
367 /*
368 * Set up buffers, so they can be used to read disk labels.
369 */
370 bufinit();
371 vm_pager_bufferinit();
d883128f
SZ		 372}
373
374static void
375cpu_finish(void *dummy __unused)
376{
377 cpu_setregs();
378}
379
380static void
381pic_finish(void *dummy __unused)
382{
383 /* Log ELCR information */
384 elcr_dump();
be1519b3 385
d904d4d9
SZ		 386 /* Log MPTABLE information */
387 mptable_pci_int_dump();
388
be1519b3
SZ		 389 /* Finalize PIC */
390 MachIntrABI.finalize();
984263bc
MD		 391}
392
984263bc
MD		 393/*
394 * Send an interrupt to process.
395 *
396 * Stack is set up to allow sigcode stored
397 * at top to call routine, followed by kcall
398 * to sigreturn routine below. After sigreturn
399 * resets the signal mask, the stack, and the
400 * frame pointer, it returns to the user
401 * specified pc, psl.
402 */
984263bc 403void
f123d5a1 404sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
984263bc 405{
065b709a
SS		 406 struct lwp *lp = curthread->td_lwp;
407 struct proc *p = lp->lwp_proc;
984263bc
MD		 408 struct trapframe *regs;
409 struct sigacts *psp = p->p_sigacts;
410 struct sigframe sf, *sfp;
411 int oonstack;
412
065b709a
SS		 413 regs = lp->lwp_md.md_regs;
414 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
984263bc
MD		 415
416 /* save user context */
417 bzero(&sf, sizeof(struct sigframe));
418 sf.sf_uc.uc_sigmask = *mask;
065b709a 419 sf.sf_uc.uc_stack = lp->lwp_sigstk;
984263bc 420 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
4e7c41c5 421 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_gs, sizeof(struct trapframe));
984263bc 422
ce3d8c4d
MD		 423 /* make the size of the saved context visible to userland */
424 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
425
984263bc 426 /* Allocate and validate space for the signal handler context. */
4643740a 427 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
984263bc 428 SIGISMEMBER(psp->ps_sigonstack, sig)) {
065b709a
SS		 429 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
430 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
431 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
4e7c41c5 432 } else {
984263bc 433 sfp = (struct sigframe *)regs->tf_esp - 1;
4e7c41c5 434 }
984263bc
MD		 435
436 /* Translate the signal is appropriate */
437 if (p->p_sysent->sv_sigtbl) {
438 if (sig <= p->p_sysent->sv_sigsize)
439 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
440 }
441
442 /* Build the argument list for the signal handler. */
443 sf.sf_signum = sig;
444 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 445 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
984263bc
MD		 446 /* Signal handler installed with SA_SIGINFO. */
447 sf.sf_siginfo = (register_t)&sfp->sf_si;
448 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
449
450 /* fill siginfo structure */
451 sf.sf_si.si_signo = sig;
452 sf.sf_si.si_code = code;
453 sf.sf_si.si_addr = (void*)regs->tf_err;
454 }
455 else {
456 /* Old FreeBSD-style arguments. */
457 sf.sf_siginfo = code;
458 sf.sf_addr = regs->tf_err;
459 sf.sf_ahu.sf_handler = catcher;
460 }
461
462 /*
463 * If we're a vm86 process, we want to save the segment registers.
464 * We also change eflags to be our emulated eflags, not the actual
465 * eflags.
466 */
467 if (regs->tf_eflags & PSL_VM) {
468 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 469 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD		 470
471 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
472 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
473 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
474 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
475
476 if (vm86->vm86_has_vme == 0)
477 sf.sf_uc.uc_mcontext.mc_eflags =
478 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
479 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
480
481 /*
482 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
483 * syscalls made by the signal handler. This just avoids
484 * wasting time for our lazy fixup of such faults. PSL_NT
485 * does nothing in vm86 mode, but vm86 programs can set it
486 * almost legitimately in probes for old cpu types.
487 */
488 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
489 }
490
491 /*
1b251f0a
MD		 492 * Save the FPU state and reinit the FP unit
493 */
494 npxpush(&sf.sf_uc.uc_mcontext);
495
496 /*
984263bc
MD		 497 * Copy the sigframe out to the user's stack.
498 */
499 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
500 /*
501 * Something is wrong with the stack pointer.
502 * ...Kill the process.
503 */
b276424c 504 sigexit(lp, SIGILL);
984263bc
MD		 505 }
506
507 regs->tf_esp = (int)sfp;
508 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
8688c24a
AE		 509
510 /*
511 * i386 abi specifies that the direction flag must be cleared
512 * on function entry
513 */
514 regs->tf_eflags &= ~(PSL_T|PSL_D);
515
984263bc
MD		 516 regs->tf_cs = _ucodesel;
517 regs->tf_ds = _udatasel;
518 regs->tf_es = _udatasel;
dd4ad62d
MD		 519
520 /*
521 * Allow the signal handler to inherit %fs in addition to %gs as
4e7c41c5
MD		 522 * the userland program might be using both.
523 *
524 * However, if a T_PROTFLT occured the segment registers could be
525 * totally broken. They must be reset in order to be able to
526 * return to userland.
dd4ad62d 527 */
4e7c41c5
MD		 528 if (regs->tf_trapno == T_PROTFLT) {
529 regs->tf_fs = _udatasel;
530 regs->tf_gs = _udatasel;
531 }
984263bc
MD		 532 regs->tf_ss = _udatasel;
533}
534
535/*
4a22e893 536 * Sanitize the trapframe for a virtual kernel passing control to a custom
4e7c41c5
MD		 537 * VM context. Remove any items that would otherwise create a privilage
538 * issue.
4a22e893 539 *
4e7c41c5
MD		 540 * XXX at the moment we allow userland to set the resume flag. Is this a
541 * bad idea?
4a22e893
MD		 542 */
543int
544cpu_sanitize_frame(struct trapframe *frame)
545{
546 frame->tf_cs = _ucodesel;
547 frame->tf_ds = _udatasel;
4e7c41c5
MD		 548 frame->tf_es = _udatasel; /* XXX allow userland this one too? */
549#if 0
4a22e893 550 frame->tf_fs = _udatasel;
4e7c41c5
MD		 551 frame->tf_gs = _udatasel;
552#endif
4a22e893 553 frame->tf_ss = _udatasel;
4e7c41c5 554 frame->tf_eflags &= (PSL_RF | PSL_USERCHANGE);
4a22e893
MD		 555 frame->tf_eflags |= PSL_RESERVED_DEFAULT | PSL_I;
556 return(0);
557}
558
4e7c41c5
MD		 559int
560cpu_sanitize_tls(struct savetls *tls)
561{
562 struct segment_descriptor *desc;
563 int i;
564
565 for (i = 0; i < NGTLS; ++i) {
566 desc = &tls->tls[i];
567 if (desc->sd_dpl == 0 && desc->sd_type == 0)
568 continue;
569 if (desc->sd_def32 == 0)
570 return(ENXIO);
571 if (desc->sd_type != SDT_MEMRWA)
572 return(ENXIO);
573 if (desc->sd_dpl != SEL_UPL)
574 return(ENXIO);
575 if (desc->sd_xx != 0 || desc->sd_p != 1)
576 return(ENXIO);
577 }
578 return(0);
579}
580
4a22e893 581/*
65957d54 582 * sigreturn(ucontext_t *sigcntxp)
41c20dac 583 *
984263bc
MD		 584 * System call to cleanup state after a signal
585 * has been taken. Reset signal mask and
586 * stack state from context left by sendsig (above).
587 * Return to previous pc and psl as specified by
588 * context left by sendsig. Check carefully to
589 * make sure that the user has not modified the
590 * state to gain improper privileges.
3919ced0
MD		 591 *
592 * MPSAFE
984263bc
MD		 593 */
594#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
595#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
596
597int
753fd850 598sys_sigreturn(struct sigreturn_args *uap)
984263bc 599{
065b709a 600 struct lwp *lp = curthread->td_lwp;
984263bc 601 struct trapframe *regs;
1b251f0a 602 ucontext_t uc;
984263bc 603 ucontext_t *ucp;
1b251f0a
MD		 604 int cs;
605 int eflags;
606 int error;
984263bc 607
1b251f0a
MD		 608 /*
609 * We have to copy the information into kernel space so userland
610 * can't modify it while we are sniffing it.
611 */
065b709a 612 regs = lp->lwp_md.md_regs;
1b251f0a
MD		 613 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
614 if (error)
615 return (error);
616 ucp = &uc;
984263bc
MD		 617 eflags = ucp->uc_mcontext.mc_eflags;
618
619 if (eflags & PSL_VM) {
620 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
621 struct vm86_kernel *vm86;
622
623 /*
624 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
625 * set up the vm86 area, and we can't enter vm86 mode.
626 */
065b709a 627 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 628 return (EINVAL);
065b709a 629 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
984263bc
MD		 630 if (vm86->vm86_inited == 0)
631 return (EINVAL);
632
633 /* go back to user mode if both flags are set */
634 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
08f2f1bb 635 trapsignal(lp, SIGBUS, 0);
984263bc
MD		 636
637 if (vm86->vm86_has_vme) {
638 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
639 (eflags & VME_USERCHANGE) | PSL_VM;
640 } else {
641 vm86->vm86_eflags = eflags; /* save VIF, VIP */
e2742650
MD		 642 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
643 (eflags & VM_USERCHANGE) | PSL_VM;
984263bc 644 }
4e7c41c5 645 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
984263bc
MD		 646 tf->tf_eflags = eflags;
647 tf->tf_vm86_ds = tf->tf_ds;
648 tf->tf_vm86_es = tf->tf_es;
649 tf->tf_vm86_fs = tf->tf_fs;
4e7c41c5 650 tf->tf_vm86_gs = tf->tf_gs;
984263bc
MD		 651 tf->tf_ds = _udatasel;
652 tf->tf_es = _udatasel;
4e7c41c5 653#if 0
984263bc 654 tf->tf_fs = _udatasel;
4e7c41c5
MD		 655 tf->tf_gs = _udatasel;
656#endif
984263bc
MD		 657 } else {
658 /*
659 * Don't allow users to change privileged or reserved flags.
660 */
661 /*
662 * XXX do allow users to change the privileged flag PSL_RF.
663 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
664 * should sometimes set it there too. tf_eflags is kept in
665 * the signal context during signal handling and there is no
666 * other place to remember it, so the PSL_RF bit may be
667 * corrupted by the signal handler without us knowing.
668 * Corruption of the PSL_RF bit at worst causes one more or
669 * one less debugger trap, so allowing it is fairly harmless.
670 */
671 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
26be20a0 672 kprintf("sigreturn: eflags = 0x%x\n", eflags);
984263bc
MD		 673 return(EINVAL);
674 }
675
676 /*
677 * Don't allow users to load a valid privileged %cs. Let the
678 * hardware check for invalid selectors, excess privilege in
679 * other selectors, invalid %eip's and invalid %esp's.
680 */
681 cs = ucp->uc_mcontext.mc_cs;
682 if (!CS_SECURE(cs)) {
26be20a0 683 kprintf("sigreturn: cs = 0x%x\n", cs);
08f2f1bb 684 trapsignal(lp, SIGBUS, T_PROTFLT);
984263bc
MD		 685 return(EINVAL);
686 }
4e7c41c5 687 bcopy(&ucp->uc_mcontext.mc_gs, regs, sizeof(struct trapframe));
984263bc
MD		 688 }
689
4b486183 690 /*
1b251f0a
MD		 691 * Restore the FPU state from the frame
692 */
3919ced0 693 crit_enter();
1b251f0a
MD		 694 npxpop(&ucp->uc_mcontext);
695
984263bc 696 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 697 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 698 else
065b709a 699 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 700
065b709a
SS		 701 lp->lwp_sigmask = ucp->uc_sigmask;
702 SIG_CANTMASK(lp->lwp_sigmask);
3919ced0 703 crit_exit();
984263bc
MD		 704 return(EJUSTRETURN);
705}
706
707/*
a722be49
MD		 708 * Stack frame on entry to function. %eax will contain the function vector,
709 * %ecx will contain the function data. flags, ecx, and eax will have
710 * already been pushed on the stack.
711 */
712struct upc_frame {
713 register_t eax;
714 register_t ecx;
0a455ac5 715 register_t edx;
a722be49
MD		 716 register_t flags;
717 register_t oldip;
718};
719
720void
721sendupcall(struct vmupcall *vu, int morepending)
722{
065b709a 723 struct lwp *lp = curthread->td_lwp;
a722be49
MD		 724 struct trapframe *regs;
725 struct upcall upcall;
726 struct upc_frame upc_frame;
6e58b5df 727 int crit_count = 0;
a722be49
MD		 728
729 /*
69c61fbe
MD		 730 * If we are a virtual kernel running an emulated user process
731 * context, switch back to the virtual kernel context before
732 * trying to post the signal.
733 */
39005e16 734 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
69c61fbe 735 lp->lwp_md.md_regs->tf_trapno = 0;
287ebb09 736 vkernel_trap(lp, lp->lwp_md.md_regs);
69c61fbe
MD		 737 }
738
739 /*
a722be49
MD		 740 * Get the upcall data structure
741 */
065b709a 742 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
6e58b5df
MD		 743 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
744 ) {
a722be49 745 vu->vu_pending = 0;
26be20a0 746 kprintf("bad upcall address\n");
a722be49
MD		 747 return;
748 }
749
750 /*
751 * If the data structure is already marked pending or has a critical
752 * section count, mark the data structure as pending and return
753 * without doing an upcall. vu_pending is left set.
754 */
6e58b5df
MD		 755 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
756 if (upcall.upc_pending < vu->vu_pending) {
757 upcall.upc_pending = vu->vu_pending;
065b709a 758 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 759 sizeof(upcall.upc_pending));
a722be49
MD		 760 }
761 return;
762 }
763
764 /*
765 * We can run this upcall now, clear vu_pending.
766 *
767 * Bump our critical section count and set or clear the
768 * user pending flag depending on whether more upcalls are
769 * pending. The user will be responsible for calling
770 * upc_dispatch(-1) to process remaining upcalls.
771 */
772 vu->vu_pending = 0;
6e58b5df 773 upcall.upc_pending = morepending;
f9235b6d 774 ++crit_count;
065b709a 775 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df
MD		 776 sizeof(upcall.upc_pending));
777 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
778 sizeof(int));
a722be49
MD		 779
780 /*
781 * Construct a stack frame and issue the upcall
782 */
065b709a 783 regs = lp->lwp_md.md_regs;
a722be49
MD		 784 upc_frame.eax = regs->tf_eax;
785 upc_frame.ecx = regs->tf_ecx;
0a455ac5 786 upc_frame.edx = regs->tf_edx;
a722be49
MD		 787 upc_frame.flags = regs->tf_eflags;
788 upc_frame.oldip = regs->tf_eip;
789 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
790 sizeof(upc_frame)) != 0) {
26be20a0 791 kprintf("bad stack on upcall\n");
a722be49
MD		 792 } else {
793 regs->tf_eax = (register_t)vu->vu_func;
794 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 795 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD		 796 regs->tf_eip = (register_t)vu->vu_ctx;
797 regs->tf_esp -= sizeof(upc_frame);
798 }
799}
800
801/*
802 * fetchupcall occurs in the context of a system call, which means that
0a455ac5
MD		 803 * we have to return EJUSTRETURN in order to prevent eax and edx from
804 * being overwritten by the syscall return value.
a722be49
MD		 805 *
806 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
807 * and the function pointer in %eax.
808 */
809int
d678dc17 810fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
a722be49
MD		 811{
812 struct upc_frame upc_frame;
065b709a 813 struct lwp *lp = curthread->td_lwp;
a722be49
MD		 814 struct trapframe *regs;
815 int error;
6e58b5df
MD		 816 struct upcall upcall;
817 int crit_count;
a722be49 818
065b709a 819 regs = lp->lwp_md.md_regs;
a722be49 820
065b709a 821 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
a722be49
MD		 822 if (error == 0) {
823 if (vu) {
824 /*
825 * This jumps us to the next ready context.
826 */
827 vu->vu_pending = 0;
065b709a 828 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
6e58b5df
MD		 829 crit_count = 0;
830 if (error == 0)
831 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 832 ++crit_count;
a722be49 833 if (error == 0)
6e58b5df 834 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
a722be49
MD		 835 regs->tf_eax = (register_t)vu->vu_func;
836 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 837 regs->tf_edx = (register_t)lp->lwp_upcall;
a722be49
MD		 838 regs->tf_eip = (register_t)vu->vu_ctx;
839 regs->tf_esp = (register_t)rsp;
840 } else {
841 /*
842 * This returns us to the originally interrupted code.
843 */
844 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
845 regs->tf_eax = upc_frame.eax;
846 regs->tf_ecx = upc_frame.ecx;
0a455ac5 847 regs->tf_edx = upc_frame.edx;
6e58b5df
MD		 848 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
849 (upc_frame.flags & PSL_USERCHANGE);
a722be49
MD		 850 regs->tf_eip = upc_frame.oldip;
851 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
852 }
853 }
854 if (error == 0)
855 error = EJUSTRETURN;
856 return(error);
857}
858
859/*
984263bc
MD		 860 * Machine dependent boot() routine
861 *
862 * I haven't seen anything to put here yet
863 * Possibly some stuff might be grafted back here from boot()
864 */
865void
866cpu_boot(int howto)
867{
868}
869
870/*
871 * Shutdown the CPU as much as possible
872 */
873void
874cpu_halt(void)
875{
876 for (;;)
1184892f 877 __asm__ __volatile("hlt");
984263bc
MD		 878}
879
880/*
8ad65e08
MD		 881 * cpu_idle() represents the idle LWKT. You cannot return from this function
882 * (unless you want to blow things up!). Instead we look for runnable threads
883 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 884 *
26a0694b 885 * The main loop is entered with a critical section held, we must release
a2a5ad0d
MD		 886 * the critical section before doing anything else. lwkt_switch() will
887 * check for pending interrupts due to entering and exiting its own
888 * critical section.
26a0694b 889 *
7d4d6fdb 890 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
7d4d6fdb 891 *
46e562ce
MD		 892 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
893 * 1 to just use hlt and for debugging purposes.
984263bc 894 */
46e562ce 895static int cpu_idle_hlt = 2;
60f945af
MD		 896static int cpu_idle_hltcnt;
897static int cpu_idle_spincnt;
be71787b 898static u_int cpu_idle_repeat = 4;
984263bc
MD		 899SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
900 &cpu_idle_hlt, 0, "Idle loop HLT enable");
60f945af
MD		 901SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
902 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
903SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
904 &cpu_idle_spincnt, 0, "Idle loop entry spins");
be71787b
MD		 905SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
906 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
984263bc 907
f9d8cd12
MD		 908static void
909cpu_idle_default_hook(void)
910{
911 /*
912 * We must guarentee that hlt is exactly the instruction
913 * following the sti.
914 */
915 __asm __volatile("sti; hlt");
916}
917
918/* Other subsystems (e.g., ACPI) can hook this later. */
919void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
920
984263bc
MD		 921void
922cpu_idle(void)
923{
be71787b 924 globaldata_t gd = mycpu;
10662728 925 struct thread *td __debugvar = gd->gd_curthread;
be71787b
MD		 926 int reqflags;
927 int quick;
a2a5ad0d 928
26a0694b 929 crit_exit();
f9235b6d 930 KKASSERT(td->td_critcount == 0);
8ad65e08 931 for (;;) {
a2a5ad0d
MD		 932 /*
933 * See if there are any LWKTs ready to go.
934 */
8ad65e08 935 lwkt_switch();
a2a5ad0d
MD		 936
937 /*
be71787b
MD		 938 * When halting inside a cli we must check for reqflags
939 * races, particularly [re]schedule requests. Running
940 * splz() does the job.
941 *
942 * cpu_idle_hlt:
943 * 0 Never halt, just spin
944 *
945 * 1 Always use HLT (or MONITOR/MWAIT if avail).
946 * This typically eats more power than the
947 * ACPI halt.
948 *
949 * 2 Use HLT/MONITOR/MWAIT up to a point and then
950 * use the ACPI halt (default). This is a hybrid
951 * approach. See machdep.cpu_idle_repeat.
952 *
953 * 3 Always use the ACPI halt. This typically
954 * eats the least amount of power but the cpu
955 * will be slow waking up. Slows down e.g.
956 * compiles and other pipe/event oriented stuff.
957 *
958 *
959 * NOTE: Interrupts are enabled and we are not in a critical
960 * section.
961 *
962 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
963 * don't bother capping gd_idle_repeat, it is ok if
964 * it overflows.
a2a5ad0d 965 */
be71787b
MD		 966 ++gd->gd_idle_repeat;
967 reqflags = gd->gd_reqflags;
968 quick = (cpu_idle_hlt == 1) ||
969 (cpu_idle_hlt < 3 &&
970 gd->gd_idle_repeat < cpu_idle_repeat);
971
972 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
973 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
974 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
975 ++cpu_idle_hltcnt;
976 } else if (cpu_idle_hlt) {
a2a5ad0d
MD		 977 __asm __volatile("cli");
978 splz();
be71787b
MD		 979 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
980 if (quick)
7d4d6fdb
MD		 981 cpu_idle_default_hook();
982 else
983 cpu_idle_hook();
984 }
7d4d6fdb 985 __asm __volatile("sti");
60f945af 986 ++cpu_idle_hltcnt;
8ad65e08 987 } else {
60f945af 988 splz();
c5724852 989 __asm __volatile("sti");
60f945af 990 ++cpu_idle_spincnt;
8ad65e08 991 }
984263bc
MD		 992 }
993}
994
7ad8cc6c
SW		 995#ifdef SMP
996
984263bc 997/*
06615ccb
MD		 998 * This routine is called if a spinlock has been held through the
999 * exponential backoff period and is seriously contested. On a real cpu
1000 * we let it spin.
1001 */
1002void
1003cpu_spinlock_contested(void)
1004{
1005 cpu_pause();
1006}
1007
7ad8cc6c
SW		 1008#endif
1009
06615ccb 1010/*
984263bc
MD		 1011 * Clear registers on exec
1012 */
1013void
08f2f1bb 1014exec_setregs(u_long entry, u_long stack, u_long ps_strings)
984263bc 1015{
08f2f1bb
SS		 1016 struct thread *td = curthread;
1017 struct lwp *lp = td->td_lwp;
1018 struct pcb *pcb = td->td_pcb;
bb3cd951 1019 struct trapframe *regs = lp->lwp_md.md_regs;
984263bc 1020
984263bc
MD		 1021 /* was i386_user_cleanup() in NetBSD */
1022 user_ldt_free(pcb);
984263bc
MD		 1023
1024 bzero((char *)regs, sizeof(struct trapframe));
1025 regs->tf_eip = entry;
1026 regs->tf_esp = stack;
1027 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
1028 regs->tf_ss = _udatasel;
1029 regs->tf_ds = _udatasel;
1030 regs->tf_es = _udatasel;
1031 regs->tf_fs = _udatasel;
4e7c41c5 1032 regs->tf_gs = _udatasel;
984263bc
MD		 1033 regs->tf_cs = _ucodesel;
1034
1035 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
1036 regs->tf_ebx = ps_strings;
1037
1038 /*
1039 * Reset the hardware debug registers if they were in use.
1040 * They won't have any meaning for the newly exec'd process.
1041 */
1042 if (pcb->pcb_flags & PCB_DBREGS) {
1043 pcb->pcb_dr0 = 0;
1044 pcb->pcb_dr1 = 0;
1045 pcb->pcb_dr2 = 0;
1046 pcb->pcb_dr3 = 0;
1047 pcb->pcb_dr6 = 0;
1048 pcb->pcb_dr7 = 0;
08f2f1bb 1049 if (pcb == td->td_pcb) {
984263bc
MD		 1050 /*
1051 * Clear the debug registers on the running
1052 * CPU, otherwise they will end up affecting
1053 * the next process we switch to.
1054 */
1055 reset_dbregs();
1056 }
1057 pcb->pcb_flags &= ~PCB_DBREGS;
1058 }
1059
1060 /*
1061 * Initialize the math emulator (if any) for the current process.
1062 * Actually, just clear the bit that says that the emulator has
1063 * been initialized. Initialization is delayed until the process
1064 * traps to the emulator (if it is done at all) mainly because
1065 * emulators don't provide an entry point for initialization.
1066 */
08f2f1bb 1067 pcb->pcb_flags &= ~FP_SOFTFP;
984263bc
MD		 1068
1069 /*
a02705a9
MD		 1070 * note: do not set CR0_TS here. npxinit() must do it after clearing
1071 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
1072 * in npxdna().
984263bc 1073 */
a02705a9
MD		 1074 crit_enter();
1075 load_cr0(rcr0() | CR0_MP);
984263bc
MD		 1076
1077#if NNPX > 0
1078 /* Initialize the npx (if any) for the current process. */
1079 npxinit(__INITIAL_NPXCW__);
1080#endif
a02705a9 1081 crit_exit();
984263bc 1082
90b9818c
MD		 1083 /*
1084 * note: linux emulator needs edx to be 0x0 on entry, which is
c0510e9a
MD		 1085 * handled in execve simply by setting the 64 bit syscall
1086 * return value to 0.
90b9818c 1087 */
984263bc
MD		 1088}
1089
1090void
1091cpu_setregs(void)
1092{
1093 unsigned int cr0;
1094
1095 cr0 = rcr0();
1096 cr0 |= CR0_NE; /* Done by npxinit() */
1097 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
4db955e1 1098 cr0 |= CR0_WP | CR0_AM;
984263bc
MD		 1099 load_cr0(cr0);
1100 load_gs(_udatasel);
1101}
1102
1103static int
1104sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1105{
1106 int error;
1107 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1108 req);
1109 if (!error && req->newptr)
1110 resettodr();
1111 return (error);
1112}
1113
1114SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1115 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1116
1117SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1118 CTLFLAG_RW, &disable_rtc_set, 0, "");
1119
1120SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1121 CTLFLAG_RD, &bootinfo, bootinfo, "");
1122
1123SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1124 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1125
b13267a5 1126extern u_long bootdev; /* not a cdev_t - encoding is different */
984263bc 1127SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
b13267a5 1128 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
984263bc
MD		 1129
1130/*
1131 * Initialize 386 and configure to run kernel
1132 */
1133
1134/*
1135 * Initialize segments & interrupt table
1136 */
1137
1138int _default_ldt;
1139union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1140static struct gate_descriptor idt0[NIDT];
1141struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1142union descriptor ldt[NLDT]; /* local descriptor table */
17a9f566
MD		 1143
1144/* table descriptors - used to load tables by cpu */
984263bc 1145struct region_descriptor r_gdt, r_idt;
984263bc 1146
984263bc
MD		 1147#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1148extern int has_f00f_bug;
1149#endif
1150
1151static struct i386tss dblfault_tss;
1152static char dblfault_stack[PAGE_SIZE];
1153
1154extern struct user *proc0paddr;
1155
1156
1157/* software prototypes -- in more palatable form */
1158struct soft_segment_descriptor gdt_segs[] = {
1159/* GNULL_SEL 0 Null Descriptor */
1160{ 0x0, /* segment base address */
1161 0x0, /* length */
1162 0, /* segment type */
1163 0, /* segment descriptor priority level */
1164 0, /* segment descriptor present */
1165 0, 0,
1166 0, /* default 32 vs 16 bit size */
1167 0 /* limit granularity (byte/page units)*/ },
1168/* GCODE_SEL 1 Code Descriptor for kernel */
1169{ 0x0, /* segment base address */
1170 0xfffff, /* length - all address space */
1171 SDT_MEMERA, /* segment type */
1172 0, /* segment descriptor priority level */
1173 1, /* segment descriptor present */
1174 0, 0,
1175 1, /* default 32 vs 16 bit size */
1176 1 /* limit granularity (byte/page units)*/ },
1177/* GDATA_SEL 2 Data Descriptor for kernel */
1178{ 0x0, /* segment base address */
1179 0xfffff, /* length - all address space */
1180 SDT_MEMRWA, /* segment type */
1181 0, /* segment descriptor priority level */
1182 1, /* segment descriptor present */
1183 0, 0,
1184 1, /* default 32 vs 16 bit size */
1185 1 /* limit granularity (byte/page units)*/ },
1186/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1187{ 0x0, /* segment base address */
1188 0xfffff, /* length - all address space */
1189 SDT_MEMRWA, /* segment type */
1190 0, /* segment descriptor priority level */
1191 1, /* segment descriptor present */
1192 0, 0,
1193 1, /* default 32 vs 16 bit size */
1194 1 /* limit granularity (byte/page units)*/ },
1195/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1196{
1197 0x0, /* segment base address */
1198 sizeof(struct i386tss)-1,/* length - all address space */
1199 SDT_SYS386TSS, /* segment type */
1200 0, /* segment descriptor priority level */
1201 1, /* segment descriptor present */
1202 0, 0,
1203 0, /* unused - default 32 vs 16 bit size */
1204 0 /* limit granularity (byte/page units)*/ },
1205/* GLDT_SEL 5 LDT Descriptor */
1206{ (int) ldt, /* segment base address */
1207 sizeof(ldt)-1, /* length - all address space */
1208 SDT_SYSLDT, /* segment type */
1209 SEL_UPL, /* segment descriptor priority level */
1210 1, /* segment descriptor present */
1211 0, 0,
1212 0, /* unused - default 32 vs 16 bit size */
1213 0 /* limit granularity (byte/page units)*/ },
1214/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1215{ (int) ldt, /* segment base address */
1216 (512 * sizeof(union descriptor)-1), /* length */
1217 SDT_SYSLDT, /* segment type */
1218 0, /* segment descriptor priority level */
1219 1, /* segment descriptor present */
1220 0, 0,
1221 0, /* unused - default 32 vs 16 bit size */
1222 0 /* limit granularity (byte/page units)*/ },
1223/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1224{ 0x0, /* segment base address */
1225 0x0, /* length - all address space */
1226 0, /* segment type */
1227 0, /* segment descriptor priority level */
1228 0, /* segment descriptor present */
1229 0, 0,
1230 0, /* default 32 vs 16 bit size */
1231 0 /* limit granularity (byte/page units)*/ },
1232/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1233{ 0x400, /* segment base address */
1234 0xfffff, /* length */
1235 SDT_MEMRWA, /* segment type */
1236 0, /* segment descriptor priority level */
1237 1, /* segment descriptor present */
1238 0, 0,
1239 1, /* default 32 vs 16 bit size */
1240 1 /* limit granularity (byte/page units)*/ },
1241/* GPANIC_SEL 9 Panic Tss Descriptor */
1242{ (int) &dblfault_tss, /* segment base address */
1243 sizeof(struct i386tss)-1,/* length - all address space */
1244 SDT_SYS386TSS, /* segment type */
1245 0, /* segment descriptor priority level */
1246 1, /* segment descriptor present */
1247 0, 0,
1248 0, /* unused - default 32 vs 16 bit size */
1249 0 /* limit granularity (byte/page units)*/ },
1250/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1251{ 0, /* segment base address (overwritten) */
1252 0xfffff, /* length */
1253 SDT_MEMERA, /* segment type */
1254 0, /* segment descriptor priority level */
1255 1, /* segment descriptor present */
1256 0, 0,
1257 0, /* default 32 vs 16 bit size */
1258 1 /* limit granularity (byte/page units)*/ },
1259/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1260{ 0, /* segment base address (overwritten) */
1261 0xfffff, /* length */
1262 SDT_MEMERA, /* segment type */
1263 0, /* segment descriptor priority level */
1264 1, /* segment descriptor present */
1265 0, 0,
1266 0, /* default 32 vs 16 bit size */
1267 1 /* limit granularity (byte/page units)*/ },
1268/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1269{ 0, /* segment base address (overwritten) */
1270 0xfffff, /* length */
1271 SDT_MEMRWA, /* segment type */
1272 0, /* segment descriptor priority level */
1273 1, /* segment descriptor present */
1274 0, 0,
1275 1, /* default 32 vs 16 bit size */
1276 1 /* limit granularity (byte/page units)*/ },
1277/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1278{ 0, /* segment base address (overwritten) */
1279 0xfffff, /* length */
1280 SDT_MEMRWA, /* segment type */
1281 0, /* segment descriptor priority level */
1282 1, /* segment descriptor present */
1283 0, 0,
1284 0, /* default 32 vs 16 bit size */
1285 1 /* limit granularity (byte/page units)*/ },
1286/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1287{ 0, /* segment base address (overwritten) */
1288 0xfffff, /* length */
1289 SDT_MEMRWA, /* segment type */
1290 0, /* segment descriptor priority level */
1291 1, /* segment descriptor present */
1292 0, 0,
1293 0, /* default 32 vs 16 bit size */
1294 1 /* limit granularity (byte/page units)*/ },
806bf111
MD		 1295/* GTLS_START 15 TLS */
1296{ 0x0, /* segment base address */
1297 0x0, /* length */
1298 0, /* segment type */
1299 0, /* segment descriptor priority level */
1300 0, /* segment descriptor present */
1301 0, 0,
1302 0, /* default 32 vs 16 bit size */
1303 0 /* limit granularity (byte/page units)*/ },
1304/* GTLS_START+1 16 TLS */
1305{ 0x0, /* segment base address */
1306 0x0, /* length */
1307 0, /* segment type */
1308 0, /* segment descriptor priority level */
1309 0, /* segment descriptor present */
1310 0, 0,
1311 0, /* default 32 vs 16 bit size */
1312 0 /* limit granularity (byte/page units)*/ },
1313/* GTLS_END 17 TLS */
1314{ 0x0, /* segment base address */
1315 0x0, /* length */
1316 0, /* segment type */
1317 0, /* segment descriptor priority level */
1318 0, /* segment descriptor present */
1319 0, 0,
1320 0, /* default 32 vs 16 bit size */
1321 0 /* limit granularity (byte/page units)*/ },
efba76b4
SW		 1322/* GNDIS_SEL 18 NDIS Descriptor */
1323{ 0x0, /* segment base address */
1324 0x0, /* length */
1325 0, /* segment type */
1326 0, /* segment descriptor priority level */
1327 0, /* segment descriptor present */
1328 0, 0,
1329 0, /* default 32 vs 16 bit size */
1330 0 /* limit granularity (byte/page units)*/ },
984263bc
MD		 1331};
1332
1333static struct soft_segment_descriptor ldt_segs[] = {
1334 /* Null Descriptor - overwritten by call gate */
1335{ 0x0, /* segment base address */
1336 0x0, /* length - all address space */
1337 0, /* segment type */
1338 0, /* segment descriptor priority level */
1339 0, /* segment descriptor present */
1340 0, 0,
1341 0, /* default 32 vs 16 bit size */
1342 0 /* limit granularity (byte/page units)*/ },
1343 /* Null Descriptor - overwritten by call gate */
1344{ 0x0, /* segment base address */
1345 0x0, /* length - all address space */
1346 0, /* segment type */
1347 0, /* segment descriptor priority level */
1348 0, /* segment descriptor present */
1349 0, 0,
1350 0, /* default 32 vs 16 bit size */
1351 0 /* limit granularity (byte/page units)*/ },
1352 /* Null Descriptor - overwritten by call gate */
1353{ 0x0, /* segment base address */
1354 0x0, /* length - all address space */
1355 0, /* segment type */
1356 0, /* segment descriptor priority level */
1357 0, /* segment descriptor present */
1358 0, 0,
1359 0, /* default 32 vs 16 bit size */
1360 0 /* limit granularity (byte/page units)*/ },
1361 /* Code Descriptor for user */
1362{ 0x0, /* segment base address */
1363 0xfffff, /* length - all address space */
1364 SDT_MEMERA, /* segment type */
1365 SEL_UPL, /* segment descriptor priority level */
1366 1, /* segment descriptor present */
1367 0, 0,
1368 1, /* default 32 vs 16 bit size */
1369 1 /* limit granularity (byte/page units)*/ },
1370 /* Null Descriptor - overwritten by call gate */
1371{ 0x0, /* segment base address */
1372 0x0, /* length - all address space */
1373 0, /* segment type */
1374 0, /* segment descriptor priority level */
1375 0, /* segment descriptor present */
1376 0, 0,
1377 0, /* default 32 vs 16 bit size */
1378 0 /* limit granularity (byte/page units)*/ },
1379 /* Data Descriptor for user */
1380{ 0x0, /* segment base address */
1381 0xfffff, /* length - all address space */
1382 SDT_MEMRWA, /* segment type */
1383 SEL_UPL, /* segment descriptor priority level */
1384 1, /* segment descriptor present */
1385 0, 0,
1386 1, /* default 32 vs 16 bit size */
1387 1 /* limit granularity (byte/page units)*/ },
1388};
1389
1390void
f123d5a1 1391setidt(int idx, inthand_t *func, int typ, int dpl, int selec)
984263bc
MD		 1392{
1393 struct gate_descriptor *ip;
1394
1395 ip = idt + idx;
1396 ip->gd_looffset = (int)func;
1397 ip->gd_selector = selec;
1398 ip->gd_stkcpy = 0;
1399 ip->gd_xx = 0;
1400 ip->gd_type = typ;
1401 ip->gd_dpl = dpl;
1402 ip->gd_p = 1;
1403 ip->gd_hioffset = ((int)func)>>16 ;
1404}
1405
1406#define IDTVEC(name) __CONCAT(X,name)
1407
1408extern inthand_t
1409 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1410 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1411 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD		 1412 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1413 IDTVEC(xmm), IDTVEC(syscall),
1414 IDTVEC(rsvd0);
a64ba182 1415extern inthand_t
f9a13fc4 1416 IDTVEC(int0x80_syscall);
984263bc 1417
f7bc9806
MD		 1418#ifdef DEBUG_INTERRUPTS
1419extern inthand_t *Xrsvdary[256];
1420#endif
1421
984263bc 1422void
f123d5a1 1423sdtossd(struct segment_descriptor *sd, struct soft_segment_descriptor *ssd)
984263bc
MD		 1424{
1425 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1426 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1427 ssd->ssd_type = sd->sd_type;
1428 ssd->ssd_dpl = sd->sd_dpl;
1429 ssd->ssd_p = sd->sd_p;
1430 ssd->ssd_def32 = sd->sd_def32;
1431 ssd->ssd_gran = sd->sd_gran;
1432}
1433
984263bc
MD		 1434/*
1435 * Populate the (physmap) array with base/bound pairs describing the
1436 * available physical memory in the system, then test this memory and
1437 * build the phys_avail array describing the actually-available memory.
1438 *
1439 * If we cannot accurately determine the physical memory map, then use
1440 * value from the 0xE801 call, and failing that, the RTC.
1441 *
1442 * Total memory size may be set by the kernel environment variable
1443 * hw.physmem or the compile-time define MAXMEM.
1444 */
1445static void
1446getmemsize(int first)
1447{
b24cd69c 1448 int i, physmap_idx, pa_indx, da_indx;
984263bc
MD		 1449 int hasbrokenint12;
1450 u_int basemem, extmem;
1451 struct vm86frame vmf;
1452 struct vm86context vmc;
ff1a75a1
MD		 1453 vm_offset_t pa;
1454 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1455 pt_entry_t *pte;
555da584 1456 quad_t maxmem;
984263bc
MD		 1457 struct {
1458 u_int64_t base;
1459 u_int64_t length;
1460 u_int32_t type;
1461 } *smap;
28abdbbb 1462 quad_t dcons_addr, dcons_size;
984263bc 1463
984263bc
MD		 1464 bzero(&vmf, sizeof(struct vm86frame));
1465 bzero(physmap, sizeof(physmap));
1466 basemem = 0;
1467
1468 /*
1469 * Some newer BIOSes has broken INT 12H implementation which cause
1470 * kernel panic immediately. In this case, we need to scan SMAP
1471 * with INT 15:E820 first, then determine base memory size.
1472 */
2ed482dc
MN		 1473 hasbrokenint12 = 0;
1474 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
984263bc
MD		 1475 if (hasbrokenint12) {
1476 goto int15e820;
1477 }
1478
1479 /*
7febcc6e
MD		 1480 * Perform "base memory" related probes & setup. If we get a crazy
1481 * value give the bios some scribble space just in case.
984263bc
MD		 1482 */
1483 vm86_intcall(0x12, &vmf);
1484 basemem = vmf.vmf_ax;
1485 if (basemem > 640) {
26be20a0 1486 kprintf("Preposterous BIOS basemem of %uK, "
7febcc6e
MD		 1487 "truncating to < 640K\n", basemem);
1488 basemem = 636;
984263bc
MD		 1489 }
1490
1491 /*
1492 * XXX if biosbasemem is now < 640, there is a `hole'
1493 * between the end of base memory and the start of
1494 * ISA memory. The hole may be empty or it may
1495 * contain BIOS code or data. Map it read/write so
1496 * that the BIOS can write to it. (Memory from 0 to
1497 * the physical end of the kernel is mapped read-only
1498 * to begin with and then parts of it are remapped.
1499 * The parts that aren't remapped form holes that
1500 * remain read-only and are unused by the kernel.
1501 * The base memory area is below the physical end of
1502 * the kernel and right now forms a read-only hole.
1503 * The part of it from PAGE_SIZE to
1504 * (trunc_page(biosbasemem * 1024) - 1) will be
1505 * remapped and used by the kernel later.)
1506 *
1507 * This code is similar to the code used in
1508 * pmap_mapdev, but since no memory needs to be
1509 * allocated we simply change the mapping.
1510 */
1511 for (pa = trunc_page(basemem * 1024);
1512 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1513 pte = vtopte(pa + KERNBASE);
984263bc
MD		 1514 *pte = pa | PG_RW | PG_V;
1515 }
1516
1517 /*
1518 * if basemem != 640, map pages r/w into vm86 page table so
1519 * that the bios can scribble on it.
1520 */
b5b32410 1521 pte = vm86paddr;
984263bc
MD		 1522 for (i = basemem / 4; i < 160; i++)
1523 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1524
1525int15e820:
1526 /*
1527 * map page 1 R/W into the kernel page table so we can use it
1528 * as a buffer. The kernel will unmap this page later.
1529 */
b5b32410 1530 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD		 1531 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1532
1533 /*
1534 * get memory map with INT 15:E820
1535 */
1536#define SMAPSIZ sizeof(*smap)
1537#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1538
1539 vmc.npages = 0;
1540 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1541 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1542
1543 physmap_idx = 0;
1544 vmf.vmf_ebx = 0;
1545 do {
1546 vmf.vmf_eax = 0xE820;
1547 vmf.vmf_edx = SMAP_SIG;
1548 vmf.vmf_ecx = SMAPSIZ;
1549 i = vm86_datacall(0x15, &vmf, &vmc);
1550 if (i || vmf.vmf_eax != SMAP_SIG)
1551 break;
1552 if (boothowto & RB_VERBOSE)
26be20a0 1553 kprintf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
984263bc
MD		 1554 smap->type,
1555 *(u_int32_t *)((char *)&smap->base + 4),
1556 (u_int32_t)smap->base,
1557 *(u_int32_t *)((char *)&smap->length + 4),
1558 (u_int32_t)smap->length);
1559
1560 if (smap->type != 0x01)
1561 goto next_run;
1562
1563 if (smap->length == 0)
1564 goto next_run;
1565
1bda0d3d
MD		 1566 Realmem += smap->length;
1567
1568 if (smap->base >= 0xffffffffLLU) {
9c3db322 1569 kprintf("%ju MB of memory above 4GB ignored\n",
1bda0d3d 1570 (uintmax_t)(smap->length / 1024 / 1024));
984263bc
MD		 1571 goto next_run;
1572 }
1573
1574 for (i = 0; i <= physmap_idx; i += 2) {
1575 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD		 1576 if (boothowto & RB_VERBOSE) {
1577 kprintf("Overlapping or non-montonic "
1578 "memory region, ignoring "
1579 "second region\n");
1580 }
1581 Realmem -= smap->length;
984263bc
MD		 1582 goto next_run;
1583 }
1584 }
1585
1586 if (smap->base == physmap[physmap_idx + 1]) {
1587 physmap[physmap_idx + 1] += smap->length;
1588 goto next_run;
1589 }
1590
1591 physmap_idx += 2;
ff1a75a1 1592 if (physmap_idx == PHYSMAP_ENTRIES*2) {
1bda0d3d
MD		 1593 kprintf("Too many segments in the physical "
1594 "address map, giving up\n");
984263bc
MD		 1595 break;
1596 }
1597 physmap[physmap_idx] = smap->base;
1598 physmap[physmap_idx + 1] = smap->base + smap->length;
1599next_run:
6b08710e 1600 ; /* fix GCC3.x warning */
984263bc
MD		 1601 } while (vmf.vmf_ebx != 0);
1602
1603 /*
1604 * Perform "base memory" related probes & setup based on SMAP
1605 */
1606 if (basemem == 0) {
1607 for (i = 0; i <= physmap_idx; i += 2) {
1608 if (physmap[i] == 0x00000000) {
1609 basemem = physmap[i + 1] / 1024;
1610 break;
1611 }
1612 }
1613
1614 if (basemem == 0) {
1615 basemem = 640;
1616 }
1617
1618 if (basemem > 640) {
1bda0d3d
MD		 1619 kprintf("Preposterous BIOS basemem of %uK, "
1620 "truncating to 640K\n", basemem);
984263bc
MD		 1621 basemem = 640;
1622 }
1623
1624 for (pa = trunc_page(basemem * 1024);
1625 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1626 pte = vtopte(pa + KERNBASE);
984263bc
MD		 1627 *pte = pa | PG_RW | PG_V;
1628 }
1629
b5b32410 1630 pte = vm86paddr;
984263bc
MD		 1631 for (i = basemem / 4; i < 160; i++)
1632 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1633 }
1634
1635 if (physmap[1] != 0)
1636 goto physmap_done;
1637
1638 /*
1639 * If we failed above, try memory map with INT 15:E801
1640 */
1641 vmf.vmf_ax = 0xE801;
1642 if (vm86_intcall(0x15, &vmf) == 0) {
1643 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1644 } else {
1645#if 0
1646 vmf.vmf_ah = 0x88;
1647 vm86_intcall(0x15, &vmf);
1648 extmem = vmf.vmf_ax;
1649#else
1650 /*
1651 * Prefer the RTC value for extended memory.
1652 */
1653 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1654#endif
1655 }
1656
1657 /*
1658 * Special hack for chipsets that still remap the 384k hole when
1659 * there's 16MB of memory - this really confuses people that
1660 * are trying to use bus mastering ISA controllers with the
1661 * "16MB limit"; they only have 16MB, but the remapping puts
1662 * them beyond the limit.
1663 *
1664 * If extended memory is between 15-16MB (16-17MB phys address range),
1665 * chop it to 15MB.
1666 */
1667 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1668 extmem = 15 * 1024;
1669
1670 physmap[0] = 0;
1671 physmap[1] = basemem * 1024;
1672 physmap_idx = 2;
1673 physmap[physmap_idx] = 0x100000;
1674 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1675
1676physmap_done:
1677 /*
1678 * Now, physmap contains a map of physical memory.
1679 */
1680
ed721f0f 1681 base_memory = physmap[1];
984263bc 1682#ifdef SMP
17a9f566 1683 /* make hole for AP bootstrap code YYY */
ed721f0f 1684 physmap[1] = mp_bootaddress(base_memory);
7d676a89 1685#endif
984263bc 1686
1876681a
SZ		 1687 /* Save EBDA address, if any */
1688 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1689 ebda_addr <<= 4;
984263bc
MD		 1690
1691 /*
1692 * Maxmem isn't the "maximum memory", it's one larger than the
1693 * highest page of the physical address space. It should be
1694 * called something like "Maxphyspage". We may adjust this
1695 * based on ``hw.physmem'' and the results of the memory test.
1696 */
1697 Maxmem = atop(physmap[physmap_idx + 1]);
1698
1699#ifdef MAXMEM
1700 Maxmem = MAXMEM / 4;
1701#endif
1702
555da584
MD		 1703 if (kgetenv_quad("hw.physmem", &maxmem))
1704 Maxmem = atop(maxmem);
984263bc
MD		 1705
1706 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1707 (boothowto & RB_VERBOSE))
26be20a0 1708 kprintf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD		 1709
1710 /*
1711 * If Maxmem has been increased beyond what the system has detected,
1712 * extend the last memory segment to the new limit.
1713 */
1714 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1715 physmap[physmap_idx + 1] = ptoa(Maxmem);
1716
1717 /* call pmap initialization to make new kernel address space */
1718 pmap_bootstrap(first, 0);
1719
1720 /*
1721 * Size up each available chunk of physical memory.
1722 */
1723 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1724 pa_indx = 0;
b24cd69c 1725 da_indx = 1;
984263bc
MD		 1726 phys_avail[pa_indx++] = physmap[0];
1727 phys_avail[pa_indx] = physmap[0];
b24cd69c
AH		 1728 dump_avail[da_indx] = physmap[0];
1729
b5b32410 1730 pte = CMAP1;
984263bc
MD		 1731
1732 /*
28abdbbb
HS		 1733 * Get dcons buffer address
1734 */
bc01a404
MD		 1735 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1736 kgetenv_quad("dcons.size", &dcons_size) == 0)
28abdbbb
HS		 1737 dcons_addr = 0;
1738
1739 /*
984263bc
MD		 1740 * physmap is in bytes, so when converting to page boundaries,
1741 * round up the start address and round down the end address.
1742 */
1743 for (i = 0; i <= physmap_idx; i += 2) {
1744 vm_offset_t end;
1745
1746 end = ptoa(Maxmem);
1747 if (physmap[i + 1] < end)
1748 end = trunc_page(physmap[i + 1]);
1749 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
b24cd69c 1750 int tmp, page_bad, full;
984263bc
MD		 1751#if 0
1752 int *ptr = 0;
1753#else
1754 int *ptr = (int *)CADDR1;
1755#endif
b24cd69c 1756 full = FALSE;
984263bc
MD		 1757
1758 /*
1759 * block out kernel memory as not available.
1760 */
1761 if (pa >= 0x100000 && pa < first)
b24cd69c 1762 goto do_dump_avail;
984263bc 1763
28abdbbb
HS		 1764 /*
1765 * block out dcons buffer
1766 */
1767 if (dcons_addr > 0
1768 && pa >= trunc_page(dcons_addr)
1769 && pa < dcons_addr + dcons_size)
b24cd69c 1770 goto do_dump_avail;
28abdbbb 1771
984263bc
MD		 1772 page_bad = FALSE;
1773
1774 /*
1775 * map page into kernel: valid, read/write,non-cacheable
1776 */
1777 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1778 cpu_invltlb();
984263bc
MD		 1779
1780 tmp = *(int *)ptr;
1781 /*
1782 * Test for alternating 1's and 0's
1783 */
1784 *(volatile int *)ptr = 0xaaaaaaaa;
1785 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1786 page_bad = TRUE;
1787 }
1788 /*
1789 * Test for alternating 0's and 1's
1790 */
1791 *(volatile int *)ptr = 0x55555555;
1792 if (*(volatile int *)ptr != 0x55555555) {
1793 page_bad = TRUE;
1794 }
1795 /*
1796 * Test for all 1's
1797 */
1798 *(volatile int *)ptr = 0xffffffff;
1799 if (*(volatile int *)ptr != 0xffffffff) {
1800 page_bad = TRUE;
1801 }
1802 /*
1803 * Test for all 0's
1804 */
1805 *(volatile int *)ptr = 0x0;
1806 if (*(volatile int *)ptr != 0x0) {
1807 page_bad = TRUE;
1808 }
1809 /*
1810 * Restore original value.
1811 */
1812 *(int *)ptr = tmp;
1813
1814 /*
1815 * Adjust array of valid/good pages.
1816 */
1817 if (page_bad == TRUE) {
1818 continue;
1819 }
1820 /*
1821 * If this good page is a continuation of the
1822 * previous set of good pages, then just increase
1823 * the end pointer. Otherwise start a new chunk.
1824 * Note that "end" points one higher than end,
1825 * making the range >= start and < end.
1826 * If we're also doing a speculative memory
1827 * test and we at or past the end, bump up Maxmem
1828 * so that we keep going. The first bad page
1829 * will terminate the loop.
1830 */
1831 if (phys_avail[pa_indx] == pa) {
1832 phys_avail[pa_indx] += PAGE_SIZE;
1833 } else {
1834 pa_indx++;
ff1a75a1 1835 if (pa_indx >= PHYSMAP_ENTRIES*2) {
26be20a0 1836 kprintf("Too many holes in the physical address space, giving up\n");
984263bc 1837 pa_indx--;
b24cd69c
AH		 1838 full = TRUE;
1839 goto do_dump_avail;
984263bc
MD		 1840 }
1841 phys_avail[pa_indx++] = pa; /* start */
1842 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1843 }
1844 physmem++;
b24cd69c
AH		 1845do_dump_avail:
1846 if (dump_avail[da_indx] == pa) {
1847 dump_avail[da_indx] += PAGE_SIZE;
1848 } else {
1849 da_indx++;
1850 if (da_indx >= PHYSMAP_ENTRIES*2) {
1851 da_indx--;
1852 goto do_next;
1853 }
1854 dump_avail[da_indx++] = pa; /* start */
1855 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1856 }
1857do_next:
1858 if (full)
1859 break;
1860
984263bc
MD		 1861 }
1862 }
1863 *pte = 0;
0f7a3396 1864 cpu_invltlb();
984263bc
MD		 1865
1866 /*
1867 * XXX
1868 * The last chunk must contain at least one page plus the message
1869 * buffer to avoid complicating other code (message buffer address
1870 * calculation, etc.).
1871 */
1872 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1873 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1874 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1875 phys_avail[pa_indx--] = 0;
1876 phys_avail[pa_indx--] = 0;
1877 }
1878
1879 Maxmem = atop(phys_avail[pa_indx]);
1880
1881 /* Trim off space for the message buffer. */
1882 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1883
1884 avail_end = phys_avail[pa_indx];
1885}
1886
30c5f287
MN		 1887struct machintr_abi MachIntrABI;
1888
f7bc9806
MD		 1889/*
1890 * IDT VECTORS:
1891 * 0 Divide by zero
1892 * 1 Debug
1893 * 2 NMI
1894 * 3 BreakPoint
1895 * 4 OverFlow
1896 * 5 Bound-Range
1897 * 6 Invalid OpCode
1898 * 7 Device Not Available (x87)
1899 * 8 Double-Fault
1900 * 9 Coprocessor Segment overrun (unsupported, reserved)
1901 * 10 Invalid-TSS
1902 * 11 Segment not present
1903 * 12 Stack
1904 * 13 General Protection
1905 * 14 Page Fault
1906 * 15 Reserved
1907 * 16 x87 FP Exception pending
1908 * 17 Alignment Check
1909 * 18 Machine Check
1910 * 19 SIMD floating point
1911 * 20-31 reserved
1912 * 32-255 INTn/external sources
1913 */
984263bc 1914void
17a9f566 1915init386(int first)
984263bc
MD		 1916{
1917 struct gate_descriptor *gdp;
1918 int gsel_tss, metadata_missing, off, x;
85100692 1919 struct mdglobaldata *gd;
984263bc
MD		 1920
1921 /*
1922 * Prevent lowering of the ipl if we call tsleep() early.
1923 */
85100692 1924 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1925 bzero(gd, sizeof(*gd));
984263bc 1926
85100692 1927 gd->mi.gd_curthread = &thread0;
4e7c41c5 1928 thread0.td_gd = &gd->mi;
984263bc
MD		 1929
1930 atdevbase = ISA_HOLE_START + KERNBASE;
1931
1932 metadata_missing = 0;
1933 if (bootinfo.bi_modulep) {
1934 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1935 preload_bootstrap_relocate(KERNBASE);
1936 } else {
1937 metadata_missing = 1;
1938 }
1939 if (bootinfo.bi_envp)
1940 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1941
27af435a
SZ		 1942 if (boothowto & RB_VERBOSE)
1943 bootverbose++;
1944
c5cc06e3 1945 /*
10db3cc6 1946 * Default MachIntrABI to ICU
30c5f287
MN		 1947 */
1948 MachIntrABI = MachIntrABI_ICU;
1e7aaefa 1949
d745d2b8
SZ		 1950 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1951 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1d6d7089 1952 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
30c5f287
MN		 1953
1954 /*
b45759e1
MD		 1955 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1956 * and ncpus_fit_mask remain 0.
c5cc06e3 1957 */
4e8e646b 1958 ncpus = 1;
c5cc06e3 1959 ncpus2 = 1;
b45759e1 1960 ncpus_fit = 1;
984263bc
MD		 1961 /* Init basic tunables, hz etc */
1962 init_param1();
1963
1964 /*
1965 * make gdt memory segments, the code segment goes up to end of the
1966 * page with etext in it, the data segment goes to the end of
1967 * the address space
1968 */
1969 /*
1970 * XXX text protection is temporarily (?) disabled. The limit was
1971 * i386_btop(round_page(etext)) - 1.
1972 */
1973 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1974 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1975
984263bc
MD		 1976 gdt_segs[GPRIV_SEL].ssd_limit =
1977 atop(sizeof(struct privatespace) - 1);
8ad65e08 1978 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1979 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1980 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1981
85100692 1982 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1983
84b592ba
MD		 1984 /*
1985 * Note: on both UP and SMP curthread must be set non-NULL
1986 * early in the boot sequence because the system assumes
1987 * that 'curthread' is never NULL.
1988 */
984263bc
MD		 1989
1990 for (x = 0; x < NGDT; x++) {
1991#ifdef BDE_DEBUGGER
1992 /* avoid overwriting db entries with APM ones */
1993 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1994 continue;
1995#endif
1996 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1997 }
1998
1999 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2000 r_gdt.rd_base = (int) gdt;
2001 lgdt(&r_gdt);
2002
73e4f7b9
MD		 2003 mi_gdinit(&gd->mi, 0);
2004 cpu_gdinit(gd, 0);
6bf59cd2 2005 mi_proc0init(&gd->mi, proc0paddr);
e43a034f 2006 safepri = TDPRI_MAX;
73e4f7b9 2007
984263bc
MD		 2008 /* make ldt memory segments */
2009 /*
88181b08 2010 * XXX - VM_MAX_USER_ADDRESS is an end address, not a max. And it
984263bc
MD		 2011 * should be spelled ...MAX_USER...
2012 */
88181b08
MD		 2013 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
2014 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAX_USER_ADDRESS - 1);
984263bc
MD		 2015 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
2016 ssdtosd(&ldt_segs[x], &ldt[x].sd);
2017
2018 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
2019 lldt(_default_ldt);
17a9f566 2020 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD		 2021 /* spinlocks and the BGL */
2022 init_locks();
984263bc 2023
2f839e54
MD		 2024 /*
2025 * Setup the hardware exception table. Most exceptions use
2026 * SDT_SYS386TGT, known as a 'trap gate'. Trap gates leave
2027 * interrupts enabled. VM page faults use SDT_SYS386IGT, known as
2028 * an 'interrupt trap gate', which disables interrupts on entry,
2029 * in order to be able to poll the appropriate CRn register to
2030 * determine the fault address.
2031 */
f7bc9806
MD		 2032 for (x = 0; x < NIDT; x++) {
2033#ifdef DEBUG_INTERRUPTS
2034 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2035#else
2036 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2037#endif
2038 }
984263bc
MD		 2039 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2040 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2041 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2042 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2043 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2044 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2045 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2046 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2047 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
2048 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2049 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2050 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2051 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2052 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2053 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 2054 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD		 2055 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2056 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2057 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2058 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2059 setidt(0x80, &IDTVEC(int0x80_syscall),
2060 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
2061
2062 r_idt.rd_limit = sizeof(idt0) - 1;
2063 r_idt.rd_base = (int) idt;
2064 lidt(&r_idt);
2065
2066 /*
2067 * Initialize the console before we print anything out.
2068 */
2069 cninit();
2070
2071 if (metadata_missing)
26be20a0 2072 kprintf("WARNING: loader(8) metadata is missing!\n");
984263bc 2073
984263bc 2074#if NISA >0
e24dd6e0 2075 elcr_probe();
984263bc
MD		 2076 isa_defaultirq();
2077#endif
2078 rand_initialize();
2079
a3dd9120
SZ		 2080 /*
2081 * Initialize IRQ mapping
2082 *
2083 * NOTE:
2084 * SHOULD be after elcr_probe()
2085 */
2086 MachIntrABI_ICU.initmap();
2087#ifdef SMP
2088 MachIntrABI_IOAPIC.initmap();
2089#endif
2090
984263bc
MD		 2091#ifdef DDB
2092 kdb_init();
2093 if (boothowto & RB_KDB)
2094 Debugger("Boot flags requested debugger");
2095#endif
2096
2097 finishidentcpu(); /* Final stage of CPU initialization */
2098 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2099 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2100 initializecpu(); /* Initialize CPU registers */
2101
b7c628e4
MD		 2102 /*
2103 * make an initial tss so cpu can get interrupt stack on syscall!
2104 * The 16 bytes is to save room for a VM86 context.
2105 */
17a9f566
MD		 2106 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
2107 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 2108 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD		 2109 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
2110 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 2111 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD		 2112 ltr(gsel_tss);
2113
2114 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
2115 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
2116 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
2117 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
2118 dblfault_tss.tss_cr3 = (int)IdlePTD;
2119 dblfault_tss.tss_eip = (int) dblfault_handler;
2120 dblfault_tss.tss_eflags = PSL_KERNEL;
2121 dblfault_tss.tss_ds = dblfault_tss.tss_es =
2122 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
2123 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
2124 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
2125 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
2126
2127 vm86_initialize();
2128 getmemsize(first);
2129 init_param2(physmem);
2130
2131 /* now running on new page tables, configured,and u/iom is accessible */
2132
2133 /* Map the message buffer. */
2134 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2135 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2136
2137 msgbufinit(msgbufp, MSGBUF_SIZE);
2138
2139 /* make a call gate to reenter kernel with */
2140 gdp = &ldt[LSYS5CALLS_SEL].gd;
2141
2142 x = (int) &IDTVEC(syscall);
2143 gdp->gd_looffset = x++;
2144 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2145 gdp->gd_stkcpy = 1;
2146 gdp->gd_type = SDT_SYS386CGT;
2147 gdp->gd_dpl = SEL_UPL;
2148 gdp->gd_p = 1;
2149 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2150
2151 /* XXX does this work? */
2152 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2153 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2154
2155 /* transfer to user mode */
2156
2157 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2158 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2159
2160 /* setup proc 0's pcb */
b7c628e4
MD		 2161 thread0.td_pcb->pcb_flags = 0;
2162 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2163 thread0.td_pcb->pcb_ext = 0;
08f2f1bb 2164 lwp0.lwp_md.md_regs = &proc0_tf;
984263bc
MD		 2165}
2166
8ad65e08 2167/*
17a9f566
MD		 2168 * Initialize machine-dependant portions of the global data structure.
2169 * Note that the global data area and cpu0's idlestack in the private
2170 * data space were allocated in locore.
ef0fdad1
MD		 2171 *
2172 * Note: the idlethread's cpl is 0
73e4f7b9
MD		 2173 *
2174 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD		 2175 */
2176void
85100692 2177cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2178{
7d0bac62 2179 if (cpu)
a2a5ad0d 2180 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2181
f470d0c8
MD		 2182 lwkt_init_thread(&gd->mi.gd_idlethread,
2183 gd->mi.gd_prvspace->idlestack,
d3d32139 2184 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 2185 0, &gd->mi);
a2a5ad0d
MD		 2186 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2187 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2188 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2189 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD		 2190}
2191
0cd275af
MD		 2192int
2193is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2194{
2195 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2196 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2197 return (TRUE);
2198 }
2199 return (FALSE);
2200}
2201
12e4aaff
MD		 2202struct globaldata *
2203globaldata_find(int cpu)
2204{
2205 KKASSERT(cpu >= 0 && cpu < ncpus);
2206 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2207}
2208
984263bc
MD		 2209#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2210static void f00f_hack(void *unused);
ba39e2e0 2211SYSINIT(f00f_hack, SI_BOOT2_BIOS, SI_ORDER_ANY, f00f_hack, NULL);
984263bc
MD		 2212
2213static void
17a9f566
MD		 2214f00f_hack(void *unused)
2215{
984263bc 2216 struct gate_descriptor *new_idt;
984263bc
MD		 2217 vm_offset_t tmp;
2218
2219 if (!has_f00f_bug)
2220 return;
2221
26be20a0 2222 kprintf("Intel Pentium detected, installing workaround for F00F bug\n");
984263bc
MD		 2223
2224 r_idt.rd_limit = sizeof(idt0) - 1;
2225
e4846942 2226 tmp = kmem_alloc(&kernel_map, PAGE_SIZE * 2);
984263bc
MD		 2227 if (tmp == 0)
2228 panic("kmem_alloc returned 0");
2229 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2230 panic("kmem_alloc returned non-page-aligned memory");
2231 /* Put the first seven entries in the lower page */
2232 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2233 bcopy(idt, new_idt, sizeof(idt0));
2234 r_idt.rd_base = (int)new_idt;
2235 lidt(&r_idt);
2236 idt = new_idt;
e4846942 2237 if (vm_map_protect(&kernel_map, tmp, tmp + PAGE_SIZE,
984263bc
MD		 2238 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2239 panic("vm_map_protect failed");
2240 return;
2241}
2242#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2243
2244int
08f2f1bb 2245ptrace_set_pc(struct lwp *lp, unsigned long addr)
984263bc 2246{
08f2f1bb 2247 lp->lwp_md.md_regs->tf_eip = addr;
984263bc
MD		 2248 return (0);
2249}
2250
2251int
e9182c58 2252ptrace_single_step(struct lwp *lp)
984263bc 2253{
e9182c58 2254 lp->lwp_md.md_regs->tf_eflags |= PSL_T;
984263bc
MD		 2255 return (0);
2256}
2257
f123d5a1 2258int
e9182c58 2259fill_regs(struct lwp *lp, struct reg *regs)
984263bc 2260{
984263bc
MD		 2261 struct trapframe *tp;
2262
e9182c58 2263 tp = lp->lwp_md.md_regs;
4e7c41c5 2264 regs->r_gs = tp->tf_gs;
984263bc
MD		 2265 regs->r_fs = tp->tf_fs;
2266 regs->r_es = tp->tf_es;
2267 regs->r_ds = tp->tf_ds;
2268 regs->r_edi = tp->tf_edi;
2269 regs->r_esi = tp->tf_esi;
2270 regs->r_ebp = tp->tf_ebp;
2271 regs->r_ebx = tp->tf_ebx;
2272 regs->r_edx = tp->tf_edx;
2273 regs->r_ecx = tp->tf_ecx;
2274 regs->r_eax = tp->tf_eax;
2275 regs->r_eip = tp->tf_eip;
2276 regs->r_cs = tp->tf_cs;
2277 regs->r_eflags = tp->tf_eflags;
2278 regs->r_esp = tp->tf_esp;
2279 regs->r_ss = tp->tf_ss;
984263bc
MD		 2280 return (0);
2281}
2282
2283int
e9182c58 2284set_regs(struct lwp *lp, struct reg *regs)
984263bc 2285{
984263bc
MD		 2286 struct trapframe *tp;
2287
e9182c58 2288 tp = lp->lwp_md.md_regs;
984263bc
MD		 2289 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2290 !CS_SECURE(regs->r_cs))
2291 return (EINVAL);
4e7c41c5 2292 tp->tf_gs = regs->r_gs;
984263bc
MD		 2293 tp->tf_fs = regs->r_fs;
2294 tp->tf_es = regs->r_es;
2295 tp->tf_ds = regs->r_ds;
2296 tp->tf_edi = regs->r_edi;
2297 tp->tf_esi = regs->r_esi;
2298 tp->tf_ebp = regs->r_ebp;
2299 tp->tf_ebx = regs->r_ebx;
2300 tp->tf_edx = regs->r_edx;
2301 tp->tf_ecx = regs->r_ecx;
2302 tp->tf_eax = regs->r_eax;
2303 tp->tf_eip = regs->r_eip;
2304 tp->tf_cs = regs->r_cs;
2305 tp->tf_eflags = regs->r_eflags;
2306 tp->tf_esp = regs->r_esp;
2307 tp->tf_ss = regs->r_ss;
984263bc
MD		 2308 return (0);
2309}
2310
642a6e88 2311#ifndef CPU_DISABLE_SSE
984263bc 2312static void
f123d5a1 2313fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
984263bc 2314{
c9faf524
RG		 2315 struct env87 *penv_87 = &sv_87->sv_env;
2316 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD		 2317 int i;
2318
2319 /* FPU control/status */
2320 penv_87->en_cw = penv_xmm->en_cw;
2321 penv_87->en_sw = penv_xmm->en_sw;
2322 penv_87->en_tw = penv_xmm->en_tw;
2323 penv_87->en_fip = penv_xmm->en_fip;
2324 penv_87->en_fcs = penv_xmm->en_fcs;
2325 penv_87->en_opcode = penv_xmm->en_opcode;
2326 penv_87->en_foo = penv_xmm->en_foo;
2327 penv_87->en_fos = penv_xmm->en_fos;
2328
2329 /* FPU registers */
2330 for (i = 0; i < 8; ++i)
2331 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
984263bc
MD		 2332}
2333
2334static void
f123d5a1 2335set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
984263bc 2336{
c9faf524
RG		 2337 struct env87 *penv_87 = &sv_87->sv_env;
2338 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD		 2339 int i;
2340
2341 /* FPU control/status */
2342 penv_xmm->en_cw = penv_87->en_cw;
2343 penv_xmm->en_sw = penv_87->en_sw;
2344 penv_xmm->en_tw = penv_87->en_tw;
2345 penv_xmm->en_fip = penv_87->en_fip;
2346 penv_xmm->en_fcs = penv_87->en_fcs;
2347 penv_xmm->en_opcode = penv_87->en_opcode;
2348 penv_xmm->en_foo = penv_87->en_foo;
2349 penv_xmm->en_fos = penv_87->en_fos;
2350
2351 /* FPU registers */
2352 for (i = 0; i < 8; ++i)
2353 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
984263bc 2354}
642a6e88 2355#endif /* CPU_DISABLE_SSE */
984263bc
MD		 2356
2357int
e9182c58 2358fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2359{
642a6e88 2360#ifndef CPU_DISABLE_SSE
984263bc 2361 if (cpu_fxsr) {
e9182c58
SZ		 2362 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2363 (struct save87 *)fpregs);
984263bc
MD		 2364 return (0);
2365 }
642a6e88 2366#endif /* CPU_DISABLE_SSE */
e9182c58 2367 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD		 2368 return (0);
2369}
2370
2371int
e9182c58 2372set_fpregs(struct lwp *lp, struct fpreg *fpregs)
984263bc 2373{
642a6e88 2374#ifndef CPU_DISABLE_SSE
984263bc
MD		 2375 if (cpu_fxsr) {
2376 set_fpregs_xmm((struct save87 *)fpregs,
e9182c58 2377 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD		 2378 return (0);
2379 }
642a6e88 2380#endif /* CPU_DISABLE_SSE */
e9182c58 2381 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD		 2382 return (0);
2383}
2384
2385int
e9182c58 2386fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2387{
e9182c58 2388 if (lp == NULL) {
984263bc
MD		 2389 dbregs->dr0 = rdr0();
2390 dbregs->dr1 = rdr1();
2391 dbregs->dr2 = rdr2();
2392 dbregs->dr3 = rdr3();
2393 dbregs->dr4 = rdr4();
2394 dbregs->dr5 = rdr5();
2395 dbregs->dr6 = rdr6();
2396 dbregs->dr7 = rdr7();
e9182c58
SZ		 2397 } else {
2398 struct pcb *pcb;
2399
2400 pcb = lp->lwp_thread->td_pcb;
984263bc
MD		 2401 dbregs->dr0 = pcb->pcb_dr0;
2402 dbregs->dr1 = pcb->pcb_dr1;
2403 dbregs->dr2 = pcb->pcb_dr2;
2404 dbregs->dr3 = pcb->pcb_dr3;
2405 dbregs->dr4 = 0;
2406 dbregs->dr5 = 0;
2407 dbregs->dr6 = pcb->pcb_dr6;
2408 dbregs->dr7 = pcb->pcb_dr7;
2409 }
2410 return (0);
2411}
2412
2413int
e9182c58 2414set_dbregs(struct lwp *lp, struct dbreg *dbregs)
984263bc 2415{
e9182c58 2416 if (lp == NULL) {
984263bc
MD		 2417 load_dr0(dbregs->dr0);
2418 load_dr1(dbregs->dr1);
2419 load_dr2(dbregs->dr2);
2420 load_dr3(dbregs->dr3);
2421 load_dr4(dbregs->dr4);
2422 load_dr5(dbregs->dr5);
2423 load_dr6(dbregs->dr6);
2424 load_dr7(dbregs->dr7);
e9182c58
SZ		 2425 } else {
2426 struct pcb *pcb;
2427 struct ucred *ucred;
2428 int i;
2429 uint32_t mask1, mask2;
2430
984263bc
MD		 2431 /*
2432 * Don't let an illegal value for dr7 get set. Specifically,
2433 * check for undefined settings. Setting these bit patterns
2434 * result in undefined behaviour and can lead to an unexpected
2435 * TRCTRAP.
2436 */
2437 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2438 i++, mask1 <<= 2, mask2 <<= 2)
2439 if ((dbregs->dr7 & mask1) == mask2)
2440 return (EINVAL);
2441
e9182c58
SZ		 2442 pcb = lp->lwp_thread->td_pcb;
2443 ucred = lp->lwp_proc->p_ucred;
2444
984263bc
MD		 2445 /*
2446 * Don't let a process set a breakpoint that is not within the
2447 * process's address space. If a process could do this, it
2448 * could halt the system by setting a breakpoint in the kernel
2449 * (if ddb was enabled). Thus, we need to check to make sure
2450 * that no breakpoints are being enabled for addresses outside
2451 * process's address space, unless, perhaps, we were called by
2452 * uid 0.
2453 *
2454 * XXX - what about when the watched area of the user's
2455 * address space is written into from within the kernel
2456 * ... wouldn't that still cause a breakpoint to be generated
2457 * from within kernel mode?
2458 */
e9182c58 2459
895c1f85 2460 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
984263bc
MD		 2461 if (dbregs->dr7 & 0x3) {
2462 /* dr0 is enabled */
88181b08 2463 if (dbregs->dr0 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2464 return (EINVAL);
2465 }
e9182c58 2466
984263bc
MD		 2467 if (dbregs->dr7 & (0x3<<2)) {
2468 /* dr1 is enabled */
88181b08 2469 if (dbregs->dr1 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2470 return (EINVAL);
2471 }
e9182c58 2472
984263bc
MD		 2473 if (dbregs->dr7 & (0x3<<4)) {
2474 /* dr2 is enabled */
88181b08 2475 if (dbregs->dr2 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2476 return (EINVAL);
2477 }
e9182c58 2478
984263bc
MD		 2479 if (dbregs->dr7 & (0x3<<6)) {
2480 /* dr3 is enabled */
88181b08 2481 if (dbregs->dr3 >= VM_MAX_USER_ADDRESS)
984263bc
MD		 2482 return (EINVAL);
2483 }
2484 }
e9182c58 2485
984263bc
MD		 2486 pcb->pcb_dr0 = dbregs->dr0;
2487 pcb->pcb_dr1 = dbregs->dr1;
2488 pcb->pcb_dr2 = dbregs->dr2;
2489 pcb->pcb_dr3 = dbregs->dr3;
2490 pcb->pcb_dr6 = dbregs->dr6;
2491 pcb->pcb_dr7 = dbregs->dr7;
e9182c58 2492
984263bc
MD		 2493 pcb->pcb_flags |= PCB_DBREGS;
2494 }
2495
2496 return (0);
2497}
2498
2499/*
2500 * Return > 0 if a hardware breakpoint has been hit, and the
2501 * breakpoint was in user space. Return 0, otherwise.
2502 */
2503int
2504user_dbreg_trap(void)
2505{
2506 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2507 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2508 int nbp; /* number of breakpoints that triggered */
2509 caddr_t addr[4]; /* breakpoint addresses */
2510 int i;
2511
2512 dr7 = rdr7();
2513 if ((dr7 & 0x000000ff) == 0) {
2514 /*
2515 * all GE and LE bits in the dr7 register are zero,
2516 * thus the trap couldn't have been caused by the
2517 * hardware debug registers
2518 */
2519 return 0;
2520 }
2521
2522 nbp = 0;
2523 dr6 = rdr6();
2524 bp = dr6 & 0x0000000f;
2525
2526 if (!bp) {
2527 /*
2528 * None of the breakpoint bits are set meaning this
2529 * trap was not caused by any of the debug registers
2530 */
2531 return 0;
2532 }
2533
2534 /*
2535 * at least one of the breakpoints were hit, check to see
2536 * which ones and if any of them are user space addresses
2537 */
2538
2539 if (bp & 0x01) {
2540 addr[nbp++] = (caddr_t)rdr0();
2541 }
2542 if (bp & 0x02) {
2543 addr[nbp++] = (caddr_t)rdr1();
2544 }
2545 if (bp & 0x04) {
2546 addr[nbp++] = (caddr_t)rdr2();
2547 }
2548 if (bp & 0x08) {
2549 addr[nbp++] = (caddr_t)rdr3();
2550 }
2551
2552 for (i=0; i<nbp; i++) {
2553 if (addr[i] <
88181b08 2554 (caddr_t)VM_MAX_USER_ADDRESS) {
984263bc
MD		 2555 /*
2556 * addr[i] is in user space
2557 */
2558 return nbp;
2559 }
2560 }
2561
2562 /*
2563 * None of the breakpoints are in user space.
2564 */
2565 return 0;
2566}
2567
2568
2569#ifndef DDB
2570void
2571Debugger(const char *msg)
2572{
26be20a0 2573 kprintf("Debugger(\"%s\") called.\n", msg);
984263bc
MD		 2574}
2575#endif /* no DDB */
2576
984263bc
MD		 2577#ifdef DDB
2578
2579/*
2580 * Provide inb() and outb() as functions. They are normally only
2581 * available as macros calling inlined functions, thus cannot be
2582 * called inside DDB.
2583 *
2584 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2585 */
2586
2587#undef inb
2588#undef outb
2589
2590/* silence compiler warnings */
2591u_char inb(u_int);
2592void outb(u_int, u_char);
2593
2594u_char
2595inb(u_int port)
2596{
2597 u_char data;
2598 /*
2599 * We use %%dx and not %1 here because i/o is done at %dx and not at
2600 * %edx, while gcc generates inferior code (movw instead of movl)
2601 * if we tell it to load (u_short) port.
2602 */
2603 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2604 return (data);
2605}
2606
2607void
2608outb(u_int port, u_char data)
2609{
2610 u_char al;
2611 /*
2612 * Use an unnecessary assignment to help gcc's register allocator.
2613 * This make a large difference for gcc-1.40 and a tiny difference
2614 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2615 * best results. gcc-2.6.0 can't handle this.
2616 */
2617 al = data;
2618 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2619}
2620
2621#endif /* DDB */
8a8d5d85
MD		 2622
2623
2624
2625#include "opt_cpu.h"
8a8d5d85
MD		 2626
2627
2628/*
2629 * initialize all the SMP locks
2630 */
2631
97359a5b 2632/* critical region when masking or unmasking interupts */
b1af91cb 2633struct spinlock_deprecated imen_spinlock;
8a8d5d85 2634
8a8d5d85 2635/* critical region for old style disable_intr/enable_intr */
b1af91cb 2636struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD		 2637
2638/* critical region around INTR() routines */
b1af91cb 2639struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD		 2640
2641/* lock region used by kernel profiling */
b1af91cb 2642struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD		 2643
2644/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2645struct spinlock_deprecated com_spinlock;
8a8d5d85 2646
8a8d5d85 2647/* lock regions around the clock hardware */
b1af91cb 2648struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD		 2649
2650/* lock around the MP rendezvous */
b1af91cb 2651struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD		 2652
2653static void
2654init_locks(void)
2655{
b5d16701 2656#ifdef SMP
8a8d5d85 2657 /*
b5d16701 2658 * Get the initial mplock with a count of 1 for the BSP.
8a8d5d85
MD		 2659 * This uses a LOGICAL cpu ID, ie BSP == 0.
2660 */
8a8d5d85
MD		 2661 cpu_get_initial_mplock();
2662#endif
41a01a4d 2663 /* DEPRECATED */
8a8d5d85 2664 spin_lock_init(&mcount_spinlock);
8a8d5d85
MD		 2665 spin_lock_init(&intr_spinlock);
2666 spin_lock_init(&mpintr_spinlock);
2667 spin_lock_init(&imen_spinlock);
2668 spin_lock_init(&smp_rv_spinlock);
2669 spin_lock_init(&com_spinlock);
2670 spin_lock_init(&clock_spinlock);
41a01a4d
MD		 2671
2672 /* our token pool needs to work early */
2673 lwkt_token_pool_init();
8a8d5d85 2674}
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