kernel - Major signal path adjustments to fix races, tsleep race fixes, +more
[dragonfly.git] / sys / platform / pc64 / x86_64 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * William Jolitz.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
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41 */
42
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43//#include "use_npx.h"
44#include "use_isa.h"
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45#include "opt_compat.h"
46#include "opt_cpu.h"
47#include "opt_ddb.h"
48#include "opt_directio.h"
49#include "opt_inet.h"
50#include "opt_ipx.h"
51#include "opt_msgbuf.h"
52#include "opt_swap.h"
53
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/sysproto.h>
57#include <sys/signalvar.h>
58#include <sys/kernel.h>
59#include <sys/linker.h>
60#include <sys/malloc.h>
61#include <sys/proc.h>
895c1f85 62#include <sys/priv.h>
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63#include <sys/buf.h>
64#include <sys/reboot.h>
65#include <sys/mbuf.h>
66#include <sys/msgbuf.h>
67#include <sys/sysent.h>
68#include <sys/sysctl.h>
69#include <sys/vmmeter.h>
70#include <sys/bus.h>
71#include <sys/upcall.h>
72#include <sys/usched.h>
73#include <sys/reg.h>
74
75#include <vm/vm.h>
76#include <vm/vm_param.h>
77#include <sys/lock.h>
78#include <vm/vm_kern.h>
79#include <vm/vm_object.h>
80#include <vm/vm_page.h>
81#include <vm/vm_map.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_extern.h>
84
85#include <sys/thread2.h>
684a93c4 86#include <sys/mplock2.h>
320c681e 87#include <sys/mutex2.h>
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88
89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
95#include <machine/cpu.h>
96#include <machine/clock.h>
97#include <machine/specialreg.h>
98#if JG
99#include <machine/bootinfo.h>
100#endif
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101#include <machine/md_var.h>
102#include <machine/metadata.h>
103#include <machine/pc/bios.h>
104#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
105#include <machine/globaldata.h> /* CPU_prvspace */
106#include <machine/smp.h>
107#ifdef PERFMON
108#include <machine/perfmon.h>
109#endif
110#include <machine/cputypes.h>
57a9c56b 111#include <machine/intr_machdep.h>
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112
113#ifdef OLD_BUS_ARCH
46d4e165 114#include <bus/isa/isa_device.h>
c8fe38ae 115#endif
57a9c56b 116#include <machine_base/isa/isa_intr.h>
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117#include <bus/isa/rtc.h>
118#include <sys/random.h>
119#include <sys/ptrace.h>
120#include <machine/sigframe.h>
121
faaf4131 122#include <sys/machintr.h>
9284cddf 123#include <machine_base/icu/icu_abi.h>
7265a4fe 124#include <machine_base/icu/elcr_var.h>
2e0ed166 125#include <machine_base/apic/lapic.h>
ed4d621d 126#include <machine_base/apic/ioapic.h>
a3dd9120 127#include <machine_base/apic/ioapic_abi.h>
8cc9a8d1 128#include <machine/mptable.h>
faaf4131 129
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130#define PHYSMAP_ENTRIES 10
131
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132extern u_int64_t hammer_time(u_int64_t, u_int64_t);
133
134extern void printcpuinfo(void); /* XXX header file */
135extern void identify_cpu(void);
136#if JG
137extern void finishidentcpu(void);
138#endif
139extern void panicifcpuunsupported(void);
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140
141static void cpu_startup(void *);
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142static void pic_finish(void *);
143static void cpu_finish(void *);
144
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145#ifndef CPU_DISABLE_SSE
146static void set_fpregs_xmm(struct save87 *, struct savexmm *);
147static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
148#endif /* CPU_DISABLE_SSE */
149#ifdef DIRECTIO
150extern void ffs_rawread_setup(void);
151#endif /* DIRECTIO */
152static void init_locks(void);
153
7c006a9e 154SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
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155SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
156SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
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157
158#ifdef DDB
159extern vm_offset_t ksym_start, ksym_end;
160#endif
161
da23a592 162struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
48ffc236 163
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164int _udatasel, _ucodesel, _ucode32sel;
165u_long atdevbase;
166#ifdef SMP
167int64_t tsc_offsets[MAXCPU];
168#else
169int64_t tsc_offsets[1];
170#endif
171
172#if defined(SWTCH_OPTIM_STATS)
173extern int swtch_optim_stats;
174SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
175 CTLFLAG_RD, &swtch_optim_stats, 0, "");
176SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
177 CTLFLAG_RD, &tlb_flush_count, 0, "");
178#endif
179
39d69dae 180long physmem = 0;
c8fe38ae 181
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182u_long ebda_addr = 0;
183
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184int imcr_present = 0;
185
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186int naps = 0; /* # of Applications processors */
187
8936cd9b 188u_int base_memory;
320c681e 189struct mtx dt_lock; /* lock for GDT and LDT */
8936cd9b 190
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191static int
192sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
193{
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194 u_long pmem = ctob(physmem);
195
196 int error = sysctl_handle_long(oidp, &pmem, 0, req);
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197 return (error);
198}
199
39d69dae 200SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
9b9532a0 201 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
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202
203static int
204sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
205{
206 int error = sysctl_handle_int(oidp, 0,
207 ctob(physmem - vmstats.v_wire_count), req);
208 return (error);
209}
210
211SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
212 0, 0, sysctl_hw_usermem, "IU", "");
213
214static int
215sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
216{
c8fe38ae 217 int error = sysctl_handle_int(oidp, 0,
b2b3ffcd 218 x86_64_btop(avail_end - avail_start), req);
c8fe38ae 219 return (error);
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220}
221
222SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
223 0, 0, sysctl_hw_availpages, "I", "");
224
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225vm_paddr_t Maxmem;
226vm_paddr_t Realmem;
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227
228/*
229 * The number of PHYSMAP entries must be one less than the number of
230 * PHYSSEG entries because the PHYSMAP entry that spans the largest
231 * physical address that is accessible by ISA DMA is split into two
232 * PHYSSEG entries.
233 */
234#define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
235
236vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
237vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
238
239/* must be 2 less so 0 0 can signal end of chunks */
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240#define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
241#define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
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242
243static vm_offset_t buffer_sva, buffer_eva;
244vm_offset_t clean_sva, clean_eva;
245static vm_offset_t pager_sva, pager_eva;
246static struct trapframe proc0_tf;
247
248static void
249cpu_startup(void *dummy)
250{
251 caddr_t v;
252 vm_size_t size = 0;
253 vm_offset_t firstaddr;
254
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255 /*
256 * Good {morning,afternoon,evening,night}.
257 */
258 kprintf("%s", version);
259 startrtclock();
260 printcpuinfo();
261 panicifcpuunsupported();
262#ifdef PERFMON
263 perfmon_init();
264#endif
15dc6550 265 kprintf("real memory = %ju (%ju MB)\n",
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266 (intmax_t)Realmem,
267 (intmax_t)Realmem / 1024 / 1024);
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268 /*
269 * Display any holes after the first chunk of extended memory.
270 */
271 if (bootverbose) {
272 int indx;
273
274 kprintf("Physical memory chunk(s):\n");
275 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
276 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
277
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278 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
279 (intmax_t)phys_avail[indx],
280 (intmax_t)phys_avail[indx + 1] - 1,
281 (intmax_t)size1,
282 (intmax_t)(size1 / PAGE_SIZE));
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283 }
284 }
285
286 /*
287 * Allocate space for system data structures.
288 * The first available kernel virtual address is in "v".
289 * As pages of kernel virtual memory are allocated, "v" is incremented.
290 * As pages of memory are allocated and cleared,
291 * "firstaddr" is incremented.
292 * An index into the kernel page table corresponding to the
293 * virtual memory address maintained in "v" is kept in "mapaddr".
294 */
295
296 /*
297 * Make two passes. The first pass calculates how much memory is
298 * needed and allocates it. The second pass assigns virtual
299 * addresses to the various data structures.
300 */
301 firstaddr = 0;
302again:
303 v = (caddr_t)firstaddr;
304
305#define valloc(name, type, num) \
306 (name) = (type *)v; v = (caddr_t)((name)+(num))
307#define valloclim(name, type, num, lim) \
308 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
309
310 /*
311 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
312 * For the first 64MB of ram nominally allocate sufficient buffers to
313 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
314 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
315 * the buffer cache we limit the eventual kva reservation to
316 * maxbcache bytes.
317 *
318 * factor represents the 1/4 x ram conversion.
319 */
320 if (nbuf == 0) {
321 int factor = 4 * BKVASIZE / 1024;
322 int kbytes = physmem * (PAGE_SIZE / 1024);
323
324 nbuf = 50;
325 if (kbytes > 4096)
326 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
327 if (kbytes > 65536)
328 nbuf += (kbytes - 65536) * 2 / (factor * 5);
329 if (maxbcache && nbuf > maxbcache / BKVASIZE)
330 nbuf = maxbcache / BKVASIZE;
331 }
332
333 /*
334 * Do not allow the buffer_map to be more then 1/2 the size of the
335 * kernel_map.
336 */
337 if (nbuf > (virtual_end - virtual_start) / (BKVASIZE * 2)) {
338 nbuf = (virtual_end - virtual_start) / (BKVASIZE * 2);
339 kprintf("Warning: nbufs capped at %d\n", nbuf);
340 }
341
342 nswbuf = max(min(nbuf/4, 256), 16);
343#ifdef NSWBUF_MIN
344 if (nswbuf < NSWBUF_MIN)
345 nswbuf = NSWBUF_MIN;
346#endif
347#ifdef DIRECTIO
348 ffs_rawread_setup();
349#endif
350
351 valloc(swbuf, struct buf, nswbuf);
352 valloc(buf, struct buf, nbuf);
353
354 /*
355 * End of first pass, size has been calculated so allocate memory
356 */
357 if (firstaddr == 0) {
358 size = (vm_size_t)(v - firstaddr);
359 firstaddr = kmem_alloc(&kernel_map, round_page(size));
360 if (firstaddr == 0)
361 panic("startup: no room for tables");
362 goto again;
363 }
364
365 /*
366 * End of second pass, addresses have been assigned
367 */
368 if ((vm_size_t)(v - firstaddr) != size)
369 panic("startup: table size inconsistency");
370
371 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
372 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
373 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
374 (nbuf*BKVASIZE));
375 buffer_map.system_map = 1;
376 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
377 (nswbuf*MAXPHYS) + pager_map_size);
378 pager_map.system_map = 1;
379
380#if defined(USERCONFIG)
381 userconfig();
382 cninit(); /* the preferred console may have changed */
383#endif
384
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385 kprintf("avail memory = %ju (%ju MB)\n",
386 (uintmax_t)ptoa(vmstats.v_free_count),
387 (uintmax_t)ptoa(vmstats.v_free_count) / 1024 / 1024);
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388
389 /*
390 * Set up buffers, so they can be used to read disk labels.
391 */
392 bufinit();
393 vm_pager_bufferinit();
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394}
395
396static void
397cpu_finish(void *dummy __unused)
398{
399 cpu_setregs();
400}
401
402static void
403pic_finish(void *dummy __unused)
404{
405 /* Log ELCR information */
406 elcr_dump();
8dc88f05 407
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408 /* Log MPTABLE information */
409 mptable_pci_int_dump();
410
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411 /* Finalize PCI */
412 MachIntrABI.finalize();
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413}
414
415/*
416 * Send an interrupt to process.
417 *
418 * Stack is set up to allow sigcode stored
419 * at top to call routine, followed by kcall
420 * to sigreturn routine below. After sigreturn
421 * resets the signal mask, the stack, and the
422 * frame pointer, it returns to the user
423 * specified pc, psl.
424 */
425void
426sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
427{
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428 struct lwp *lp = curthread->td_lwp;
429 struct proc *p = lp->lwp_proc;
430 struct trapframe *regs;
431 struct sigacts *psp = p->p_sigacts;
432 struct sigframe sf, *sfp;
433 int oonstack;
a6a09809 434 char *sp;
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435
436 regs = lp->lwp_md.md_regs;
437 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
438
a6a09809 439 /* Save user context */
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440 bzero(&sf, sizeof(struct sigframe));
441 sf.sf_uc.uc_sigmask = *mask;
442 sf.sf_uc.uc_stack = lp->lwp_sigstk;
443 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
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444 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
445 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
c8fe38ae 446
a6a09809 447 /* Make the size of the saved context visible to userland */
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448 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
449
c8fe38ae 450 /* Allocate and validate space for the signal handler context. */
4643740a 451 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
c8fe38ae 452 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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453 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
454 sizeof(struct sigframe));
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455 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
456 } else {
89954408
JG
457 /* We take red zone into account */
458 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
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459 }
460
a6a09809 461 /* Align to 16 bytes */
4117f2fd 462 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
a6a09809 463
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464 /* Translate the signal is appropriate */
465 if (p->p_sysent->sv_sigtbl) {
466 if (sig <= p->p_sysent->sv_sigsize)
467 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
468 }
469
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470 /*
471 * Build the argument list for the signal handler.
472 *
473 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
474 */
475 regs->tf_rdi = sig; /* argument 1 */
476 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
477
c8fe38ae 478 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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479 /*
480 * Signal handler installed with SA_SIGINFO.
481 *
482 * action(signo, siginfo, ucontext)
483 */
484 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
630d9ab4 485 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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486 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
487
488 /* fill siginfo structure */
489 sf.sf_si.si_signo = sig;
490 sf.sf_si.si_code = code;
630d9ab4 491 sf.sf_si.si_addr = (void *)regs->tf_addr;
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492 } else {
493 /*
494 * Old FreeBSD-style arguments.
495 *
496 * handler (signo, code, [uc], addr)
497 */
498 regs->tf_rsi = (register_t)code; /* argument 2 */
630d9ab4 499 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
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500 sf.sf_ahu.sf_handler = catcher;
501 }
502
503 /*
504 * If we're a vm86 process, we want to save the segment registers.
505 * We also change eflags to be our emulated eflags, not the actual
506 * eflags.
507 */
508#if JG
509 if (regs->tf_eflags & PSL_VM) {
510 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
511 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
512
513 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
514 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
515 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
516 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
517
518 if (vm86->vm86_has_vme == 0)
519 sf.sf_uc.uc_mcontext.mc_eflags =
520 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
521 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
522
523 /*
524 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
525 * syscalls made by the signal handler. This just avoids
526 * wasting time for our lazy fixup of such faults. PSL_NT
527 * does nothing in vm86 mode, but vm86 programs can set it
528 * almost legitimately in probes for old cpu types.
529 */
530 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
531 }
532#endif
533
534 /*
535 * Save the FPU state and reinit the FP unit
536 */
c8fe38ae 537 npxpush(&sf.sf_uc.uc_mcontext);
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538
539 /*
540 * Copy the sigframe out to the user's stack.
541 */
542 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
543 /*
544 * Something is wrong with the stack pointer.
545 * ...Kill the process.
546 */
547 sigexit(lp, SIGILL);
548 }
549
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550 regs->tf_rsp = (register_t)sfp;
551 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
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552
553 /*
554 * i386 abi specifies that the direction flag must be cleared
555 * on function entry
556 */
5b9f6cc4 557 regs->tf_rflags &= ~(PSL_T|PSL_D);
c8fe38ae 558
c8fe38ae 559 /*
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560 * 64 bit mode has a code and stack selector but
561 * no data or extra selector. %fs and %gs are not
562 * stored in-context.
c8fe38ae 563 */
a6a09809 564 regs->tf_cs = _ucodesel;
c8fe38ae 565 regs->tf_ss = _udatasel;
f2081646 566 clear_quickret();
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567}
568
569/*
570 * Sanitize the trapframe for a virtual kernel passing control to a custom
571 * VM context. Remove any items that would otherwise create a privilage
572 * issue.
573 *
574 * XXX at the moment we allow userland to set the resume flag. Is this a
575 * bad idea?
576 */
577int
578cpu_sanitize_frame(struct trapframe *frame)
579{
c8fe38ae 580 frame->tf_cs = _ucodesel;
c8fe38ae 581 frame->tf_ss = _udatasel;
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582 /* XXX VM (8086) mode not supported? */
583 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
584 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
585
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586 return(0);
587}
588
589/*
590 * Sanitize the tls so loading the descriptor does not blow up
b2b3ffcd 591 * on us. For x86_64 we don't have to do anything.
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592 */
593int
594cpu_sanitize_tls(struct savetls *tls)
595{
596 return(0);
597}
598
599/*
600 * sigreturn(ucontext_t *sigcntxp)
601 *
602 * System call to cleanup state after a signal
603 * has been taken. Reset signal mask and
604 * stack state from context left by sendsig (above).
605 * Return to previous pc and psl as specified by
606 * context left by sendsig. Check carefully to
607 * make sure that the user has not modified the
608 * state to gain improper privileges.
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609 *
610 * MPSAFE
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611 */
612#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
613#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
614
615int
616sys_sigreturn(struct sigreturn_args *uap)
617{
618 struct lwp *lp = curthread->td_lwp;
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619 struct trapframe *regs;
620 ucontext_t uc;
621 ucontext_t *ucp;
5b9f6cc4 622 register_t rflags;
c8fe38ae 623 int cs;
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624 int error;
625
626 /*
627 * We have to copy the information into kernel space so userland
628 * can't modify it while we are sniffing it.
629 */
630 regs = lp->lwp_md.md_regs;
631 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
632 if (error)
633 return (error);
634 ucp = &uc;
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635 rflags = ucp->uc_mcontext.mc_rflags;
636
637 /* VM (8086) mode not supported */
638 rflags &= ~PSL_VM_UNSUPP;
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639
640#if JG
641 if (eflags & PSL_VM) {
642 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
643 struct vm86_kernel *vm86;
644
645 /*
646 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
647 * set up the vm86 area, and we can't enter vm86 mode.
648 */
649 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
650 return (EINVAL);
651 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
652 if (vm86->vm86_inited == 0)
653 return (EINVAL);
654
655 /* go back to user mode if both flags are set */
656 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
657 trapsignal(lp, SIGBUS, 0);
658
659 if (vm86->vm86_has_vme) {
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660 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
661 (eflags & VME_USERCHANGE) | PSL_VM;
c8fe38ae 662 } else {
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663 vm86->vm86_eflags = eflags; /* save VIF, VIP */
664 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
665 (eflags & VM_USERCHANGE) | PSL_VM;
c8fe38ae 666 }
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667 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
668 tf->tf_eflags = eflags;
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669 tf->tf_vm86_ds = tf->tf_ds;
670 tf->tf_vm86_es = tf->tf_es;
671 tf->tf_vm86_fs = tf->tf_fs;
672 tf->tf_vm86_gs = tf->tf_gs;
673 tf->tf_ds = _udatasel;
674 tf->tf_es = _udatasel;
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675 tf->tf_fs = _udatasel;
676 tf->tf_gs = _udatasel;
5b9f6cc4 677 } else
c8fe38ae 678#endif
5b9f6cc4 679 {
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680 /*
681 * Don't allow users to change privileged or reserved flags.
682 */
683 /*
684 * XXX do allow users to change the privileged flag PSL_RF.
685 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
686 * should sometimes set it there too. tf_eflags is kept in
687 * the signal context during signal handling and there is no
688 * other place to remember it, so the PSL_RF bit may be
689 * corrupted by the signal handler without us knowing.
690 * Corruption of the PSL_RF bit at worst causes one more or
691 * one less debugger trap, so allowing it is fairly harmless.
692 */
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693 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
694 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
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695 return(EINVAL);
696 }
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697
698 /*
699 * Don't allow users to load a valid privileged %cs. Let the
700 * hardware check for invalid selectors, excess privilege in
701 * other selectors, invalid %eip's and invalid %esp's.
702 */
703 cs = ucp->uc_mcontext.mc_cs;
704 if (!CS_SECURE(cs)) {
705 kprintf("sigreturn: cs = 0x%x\n", cs);
706 trapsignal(lp, SIGBUS, T_PROTFLT);
707 return(EINVAL);
708 }
5b9f6cc4 709 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
c8fe38ae 710 }
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711
712 /*
713 * Restore the FPU state from the frame
714 */
3919ced0 715 crit_enter();
c8fe38ae 716 npxpop(&ucp->uc_mcontext);
c8fe38ae 717
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718 if (ucp->uc_mcontext.mc_onstack & 1)
719 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
720 else
721 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
722
723 lp->lwp_sigmask = ucp->uc_sigmask;
724 SIG_CANTMASK(lp->lwp_sigmask);
f2081646 725 clear_quickret();
3919ced0 726 crit_exit();
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727 return(EJUSTRETURN);
728}
729
730/*
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731 * Stack frame on entry to function. %rax will contain the function vector,
732 * %rcx will contain the function data. flags, rcx, and rax will have
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733 * already been pushed on the stack.
734 */
735struct upc_frame {
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736 register_t rax;
737 register_t rcx;
738 register_t rdx;
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739 register_t flags;
740 register_t oldip;
741};
742
743void
744sendupcall(struct vmupcall *vu, int morepending)
745{
746 struct lwp *lp = curthread->td_lwp;
747 struct trapframe *regs;
748 struct upcall upcall;
749 struct upc_frame upc_frame;
750 int crit_count = 0;
751
752 /*
753 * If we are a virtual kernel running an emulated user process
754 * context, switch back to the virtual kernel context before
755 * trying to post the signal.
756 */
757 if (lp->lwp_vkernel && lp->lwp_vkernel->ve) {
758 lp->lwp_md.md_regs->tf_trapno = 0;
759 vkernel_trap(lp, lp->lwp_md.md_regs);
760 }
761
762 /*
763 * Get the upcall data structure
764 */
765 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
766 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
767 ) {
768 vu->vu_pending = 0;
769 kprintf("bad upcall address\n");
770 return;
771 }
772
773 /*
774 * If the data structure is already marked pending or has a critical
775 * section count, mark the data structure as pending and return
776 * without doing an upcall. vu_pending is left set.
777 */
778 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
779 if (upcall.upc_pending < vu->vu_pending) {
780 upcall.upc_pending = vu->vu_pending;
781 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
782 sizeof(upcall.upc_pending));
783 }
784 return;
785 }
786
787 /*
788 * We can run this upcall now, clear vu_pending.
789 *
790 * Bump our critical section count and set or clear the
791 * user pending flag depending on whether more upcalls are
792 * pending. The user will be responsible for calling
793 * upc_dispatch(-1) to process remaining upcalls.
794 */
795 vu->vu_pending = 0;
796 upcall.upc_pending = morepending;
f9235b6d 797 ++crit_count;
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798 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
799 sizeof(upcall.upc_pending));
800 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
801 sizeof(int));
802
803 /*
804 * Construct a stack frame and issue the upcall
805 */
806 regs = lp->lwp_md.md_regs;
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807 upc_frame.rax = regs->tf_rax;
808 upc_frame.rcx = regs->tf_rcx;
809 upc_frame.rdx = regs->tf_rdx;
810 upc_frame.flags = regs->tf_rflags;
811 upc_frame.oldip = regs->tf_rip;
812 if (copyout(&upc_frame, (void *)(regs->tf_rsp - sizeof(upc_frame)),
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813 sizeof(upc_frame)) != 0) {
814 kprintf("bad stack on upcall\n");
815 } else {
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816 regs->tf_rax = (register_t)vu->vu_func;
817 regs->tf_rcx = (register_t)vu->vu_data;
818 regs->tf_rdx = (register_t)lp->lwp_upcall;
819 regs->tf_rip = (register_t)vu->vu_ctx;
820 regs->tf_rsp -= sizeof(upc_frame);
c8fe38ae 821 }
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822}
823
824/*
825 * fetchupcall occurs in the context of a system call, which means that
826 * we have to return EJUSTRETURN in order to prevent eax and edx from
827 * being overwritten by the syscall return value.
828 *
829 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
830 * and the function pointer in %eax.
831 */
832int
833fetchupcall(struct vmupcall *vu, int morepending, void *rsp)
834{
835 struct upc_frame upc_frame;
836 struct lwp *lp = curthread->td_lwp;
837 struct trapframe *regs;
838 int error;
839 struct upcall upcall;
840 int crit_count;
841
842 regs = lp->lwp_md.md_regs;
843
844 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
845 if (error == 0) {
846 if (vu) {
847 /*
848 * This jumps us to the next ready context.
849 */
850 vu->vu_pending = 0;
851 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
852 crit_count = 0;
853 if (error == 0)
854 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
f9235b6d 855 ++crit_count;
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856 if (error == 0)
857 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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858 regs->tf_rax = (register_t)vu->vu_func;
859 regs->tf_rcx = (register_t)vu->vu_data;
860 regs->tf_rdx = (register_t)lp->lwp_upcall;
861 regs->tf_rip = (register_t)vu->vu_ctx;
862 regs->tf_rsp = (register_t)rsp;
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863 } else {
864 /*
865 * This returns us to the originally interrupted code.
866 */
867 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
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868 regs->tf_rax = upc_frame.rax;
869 regs->tf_rcx = upc_frame.rcx;
870 regs->tf_rdx = upc_frame.rdx;
871 regs->tf_rflags = (regs->tf_rflags & ~PSL_USERCHANGE) |
c8fe38ae 872 (upc_frame.flags & PSL_USERCHANGE);
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873 regs->tf_rip = upc_frame.oldip;
874 regs->tf_rsp = (register_t)((char *)rsp + sizeof(upc_frame));
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875 }
876 }
877 if (error == 0)
878 error = EJUSTRETURN;
879 return(error);
880}
881
882/*
883 * Machine dependent boot() routine
884 *
885 * I haven't seen anything to put here yet
886 * Possibly some stuff might be grafted back here from boot()
887 */
888void
889cpu_boot(int howto)
890{
891}
892
893/*
894 * Shutdown the CPU as much as possible
895 */
896void
897cpu_halt(void)
898{
899 for (;;)
900 __asm__ __volatile("hlt");
901}
902
903/*
904 * cpu_idle() represents the idle LWKT. You cannot return from this function
905 * (unless you want to blow things up!). Instead we look for runnable threads
906 * and loop or halt as appropriate. Giant is not held on entry to the thread.
907 *
908 * The main loop is entered with a critical section held, we must release
909 * the critical section before doing anything else. lwkt_switch() will
910 * check for pending interrupts due to entering and exiting its own
911 * critical section.
912 *
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913 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
914 * However, there are cases where the idlethread will be entered with
915 * the possibility that no IPI will occur and in such cases
916 * lwkt_switch() sets TDF_IDLE_NOHLT.
917 *
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918 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
919 * 1 to just use hlt and for debugging purposes.
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920 *
921 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
922 * must occur before it starts using ACPI halt.
c8fe38ae 923 */
46e562ce 924static int cpu_idle_hlt = 2;
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925static int cpu_idle_hltcnt;
926static int cpu_idle_spincnt;
be71787b 927static u_int cpu_idle_repeat = 4;
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928SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
929 &cpu_idle_hlt, 0, "Idle loop HLT enable");
930SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
931 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
932SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
933 &cpu_idle_spincnt, 0, "Idle loop entry spins");
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934SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
935 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
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936
937static void
938cpu_idle_default_hook(void)
939{
940 /*
941 * We must guarentee that hlt is exactly the instruction
942 * following the sti.
943 */
944 __asm __volatile("sti; hlt");
945}
946
947/* Other subsystems (e.g., ACPI) can hook this later. */
948void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
949
950void
951cpu_idle(void)
952{
0f0466c0 953 globaldata_t gd = mycpu;
86232a57 954 struct thread *td __debugvar = gd->gd_curthread;
0f0466c0 955 int reqflags;
be71787b 956 int quick;
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957
958 crit_exit();
f9235b6d 959 KKASSERT(td->td_critcount == 0);
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960 for (;;) {
961 /*
962 * See if there are any LWKTs ready to go.
963 */
964 lwkt_switch();
965
966 /*
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967 * When halting inside a cli we must check for reqflags
968 * races, particularly [re]schedule requests. Running
969 * splz() does the job.
970 *
971 * cpu_idle_hlt:
972 * 0 Never halt, just spin
973 *
974 * 1 Always use HLT (or MONITOR/MWAIT if avail).
975 * This typically eats more power than the
976 * ACPI halt.
977 *
978 * 2 Use HLT/MONITOR/MWAIT up to a point and then
979 * use the ACPI halt (default). This is a hybrid
980 * approach. See machdep.cpu_idle_repeat.
981 *
982 * 3 Always use the ACPI halt. This typically
983 * eats the least amount of power but the cpu
984 * will be slow waking up. Slows down e.g.
985 * compiles and other pipe/event oriented stuff.
986 *
987 * NOTE: Interrupts are enabled and we are not in a critical
988 * section.
989 *
990 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
991 * don't bother capping gd_idle_repeat, it is ok if
992 * it overflows.
c8fe38ae 993 */
be71787b 994 ++gd->gd_idle_repeat;
0f0466c0 995 reqflags = gd->gd_reqflags;
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996 quick = (cpu_idle_hlt == 1) ||
997 (cpu_idle_hlt < 3 &&
998 gd->gd_idle_repeat < cpu_idle_repeat);
999
1000 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
0f0466c0 1001 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
701c977e 1002 splz(); /* XXX */
0f0466c0 1003 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags);
be71787b 1004 ++cpu_idle_hltcnt;
0f0466c0 1005 } else if (cpu_idle_hlt) {
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1006 __asm __volatile("cli");
1007 splz();
0f0466c0 1008 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
be71787b 1009 if (quick)
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1010 cpu_idle_default_hook();
1011 else
1012 cpu_idle_hook();
1013 }
7d4d6fdb 1014 __asm __volatile("sti");
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1015 ++cpu_idle_hltcnt;
1016 } else {
c8fe38ae 1017 splz();
c5724852 1018 __asm __volatile("sti");
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1019 ++cpu_idle_spincnt;
1020 }
1021 }
1022}
1023
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1024#ifdef SMP
1025
c8fe38ae 1026/*
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1027 * This routine is called if a spinlock has been held through the
1028 * exponential backoff period and is seriously contested. On a real cpu
1029 * we let it spin.
1030 */
1031void
1032cpu_spinlock_contested(void)
1033{
1034 cpu_pause();
1035}
1036
7ad8cc6c
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1037#endif
1038
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1039/*
1040 * Clear registers on exec
1041 */
1042void
1043exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1044{
1045 struct thread *td = curthread;
1046 struct lwp *lp = td->td_lwp;
1047 struct pcb *pcb = td->td_pcb;
1048 struct trapframe *regs = lp->lwp_md.md_regs;
1049
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1050 /* was i386_user_cleanup() in NetBSD */
1051 user_ldt_free(pcb);
1052
f2081646 1053 clear_quickret();
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1054 bzero((char *)regs, sizeof(struct trapframe));
1055 regs->tf_rip = entry;
1056 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1057 regs->tf_rdi = stack; /* argv */
1058 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1059 regs->tf_ss = _udatasel;
1060 regs->tf_cs = _ucodesel;
1061 regs->tf_rbx = ps_strings;
1062
1063 /*
1064 * Reset the hardware debug registers if they were in use.
1065 * They won't have any meaning for the newly exec'd process.
1066 */
1067 if (pcb->pcb_flags & PCB_DBREGS) {
1068 pcb->pcb_dr0 = 0;
1069 pcb->pcb_dr1 = 0;
1070 pcb->pcb_dr2 = 0;
1071 pcb->pcb_dr3 = 0;
1072 pcb->pcb_dr6 = 0;
0855a2af 1073 pcb->pcb_dr7 = 0; /* JG set bit 10? */
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1074 if (pcb == td->td_pcb) {
1075 /*
1076 * Clear the debug registers on the running
1077 * CPU, otherwise they will end up affecting
1078 * the next process we switch to.
1079 */
1080 reset_dbregs();
1081 }
1082 pcb->pcb_flags &= ~PCB_DBREGS;
1083 }
1084
1085 /*
1086 * Initialize the math emulator (if any) for the current process.
1087 * Actually, just clear the bit that says that the emulator has
1088 * been initialized. Initialization is delayed until the process
1089 * traps to the emulator (if it is done at all) mainly because
1090 * emulators don't provide an entry point for initialization.
1091 */
c8fe38ae 1092 pcb->pcb_flags &= ~FP_SOFTFP;
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1093
1094 /*
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1095 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1096 * gd_npxthread. Otherwise a preemptive interrupt thread
1097 * may panic in npxdna().
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1098 */
1099 crit_enter();
1100 load_cr0(rcr0() | CR0_MP);
1101
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1102 /*
1103 * NOTE: The MSR values must be correct so we can return to
1104 * userland. gd_user_fs/gs must be correct so the switch
1105 * code knows what the current MSR values are.
1106 */
1107 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
c8fe38ae 1108 pcb->pcb_gsbase = 0;
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1109 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1110 mdcpu->gd_user_gs = 0;
1111 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1112 wrmsr(MSR_KGSBASE, 0);
c8fe38ae 1113
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1114 /* Initialize the npx (if any) for the current process. */
1115 npxinit(__INITIAL_NPXCW__);
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1116 crit_exit();
1117
1118 pcb->pcb_ds = _udatasel;
1119 pcb->pcb_es = _udatasel;
1120 pcb->pcb_fs = _udatasel;
1121 pcb->pcb_gs = _udatasel;
1122}
1123
1124void
1125cpu_setregs(void)
1126{
1127 register_t cr0;
1128
1129 cr0 = rcr0();
1130 cr0 |= CR0_NE; /* Done by npxinit() */
1131 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1132 cr0 |= CR0_WP | CR0_AM;
1133 load_cr0(cr0);
1134 load_gs(_udatasel);
1135}
1136
1137static int
1138sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1139{
1140 int error;
1141 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1142 req);
1143 if (!error && req->newptr)
1144 resettodr();
1145 return (error);
1146}
1147
1148SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1149 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1150
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1151SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1152 CTLFLAG_RW, &disable_rtc_set, 0, "");
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1153
1154#if JG
1155SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1156 CTLFLAG_RD, &bootinfo, bootinfo, "");
1157#endif
1158
1159SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1160 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1161
1162extern u_long bootdev; /* not a cdev_t - encoding is different */
1163SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1164 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1165
1166/*
1167 * Initialize 386 and configure to run kernel
1168 */
1169
1170/*
1171 * Initialize segments & interrupt table
1172 */
1173
1174int _default_ldt;
1175struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1176static struct gate_descriptor idt0[NIDT];
1177struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1178#if JG
1179union descriptor ldt[NLDT]; /* local descriptor table */
1180#endif
1181
1182/* table descriptors - used to load tables by cpu */
1183struct region_descriptor r_gdt, r_idt;
1184
c8fe38ae
MD
1185/* JG proc0paddr is a virtual address */
1186void *proc0paddr;
1187/* JG alignment? */
1188char proc0paddr_buff[LWKT_THREAD_STACK];
1189
1190
1191/* software prototypes -- in more palatable form */
1192struct soft_segment_descriptor gdt_segs[] = {
1193/* GNULL_SEL 0 Null Descriptor */
1194{ 0x0, /* segment base address */
1195 0x0, /* length */
1196 0, /* segment type */
1197 0, /* segment descriptor priority level */
1198 0, /* segment descriptor present */
1199 0, /* long */
1200 0, /* default 32 vs 16 bit size */
1201 0 /* limit granularity (byte/page units)*/ },
1202/* GCODE_SEL 1 Code Descriptor for kernel */
1203{ 0x0, /* segment base address */
1204 0xfffff, /* length - all address space */
1205 SDT_MEMERA, /* segment type */
1206 SEL_KPL, /* segment descriptor priority level */
1207 1, /* segment descriptor present */
1208 1, /* long */
1209 0, /* default 32 vs 16 bit size */
1210 1 /* limit granularity (byte/page units)*/ },
1211/* GDATA_SEL 2 Data Descriptor for kernel */
1212{ 0x0, /* segment base address */
1213 0xfffff, /* length - all address space */
1214 SDT_MEMRWA, /* segment type */
1215 SEL_KPL, /* segment descriptor priority level */
1216 1, /* segment descriptor present */
1217 1, /* long */
1218 0, /* default 32 vs 16 bit size */
1219 1 /* limit granularity (byte/page units)*/ },
1220/* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1221{ 0x0, /* segment base address */
1222 0xfffff, /* length - all address space */
1223 SDT_MEMERA, /* segment type */
1224 SEL_UPL, /* segment descriptor priority level */
1225 1, /* segment descriptor present */
1226 0, /* long */
1227 1, /* default 32 vs 16 bit size */
1228 1 /* limit granularity (byte/page units)*/ },
1229/* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1230{ 0x0, /* segment base address */
1231 0xfffff, /* length - all address space */
1232 SDT_MEMRWA, /* segment type */
1233 SEL_UPL, /* segment descriptor priority level */
1234 1, /* segment descriptor present */
1235 0, /* long */
1236 1, /* default 32 vs 16 bit size */
1237 1 /* limit granularity (byte/page units)*/ },
1238/* GUCODE_SEL 5 64 bit Code Descriptor for user */
1239{ 0x0, /* segment base address */
1240 0xfffff, /* length - all address space */
1241 SDT_MEMERA, /* segment type */
1242 SEL_UPL, /* segment descriptor priority level */
1243 1, /* segment descriptor present */
1244 1, /* long */
1245 0, /* default 32 vs 16 bit size */
1246 1 /* limit granularity (byte/page units)*/ },
1247/* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1248{
1249 0x0, /* segment base address */
b2b3ffcd 1250 sizeof(struct x86_64tss)-1,/* length - all address space */
c8fe38ae
MD
1251 SDT_SYSTSS, /* segment type */
1252 SEL_KPL, /* segment descriptor priority level */
1253 1, /* segment descriptor present */
1254 0, /* long */
1255 0, /* unused - default 32 vs 16 bit size */
1256 0 /* limit granularity (byte/page units)*/ },
1257/* Actually, the TSS is a system descriptor which is double size */
1258{ 0x0, /* segment base address */
1259 0x0, /* length */
1260 0, /* segment type */
1261 0, /* segment descriptor priority level */
1262 0, /* segment descriptor present */
1263 0, /* long */
1264 0, /* default 32 vs 16 bit size */
1265 0 /* limit granularity (byte/page units)*/ },
1266/* GUGS32_SEL 8 32 bit GS Descriptor for user */
1267{ 0x0, /* segment base address */
1268 0xfffff, /* length - all address space */
1269 SDT_MEMRWA, /* segment type */
1270 SEL_UPL, /* segment descriptor priority level */
1271 1, /* segment descriptor present */
1272 0, /* long */
1273 1, /* default 32 vs 16 bit size */
1274 1 /* limit granularity (byte/page units)*/ },
1275};
1276
1277void
1278setidt(int idx, inthand_t *func, int typ, int dpl, int ist)
1279{
1280 struct gate_descriptor *ip;
1281
1282 ip = idt + idx;
1283 ip->gd_looffset = (uintptr_t)func;
1284 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1285 ip->gd_ist = ist;
1286 ip->gd_xx = 0;
1287 ip->gd_type = typ;
1288 ip->gd_dpl = dpl;
1289 ip->gd_p = 1;
1290 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1291}
1292
1293#define IDTVEC(name) __CONCAT(X,name)
1294
1295extern inthand_t
1296 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1297 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1298 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1299 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1300 IDTVEC(xmm), IDTVEC(dblfault),
1301 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1302
1303#ifdef DEBUG_INTERRUPTS
1304extern inthand_t *Xrsvdary[256];
1305#endif
1306
1307void
1308sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1309{
1310 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1311 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1312 ssd->ssd_type = sd->sd_type;
1313 ssd->ssd_dpl = sd->sd_dpl;
1314 ssd->ssd_p = sd->sd_p;
1315 ssd->ssd_def32 = sd->sd_def32;
1316 ssd->ssd_gran = sd->sd_gran;
1317}
1318
1319void
1320ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1321{
1322
1323 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1324 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1325 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1326 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1327 sd->sd_type = ssd->ssd_type;
1328 sd->sd_dpl = ssd->ssd_dpl;
1329 sd->sd_p = ssd->ssd_p;
1330 sd->sd_long = ssd->ssd_long;
1331 sd->sd_def32 = ssd->ssd_def32;
1332 sd->sd_gran = ssd->ssd_gran;
1333}
1334
1335void
1336ssdtosyssd(struct soft_segment_descriptor *ssd,
1337 struct system_segment_descriptor *sd)
1338{
1339
1340 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1341 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1342 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1343 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1344 sd->sd_type = ssd->ssd_type;
1345 sd->sd_dpl = ssd->ssd_dpl;
1346 sd->sd_p = ssd->ssd_p;
1347 sd->sd_gran = ssd->ssd_gran;
1348}
1349
c8fe38ae
MD
1350/*
1351 * Populate the (physmap) array with base/bound pairs describing the
1352 * available physical memory in the system, then test this memory and
1353 * build the phys_avail array describing the actually-available memory.
1354 *
1355 * If we cannot accurately determine the physical memory map, then use
1356 * value from the 0xE801 call, and failing that, the RTC.
1357 *
1358 * Total memory size may be set by the kernel environment variable
1359 * hw.physmem or the compile-time define MAXMEM.
1360 *
b4d9abe2
MD
1361 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1362 * of PAGE_SIZE. This also greatly reduces the memory test time
1363 * which would otherwise be excessive on machines with > 8G of ram.
1364 *
c8fe38ae
MD
1365 * XXX first should be vm_paddr_t.
1366 */
b4d9abe2
MD
1367
1368#define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1369#define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1370
c8fe38ae
MD
1371static void
1372getmemsize(caddr_t kmdp, u_int64_t first)
1373{
b4d9abe2
MD
1374 int off, physmap_idx, pa_indx, da_indx;
1375 int i, j;
1376 vm_paddr_t physmap[PHYSMAP_SIZE];
1377 vm_paddr_t pa;
1378 vm_paddr_t msgbuf_size;
c8fe38ae
MD
1379 u_long physmem_tunable;
1380 pt_entry_t *pte;
1381 struct bios_smap *smapbase, *smap, *smapend;
1382 u_int32_t smapsize;
1383 quad_t dcons_addr, dcons_size;
1384
1385 bzero(physmap, sizeof(physmap));
c8fe38ae
MD
1386 physmap_idx = 0;
1387
1388 /*
1389 * get memory map from INT 15:E820, kindly supplied by the loader.
1390 *
1391 * subr_module.c says:
1392 * "Consumer may safely assume that size value precedes data."
1393 * ie: an int32_t immediately precedes smap.
1394 */
1395 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1396 MODINFO_METADATA | MODINFOMD_SMAP);
1397 if (smapbase == NULL)
1398 panic("No BIOS smap info from loader!");
1399
1400 smapsize = *((u_int32_t *)smapbase - 1);
1401 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1402
1403 for (smap = smapbase; smap < smapend; smap++) {
1404 if (boothowto & RB_VERBOSE)
1405 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1406 smap->type, smap->base, smap->length);
1407
1408 if (smap->type != SMAP_TYPE_MEMORY)
1409 continue;
1410
1411 if (smap->length == 0)
1412 continue;
1413
1414 for (i = 0; i <= physmap_idx; i += 2) {
1415 if (smap->base < physmap[i + 1]) {
1bda0d3d
MD
1416 if (boothowto & RB_VERBOSE) {
1417 kprintf("Overlapping or non-monotonic "
1418 "memory region, ignoring "
1419 "second region\n");
1420 }
c8fe38ae
MD
1421 continue;
1422 }
1423 }
1bda0d3d 1424 Realmem += smap->length;
c8fe38ae
MD
1425
1426 if (smap->base == physmap[physmap_idx + 1]) {
1427 physmap[physmap_idx + 1] += smap->length;
1428 continue;
1429 }
1430
1431 physmap_idx += 2;
1432 if (physmap_idx == PHYSMAP_SIZE) {
1bda0d3d
MD
1433 kprintf("Too many segments in the physical "
1434 "address map, giving up\n");
c8fe38ae
MD
1435 break;
1436 }
1437 physmap[physmap_idx] = smap->base;
1438 physmap[physmap_idx + 1] = smap->base + smap->length;
1439 }
1440
8936cd9b 1441 base_memory = physmap[1] / 1024;
c8fe38ae
MD
1442#ifdef SMP
1443 /* make hole for AP bootstrap code */
8936cd9b 1444 physmap[1] = mp_bootaddress(base_memory);
2c36eb24 1445#endif
2331304b 1446
927c4c1f
MN
1447 /* Save EBDA address, if any */
1448 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1449 ebda_addr <<= 4;
c8fe38ae
MD
1450
1451 /*
1452 * Maxmem isn't the "maximum memory", it's one larger than the
1453 * highest page of the physical address space. It should be
1454 * called something like "Maxphyspage". We may adjust this
1455 * based on ``hw.physmem'' and the results of the memory test.
1456 */
1457 Maxmem = atop(physmap[physmap_idx + 1]);
1458
1459#ifdef MAXMEM
1460 Maxmem = MAXMEM / 4;
1461#endif
1462
1463 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1464 Maxmem = atop(physmem_tunable);
1465
1466 /*
1467 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1468 * in the system.
1469 */
1470 if (Maxmem > atop(physmap[physmap_idx + 1]))
1471 Maxmem = atop(physmap[physmap_idx + 1]);
1472
8e5ea5f7 1473 /*
b4d9abe2 1474 * Blowing out the DMAP will blow up the system.
8e5ea5f7
MD
1475 */
1476 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1477 kprintf("Limiting Maxmem due to DMAP size\n");
1478 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1479 }
1480
c8fe38ae 1481 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
b4d9abe2 1482 (boothowto & RB_VERBOSE)) {
c8fe38ae 1483 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
b4d9abe2 1484 }
c8fe38ae 1485
b4d9abe2
MD
1486 /*
1487 * Call pmap initialization to make new kernel address space
1488 *
1489 * Mask off page 0.
1490 */
48ffc236 1491 pmap_bootstrap(&first);
b4d9abe2
MD
1492 physmap[0] = PAGE_SIZE;
1493
1494 /*
1495 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1496 * exceeding Maxmem.
1497 */
1498 for (i = j = 0; i <= physmap_idx; i += 2) {
1499 if (physmap[i+1] > ptoa((vm_paddr_t)Maxmem))
1500 physmap[i+1] = ptoa((vm_paddr_t)Maxmem);
1501 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1502 ~PHYSMAP_ALIGN_MASK;
1503 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1504
1505 physmap[j] = physmap[i];
1506 physmap[j+1] = physmap[i+1];
1507
1508 if (physmap[i] < physmap[i+1])
1509 j += 2;
1510 }
1511 physmap_idx = j - 2;
1512
1513 /*
1514 * Align anything else used in the validation loop.
1515 */
1516 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
c8fe38ae
MD
1517
1518 /*
1519 * Size up each available chunk of physical memory.
1520 */
c8fe38ae
MD
1521 pa_indx = 0;
1522 da_indx = 1;
1523 phys_avail[pa_indx++] = physmap[0];
1524 phys_avail[pa_indx] = physmap[0];
1525 dump_avail[da_indx] = physmap[0];
1526 pte = CMAP1;
1527
1528 /*
1529 * Get dcons buffer address
1530 */
1531 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1532 kgetenv_quad("dcons.size", &dcons_size) == 0)
1533 dcons_addr = 0;
1534
1535 /*
b4d9abe2
MD
1536 * Validate the physical memory. The physical memory segments
1537 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1538 * of PAGE_SIZE.
c8fe38ae
MD
1539 */
1540 for (i = 0; i <= physmap_idx; i += 2) {
1541 vm_paddr_t end;
1542
b4d9abe2
MD
1543 end = physmap[i + 1];
1544
1545 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
c8fe38ae
MD
1546 int tmp, page_bad, full;
1547 int *ptr = (int *)CADDR1;
1548
1549 full = FALSE;
1550 /*
1551 * block out kernel memory as not available.
1552 */
1553 if (pa >= 0x100000 && pa < first)
1554 goto do_dump_avail;
1555
1556 /*
1557 * block out dcons buffer
1558 */
1559 if (dcons_addr > 0
1560 && pa >= trunc_page(dcons_addr)
b4d9abe2 1561 && pa < dcons_addr + dcons_size) {
c8fe38ae 1562 goto do_dump_avail;
b4d9abe2 1563 }
c8fe38ae
MD
1564
1565 page_bad = FALSE;
1566
1567 /*
1568 * map page into kernel: valid, read/write,non-cacheable
1569 */
1570 *pte = pa | PG_V | PG_RW | PG_N;
1571 cpu_invltlb();
1572
1573 tmp = *(int *)ptr;
1574 /*
1575 * Test for alternating 1's and 0's
1576 */
1577 *(volatile int *)ptr = 0xaaaaaaaa;
b4d9abe2 1578 cpu_mfence();
c8fe38ae
MD
1579 if (*(volatile int *)ptr != 0xaaaaaaaa)
1580 page_bad = TRUE;
1581 /*
1582 * Test for alternating 0's and 1's
1583 */
1584 *(volatile int *)ptr = 0x55555555;
b4d9abe2 1585 cpu_mfence();
c8fe38ae
MD
1586 if (*(volatile int *)ptr != 0x55555555)
1587 page_bad = TRUE;
1588 /*
1589 * Test for all 1's
1590 */
1591 *(volatile int *)ptr = 0xffffffff;
b4d9abe2 1592 cpu_mfence();
c8fe38ae
MD
1593 if (*(volatile int *)ptr != 0xffffffff)
1594 page_bad = TRUE;
1595 /*
1596 * Test for all 0's
1597 */
1598 *(volatile int *)ptr = 0x0;
b4d9abe2 1599 cpu_mfence();
c8fe38ae
MD
1600 if (*(volatile int *)ptr != 0x0)
1601 page_bad = TRUE;
1602 /*
1603 * Restore original value.
1604 */
1605 *(int *)ptr = tmp;
1606
1607 /*
1608 * Adjust array of valid/good pages.
1609 */
1610 if (page_bad == TRUE)
1611 continue;
1612 /*
1613 * If this good page is a continuation of the
1614 * previous set of good pages, then just increase
1615 * the end pointer. Otherwise start a new chunk.
1616 * Note that "end" points one higher than end,
1617 * making the range >= start and < end.
1618 * If we're also doing a speculative memory
1619 * test and we at or past the end, bump up Maxmem
1620 * so that we keep going. The first bad page
1621 * will terminate the loop.
1622 */
1623 if (phys_avail[pa_indx] == pa) {
b4d9abe2 1624 phys_avail[pa_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1625 } else {
1626 pa_indx++;
1627 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1628 kprintf(
1629 "Too many holes in the physical address space, giving up\n");
1630 pa_indx--;
1631 full = TRUE;
1632 goto do_dump_avail;
1633 }
b4d9abe2
MD
1634 phys_avail[pa_indx++] = pa;
1635 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae 1636 }
7a3eee88 1637 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
c8fe38ae
MD
1638do_dump_avail:
1639 if (dump_avail[da_indx] == pa) {
b4d9abe2 1640 dump_avail[da_indx] += PHYSMAP_ALIGN;
c8fe38ae
MD
1641 } else {
1642 da_indx++;
1643 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1644 da_indx--;
1645 goto do_next;
1646 }
b4d9abe2
MD
1647 dump_avail[da_indx++] = pa;
1648 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
c8fe38ae
MD
1649 }
1650do_next:
1651 if (full)
1652 break;
1653 }
1654 }
1655 *pte = 0;
1656 cpu_invltlb();
1657
1658 /*
c8fe38ae
MD
1659 * The last chunk must contain at least one page plus the message
1660 * buffer to avoid complicating other code (message buffer address
1661 * calculation, etc.).
1662 */
b4d9abe2
MD
1663 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1664
1665 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1666 msgbuf_size >= phys_avail[pa_indx]) {
c8fe38ae
MD
1667 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1668 phys_avail[pa_indx--] = 0;
1669 phys_avail[pa_indx--] = 0;
1670 }
1671
1672 Maxmem = atop(phys_avail[pa_indx]);
1673
1674 /* Trim off space for the message buffer. */
b4d9abe2 1675 phys_avail[pa_indx] -= msgbuf_size;
c8fe38ae 1676
1185babf
JG
1677 avail_end = phys_avail[pa_indx];
1678
c8fe38ae 1679 /* Map the message buffer. */
b4d9abe2
MD
1680 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1681 pmap_kenter((vm_offset_t)msgbufp + off,
1682 phys_avail[pa_indx] + off);
1683 }
c8fe38ae
MD
1684}
1685
faaf4131
MN
1686struct machintr_abi MachIntrABI;
1687
c8fe38ae
MD
1688/*
1689 * IDT VECTORS:
1690 * 0 Divide by zero
1691 * 1 Debug
1692 * 2 NMI
1693 * 3 BreakPoint
1694 * 4 OverFlow
1695 * 5 Bound-Range
1696 * 6 Invalid OpCode
1697 * 7 Device Not Available (x87)
1698 * 8 Double-Fault
1699 * 9 Coprocessor Segment overrun (unsupported, reserved)
1700 * 10 Invalid-TSS
1701 * 11 Segment not present
1702 * 12 Stack
1703 * 13 General Protection
1704 * 14 Page Fault
1705 * 15 Reserved
1706 * 16 x87 FP Exception pending
1707 * 17 Alignment Check
1708 * 18 Machine Check
1709 * 19 SIMD floating point
1710 * 20-31 reserved
1711 * 32-255 INTn/external sources
1712 */
1713u_int64_t
1714hammer_time(u_int64_t modulep, u_int64_t physfree)
1715{
1716 caddr_t kmdp;
5b9f6cc4
MD
1717 int gsel_tss, x;
1718#if JG
1719 int metadata_missing, off;
1720#endif
c8fe38ae
MD
1721 struct mdglobaldata *gd;
1722 u_int64_t msr;
c8fe38ae 1723
c8fe38ae
MD
1724 /*
1725 * Prevent lowering of the ipl if we call tsleep() early.
1726 */
1727 gd = &CPU_prvspace[0].mdglobaldata;
1728 bzero(gd, sizeof(*gd));
1729
1730 /*
1731 * Note: on both UP and SMP curthread must be set non-NULL
1732 * early in the boot sequence because the system assumes
1733 * that 'curthread' is never NULL.
1734 */
1735
1736 gd->mi.gd_curthread = &thread0;
1737 thread0.td_gd = &gd->mi;
1738
1739 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1740
1741#if JG
1742 metadata_missing = 0;
1743 if (bootinfo.bi_modulep) {
1744 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1745 preload_bootstrap_relocate(KERNBASE);
1746 } else {
1747 metadata_missing = 1;
1748 }
1749 if (bootinfo.bi_envp)
1750 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1751#endif
1752
1753 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1754 preload_bootstrap_relocate(PTOV_OFFSET);
1755 kmdp = preload_search_by_type("elf kernel");
1756 if (kmdp == NULL)
1757 kmdp = preload_search_by_type("elf64 kernel");
1758 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1759 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1760#ifdef DDB
1761 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1762 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1763#endif
1764
27af435a
SZ
1765 if (boothowto & RB_VERBOSE)
1766 bootverbose++;
1767
c8fe38ae 1768 /*
10db3cc6 1769 * Default MachIntrABI to ICU
faaf4131
MN
1770 */
1771 MachIntrABI = MachIntrABI_ICU;
9a4bd8f3 1772
d745d2b8
SZ
1773 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1774 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2e0ed166 1775 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
faaf4131
MN
1776
1777 /*
c8fe38ae
MD
1778 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1779 * and ncpus_fit_mask remain 0.
1780 */
1781 ncpus = 1;
1782 ncpus2 = 1;
1783 ncpus_fit = 1;
1784 /* Init basic tunables, hz etc */
1785 init_param1();
1786
1787 /*
1788 * make gdt memory segments
1789 */
1790 gdt_segs[GPROC0_SEL].ssd_base =
1791 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1792
1793 gd->mi.gd_prvspace = &CPU_prvspace[0];
1794
1795 for (x = 0; x < NGDT; x++) {
1796 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1797 ssdtosd(&gdt_segs[x], &gdt[x]);
1798 }
1799 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1800 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
48ffc236 1801
c8fe38ae
MD
1802 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1803 r_gdt.rd_base = (long) gdt;
1804 lgdt(&r_gdt);
1805
1806 wrmsr(MSR_FSBASE, 0); /* User value */
1807 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1808 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1809
1810 mi_gdinit(&gd->mi, 0);
1811 cpu_gdinit(gd, 0);
1812 proc0paddr = proc0paddr_buff;
1813 mi_proc0init(&gd->mi, proc0paddr);
1814 safepri = TDPRI_MAX;
1815
1816 /* spinlocks and the BGL */
1817 init_locks();
1818
1819 /* exceptions */
1820 for (x = 0; x < NIDT; x++)
1821 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1822 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1823 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1824 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1825 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1826 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1827 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1828 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1829 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1830 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1831 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1832 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1833 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1834 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1835 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1836 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1837 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1838 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1839 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1840 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1841
1842 r_idt.rd_limit = sizeof(idt0) - 1;
1843 r_idt.rd_base = (long) idt;
1844 lidt(&r_idt);
1845
1846 /*
1847 * Initialize the console before we print anything out.
1848 */
1849 cninit();
1850
1851#if JG
1852 if (metadata_missing)
1853 kprintf("WARNING: loader(8) metadata is missing!\n");
1854#endif
1855
1856#if NISA >0
e24dd6e0 1857 elcr_probe();
c8fe38ae
MD
1858 isa_defaultirq();
1859#endif
1860 rand_initialize();
1861
a3dd9120
SZ
1862 /*
1863 * Initialize IRQ mapping
1864 *
1865 * NOTE:
1866 * SHOULD be after elcr_probe()
1867 */
1868 MachIntrABI_ICU.initmap();
1869#ifdef SMP
1870 MachIntrABI_IOAPIC.initmap();
1871#endif
1872
c8fe38ae
MD
1873#ifdef DDB
1874 kdb_init();
1875 if (boothowto & RB_KDB)
1876 Debugger("Boot flags requested debugger");
1877#endif
1878
1879#if JG
1880 finishidentcpu(); /* Final stage of CPU initialization */
2883d2d8
MD
1881 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1882 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
c8fe38ae
MD
1883#endif
1884 identify_cpu(); /* Final stage of CPU initialization */
1885 initializecpu(); /* Initialize CPU registers */
1886
1887 /* make an initial tss so cpu can get interrupt stack on syscall! */
5b9f6cc4
MD
1888 gd->gd_common_tss.tss_rsp0 =
1889 (register_t)(thread0.td_kstack +
1890 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
c8fe38ae 1891 /* Ensure the stack is aligned to 16 bytes */
2883d2d8 1892 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
c8fe38ae 1893
093565f2
MD
1894 /* double fault stack */
1895 gd->gd_common_tss.tss_ist1 =
1896 (long)&gd->mi.gd_prvspace->idlestack[
1897 sizeof(gd->mi.gd_prvspace->idlestack)];
c8fe38ae
MD
1898
1899 /* Set the IO permission bitmap (empty due to tss seg limit) */
b2b3ffcd 1900 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
c8fe38ae
MD
1901
1902 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1903 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1904 gd->gd_common_tssd = *gd->gd_tss_gdt;
1905 ltr(gsel_tss);
1906
1907 /* Set up the fast syscall stuff */
1908 msr = rdmsr(MSR_EFER) | EFER_SCE;
1909 wrmsr(MSR_EFER, msr);
1910 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1911 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1912 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1913 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1914 wrmsr(MSR_STAR, msr);
1915 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1916
1917 getmemsize(kmdp, physfree);
1918 init_param2(physmem);
1919
1920 /* now running on new page tables, configured,and u/iom is accessible */
1921
1922 /* Map the message buffer. */
1923#if JG
1924 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1925 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1926#endif
1927
1928 msgbufinit(msgbufp, MSGBUF_SIZE);
1929
1930
1931 /* transfer to user mode */
1932
1933 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1934 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1935 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1936
1937 load_ds(_udatasel);
1938 load_es(_udatasel);
1939 load_fs(_udatasel);
1940
1941 /* setup proc 0's pcb */
1942 thread0.td_pcb->pcb_flags = 0;
c8fe38ae 1943 thread0.td_pcb->pcb_cr3 = KPML4phys;
c8fe38ae 1944 thread0.td_pcb->pcb_ext = 0;
d1368d1a 1945 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
c8fe38ae
MD
1946
1947 /* Location of kernel stack for locore */
1948 return ((u_int64_t)thread0.td_pcb);
1949}
1950
1951/*
1952 * Initialize machine-dependant portions of the global data structure.
1953 * Note that the global data area and cpu0's idlestack in the private
1954 * data space were allocated in locore.
1955 *
1956 * Note: the idlethread's cpl is 0
1957 *
1958 * WARNING! Called from early boot, 'mycpu' may not work yet.
1959 */
1960void
1961cpu_gdinit(struct mdglobaldata *gd, int cpu)
1962{
1963 if (cpu)
1964 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1965
1966 lwkt_init_thread(&gd->mi.gd_idlethread,
1967 gd->mi.gd_prvspace->idlestack,
1968 sizeof(gd->mi.gd_prvspace->idlestack),
fdce8919 1969 0, &gd->mi);
c8fe38ae
MD
1970 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1971 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1972 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1973 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
1974}
1975
1976int
1977is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
1978{
1979 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
1980 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
1981 return (TRUE);
1982 }
616516c8
MD
1983 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
1984 return (TRUE);
c8fe38ae
MD
1985 return (FALSE);
1986}
1987
1988struct globaldata *
1989globaldata_find(int cpu)
1990{
1991 KKASSERT(cpu >= 0 && cpu < ncpus);
1992 return(&CPU_prvspace[cpu].mdglobaldata.mi);
1993}
1994
c8fe38ae
MD
1995int
1996ptrace_set_pc(struct lwp *lp, unsigned long addr)
1997{
5b9f6cc4 1998 lp->lwp_md.md_regs->tf_rip = addr;
c8fe38ae
MD
1999 return (0);
2000}
2001
2002int
2003ptrace_single_step(struct lwp *lp)
2004{
5b9f6cc4 2005 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
c8fe38ae
MD
2006 return (0);
2007}
2008
2009int
2010fill_regs(struct lwp *lp, struct reg *regs)
2011{
c8fe38ae
MD
2012 struct trapframe *tp;
2013
2014 tp = lp->lwp_md.md_regs;
5b9f6cc4 2015 bcopy(&tp->tf_rdi, &regs->r_rdi, sizeof(*regs));
c8fe38ae
MD
2016 return (0);
2017}
2018
2019int
2020set_regs(struct lwp *lp, struct reg *regs)
2021{
c8fe38ae
MD
2022 struct trapframe *tp;
2023
2024 tp = lp->lwp_md.md_regs;
5b9f6cc4 2025 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
c8fe38ae
MD
2026 !CS_SECURE(regs->r_cs))
2027 return (EINVAL);
5b9f6cc4 2028 bcopy(&regs->r_rdi, &tp->tf_rdi, sizeof(*regs));
f2081646 2029 clear_quickret();
c8fe38ae
MD
2030 return (0);
2031}
2032
2033#ifndef CPU_DISABLE_SSE
2034static void
2035fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2036{
2037 struct env87 *penv_87 = &sv_87->sv_env;
2038 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2039 int i;
2040
2041 /* FPU control/status */
2042 penv_87->en_cw = penv_xmm->en_cw;
2043 penv_87->en_sw = penv_xmm->en_sw;
2044 penv_87->en_tw = penv_xmm->en_tw;
2045 penv_87->en_fip = penv_xmm->en_fip;
2046 penv_87->en_fcs = penv_xmm->en_fcs;
2047 penv_87->en_opcode = penv_xmm->en_opcode;
2048 penv_87->en_foo = penv_xmm->en_foo;
2049 penv_87->en_fos = penv_xmm->en_fos;
2050
2051 /* FPU registers */
2052 for (i = 0; i < 8; ++i)
2053 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
c8fe38ae
MD
2054}
2055
2056static void
2057set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2058{
2059 struct env87 *penv_87 = &sv_87->sv_env;
2060 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2061 int i;
2062
2063 /* FPU control/status */
2064 penv_xmm->en_cw = penv_87->en_cw;
2065 penv_xmm->en_sw = penv_87->en_sw;
2066 penv_xmm->en_tw = penv_87->en_tw;
2067 penv_xmm->en_fip = penv_87->en_fip;
2068 penv_xmm->en_fcs = penv_87->en_fcs;
2069 penv_xmm->en_opcode = penv_87->en_opcode;
2070 penv_xmm->en_foo = penv_87->en_foo;
2071 penv_xmm->en_fos = penv_87->en_fos;
2072
2073 /* FPU registers */
2074 for (i = 0; i < 8; ++i)
2075 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
c8fe38ae
MD
2076}
2077#endif /* CPU_DISABLE_SSE */
2078
2079int
2080fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2081{
2082#ifndef CPU_DISABLE_SSE
2083 if (cpu_fxsr) {
2084 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2085 (struct save87 *)fpregs);
2086 return (0);
2087 }
2088#endif /* CPU_DISABLE_SSE */
2089 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2090 return (0);
2091}
2092
2093int
2094set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2095{
2096#ifndef CPU_DISABLE_SSE
2097 if (cpu_fxsr) {
2098 set_fpregs_xmm((struct save87 *)fpregs,
2099 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2100 return (0);
2101 }
2102#endif /* CPU_DISABLE_SSE */
2103 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2104 return (0);
2105}
2106
2107int
2108fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2109{
2110 if (lp == NULL) {
0855a2af
JG
2111 dbregs->dr[0] = rdr0();
2112 dbregs->dr[1] = rdr1();
2113 dbregs->dr[2] = rdr2();
2114 dbregs->dr[3] = rdr3();
2115 dbregs->dr[4] = rdr4();
2116 dbregs->dr[5] = rdr5();
2117 dbregs->dr[6] = rdr6();
2118 dbregs->dr[7] = rdr7();
c8fe38ae
MD
2119 } else {
2120 struct pcb *pcb;
2121
2122 pcb = lp->lwp_thread->td_pcb;
0855a2af
JG
2123 dbregs->dr[0] = pcb->pcb_dr0;
2124 dbregs->dr[1] = pcb->pcb_dr1;
2125 dbregs->dr[2] = pcb->pcb_dr2;
2126 dbregs->dr[3] = pcb->pcb_dr3;
2127 dbregs->dr[4] = 0;
2128 dbregs->dr[5] = 0;
2129 dbregs->dr[6] = pcb->pcb_dr6;
2130 dbregs->dr[7] = pcb->pcb_dr7;
c8fe38ae
MD
2131 }
2132 return (0);
2133}
2134
2135int
2136set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2137{
2138 if (lp == NULL) {
0855a2af
JG
2139 load_dr0(dbregs->dr[0]);
2140 load_dr1(dbregs->dr[1]);
2141 load_dr2(dbregs->dr[2]);
2142 load_dr3(dbregs->dr[3]);
2143 load_dr4(dbregs->dr[4]);
2144 load_dr5(dbregs->dr[5]);
2145 load_dr6(dbregs->dr[6]);
2146 load_dr7(dbregs->dr[7]);
c8fe38ae
MD
2147 } else {
2148 struct pcb *pcb;
2149 struct ucred *ucred;
2150 int i;
0855a2af 2151 uint64_t mask1, mask2;
c8fe38ae
MD
2152
2153 /*
2154 * Don't let an illegal value for dr7 get set. Specifically,
2155 * check for undefined settings. Setting these bit patterns
2156 * result in undefined behaviour and can lead to an unexpected
2157 * TRCTRAP.
2158 */
0855a2af
JG
2159 /* JG this loop looks unreadable */
2160 /* Check 4 2-bit fields for invalid patterns.
2161 * These fields are R/Wi, for i = 0..3
2162 */
2163 /* Is 10 in LENi allowed when running in compatibility mode? */
2164 /* Pattern 10 in R/Wi might be used to indicate
2165 * breakpoint on I/O. Further analysis should be
2166 * carried to decide if it is safe and useful to
2167 * provide access to that capability
2168 */
2169 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2170 i++, mask1 <<= 4, mask2 <<= 4)
2171 if ((dbregs->dr[7] & mask1) == mask2)
c8fe38ae 2172 return (EINVAL);
c8fe38ae
MD
2173
2174 pcb = lp->lwp_thread->td_pcb;
2175 ucred = lp->lwp_proc->p_ucred;
2176
2177 /*
2178 * Don't let a process set a breakpoint that is not within the
2179 * process's address space. If a process could do this, it
2180 * could halt the system by setting a breakpoint in the kernel
2181 * (if ddb was enabled). Thus, we need to check to make sure
2182 * that no breakpoints are being enabled for addresses outside
2183 * process's address space, unless, perhaps, we were called by
2184 * uid 0.
2185 *
2186 * XXX - what about when the watched area of the user's
2187 * address space is written into from within the kernel
2188 * ... wouldn't that still cause a breakpoint to be generated
2189 * from within kernel mode?
2190 */
2191
895c1f85 2192 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
0855a2af 2193 if (dbregs->dr[7] & 0x3) {
c8fe38ae 2194 /* dr0 is enabled */
0855a2af 2195 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2196 return (EINVAL);
2197 }
2198
0855a2af 2199 if (dbregs->dr[7] & (0x3<<2)) {
c8fe38ae 2200 /* dr1 is enabled */
0855a2af 2201 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2202 return (EINVAL);
2203 }
2204
0855a2af 2205 if (dbregs->dr[7] & (0x3<<4)) {
c8fe38ae 2206 /* dr2 is enabled */
0855a2af 2207 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2208 return (EINVAL);
2209 }
2210
0855a2af 2211 if (dbregs->dr[7] & (0x3<<6)) {
c8fe38ae 2212 /* dr3 is enabled */
0855a2af 2213 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
c8fe38ae
MD
2214 return (EINVAL);
2215 }
c8fe38ae
MD
2216 }
2217
0855a2af
JG
2218 pcb->pcb_dr0 = dbregs->dr[0];
2219 pcb->pcb_dr1 = dbregs->dr[1];
2220 pcb->pcb_dr2 = dbregs->dr[2];
2221 pcb->pcb_dr3 = dbregs->dr[3];
2222 pcb->pcb_dr6 = dbregs->dr[6];
2223 pcb->pcb_dr7 = dbregs->dr[7];
c8fe38ae
MD
2224
2225 pcb->pcb_flags |= PCB_DBREGS;
2226 }
2227
2228 return (0);
2229}
2230
2231/*
2232 * Return > 0 if a hardware breakpoint has been hit, and the
2233 * breakpoint was in user space. Return 0, otherwise.
2234 */
2235int
2236user_dbreg_trap(void)
2237{
0855a2af
JG
2238 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2239 u_int64_t bp; /* breakpoint bits extracted from dr6 */
c8fe38ae
MD
2240 int nbp; /* number of breakpoints that triggered */
2241 caddr_t addr[4]; /* breakpoint addresses */
2242 int i;
2243
2244 dr7 = rdr7();
0855a2af 2245 if ((dr7 & 0xff) == 0) {
c8fe38ae
MD
2246 /*
2247 * all GE and LE bits in the dr7 register are zero,
2248 * thus the trap couldn't have been caused by the
2249 * hardware debug registers
2250 */
2251 return 0;
2252 }
2253
2254 nbp = 0;
2255 dr6 = rdr6();
0855a2af 2256 bp = dr6 & 0xf;
c8fe38ae 2257
0855a2af 2258 if (bp == 0) {
c8fe38ae
MD
2259 /*
2260 * None of the breakpoint bits are set meaning this
2261 * trap was not caused by any of the debug registers
2262 */
2263 return 0;
2264 }
2265
2266 /*
2267 * at least one of the breakpoints were hit, check to see
2268 * which ones and if any of them are user space addresses
2269 */
2270
2271 if (bp & 0x01) {
2272 addr[nbp++] = (caddr_t)rdr0();
2273 }
2274 if (bp & 0x02) {
2275 addr[nbp++] = (caddr_t)rdr1();
2276 }
2277 if (bp & 0x04) {
2278 addr[nbp++] = (caddr_t)rdr2();
2279 }
2280 if (bp & 0x08) {
2281 addr[nbp++] = (caddr_t)rdr3();
2282 }
2283
2284 for (i=0; i<nbp; i++) {
2285 if (addr[i] <
2286 (caddr_t)VM_MAX_USER_ADDRESS) {
2287 /*
2288 * addr[i] is in user space
2289 */
2290 return nbp;
2291 }
2292 }
2293
2294 /*
2295 * None of the breakpoints are in user space.
2296 */
2297 return 0;
2298}
2299
2300
2301#ifndef DDB
2302void
2303Debugger(const char *msg)
2304{
2305 kprintf("Debugger(\"%s\") called.\n", msg);
2306}
2307#endif /* no DDB */
2308
2309#ifdef DDB
2310
2311/*
2312 * Provide inb() and outb() as functions. They are normally only
2313 * available as macros calling inlined functions, thus cannot be
2314 * called inside DDB.
2315 *
2316 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2317 */
2318
2319#undef inb
2320#undef outb
2321
2322/* silence compiler warnings */
2323u_char inb(u_int);
2324void outb(u_int, u_char);
2325
2326u_char
2327inb(u_int port)
2328{
2329 u_char data;
2330 /*
2331 * We use %%dx and not %1 here because i/o is done at %dx and not at
2332 * %edx, while gcc generates inferior code (movw instead of movl)
2333 * if we tell it to load (u_short) port.
2334 */
2335 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2336 return (data);
2337}
2338
2339void
2340outb(u_int port, u_char data)
2341{
2342 u_char al;
2343 /*
2344 * Use an unnecessary assignment to help gcc's register allocator.
2345 * This make a large difference for gcc-1.40 and a tiny difference
2346 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2347 * best results. gcc-2.6.0 can't handle this.
2348 */
2349 al = data;
2350 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2351}
2352
2353#endif /* DDB */
2354
2355
2356
2357#include "opt_cpu.h"
2358
2359
2360/*
2361 * initialize all the SMP locks
2362 */
2363
2364/* critical region when masking or unmasking interupts */
2365struct spinlock_deprecated imen_spinlock;
2366
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2367/* critical region for old style disable_intr/enable_intr */
2368struct spinlock_deprecated mpintr_spinlock;
2369
2370/* critical region around INTR() routines */
2371struct spinlock_deprecated intr_spinlock;
2372
2373/* lock region used by kernel profiling */
2374struct spinlock_deprecated mcount_spinlock;
2375
2376/* locks com (tty) data/hardware accesses: a FASTINTR() */
2377struct spinlock_deprecated com_spinlock;
2378
c8fe38ae
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2379/* lock regions around the clock hardware */
2380struct spinlock_deprecated clock_spinlock;
2381
c8fe38ae
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2382static void
2383init_locks(void)
2384{
b5d16701 2385#ifdef SMP
c8fe38ae 2386 /*
b5d16701 2387 * Get the initial mplock with a count of 1 for the BSP.
c8fe38ae
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2388 * This uses a LOGICAL cpu ID, ie BSP == 0.
2389 */
c8fe38ae
MD
2390 cpu_get_initial_mplock();
2391#endif
2392 /* DEPRECATED */
2393 spin_lock_init(&mcount_spinlock);
c8fe38ae
MD
2394 spin_lock_init(&intr_spinlock);
2395 spin_lock_init(&mpintr_spinlock);
2396 spin_lock_init(&imen_spinlock);
c8fe38ae
MD
2397 spin_lock_init(&com_spinlock);
2398 spin_lock_init(&clock_spinlock);
c8fe38ae
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2399
2400 /* our token pool needs to work early */
2401 lwkt_token_pool_init();
2402}
2403