[dragonfly.git] / sys / platform / pc32 / icu / icu_abi.c

/*
 * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
 * Copyright (c) 1991 The Regents of the University of California.
 * All rights reserved.
 * 
 * This code is derived from software contributed to The DragonFly Project
 * by Matthew Dillon <dillon@backplane.com>
 *
 * This code is derived from software contributed to Berkeley by
 * William Jolitz.
 * 
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 * 3. Neither the name of The DragonFly Project nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific, prior written permission.
 * 
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
 */

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/machintr.h>
#include <sys/interrupt.h>
#include <sys/bus.h>

#include <machine/segments.h>
#include <machine/md_var.h>
#include <machine/intr_machdep.h>
#include <machine/globaldata.h>
#include <machine/smp.h>

#include <sys/thread2.h>

#include <machine_base/apic/ioapic_abi.h>
#include <machine_base/isa/elcr_var.h>

#include "icu.h"
#include "icu_ipl.h"

extern inthand_t
	IDTVEC(icu_intr0),	IDTVEC(icu_intr1),
	IDTVEC(icu_intr2),	IDTVEC(icu_intr3),
	IDTVEC(icu_intr4),	IDTVEC(icu_intr5),
	IDTVEC(icu_intr6),	IDTVEC(icu_intr7),
	IDTVEC(icu_intr8),	IDTVEC(icu_intr9),
	IDTVEC(icu_intr10),	IDTVEC(icu_intr11),
	IDTVEC(icu_intr12),	IDTVEC(icu_intr13),
	IDTVEC(icu_intr14),	IDTVEC(icu_intr15);

static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
	&IDTVEC(icu_intr0),	&IDTVEC(icu_intr1),
	&IDTVEC(icu_intr2),	&IDTVEC(icu_intr3),
	&IDTVEC(icu_intr4),	&IDTVEC(icu_intr5),
	&IDTVEC(icu_intr6),	&IDTVEC(icu_intr7),
	&IDTVEC(icu_intr8),	&IDTVEC(icu_intr9),
	&IDTVEC(icu_intr10),	&IDTVEC(icu_intr11),
	&IDTVEC(icu_intr12),	&IDTVEC(icu_intr13),
	&IDTVEC(icu_intr14),	&IDTVEC(icu_intr15)
};

static struct icu_irqmap {
	int			im_type;	/* ICU_IMT_ */
	enum intr_trigger	im_trig;
} icu_irqmaps[MAX_HARDINTS];	/* XXX MAX_HARDINTS may not be correct */

#define ICU_IMT_UNUSED		0	/* KEEP THIS */
#define ICU_IMT_RESERVED	1
#define ICU_IMT_LINE		2
#define ICU_IMT_SYSCALL		3

extern void	ICU_INTREN(int);
extern void	ICU_INTRDIS(int);

static int	icu_vectorctl(int, int, int);
static int	icu_setvar(int, const void *);
static int	icu_getvar(int, void *);
static void	icu_finalize(void);
static void	icu_cleanup(void);
static void	icu_setdefault(void);
static void	icu_stabilize(void);
static void	icu_initmap(void);

struct machintr_abi MachIntrABI_ICU = {
	MACHINTR_ICU,
	.intrdis	= ICU_INTRDIS,
	.intren		= ICU_INTREN,
	.vectorctl	= icu_vectorctl,
	.setvar		= icu_setvar,
	.getvar		= icu_getvar,
	.finalize	= icu_finalize,
	.cleanup	= icu_cleanup,
	.setdefault	= icu_setdefault,
	.stabilize	= icu_stabilize,
	.initmap	= icu_initmap
};

static int	icu_imcr_present;

/*
 * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
 */
static int
icu_setvar(int varid, const void *buf)
{
	int error = 0;
	
	switch (varid) {
	case MACHINTR_VAR_IMCR_PRESENT:
		icu_imcr_present = *(const int *)buf;
		break;

	default:
		error = ENOENT;
		break;
	}
	return error;
}

static int
icu_getvar(int varid, void *buf)
{
	int error = 0;
	
	switch (varid) {
	case MACHINTR_VAR_IMCR_PRESENT:
		*(int *)buf = icu_imcr_present;
		break;

	default:
		error = ENOENT;
		break;
	}
	return error;
}

/*
 * Called before interrupts are physically enabled
 */
static void
icu_stabilize(void)
{
	int intr;

	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
		machintr_intrdis(intr);
	machintr_intren(ICU_IRQ_SLAVE);
}

/*
 * Called after interrupts physically enabled but before the
 * critical section is released.
 */
static void
icu_cleanup(void)
{
	bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
}

/*
 * Called after stablize and cleanup; critical section is not
 * held and interrupts are not physically disabled.
 *
 * For SMP:
 * Further delayed after BSP's LAPIC is initialized
 */
static void
icu_finalize(void)
{
	KKASSERT(MachIntrABI.type == MACHINTR_ICU);

#ifdef SMP
	if (apic_io_enable) {
		/*
		 * MachIntrABI switching will happen in
		 * MachIntrABI_IOAPIC.finalize()
		 */
		MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
					  &icu_imcr_present);
		MachIntrABI_IOAPIC.finalize();
		return;
	}

	/*
	 * If an IMCR is present, programming bit 0 disconnects the 8259
	 * from the BSP.  The 8259 may still be connected to LINT0 on the
	 * BSP's LAPIC.
	 *
	 * If we are running SMP the LAPIC is active, try to use virtual
	 * wire mode so we can use other interrupt sources within the LAPIC
	 * in addition to the 8259.
	 */
	if (icu_imcr_present) {
		u_long ef;

		crit_enter();

		ef = read_eflags();
		cpu_disable_intr();

		outb(0x22, 0x70);
		outb(0x23, 0x01);

		write_eflags(ef);

		crit_exit();
	}
#endif	/* SMP */
}

static int
icu_vectorctl(int op, int intr, int flags)
{
	int error;
	u_long ef;

	if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
		return EINVAL;

	ef = read_eflags();
	cpu_disable_intr();
	error = 0;

	switch (op) {
	case MACHINTR_VECTOR_SETUP:
		setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
		       SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
		machintr_intren(intr);
		break;

	case MACHINTR_VECTOR_TEARDOWN:
		machintr_intrdis(intr);
		setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
		       SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
		break;

	default:
		error = EOPNOTSUPP;
		break;
	}
	write_eflags(ef);
	return error;
}

static void
icu_setdefault(void)
{
	int intr;

	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
		if (intr == ICU_IRQ_SLAVE)
			continue;
		setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
		       SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
	}
}

static void
icu_initmap(void)
{
	int i;

	for (i = 0; i < ICU_HWI_VECTORS; ++i)
		icu_irqmaps[i].im_type = ICU_IMT_LINE;
	icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;

	if (elcr_found) {
		for (i = 0; i < ICU_HWI_VECTORS; ++i)
			icu_irqmaps[i].im_trig = elcr_read_trigger(i);
	} else {
		for (i = 0; i < ICU_HWI_VECTORS; ++i) {
			switch (i) {
			case 0:
			case 1:
			case 2:
			case 8:
			case 13:
				icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
				break;

			default:
				icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
				break;
			}
		}
	}
	icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
}
Commit	Line	Data
06f5be02 MD	1	/*
06f5be02 MD	2	* Copyright (c) 2005 The DragonFly Project. All rights reserved.
10ff1029 MD	3	* Copyright (c) 1991 The Regents of the University of California.
10ff1029 MD	4	* All rights reserved.
06f5be02 MD	5	*
	6	* This code is derived from software contributed to The DragonFly Project
	7	* by Matthew Dillon <dillon@backplane.com>
10ff1029 MD	8	*
	9	* This code is derived from software contributed to Berkeley by
	10	* William Jolitz.
06f5be02 MD	11	*
	12	* Redistribution and use in source and binary forms, with or without
	13	* modification, are permitted provided that the following conditions
	14	* are met:
	15	*
	16	* 1. Redistributions of source code must retain the above copyright
	17	* notice, this list of conditions and the following disclaimer.
	18	* 2. Redistributions in binary form must reproduce the above copyright
	19	* notice, this list of conditions and the following disclaimer in
	20	* the documentation and/or other materials provided with the
	21	* distribution.
	22	* 3. Neither the name of The DragonFly Project nor the names of its
	23	* contributors may be used to endorse or promote products derived
	24	* from this software without specific, prior written permission.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	27	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	28	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
	29	* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
	30	* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	31	* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
	32	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	33	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
	34	* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
	35	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
	36	* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	37	* SUCH DAMAGE.
	38	*
d916dbc1	39	* $DragonFly: src/sys/platform/pc32/icu/icu_abi.c,v 1.14 2007/07/07 12:13:47 sephe Exp $
06f5be02 MD	40	*/
06f5be02 MD	41
37e7efec MD	42	#include <sys/param.h>
	43	#include <sys/systm.h>
	44	#include <sys/kernel.h>
	45	#include <sys/machintr.h>
10ff1029 MD	46	#include <sys/interrupt.h>
	47	#include <sys/bus.h>
	48
	49	#include <machine/segments.h>
	50	#include <machine/md_var.h>
87cf6827	51	#include <machine/intr_machdep.h>
0b692e79	52	#include <machine/globaldata.h>
10db3cc6	53	#include <machine/smp.h>
0b692e79 MD	54
0b692e79 MD	55	#include <sys/thread2.h>
5f456c40	56
9e0e3f85	57	#include <machine_base/apic/ioapic_abi.h>
a3dd9120	58	#include <machine_base/isa/elcr_var.h>
9e0e3f85	59
5f456c40 MD	60	#include "icu.h"
5f456c40 MD	61	#include "icu_ipl.h"
37e7efec	62
10ff1029	63	extern inthand_t
081be8a5 SZ	64	IDTVEC(icu_intr0), IDTVEC(icu_intr1),
	65	IDTVEC(icu_intr2), IDTVEC(icu_intr3),
	66	IDTVEC(icu_intr4), IDTVEC(icu_intr5),
	67	IDTVEC(icu_intr6), IDTVEC(icu_intr7),
	68	IDTVEC(icu_intr8), IDTVEC(icu_intr9),
	69	IDTVEC(icu_intr10), IDTVEC(icu_intr11),
	70	IDTVEC(icu_intr12), IDTVEC(icu_intr13),
	71	IDTVEC(icu_intr14), IDTVEC(icu_intr15);
10ff1029	72
081be8a5 SZ	73	static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
	74	&IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
	75	&IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
	76	&IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
	77	&IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
	78	&IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
	79	&IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
	80	&IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
	81	&IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
10ff1029 MD	82	};
10ff1029 MD	83
a3dd9120 SZ	84	static struct icu_irqmap {
	85	int im_type; /* ICU_IMT_ */
	86	enum intr_trigger im_trig;
	87	} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
	88
	89	#define ICU_IMT_UNUSED 0 /* KEEP THIS */
	90	#define ICU_IMT_RESERVED 1
	91	#define ICU_IMT_LINE 2
474ba684	92	#define ICU_IMT_SYSCALL 3
a3dd9120	93
10db3cc6 SZ	94	extern void ICU_INTREN(int);
	95	extern void ICU_INTRDIS(int);
	96
	97	static int icu_vectorctl(int, int, int);
	98	static int icu_setvar(int, const void *);
	99	static int icu_getvar(int, void *);
	100	static void icu_finalize(void);
	101	static void icu_cleanup(void);
	102	static void icu_setdefault(void);
7bf5fa56	103	static void icu_stabilize(void);
a3dd9120	104	static void icu_initmap(void);
10db3cc6	105
30c5f287	106	struct machintr_abi MachIntrABI_ICU = {
54e1df6b SZ	107	MACHINTR_ICU,
	108	.intrdis = ICU_INTRDIS,
	109	.intren = ICU_INTREN,
	110	.vectorctl = icu_vectorctl,
	111	.setvar = icu_setvar,
	112	.getvar = icu_getvar,
	113	.finalize = icu_finalize,
10db3cc6	114	.cleanup = icu_cleanup,
7bf5fa56	115	.setdefault = icu_setdefault,
a3dd9120 SZ	116	.stabilize = icu_stabilize,
a3dd9120 SZ	117	.initmap = icu_initmap
37e7efec MD	118	};
37e7efec MD	119
54e1df6b	120	static int icu_imcr_present;
e96ee753	121
97359a5b MD	122	/*
	123	* WARNING! SMP builds can use the ICU now so this code must be MP safe.
	124	*/
54e1df6b	125	static int
d916dbc1	126	icu_setvar(int varid, const void *buf)
37e7efec	127	{
54e1df6b	128	int error = 0;
e96ee753	129
54e1df6b SZ	130	switch (varid) {
	131	case MACHINTR_VAR_IMCR_PRESENT:
	132	icu_imcr_present = (const int )buf;
	133	break;
	134
	135	default:
	136	error = ENOENT;
	137	break;
	138	}
	139	return error;
37e7efec MD	140	}
37e7efec MD	141
54e1df6b	142	static int
d916dbc1	143	icu_getvar(int varid, void *buf)
37e7efec	144	{
54e1df6b	145	int error = 0;
e96ee753	146
54e1df6b SZ	147	switch (varid) {
	148	case MACHINTR_VAR_IMCR_PRESENT:
	149	(int )buf = icu_imcr_present;
	150	break;
	151
	152	default:
	153	error = ENOENT;
	154	break;
	155	}
	156	return error;
37e7efec MD	157	}
37e7efec MD	158
0b692e79 MD	159	/*
	160	* Called before interrupts are physically enabled
	161	*/
37e7efec	162	static void
7bf5fa56	163	icu_stabilize(void)
37e7efec	164	{
54e1df6b SZ	165	int intr;
54e1df6b SZ	166
7bf5fa56 SZ	167	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
	168	machintr_intrdis(intr);
	169	machintr_intren(ICU_IRQ_SLAVE);
	170	}
	171
	172	/*
	173	* Called after interrupts physically enabled but before the
	174	* critical section is released.
	175	*/
	176	static void
	177	icu_cleanup(void)
	178	{
	179	bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
	180	}
	181
	182	/*
	183	* Called after stablize and cleanup; critical section is not
	184	* held and interrupts are not physically disabled.
	185	*
	186	* For SMP:
	187	* Further delayed after BSP's LAPIC is initialized
	188	*/
	189	static void
	190	icu_finalize(void)
	191	{
	192	KKASSERT(MachIntrABI.type == MACHINTR_ICU);
	193
10db3cc6 SZ	194	#ifdef SMP
10db3cc6 SZ	195	if (apic_io_enable) {
7bf5fa56 SZ	196	/*
	197	* MachIntrABI switching will happen in
	198	* MachIntrABI_IOAPIC.finalize()
	199	*/
9e0e3f85 SZ	200	MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
	201	&icu_imcr_present);
	202	MachIntrABI_IOAPIC.finalize();
10db3cc6 SZ	203	return;
10db3cc6 SZ	204	}
54e1df6b	205
54e1df6b SZ	206	/*
	207	* If an IMCR is present, programming bit 0 disconnects the 8259
	208	* from the BSP. The 8259 may still be connected to LINT0 on the
	209	* BSP's LAPIC.
	210	*
	211	* If we are running SMP the LAPIC is active, try to use virtual
	212	* wire mode so we can use other interrupt sources within the LAPIC
	213	* in addition to the 8259.
	214	*/
	215	if (icu_imcr_present) {
7bf5fa56 SZ	216	u_long ef;
	217
	218	crit_enter();
	219
	220	ef = read_eflags();
	221	cpu_disable_intr();
	222
54e1df6b SZ	223	outb(0x22, 0x70);
54e1df6b SZ	224	outb(0x23, 0x01);
37e7efec	225
7bf5fa56 SZ	226	write_eflags(ef);
	227
	228	crit_exit();
	229	}
	230	#endif /* SMP */
0b692e79 MD	231	}
0b692e79 MD	232
54e1df6b	233	static int
10ff1029 MD	234	icu_vectorctl(int op, int intr, int flags)
10ff1029 MD	235	{
54e1df6b SZ	236	int error;
	237	u_long ef;
	238
	239	if (intr < 0 \|\| intr >= ICU_HWI_VECTORS \|\| intr == ICU_IRQ_SLAVE)
	240	return EINVAL;
	241
	242	ef = read_eflags();
	243	cpu_disable_intr();
	244	error = 0;
	245
	246	switch (op) {
	247	case MACHINTR_VECTOR_SETUP:
081be8a5	248	setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b SZ	249	SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
	250	machintr_intren(intr);
	251	break;
	252
	253	case MACHINTR_VECTOR_TEARDOWN:
10db3cc6	254	machintr_intrdis(intr);
081be8a5	255	setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
54e1df6b	256	SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
54e1df6b SZ	257	break;
	258
	259	default:
	260	error = EOPNOTSUPP;
	261	break;
	262	}
	263	write_eflags(ef);
	264	return error;
10ff1029	265	}
10db3cc6 SZ	266
	267	static void
	268	icu_setdefault(void)
	269	{
	270	int intr;
	271
	272	for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
	273	if (intr == ICU_IRQ_SLAVE)
	274	continue;
	275	setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYS386IGT,
	276	SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
	277	}
	278	}
a3dd9120 SZ	279
	280	static void
	281	icu_initmap(void)
	282	{
	283	int i;
	284
	285	for (i = 0; i < ICU_HWI_VECTORS; ++i)
	286	icu_irqmaps[i].im_type = ICU_IMT_LINE;
	287	icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
	288
	289	if (elcr_found) {
	290	for (i = 0; i < ICU_HWI_VECTORS; ++i)
	291	icu_irqmaps[i].im_trig = elcr_read_trigger(i);
	292	} else {
	293	for (i = 0; i < ICU_HWI_VECTORS; ++i) {
	294	switch (i) {
	295	case 0:
	296	case 1:
	297	case 2:
	298	case 8:
	299	case 13:
	300	icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
	301	break;
	302
	303	default:
	304	icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
	305	break;
	306	}
	307	}
	308	}
474ba684	309	icu_irqmaps[IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type = ICU_IMT_SYSCALL;
a3dd9120	310	}