irqmap: Consume the syscall entry in irqmap
[dragonfly.git] / sys / platform / pc64 / icu / icu_abi.c
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1/*
2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2005,2008 The DragonFly Project.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
8 *
9 * This code is derived from software contributed to Berkeley by
10 * William Jolitz.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
21 * distribution.
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * $DragonFly: src/sys/platform/pc64/icu/icu_abi.c,v 1.1 2008/08/29 17:07:16 dillon Exp $
40 */
41
42#include <sys/param.h>
43#include <sys/systm.h>
44#include <sys/kernel.h>
45#include <sys/machintr.h>
46#include <sys/interrupt.h>
47#include <sys/bus.h>
48
49#include <machine/segments.h>
50#include <machine/md_var.h>
57a9c56b 51#include <machine/intr_machdep.h>
c8fe38ae 52#include <machine/globaldata.h>
10db3cc6 53#include <machine/smp.h>
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54
55#include <sys/thread2.h>
56
9e0e3f85 57#include <machine_base/apic/ioapic_abi.h>
a3dd9120 58#include <machine_base/isa/elcr_var.h>
9e0e3f85 59
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60#include "icu.h"
61#include "icu_ipl.h"
62
c8fe38ae 63extern inthand_t
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64 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
65 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
66 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
67 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
68 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
69 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
70 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
71 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
c8fe38ae 72
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73static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
74 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
75 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
76 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
77 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
78 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
79 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
80 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
81 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
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82};
83
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84static struct icu_irqmap {
85 int im_type; /* ICU_IMT_ */
86 enum intr_trigger im_trig;
87} icu_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
88
89#define ICU_IMT_UNUSED 0 /* KEEP THIS */
90#define ICU_IMT_RESERVED 1
91#define ICU_IMT_LINE 2
474ba684 92#define ICU_IMT_SYSCALL 3
a3dd9120 93
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94extern void ICU_INTREN(int);
95extern void ICU_INTRDIS(int);
96
97static int icu_vectorctl(int, int, int);
98static int icu_setvar(int, const void *);
99static int icu_getvar(int, void *);
100static void icu_finalize(void);
101static void icu_cleanup(void);
102static void icu_setdefault(void);
7bf5fa56 103static void icu_stabilize(void);
a3dd9120 104static void icu_initmap(void);
10db3cc6 105
faaf4131 106struct machintr_abi MachIntrABI_ICU = {
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107 MACHINTR_ICU,
108 .intrdis = ICU_INTRDIS,
109 .intren = ICU_INTREN,
110 .vectorctl = icu_vectorctl,
111 .setvar = icu_setvar,
112 .getvar = icu_getvar,
113 .finalize = icu_finalize,
10db3cc6 114 .cleanup = icu_cleanup,
7bf5fa56 115 .setdefault = icu_setdefault,
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116 .stabilize = icu_stabilize,
117 .initmap = icu_initmap
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118};
119
339478ac 120static int icu_imcr_present;
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121
122/*
123 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
124 */
339478ac 125static int
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126icu_setvar(int varid, const void *buf)
127{
339478ac 128 int error = 0;
c8fe38ae 129
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130 switch(varid) {
131 case MACHINTR_VAR_IMCR_PRESENT:
132 icu_imcr_present = *(const int *)buf;
133 break;
134
135 default:
136 error = ENOENT;
137 break;
138 }
139 return error;
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140}
141
339478ac 142static int
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143icu_getvar(int varid, void *buf)
144{
339478ac 145 int error = 0;
c8fe38ae 146
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147 switch(varid) {
148 case MACHINTR_VAR_IMCR_PRESENT:
149 *(int *)buf = icu_imcr_present;
150 break;
151
152 default:
153 error = ENOENT;
154 break;
155 }
156 return error;
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157}
158
159/*
160 * Called before interrupts are physically enabled
161 */
162static void
7bf5fa56 163icu_stabilize(void)
c8fe38ae 164{
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165 int intr;
166
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167 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
168 machintr_intrdis(intr);
169 machintr_intren(ICU_IRQ_SLAVE);
170}
171
172/*
173 * Called after interrupts physically enabled but before the
174 * critical section is released.
175 */
176static void
177icu_cleanup(void)
178{
179 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
180}
181
182/*
183 * Called after stablize and cleanup; critical section is not
184 * held and interrupts are not physically disabled.
185 *
186 * For SMP:
187 * Further delayed after BSP's LAPIC is initialized
188 */
189static void
190icu_finalize(void)
191{
192 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
193
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194#ifdef SMP
195 if (apic_io_enable) {
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196 /*
197 * MachIntrABI switching will happen in
198 * MachIntrABI_IOAPIC.finalize()
199 */
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200 MachIntrABI_IOAPIC.setvar(MACHINTR_VAR_IMCR_PRESENT,
201 &icu_imcr_present);
202 MachIntrABI_IOAPIC.finalize();
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203 return;
204 }
339478ac 205
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206 /*
207 * If an IMCR is present, programming bit 0 disconnects the 8259
208 * from the BSP. The 8259 may still be connected to LINT0 on the
209 * BSP's LAPIC.
210 *
211 * If we are running SMP the LAPIC is active, try to use virtual
212 * wire mode so we can use other interrupt sources within the LAPIC
213 * in addition to the 8259.
214 */
215 if (icu_imcr_present) {
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216 register_t ef;
217
218 crit_enter();
219
220 ef = read_rflags();
221 cpu_disable_intr();
222
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223 outb(0x22, 0x70);
224 outb(0x23, 0x01);
c8fe38ae 225
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226 write_rflags(ef);
227
228 crit_exit();
229 }
230#endif /* SMP */
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231}
232
339478ac 233static int
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234icu_vectorctl(int op, int intr, int flags)
235{
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236 int error;
237 register_t ef;
238
239 if (intr < 0 || intr >= ICU_HWI_VECTORS || intr == ICU_IRQ_SLAVE)
240 return EINVAL;
241
242 ef = read_rflags();
243 cpu_disable_intr();
244 error = 0;
245
246 switch(op) {
247 case MACHINTR_VECTOR_SETUP:
35e45e47 248 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
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249 SEL_KPL, 0);
250 machintr_intren(intr);
251 break;
252
253 case MACHINTR_VECTOR_TEARDOWN:
10db3cc6 254 machintr_intrdis(intr);
35e45e47 255 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
339478ac 256 SEL_KPL, 0);
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257 break;
258
259 default:
260 error = EOPNOTSUPP;
261 break;
262 }
263 write_rflags(ef);
264 return error;
c8fe38ae 265}
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266
267static void
268icu_setdefault(void)
269{
270 int intr;
271
272 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
273 if (intr == ICU_IRQ_SLAVE)
274 continue;
275 setidt(IDT_OFFSET + intr, icu_intr[intr], SDT_SYSIGT,
276 SEL_KPL, 0);
277 }
278}
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279
280static void
281icu_initmap(void)
282{
283 int i;
284
285 for (i = 0; i < ICU_HWI_VECTORS; ++i)
286 icu_irqmaps[i].im_type = ICU_IMT_LINE;
287 icu_irqmaps[ICU_IRQ_SLAVE].im_type = ICU_IMT_RESERVED;
288
289 if (elcr_found) {
290 for (i = 0; i < ICU_HWI_VECTORS; ++i)
291 icu_irqmaps[i].im_trig = elcr_read_trigger(i);
292 } else {
293 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
294 switch (i) {
295 case 0:
296 case 1:
297 case 2:
298 case 8:
299 case 13:
300 icu_irqmaps[i].im_trig = INTR_TRIGGER_EDGE;
301 break;
302
303 default:
304 icu_irqmaps[i].im_trig = INTR_TRIGGER_LEVEL;
305 break;
306 }
307 }
308 }
474ba684 309 icu_irqmaps[i].im_type = ICU_IMT_SYSCALL;
a3dd9120 310}