Increase the MSGBUF_SIZE from 32K to 64K, boot verbose messages don't
[dragonfly.git] / sys / platform / pc32 / i386 / machdep.c
CommitLineData
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1/*-
2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
38 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
065b709a 39 * $DragonFly: src/sys/platform/pc32/i386/machdep.c,v 1.79 2005/10/07 21:55:15 corecode Exp $
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40 */
41
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42#include "use_apm.h"
43#include "use_ether.h"
44#include "use_npx.h"
45#include "use_isa.h"
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46#include "opt_atalk.h"
47#include "opt_compat.h"
48#include "opt_cpu.h"
49#include "opt_ddb.h"
50#include "opt_directio.h"
51#include "opt_inet.h"
52#include "opt_ipx.h"
53#include "opt_maxmem.h"
54#include "opt_msgbuf.h"
55#include "opt_perfmon.h"
56#include "opt_swap.h"
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57#include "opt_userconfig.h"
58
59#include <sys/param.h>
60#include <sys/systm.h>
61#include <sys/sysproto.h>
62#include <sys/signalvar.h>
63#include <sys/kernel.h>
64#include <sys/linker.h>
65#include <sys/malloc.h>
66#include <sys/proc.h>
67#include <sys/buf.h>
68#include <sys/reboot.h>
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69#include <sys/mbuf.h>
70#include <sys/msgbuf.h>
71#include <sys/sysent.h>
72#include <sys/sysctl.h>
73#include <sys/vmmeter.h>
74#include <sys/bus.h>
a722be49 75#include <sys/upcall.h>
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76
77#include <vm/vm.h>
78#include <vm/vm_param.h>
79#include <sys/lock.h>
80#include <vm/vm_kern.h>
81#include <vm/vm_object.h>
82#include <vm/vm_page.h>
83#include <vm/vm_map.h>
84#include <vm/vm_pager.h>
85#include <vm/vm_extern.h>
86
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87#include <sys/thread2.h>
88
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89#include <sys/user.h>
90#include <sys/exec.h>
91#include <sys/cons.h>
92
93#include <ddb/ddb.h>
94
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95#include <machine/cpu.h>
96#include <machine/reg.h>
97#include <machine/clock.h>
98#include <machine/specialreg.h>
99#include <machine/bootinfo.h>
100#include <machine/ipl.h>
101#include <machine/md_var.h>
102#include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
85100692 103#include <machine/globaldata.h> /* CPU_prvspace */
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104#ifdef SMP
105#include <machine/smp.h>
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106#endif
107#ifdef PERFMON
108#include <machine/perfmon.h>
109#endif
110#include <machine/cputypes.h>
111
112#ifdef OLD_BUS_ARCH
1f2de5d4 113#include <bus/isa/i386/isa_device.h>
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114#endif
115#include <i386/isa/intr_machdep.h>
1f2de5d4 116#include <bus/isa/rtc.h>
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117#include <machine/vm86.h>
118#include <sys/random.h>
119#include <sys/ptrace.h>
120#include <machine/sigframe.h>
121
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122#define PHYSMAP_ENTRIES 10
123
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124extern void init386 (int first);
125extern void dblfault_handler (void);
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126
127extern void printcpuinfo(void); /* XXX header file */
128extern void finishidentcpu(void);
129extern void panicifcpuunsupported(void);
130extern void initializecpu(void);
131
3ae0cd58 132static void cpu_startup (void *);
642a6e88 133#ifndef CPU_DISABLE_SSE
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134static void set_fpregs_xmm (struct save87 *, struct savexmm *);
135static void fill_fpregs_xmm (struct savexmm *, struct save87 *);
642a6e88 136#endif /* CPU_DISABLE_SSE */
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137#ifdef DIRECTIO
138extern void ffs_rawread_setup(void);
139#endif /* DIRECTIO */
8a8d5d85 140static void init_locks(void);
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141
142SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
143
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144int _udatasel, _ucodesel;
145u_int atdevbase;
146
147#if defined(SWTCH_OPTIM_STATS)
148extern int swtch_optim_stats;
149SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
150 CTLFLAG_RD, &swtch_optim_stats, 0, "");
151SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
152 CTLFLAG_RD, &tlb_flush_count, 0, "");
153#endif
154
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155int physmem = 0;
156int cold = 1;
157
158static int
159sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
160{
161 int error = sysctl_handle_int(oidp, 0, ctob(physmem), req);
162 return (error);
163}
164
165SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_INT|CTLFLAG_RD,
166 0, 0, sysctl_hw_physmem, "IU", "");
167
168static int
169sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
170{
171 int error = sysctl_handle_int(oidp, 0,
12e4aaff 172 ctob(physmem - vmstats.v_wire_count), req);
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173 return (error);
174}
175
176SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
177 0, 0, sysctl_hw_usermem, "IU", "");
178
179static int
180sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
181{
182 int error = sysctl_handle_int(oidp, 0,
183 i386_btop(avail_end - avail_start), req);
184 return (error);
185}
186
187SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
188 0, 0, sysctl_hw_availpages, "I", "");
189
190static int
191sysctl_machdep_msgbuf(SYSCTL_HANDLER_ARGS)
192{
193 int error;
194
195 /* Unwind the buffer, so that it's linear (possibly starting with
196 * some initial nulls).
197 */
198 error=sysctl_handle_opaque(oidp,msgbufp->msg_ptr+msgbufp->msg_bufr,
199 msgbufp->msg_size-msgbufp->msg_bufr,req);
200 if(error) return(error);
201 if(msgbufp->msg_bufr>0) {
202 error=sysctl_handle_opaque(oidp,msgbufp->msg_ptr,
203 msgbufp->msg_bufr,req);
204 }
205 return(error);
206}
207
208SYSCTL_PROC(_machdep, OID_AUTO, msgbuf, CTLTYPE_STRING|CTLFLAG_RD,
209 0, 0, sysctl_machdep_msgbuf, "A","Contents of kernel message buffer");
210
211static int msgbuf_clear;
212
213static int
214sysctl_machdep_msgbuf_clear(SYSCTL_HANDLER_ARGS)
215{
216 int error;
217 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
218 req);
219 if (!error && req->newptr) {
220 /* Clear the buffer and reset write pointer */
221 bzero(msgbufp->msg_ptr,msgbufp->msg_size);
222 msgbufp->msg_bufr=msgbufp->msg_bufx=0;
223 msgbuf_clear=0;
224 }
225 return (error);
226}
227
228SYSCTL_PROC(_machdep, OID_AUTO, msgbuf_clear, CTLTYPE_INT|CTLFLAG_RW,
229 &msgbuf_clear, 0, sysctl_machdep_msgbuf_clear, "I",
230 "Clear kernel message buffer");
231
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232int bootverbose = 0;
233vm_paddr_t Maxmem = 0;
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234long dumplo;
235
ff1a75a1 236vm_paddr_t phys_avail[PHYSMAP_ENTRIES*2+2];
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237
238static vm_offset_t buffer_sva, buffer_eva;
239vm_offset_t clean_sva, clean_eva;
240static vm_offset_t pager_sva, pager_eva;
241static struct trapframe proc0_tf;
242
243static void
244cpu_startup(dummy)
245 void *dummy;
246{
c9faf524 247 caddr_t v;
cb840899 248 vm_offset_t minaddr;
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249 vm_offset_t maxaddr;
250 vm_size_t size = 0;
251 int firstaddr;
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252
253 if (boothowto & RB_VERBOSE)
254 bootverbose++;
255
256 /*
257 * Good {morning,afternoon,evening,night}.
258 */
259 printf("%s", version);
260 startrtclock();
261 printcpuinfo();
262 panicifcpuunsupported();
263#ifdef PERFMON
264 perfmon_init();
265#endif
6ef943a3 266 printf("real memory = %llu (%lluK bytes)\n", ptoa(Maxmem), ptoa(Maxmem) / 1024);
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267 /*
268 * Display any holes after the first chunk of extended memory.
269 */
270 if (bootverbose) {
271 int indx;
272
273 printf("Physical memory chunk(s):\n");
274 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
6ef943a3 275 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
984263bc 276
6ef943a3 277 printf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
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278 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
279 size1 / PAGE_SIZE);
280 }
281 }
282
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283 /*
284 * Allocate space for system data structures.
285 * The first available kernel virtual address is in "v".
286 * As pages of kernel virtual memory are allocated, "v" is incremented.
287 * As pages of memory are allocated and cleared,
288 * "firstaddr" is incremented.
289 * An index into the kernel page table corresponding to the
290 * virtual memory address maintained in "v" is kept in "mapaddr".
291 */
292
293 /*
294 * Make two passes. The first pass calculates how much memory is
295 * needed and allocates it. The second pass assigns virtual
296 * addresses to the various data structures.
297 */
298 firstaddr = 0;
299again:
300 v = (caddr_t)firstaddr;
301
302#define valloc(name, type, num) \
303 (name) = (type *)v; v = (caddr_t)((name)+(num))
304#define valloclim(name, type, num, lim) \
305 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
306
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307 /*
308 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
309 * For the first 64MB of ram nominally allocate sufficient buffers to
310 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
311 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
312 * the buffer cache we limit the eventual kva reservation to
313 * maxbcache bytes.
314 *
315 * factor represents the 1/4 x ram conversion.
316 */
317 if (nbuf == 0) {
318 int factor = 4 * BKVASIZE / 1024;
319 int kbytes = physmem * (PAGE_SIZE / 1024);
320
321 nbuf = 50;
322 if (kbytes > 4096)
323 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
324 if (kbytes > 65536)
325 nbuf += (kbytes - 65536) * 2 / (factor * 5);
326 if (maxbcache && nbuf > maxbcache / BKVASIZE)
327 nbuf = maxbcache / BKVASIZE;
328 }
329
330 /*
331 * Do not allow the buffer_map to be more then 1/2 the size of the
332 * kernel_map.
333 */
334 if (nbuf > (kernel_map->max_offset - kernel_map->min_offset) /
335 (BKVASIZE * 2)) {
336 nbuf = (kernel_map->max_offset - kernel_map->min_offset) /
337 (BKVASIZE * 2);
338 printf("Warning: nbufs capped at %d\n", nbuf);
339 }
340
341 nswbuf = max(min(nbuf/4, 256), 16);
342#ifdef NSWBUF_MIN
343 if (nswbuf < NSWBUF_MIN)
344 nswbuf = NSWBUF_MIN;
345#endif
346#ifdef DIRECTIO
347 ffs_rawread_setup();
348#endif
349
350 valloc(swbuf, struct buf, nswbuf);
351 valloc(buf, struct buf, nbuf);
352 v = bufhashinit(v);
353
354 /*
355 * End of first pass, size has been calculated so allocate memory
356 */
357 if (firstaddr == 0) {
358 size = (vm_size_t)(v - firstaddr);
359 firstaddr = (int)kmem_alloc(kernel_map, round_page(size));
360 if (firstaddr == 0)
361 panic("startup: no room for tables");
362 goto again;
363 }
364
365 /*
366 * End of second pass, addresses have been assigned
367 */
368 if ((vm_size_t)(v - firstaddr) != size)
369 panic("startup: table size inconsistency");
370
371 clean_map = kmem_suballoc(kernel_map, &clean_sva, &clean_eva,
372 (nbuf*BKVASIZE) + (nswbuf*MAXPHYS) + pager_map_size);
373 buffer_map = kmem_suballoc(clean_map, &buffer_sva, &buffer_eva,
374 (nbuf*BKVASIZE));
375 buffer_map->system_map = 1;
376 pager_map = kmem_suballoc(clean_map, &pager_sva, &pager_eva,
377 (nswbuf*MAXPHYS) + pager_map_size);
378 pager_map->system_map = 1;
379 exec_map = kmem_suballoc(kernel_map, &minaddr, &maxaddr,
380 (16*(ARG_MAX+(PAGE_SIZE*3))));
381
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382#if defined(USERCONFIG)
383 userconfig();
384 cninit(); /* the preferred console may have changed */
385#endif
386
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387 printf("avail memory = %u (%uK bytes)\n", ptoa(vmstats.v_free_count),
388 ptoa(vmstats.v_free_count) / 1024);
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389
390 /*
391 * Set up buffers, so they can be used to read disk labels.
392 */
393 bufinit();
394 vm_pager_bufferinit();
395
396#ifdef SMP
397 /*
398 * OK, enough kmem_alloc/malloc state should be up, lets get on with it!
399 */
400 mp_start(); /* fire up the APs and APICs */
401 mp_announce();
402#endif /* SMP */
403 cpu_setregs();
404}
405
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406/*
407 * Send an interrupt to process.
408 *
409 * Stack is set up to allow sigcode stored
410 * at top to call routine, followed by kcall
411 * to sigreturn routine below. After sigreturn
412 * resets the signal mask, the stack, and the
413 * frame pointer, it returns to the user
414 * specified pc, psl.
415 */
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416void
417sendsig(catcher, sig, mask, code)
418 sig_t catcher;
419 int sig;
420 sigset_t *mask;
421 u_long code;
422{
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423 struct lwp *lp = curthread->td_lwp;
424 struct proc *p = lp->lwp_proc;
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425 struct trapframe *regs;
426 struct sigacts *psp = p->p_sigacts;
427 struct sigframe sf, *sfp;
428 int oonstack;
429
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430 regs = lp->lwp_md.md_regs;
431 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
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432
433 /* save user context */
434 bzero(&sf, sizeof(struct sigframe));
435 sf.sf_uc.uc_sigmask = *mask;
065b709a 436 sf.sf_uc.uc_stack = lp->lwp_sigstk;
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437 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
438 sf.sf_uc.uc_mcontext.mc_gs = rgs();
439 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_fs, sizeof(struct trapframe));
440
441 /* Allocate and validate space for the signal handler context. */
065b709a 442 /* XXX lwp flags */
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443 if ((p->p_flag & P_ALTSTACK) != 0 && !oonstack &&
444 SIGISMEMBER(psp->ps_sigonstack, sig)) {
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445 sfp = (struct sigframe *)(lp->lwp_sigstk.ss_sp +
446 lp->lwp_sigstk.ss_size - sizeof(struct sigframe));
447 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
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448 }
449 else
450 sfp = (struct sigframe *)regs->tf_esp - 1;
451
452 /* Translate the signal is appropriate */
453 if (p->p_sysent->sv_sigtbl) {
454 if (sig <= p->p_sysent->sv_sigsize)
455 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
456 }
457
458 /* Build the argument list for the signal handler. */
459 sf.sf_signum = sig;
460 sf.sf_ucontext = (register_t)&sfp->sf_uc;
065b709a 461 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
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462 /* Signal handler installed with SA_SIGINFO. */
463 sf.sf_siginfo = (register_t)&sfp->sf_si;
464 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
465
466 /* fill siginfo structure */
467 sf.sf_si.si_signo = sig;
468 sf.sf_si.si_code = code;
469 sf.sf_si.si_addr = (void*)regs->tf_err;
470 }
471 else {
472 /* Old FreeBSD-style arguments. */
473 sf.sf_siginfo = code;
474 sf.sf_addr = regs->tf_err;
475 sf.sf_ahu.sf_handler = catcher;
476 }
477
478 /*
479 * If we're a vm86 process, we want to save the segment registers.
480 * We also change eflags to be our emulated eflags, not the actual
481 * eflags.
482 */
483 if (regs->tf_eflags & PSL_VM) {
484 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
065b709a 485 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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486
487 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
488 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
489 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
490 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
491
492 if (vm86->vm86_has_vme == 0)
493 sf.sf_uc.uc_mcontext.mc_eflags =
494 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
495 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
496
497 /*
498 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
499 * syscalls made by the signal handler. This just avoids
500 * wasting time for our lazy fixup of such faults. PSL_NT
501 * does nothing in vm86 mode, but vm86 programs can set it
502 * almost legitimately in probes for old cpu types.
503 */
504 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
505 }
506
507 /*
508 * Copy the sigframe out to the user's stack.
509 */
510 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
511 /*
512 * Something is wrong with the stack pointer.
513 * ...Kill the process.
514 */
515 sigexit(p, SIGILL);
516 }
517
518 regs->tf_esp = (int)sfp;
519 regs->tf_eip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
520 regs->tf_eflags &= ~PSL_T;
521 regs->tf_cs = _ucodesel;
522 regs->tf_ds = _udatasel;
523 regs->tf_es = _udatasel;
524 regs->tf_fs = _udatasel;
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525 regs->tf_ss = _udatasel;
526}
527
528/*
65957d54 529 * sigreturn(ucontext_t *sigcntxp)
41c20dac 530 *
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531 * System call to cleanup state after a signal
532 * has been taken. Reset signal mask and
533 * stack state from context left by sendsig (above).
534 * Return to previous pc and psl as specified by
535 * context left by sendsig. Check carefully to
536 * make sure that the user has not modified the
537 * state to gain improper privileges.
538 */
539#define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
540#define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
541
984263bc 542int
41c20dac 543sigreturn(struct sigreturn_args *uap)
984263bc 544{
065b709a 545 struct lwp *lp = curthread->td_lwp;
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546 struct trapframe *regs;
547 ucontext_t *ucp;
548 int cs, eflags;
549
550 ucp = uap->sigcntxp;
551
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552 if (!useracc((caddr_t)ucp, sizeof(ucontext_t), VM_PROT_READ))
553 return (EFAULT);
554
065b709a 555 regs = lp->lwp_md.md_regs;
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556 eflags = ucp->uc_mcontext.mc_eflags;
557
558 if (eflags & PSL_VM) {
559 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
560 struct vm86_kernel *vm86;
561
562 /*
563 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
564 * set up the vm86 area, and we can't enter vm86 mode.
565 */
065b709a 566 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
984263bc 567 return (EINVAL);
065b709a 568 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
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569 if (vm86->vm86_inited == 0)
570 return (EINVAL);
571
572 /* go back to user mode if both flags are set */
573 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
065b709a 574 trapsignal(lp->lwp_proc, SIGBUS, 0);
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575
576 if (vm86->vm86_has_vme) {
577 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
578 (eflags & VME_USERCHANGE) | PSL_VM;
579 } else {
580 vm86->vm86_eflags = eflags; /* save VIF, VIP */
581 eflags = (tf->tf_eflags & ~VM_USERCHANGE) | (eflags & VM_USERCHANGE) | PSL_VM;
582 }
583 bcopy(&ucp->uc_mcontext.mc_fs, tf, sizeof(struct trapframe));
584 tf->tf_eflags = eflags;
585 tf->tf_vm86_ds = tf->tf_ds;
586 tf->tf_vm86_es = tf->tf_es;
587 tf->tf_vm86_fs = tf->tf_fs;
588 tf->tf_vm86_gs = ucp->uc_mcontext.mc_gs;
589 tf->tf_ds = _udatasel;
590 tf->tf_es = _udatasel;
591 tf->tf_fs = _udatasel;
592 } else {
593 /*
594 * Don't allow users to change privileged or reserved flags.
595 */
596 /*
597 * XXX do allow users to change the privileged flag PSL_RF.
598 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
599 * should sometimes set it there too. tf_eflags is kept in
600 * the signal context during signal handling and there is no
601 * other place to remember it, so the PSL_RF bit may be
602 * corrupted by the signal handler without us knowing.
603 * Corruption of the PSL_RF bit at worst causes one more or
604 * one less debugger trap, so allowing it is fairly harmless.
605 */
606 if (!EFL_SECURE(eflags & ~PSL_RF, regs->tf_eflags & ~PSL_RF)) {
607 printf("sigreturn: eflags = 0x%x\n", eflags);
608 return(EINVAL);
609 }
610
611 /*
612 * Don't allow users to load a valid privileged %cs. Let the
613 * hardware check for invalid selectors, excess privilege in
614 * other selectors, invalid %eip's and invalid %esp's.
615 */
616 cs = ucp->uc_mcontext.mc_cs;
617 if (!CS_SECURE(cs)) {
618 printf("sigreturn: cs = 0x%x\n", cs);
065b709a 619 trapsignal(lp->lwp_proc, SIGBUS, T_PROTFLT);
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620 return(EINVAL);
621 }
622 bcopy(&ucp->uc_mcontext.mc_fs, regs, sizeof(struct trapframe));
623 }
624
625 if (ucp->uc_mcontext.mc_onstack & 1)
065b709a 626 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
984263bc 627 else
065b709a 628 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
984263bc 629
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630 lp->lwp_sigmask = ucp->uc_sigmask;
631 SIG_CANTMASK(lp->lwp_sigmask);
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632 return(EJUSTRETURN);
633}
634
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635/*
636 * Stack frame on entry to function. %eax will contain the function vector,
637 * %ecx will contain the function data. flags, ecx, and eax will have
638 * already been pushed on the stack.
639 */
640struct upc_frame {
641 register_t eax;
642 register_t ecx;
0a455ac5 643 register_t edx;
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644 register_t flags;
645 register_t oldip;
646};
647
648void
649sendupcall(struct vmupcall *vu, int morepending)
650{
065b709a 651 struct lwp *lp = curthread->td_lwp;
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652 struct trapframe *regs;
653 struct upcall upcall;
654 struct upc_frame upc_frame;
6e58b5df 655 int crit_count = 0;
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656
657 /*
658 * Get the upcall data structure
659 */
065b709a 660 if (copyin(lp->lwp_upcall, &upcall, sizeof(upcall)) ||
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661 copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int))
662 ) {
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663 vu->vu_pending = 0;
664 printf("bad upcall address\n");
665 return;
666 }
667
668 /*
669 * If the data structure is already marked pending or has a critical
670 * section count, mark the data structure as pending and return
671 * without doing an upcall. vu_pending is left set.
672 */
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673 if (upcall.upc_pending || crit_count >= vu->vu_pending) {
674 if (upcall.upc_pending < vu->vu_pending) {
675 upcall.upc_pending = vu->vu_pending;
065b709a 676 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
6e58b5df 677 sizeof(upcall.upc_pending));
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678 }
679 return;
680 }
681
682 /*
683 * We can run this upcall now, clear vu_pending.
684 *
685 * Bump our critical section count and set or clear the
686 * user pending flag depending on whether more upcalls are
687 * pending. The user will be responsible for calling
688 * upc_dispatch(-1) to process remaining upcalls.
689 */
690 vu->vu_pending = 0;
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691 upcall.upc_pending = morepending;
692 crit_count += TDPRI_CRIT;
065b709a 693 copyout(&upcall.upc_pending, &lp->lwp_upcall->upc_pending,
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694 sizeof(upcall.upc_pending));
695 copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff,
696 sizeof(int));
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697
698 /*
699 * Construct a stack frame and issue the upcall
700 */
065b709a 701 regs = lp->lwp_md.md_regs;
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702 upc_frame.eax = regs->tf_eax;
703 upc_frame.ecx = regs->tf_ecx;
0a455ac5 704 upc_frame.edx = regs->tf_edx;
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705 upc_frame.flags = regs->tf_eflags;
706 upc_frame.oldip = regs->tf_eip;
707 if (copyout(&upc_frame, (void *)(regs->tf_esp - sizeof(upc_frame)),
708 sizeof(upc_frame)) != 0) {
709 printf("bad stack on upcall\n");
710 } else {
711 regs->tf_eax = (register_t)vu->vu_func;
712 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 713 regs->tf_edx = (register_t)lp->lwp_upcall;
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714 regs->tf_eip = (register_t)vu->vu_ctx;
715 regs->tf_esp -= sizeof(upc_frame);
716 }
717}
718
719/*
720 * fetchupcall occurs in the context of a system call, which means that
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721 * we have to return EJUSTRETURN in order to prevent eax and edx from
722 * being overwritten by the syscall return value.
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723 *
724 * if vu is not NULL we return the new context in %edx, the new data in %ecx,
725 * and the function pointer in %eax.
726 */
727int
0a455ac5 728fetchupcall (struct vmupcall *vu, int morepending, void *rsp)
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729{
730 struct upc_frame upc_frame;
065b709a 731 struct lwp *lp = curthread->td_lwp;
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732 struct trapframe *regs;
733 int error;
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734 struct upcall upcall;
735 int crit_count;
a722be49 736
065b709a 737 regs = lp->lwp_md.md_regs;
a722be49 738
065b709a 739 error = copyout(&morepending, &lp->lwp_upcall->upc_pending, sizeof(int));
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740 if (error == 0) {
741 if (vu) {
742 /*
743 * This jumps us to the next ready context.
744 */
745 vu->vu_pending = 0;
065b709a 746 error = copyin(lp->lwp_upcall, &upcall, sizeof(upcall));
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747 crit_count = 0;
748 if (error == 0)
749 error = copyin((char *)upcall.upc_uthread + upcall.upc_critoff, &crit_count, sizeof(int));
750 crit_count += TDPRI_CRIT;
a722be49 751 if (error == 0)
6e58b5df 752 error = copyout(&crit_count, (char *)upcall.upc_uthread + upcall.upc_critoff, sizeof(int));
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753 regs->tf_eax = (register_t)vu->vu_func;
754 regs->tf_ecx = (register_t)vu->vu_data;
065b709a 755 regs->tf_edx = (register_t)lp->lwp_upcall;
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756 regs->tf_eip = (register_t)vu->vu_ctx;
757 regs->tf_esp = (register_t)rsp;
758 } else {
759 /*
760 * This returns us to the originally interrupted code.
761 */
762 error = copyin(rsp, &upc_frame, sizeof(upc_frame));
763 regs->tf_eax = upc_frame.eax;
764 regs->tf_ecx = upc_frame.ecx;
0a455ac5 765 regs->tf_edx = upc_frame.edx;
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766 regs->tf_eflags = (regs->tf_eflags & ~PSL_USERCHANGE) |
767 (upc_frame.flags & PSL_USERCHANGE);
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768 regs->tf_eip = upc_frame.oldip;
769 regs->tf_esp = (register_t)((char *)rsp + sizeof(upc_frame));
770 }
771 }
772 if (error == 0)
773 error = EJUSTRETURN;
774 return(error);
775}
776
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777/*
778 * Machine dependent boot() routine
779 *
780 * I haven't seen anything to put here yet
781 * Possibly some stuff might be grafted back here from boot()
782 */
783void
784cpu_boot(int howto)
785{
786}
787
788/*
789 * Shutdown the CPU as much as possible
790 */
791void
792cpu_halt(void)
793{
794 for (;;)
795 __asm__ ("hlt");
796}
797
798/*
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799 * cpu_idle() represents the idle LWKT. You cannot return from this function
800 * (unless you want to blow things up!). Instead we look for runnable threads
801 * and loop or halt as appropriate. Giant is not held on entry to the thread.
984263bc 802 *
26a0694b 803 * The main loop is entered with a critical section held, we must release
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804 * the critical section before doing anything else. lwkt_switch() will
805 * check for pending interrupts due to entering and exiting its own
806 * critical section.
26a0694b 807 *
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808 * Note on cpu_idle_hlt: On an SMP system we rely on a scheduler IPI
809 * to wake a HLTed cpu up. However, there are cases where the idlethread
810 * will be entered with the possibility that no IPI will occur and in such
811 * cases lwkt_switch() sets TDF_IDLE_NOHLT.
984263bc 812 */
96728c05 813static int cpu_idle_hlt = 1;
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814static int cpu_idle_hltcnt;
815static int cpu_idle_spincnt;
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816SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
817 &cpu_idle_hlt, 0, "Idle loop HLT enable");
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818SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
819 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
820SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
821 &cpu_idle_spincnt, 0, "Idle loop entry spins");
984263bc 822
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823static void
824cpu_idle_default_hook(void)
825{
826 /*
827 * We must guarentee that hlt is exactly the instruction
828 * following the sti.
829 */
830 __asm __volatile("sti; hlt");
831}
832
833/* Other subsystems (e.g., ACPI) can hook this later. */
834void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
835
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836void
837cpu_idle(void)
838{
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839 struct thread *td = curthread;
840
26a0694b 841 crit_exit();
a2a5ad0d 842 KKASSERT(td->td_pri < TDPRI_CRIT);
8ad65e08 843 for (;;) {
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844 /*
845 * See if there are any LWKTs ready to go.
846 */
8ad65e08 847 lwkt_switch();
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848
849 /*
850 * If we are going to halt call splz unconditionally after
851 * CLIing to catch any interrupt races. Note that we are
852 * at SPL0 and interrupts are enabled.
853 */
854 if (cpu_idle_hlt && !lwkt_runnable() &&
855 (td->td_flags & TDF_IDLE_NOHLT) == 0) {
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856 __asm __volatile("cli");
857 splz();
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858 if (!lwkt_runnable())
859 cpu_idle_hook();
860#ifdef SMP
861 else
862 __asm __volatile("pause");
863#endif
60f945af 864 ++cpu_idle_hltcnt;
8ad65e08 865 } else {
a2a5ad0d 866 td->td_flags &= ~TDF_IDLE_NOHLT;
60f945af 867 splz();
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868#ifdef SMP
869 __asm __volatile("sti; pause");
870#else
8ad65e08 871 __asm __volatile("sti");
8b6d0f3f 872#endif
60f945af 873 ++cpu_idle_spincnt;
8ad65e08 874 }
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875 }
876}
877
878/*
879 * Clear registers on exec
880 */
881void
882setregs(p, entry, stack, ps_strings)
883 struct proc *p;
884 u_long entry;
885 u_long stack;
886 u_long ps_strings;
887{
888 struct trapframe *regs = p->p_md.md_regs;
b7c628e4 889 struct pcb *pcb = p->p_thread->td_pcb;
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890
891 /* Reset pc->pcb_gs and %gs before possibly invalidating it. */
892 pcb->pcb_gs = _udatasel;
893 load_gs(_udatasel);
894
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895 /* was i386_user_cleanup() in NetBSD */
896 user_ldt_free(pcb);
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897
898 bzero((char *)regs, sizeof(struct trapframe));
899 regs->tf_eip = entry;
900 regs->tf_esp = stack;
901 regs->tf_eflags = PSL_USER | (regs->tf_eflags & PSL_T);
902 regs->tf_ss = _udatasel;
903 regs->tf_ds = _udatasel;
904 regs->tf_es = _udatasel;
905 regs->tf_fs = _udatasel;
906 regs->tf_cs = _ucodesel;
907
908 /* PS_STRINGS value for BSD/OS binaries. It is 0 for non-BSD/OS. */
909 regs->tf_ebx = ps_strings;
910
911 /*
912 * Reset the hardware debug registers if they were in use.
913 * They won't have any meaning for the newly exec'd process.
914 */
915 if (pcb->pcb_flags & PCB_DBREGS) {
916 pcb->pcb_dr0 = 0;
917 pcb->pcb_dr1 = 0;
918 pcb->pcb_dr2 = 0;
919 pcb->pcb_dr3 = 0;
920 pcb->pcb_dr6 = 0;
921 pcb->pcb_dr7 = 0;
b7c628e4 922 if (pcb == curthread->td_pcb) {
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923 /*
924 * Clear the debug registers on the running
925 * CPU, otherwise they will end up affecting
926 * the next process we switch to.
927 */
928 reset_dbregs();
929 }
930 pcb->pcb_flags &= ~PCB_DBREGS;
931 }
932
933 /*
934 * Initialize the math emulator (if any) for the current process.
935 * Actually, just clear the bit that says that the emulator has
936 * been initialized. Initialization is delayed until the process
937 * traps to the emulator (if it is done at all) mainly because
938 * emulators don't provide an entry point for initialization.
939 */
b7c628e4 940 p->p_thread->td_pcb->pcb_flags &= ~FP_SOFTFP;
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941
942 /*
a02705a9
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943 * note: do not set CR0_TS here. npxinit() must do it after clearing
944 * gd_npxthread. Otherwise a preemptive interrupt thread may panic
945 * in npxdna().
984263bc 946 */
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947 crit_enter();
948 load_cr0(rcr0() | CR0_MP);
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949
950#if NNPX > 0
951 /* Initialize the npx (if any) for the current process. */
952 npxinit(__INITIAL_NPXCW__);
953#endif
a02705a9 954 crit_exit();
984263bc 955
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956 /*
957 * note: linux emulator needs edx to be 0x0 on entry, which is
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958 * handled in execve simply by setting the 64 bit syscall
959 * return value to 0.
90b9818c 960 */
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961}
962
963void
964cpu_setregs(void)
965{
966 unsigned int cr0;
967
968 cr0 = rcr0();
969 cr0 |= CR0_NE; /* Done by npxinit() */
970 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
971#ifdef I386_CPU
972 if (cpu_class != CPUCLASS_386)
973#endif
974 cr0 |= CR0_WP | CR0_AM;
975 load_cr0(cr0);
976 load_gs(_udatasel);
977}
978
979static int
980sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
981{
982 int error;
983 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
984 req);
985 if (!error && req->newptr)
986 resettodr();
987 return (error);
988}
989
990SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
991 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
992
993SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
994 CTLFLAG_RW, &disable_rtc_set, 0, "");
995
996SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
997 CTLFLAG_RD, &bootinfo, bootinfo, "");
998
999SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1000 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1001
1002extern u_long bootdev; /* not a dev_t - encoding is different */
1003SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1004 CTLFLAG_RD, &bootdev, 0, "Boot device (not in dev_t format)");
1005
1006/*
1007 * Initialize 386 and configure to run kernel
1008 */
1009
1010/*
1011 * Initialize segments & interrupt table
1012 */
1013
1014int _default_ldt;
1015union descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1016static struct gate_descriptor idt0[NIDT];
1017struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1018union descriptor ldt[NLDT]; /* local descriptor table */
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1019
1020/* table descriptors - used to load tables by cpu */
984263bc 1021struct region_descriptor r_gdt, r_idt;
984263bc 1022
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1023#if defined(I586_CPU) && !defined(NO_F00F_HACK)
1024extern int has_f00f_bug;
1025#endif
1026
1027static struct i386tss dblfault_tss;
1028static char dblfault_stack[PAGE_SIZE];
1029
1030extern struct user *proc0paddr;
1031
1032
1033/* software prototypes -- in more palatable form */
1034struct soft_segment_descriptor gdt_segs[] = {
1035/* GNULL_SEL 0 Null Descriptor */
1036{ 0x0, /* segment base address */
1037 0x0, /* length */
1038 0, /* segment type */
1039 0, /* segment descriptor priority level */
1040 0, /* segment descriptor present */
1041 0, 0,
1042 0, /* default 32 vs 16 bit size */
1043 0 /* limit granularity (byte/page units)*/ },
1044/* GCODE_SEL 1 Code Descriptor for kernel */
1045{ 0x0, /* segment base address */
1046 0xfffff, /* length - all address space */
1047 SDT_MEMERA, /* segment type */
1048 0, /* segment descriptor priority level */
1049 1, /* segment descriptor present */
1050 0, 0,
1051 1, /* default 32 vs 16 bit size */
1052 1 /* limit granularity (byte/page units)*/ },
1053/* GDATA_SEL 2 Data Descriptor for kernel */
1054{ 0x0, /* segment base address */
1055 0xfffff, /* length - all address space */
1056 SDT_MEMRWA, /* segment type */
1057 0, /* segment descriptor priority level */
1058 1, /* segment descriptor present */
1059 0, 0,
1060 1, /* default 32 vs 16 bit size */
1061 1 /* limit granularity (byte/page units)*/ },
1062/* GPRIV_SEL 3 SMP Per-Processor Private Data Descriptor */
1063{ 0x0, /* segment base address */
1064 0xfffff, /* length - all address space */
1065 SDT_MEMRWA, /* segment type */
1066 0, /* segment descriptor priority level */
1067 1, /* segment descriptor present */
1068 0, 0,
1069 1, /* default 32 vs 16 bit size */
1070 1 /* limit granularity (byte/page units)*/ },
1071/* GPROC0_SEL 4 Proc 0 Tss Descriptor */
1072{
1073 0x0, /* segment base address */
1074 sizeof(struct i386tss)-1,/* length - all address space */
1075 SDT_SYS386TSS, /* segment type */
1076 0, /* segment descriptor priority level */
1077 1, /* segment descriptor present */
1078 0, 0,
1079 0, /* unused - default 32 vs 16 bit size */
1080 0 /* limit granularity (byte/page units)*/ },
1081/* GLDT_SEL 5 LDT Descriptor */
1082{ (int) ldt, /* segment base address */
1083 sizeof(ldt)-1, /* length - all address space */
1084 SDT_SYSLDT, /* segment type */
1085 SEL_UPL, /* segment descriptor priority level */
1086 1, /* segment descriptor present */
1087 0, 0,
1088 0, /* unused - default 32 vs 16 bit size */
1089 0 /* limit granularity (byte/page units)*/ },
1090/* GUSERLDT_SEL 6 User LDT Descriptor per process */
1091{ (int) ldt, /* segment base address */
1092 (512 * sizeof(union descriptor)-1), /* length */
1093 SDT_SYSLDT, /* segment type */
1094 0, /* segment descriptor priority level */
1095 1, /* segment descriptor present */
1096 0, 0,
1097 0, /* unused - default 32 vs 16 bit size */
1098 0 /* limit granularity (byte/page units)*/ },
1099/* GTGATE_SEL 7 Null Descriptor - Placeholder */
1100{ 0x0, /* segment base address */
1101 0x0, /* length - all address space */
1102 0, /* segment type */
1103 0, /* segment descriptor priority level */
1104 0, /* segment descriptor present */
1105 0, 0,
1106 0, /* default 32 vs 16 bit size */
1107 0 /* limit granularity (byte/page units)*/ },
1108/* GBIOSLOWMEM_SEL 8 BIOS access to realmode segment 0x40, must be #8 in GDT */
1109{ 0x400, /* segment base address */
1110 0xfffff, /* length */
1111 SDT_MEMRWA, /* segment type */
1112 0, /* segment descriptor priority level */
1113 1, /* segment descriptor present */
1114 0, 0,
1115 1, /* default 32 vs 16 bit size */
1116 1 /* limit granularity (byte/page units)*/ },
1117/* GPANIC_SEL 9 Panic Tss Descriptor */
1118{ (int) &dblfault_tss, /* segment base address */
1119 sizeof(struct i386tss)-1,/* length - all address space */
1120 SDT_SYS386TSS, /* segment type */
1121 0, /* segment descriptor priority level */
1122 1, /* segment descriptor present */
1123 0, 0,
1124 0, /* unused - default 32 vs 16 bit size */
1125 0 /* limit granularity (byte/page units)*/ },
1126/* GBIOSCODE32_SEL 10 BIOS 32-bit interface (32bit Code) */
1127{ 0, /* segment base address (overwritten) */
1128 0xfffff, /* length */
1129 SDT_MEMERA, /* segment type */
1130 0, /* segment descriptor priority level */
1131 1, /* segment descriptor present */
1132 0, 0,
1133 0, /* default 32 vs 16 bit size */
1134 1 /* limit granularity (byte/page units)*/ },
1135/* GBIOSCODE16_SEL 11 BIOS 32-bit interface (16bit Code) */
1136{ 0, /* segment base address (overwritten) */
1137 0xfffff, /* length */
1138 SDT_MEMERA, /* segment type */
1139 0, /* segment descriptor priority level */
1140 1, /* segment descriptor present */
1141 0, 0,
1142 0, /* default 32 vs 16 bit size */
1143 1 /* limit granularity (byte/page units)*/ },
1144/* GBIOSDATA_SEL 12 BIOS 32-bit interface (Data) */
1145{ 0, /* segment base address (overwritten) */
1146 0xfffff, /* length */
1147 SDT_MEMRWA, /* segment type */
1148 0, /* segment descriptor priority level */
1149 1, /* segment descriptor present */
1150 0, 0,
1151 1, /* default 32 vs 16 bit size */
1152 1 /* limit granularity (byte/page units)*/ },
1153/* GBIOSUTIL_SEL 13 BIOS 16-bit interface (Utility) */
1154{ 0, /* segment base address (overwritten) */
1155 0xfffff, /* length */
1156 SDT_MEMRWA, /* segment type */
1157 0, /* segment descriptor priority level */
1158 1, /* segment descriptor present */
1159 0, 0,
1160 0, /* default 32 vs 16 bit size */
1161 1 /* limit granularity (byte/page units)*/ },
1162/* GBIOSARGS_SEL 14 BIOS 16-bit interface (Arguments) */
1163{ 0, /* segment base address (overwritten) */
1164 0xfffff, /* length */
1165 SDT_MEMRWA, /* segment type */
1166 0, /* segment descriptor priority level */
1167 1, /* segment descriptor present */
1168 0, 0,
1169 0, /* default 32 vs 16 bit size */
1170 1 /* limit granularity (byte/page units)*/ },
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MD
1171/* GTLS_START 15 TLS */
1172{ 0x0, /* segment base address */
1173 0x0, /* length */
1174 0, /* segment type */
1175 0, /* segment descriptor priority level */
1176 0, /* segment descriptor present */
1177 0, 0,
1178 0, /* default 32 vs 16 bit size */
1179 0 /* limit granularity (byte/page units)*/ },
1180/* GTLS_START+1 16 TLS */
1181{ 0x0, /* segment base address */
1182 0x0, /* length */
1183 0, /* segment type */
1184 0, /* segment descriptor priority level */
1185 0, /* segment descriptor present */
1186 0, 0,
1187 0, /* default 32 vs 16 bit size */
1188 0 /* limit granularity (byte/page units)*/ },
1189/* GTLS_END 17 TLS */
1190{ 0x0, /* segment base address */
1191 0x0, /* length */
1192 0, /* segment type */
1193 0, /* segment descriptor priority level */
1194 0, /* segment descriptor present */
1195 0, 0,
1196 0, /* default 32 vs 16 bit size */
1197 0 /* limit granularity (byte/page units)*/ },
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MD
1198};
1199
1200static struct soft_segment_descriptor ldt_segs[] = {
1201 /* Null Descriptor - overwritten by call gate */
1202{ 0x0, /* segment base address */
1203 0x0, /* length - all address space */
1204 0, /* segment type */
1205 0, /* segment descriptor priority level */
1206 0, /* segment descriptor present */
1207 0, 0,
1208 0, /* default 32 vs 16 bit size */
1209 0 /* limit granularity (byte/page units)*/ },
1210 /* Null Descriptor - overwritten by call gate */
1211{ 0x0, /* segment base address */
1212 0x0, /* length - all address space */
1213 0, /* segment type */
1214 0, /* segment descriptor priority level */
1215 0, /* segment descriptor present */
1216 0, 0,
1217 0, /* default 32 vs 16 bit size */
1218 0 /* limit granularity (byte/page units)*/ },
1219 /* Null Descriptor - overwritten by call gate */
1220{ 0x0, /* segment base address */
1221 0x0, /* length - all address space */
1222 0, /* segment type */
1223 0, /* segment descriptor priority level */
1224 0, /* segment descriptor present */
1225 0, 0,
1226 0, /* default 32 vs 16 bit size */
1227 0 /* limit granularity (byte/page units)*/ },
1228 /* Code Descriptor for user */
1229{ 0x0, /* segment base address */
1230 0xfffff, /* length - all address space */
1231 SDT_MEMERA, /* segment type */
1232 SEL_UPL, /* segment descriptor priority level */
1233 1, /* segment descriptor present */
1234 0, 0,
1235 1, /* default 32 vs 16 bit size */
1236 1 /* limit granularity (byte/page units)*/ },
1237 /* Null Descriptor - overwritten by call gate */
1238{ 0x0, /* segment base address */
1239 0x0, /* length - all address space */
1240 0, /* segment type */
1241 0, /* segment descriptor priority level */
1242 0, /* segment descriptor present */
1243 0, 0,
1244 0, /* default 32 vs 16 bit size */
1245 0 /* limit granularity (byte/page units)*/ },
1246 /* Data Descriptor for user */
1247{ 0x0, /* segment base address */
1248 0xfffff, /* length - all address space */
1249 SDT_MEMRWA, /* segment type */
1250 SEL_UPL, /* segment descriptor priority level */
1251 1, /* segment descriptor present */
1252 0, 0,
1253 1, /* default 32 vs 16 bit size */
1254 1 /* limit granularity (byte/page units)*/ },
1255};
1256
1257void
1258setidt(idx, func, typ, dpl, selec)
1259 int idx;
1260 inthand_t *func;
1261 int typ;
1262 int dpl;
1263 int selec;
1264{
1265 struct gate_descriptor *ip;
1266
1267 ip = idt + idx;
1268 ip->gd_looffset = (int)func;
1269 ip->gd_selector = selec;
1270 ip->gd_stkcpy = 0;
1271 ip->gd_xx = 0;
1272 ip->gd_type = typ;
1273 ip->gd_dpl = dpl;
1274 ip->gd_p = 1;
1275 ip->gd_hioffset = ((int)func)>>16 ;
1276}
1277
1278#define IDTVEC(name) __CONCAT(X,name)
1279
1280extern inthand_t
1281 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1282 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1283 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
f7bc9806
MD
1284 IDTVEC(page), IDTVEC(mchk), IDTVEC(fpu), IDTVEC(align),
1285 IDTVEC(xmm), IDTVEC(syscall),
1286 IDTVEC(rsvd0);
a64ba182 1287extern inthand_t
7062f5b4
EN
1288 IDTVEC(int0x80_syscall), IDTVEC(int0x81_syscall),
1289 IDTVEC(int0x82_syscall);
984263bc 1290
f7bc9806
MD
1291#ifdef DEBUG_INTERRUPTS
1292extern inthand_t *Xrsvdary[256];
1293#endif
1294
984263bc
MD
1295void
1296sdtossd(sd, ssd)
1297 struct segment_descriptor *sd;
1298 struct soft_segment_descriptor *ssd;
1299{
1300 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1301 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1302 ssd->ssd_type = sd->sd_type;
1303 ssd->ssd_dpl = sd->sd_dpl;
1304 ssd->ssd_p = sd->sd_p;
1305 ssd->ssd_def32 = sd->sd_def32;
1306 ssd->ssd_gran = sd->sd_gran;
1307}
1308
984263bc
MD
1309/*
1310 * Populate the (physmap) array with base/bound pairs describing the
1311 * available physical memory in the system, then test this memory and
1312 * build the phys_avail array describing the actually-available memory.
1313 *
1314 * If we cannot accurately determine the physical memory map, then use
1315 * value from the 0xE801 call, and failing that, the RTC.
1316 *
1317 * Total memory size may be set by the kernel environment variable
1318 * hw.physmem or the compile-time define MAXMEM.
1319 */
1320static void
1321getmemsize(int first)
1322{
1323 int i, physmap_idx, pa_indx;
1324 int hasbrokenint12;
1325 u_int basemem, extmem;
1326 struct vm86frame vmf;
1327 struct vm86context vmc;
ff1a75a1
MD
1328 vm_offset_t pa;
1329 vm_offset_t physmap[PHYSMAP_ENTRIES*2];
b5b32410 1330 pt_entry_t *pte;
984263bc
MD
1331 const char *cp;
1332 struct {
1333 u_int64_t base;
1334 u_int64_t length;
1335 u_int32_t type;
1336 } *smap;
28abdbbb 1337 quad_t dcons_addr, dcons_size;
984263bc
MD
1338
1339 hasbrokenint12 = 0;
1340 TUNABLE_INT_FETCH("hw.hasbrokenint12", &hasbrokenint12);
1341 bzero(&vmf, sizeof(struct vm86frame));
1342 bzero(physmap, sizeof(physmap));
1343 basemem = 0;
1344
1345 /*
1346 * Some newer BIOSes has broken INT 12H implementation which cause
1347 * kernel panic immediately. In this case, we need to scan SMAP
1348 * with INT 15:E820 first, then determine base memory size.
1349 */
1350 if (hasbrokenint12) {
1351 goto int15e820;
1352 }
1353
1354 /*
7febcc6e
MD
1355 * Perform "base memory" related probes & setup. If we get a crazy
1356 * value give the bios some scribble space just in case.
984263bc
MD
1357 */
1358 vm86_intcall(0x12, &vmf);
1359 basemem = vmf.vmf_ax;
1360 if (basemem > 640) {
7febcc6e
MD
1361 printf("Preposterous BIOS basemem of %uK, "
1362 "truncating to < 640K\n", basemem);
1363 basemem = 636;
984263bc
MD
1364 }
1365
1366 /*
1367 * XXX if biosbasemem is now < 640, there is a `hole'
1368 * between the end of base memory and the start of
1369 * ISA memory. The hole may be empty or it may
1370 * contain BIOS code or data. Map it read/write so
1371 * that the BIOS can write to it. (Memory from 0 to
1372 * the physical end of the kernel is mapped read-only
1373 * to begin with and then parts of it are remapped.
1374 * The parts that aren't remapped form holes that
1375 * remain read-only and are unused by the kernel.
1376 * The base memory area is below the physical end of
1377 * the kernel and right now forms a read-only hole.
1378 * The part of it from PAGE_SIZE to
1379 * (trunc_page(biosbasemem * 1024) - 1) will be
1380 * remapped and used by the kernel later.)
1381 *
1382 * This code is similar to the code used in
1383 * pmap_mapdev, but since no memory needs to be
1384 * allocated we simply change the mapping.
1385 */
1386 for (pa = trunc_page(basemem * 1024);
1387 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1388 pte = vtopte(pa + KERNBASE);
984263bc
MD
1389 *pte = pa | PG_RW | PG_V;
1390 }
1391
1392 /*
1393 * if basemem != 640, map pages r/w into vm86 page table so
1394 * that the bios can scribble on it.
1395 */
b5b32410 1396 pte = vm86paddr;
984263bc
MD
1397 for (i = basemem / 4; i < 160; i++)
1398 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1399
1400int15e820:
1401 /*
1402 * map page 1 R/W into the kernel page table so we can use it
1403 * as a buffer. The kernel will unmap this page later.
1404 */
b5b32410 1405 pte = vtopte(KERNBASE + (1 << PAGE_SHIFT));
984263bc
MD
1406 *pte = (1 << PAGE_SHIFT) | PG_RW | PG_V;
1407
1408 /*
1409 * get memory map with INT 15:E820
1410 */
1411#define SMAPSIZ sizeof(*smap)
1412#define SMAP_SIG 0x534D4150 /* 'SMAP' */
1413
1414 vmc.npages = 0;
1415 smap = (void *)vm86_addpage(&vmc, 1, KERNBASE + (1 << PAGE_SHIFT));
1416 vm86_getptr(&vmc, (vm_offset_t)smap, &vmf.vmf_es, &vmf.vmf_di);
1417
1418 physmap_idx = 0;
1419 vmf.vmf_ebx = 0;
1420 do {
1421 vmf.vmf_eax = 0xE820;
1422 vmf.vmf_edx = SMAP_SIG;
1423 vmf.vmf_ecx = SMAPSIZ;
1424 i = vm86_datacall(0x15, &vmf, &vmc);
1425 if (i || vmf.vmf_eax != SMAP_SIG)
1426 break;
1427 if (boothowto & RB_VERBOSE)
1428 printf("SMAP type=%02x base=%08x %08x len=%08x %08x\n",
1429 smap->type,
1430 *(u_int32_t *)((char *)&smap->base + 4),
1431 (u_int32_t)smap->base,
1432 *(u_int32_t *)((char *)&smap->length + 4),
1433 (u_int32_t)smap->length);
1434
1435 if (smap->type != 0x01)
1436 goto next_run;
1437
1438 if (smap->length == 0)
1439 goto next_run;
1440
1441 if (smap->base >= 0xffffffff) {
1442 printf("%uK of memory above 4GB ignored\n",
1443 (u_int)(smap->length / 1024));
1444 goto next_run;
1445 }
1446
1447 for (i = 0; i <= physmap_idx; i += 2) {
1448 if (smap->base < physmap[i + 1]) {
1449 if (boothowto & RB_VERBOSE)
1450 printf(
1451 "Overlapping or non-montonic memory region, ignoring second region\n");
1452 goto next_run;
1453 }
1454 }
1455
1456 if (smap->base == physmap[physmap_idx + 1]) {
1457 physmap[physmap_idx + 1] += smap->length;
1458 goto next_run;
1459 }
1460
1461 physmap_idx += 2;
ff1a75a1 1462 if (physmap_idx == PHYSMAP_ENTRIES*2) {
984263bc
MD
1463 printf(
1464 "Too many segments in the physical address map, giving up\n");
1465 break;
1466 }
1467 physmap[physmap_idx] = smap->base;
1468 physmap[physmap_idx + 1] = smap->base + smap->length;
1469next_run:
6b08710e 1470 ; /* fix GCC3.x warning */
984263bc
MD
1471 } while (vmf.vmf_ebx != 0);
1472
1473 /*
1474 * Perform "base memory" related probes & setup based on SMAP
1475 */
1476 if (basemem == 0) {
1477 for (i = 0; i <= physmap_idx; i += 2) {
1478 if (physmap[i] == 0x00000000) {
1479 basemem = physmap[i + 1] / 1024;
1480 break;
1481 }
1482 }
1483
1484 if (basemem == 0) {
1485 basemem = 640;
1486 }
1487
1488 if (basemem > 640) {
1489 printf("Preposterous BIOS basemem of %uK, truncating to 640K\n",
1490 basemem);
1491 basemem = 640;
1492 }
1493
1494 for (pa = trunc_page(basemem * 1024);
1495 pa < ISA_HOLE_START; pa += PAGE_SIZE) {
b5b32410 1496 pte = vtopte(pa + KERNBASE);
984263bc
MD
1497 *pte = pa | PG_RW | PG_V;
1498 }
1499
b5b32410 1500 pte = vm86paddr;
984263bc
MD
1501 for (i = basemem / 4; i < 160; i++)
1502 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
1503 }
1504
1505 if (physmap[1] != 0)
1506 goto physmap_done;
1507
1508 /*
1509 * If we failed above, try memory map with INT 15:E801
1510 */
1511 vmf.vmf_ax = 0xE801;
1512 if (vm86_intcall(0x15, &vmf) == 0) {
1513 extmem = vmf.vmf_cx + vmf.vmf_dx * 64;
1514 } else {
1515#if 0
1516 vmf.vmf_ah = 0x88;
1517 vm86_intcall(0x15, &vmf);
1518 extmem = vmf.vmf_ax;
1519#else
1520 /*
1521 * Prefer the RTC value for extended memory.
1522 */
1523 extmem = rtcin(RTC_EXTLO) + (rtcin(RTC_EXTHI) << 8);
1524#endif
1525 }
1526
1527 /*
1528 * Special hack for chipsets that still remap the 384k hole when
1529 * there's 16MB of memory - this really confuses people that
1530 * are trying to use bus mastering ISA controllers with the
1531 * "16MB limit"; they only have 16MB, but the remapping puts
1532 * them beyond the limit.
1533 *
1534 * If extended memory is between 15-16MB (16-17MB phys address range),
1535 * chop it to 15MB.
1536 */
1537 if ((extmem > 15 * 1024) && (extmem < 16 * 1024))
1538 extmem = 15 * 1024;
1539
1540 physmap[0] = 0;
1541 physmap[1] = basemem * 1024;
1542 physmap_idx = 2;
1543 physmap[physmap_idx] = 0x100000;
1544 physmap[physmap_idx + 1] = physmap[physmap_idx] + extmem * 1024;
1545
1546physmap_done:
1547 /*
1548 * Now, physmap contains a map of physical memory.
1549 */
1550
1551#ifdef SMP
17a9f566 1552 /* make hole for AP bootstrap code YYY */
984263bc
MD
1553 physmap[1] = mp_bootaddress(physmap[1] / 1024);
1554
1555 /* look for the MP hardware - needed for apic addresses */
1556 mp_probe();
1557#endif
1558
1559 /*
1560 * Maxmem isn't the "maximum memory", it's one larger than the
1561 * highest page of the physical address space. It should be
1562 * called something like "Maxphyspage". We may adjust this
1563 * based on ``hw.physmem'' and the results of the memory test.
1564 */
1565 Maxmem = atop(physmap[physmap_idx + 1]);
1566
1567#ifdef MAXMEM
1568 Maxmem = MAXMEM / 4;
1569#endif
1570
1571 /*
eb7d35b8 1572 * hw.physmem is a size in bytes; we also allow k, m, and g suffixes
984263bc
MD
1573 * for the appropriate modifiers. This overrides MAXMEM.
1574 */
1575 if ((cp = getenv("hw.physmem")) != NULL) {
1576 u_int64_t AllowMem, sanity;
1577 char *ep;
1578
1579 sanity = AllowMem = strtouq(cp, &ep, 0);
1580 if ((ep != cp) && (*ep != 0)) {
1581 switch(*ep) {
1582 case 'g':
1583 case 'G':
1584 AllowMem <<= 10;
1585 case 'm':
1586 case 'M':
1587 AllowMem <<= 10;
1588 case 'k':
1589 case 'K':
1590 AllowMem <<= 10;
1591 break;
1592 default:
1593 AllowMem = sanity = 0;
1594 }
1595 if (AllowMem < sanity)
1596 AllowMem = 0;
1597 }
1598 if (AllowMem == 0)
1599 printf("Ignoring invalid memory size of '%s'\n", cp);
1600 else
1601 Maxmem = atop(AllowMem);
1602 }
1603
1604 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1605 (boothowto & RB_VERBOSE))
6ef943a3 1606 printf("Physical memory use set to %lluK\n", Maxmem * 4);
984263bc
MD
1607
1608 /*
1609 * If Maxmem has been increased beyond what the system has detected,
1610 * extend the last memory segment to the new limit.
1611 */
1612 if (atop(physmap[physmap_idx + 1]) < Maxmem)
1613 physmap[physmap_idx + 1] = ptoa(Maxmem);
1614
1615 /* call pmap initialization to make new kernel address space */
1616 pmap_bootstrap(first, 0);
1617
1618 /*
1619 * Size up each available chunk of physical memory.
1620 */
1621 physmap[0] = PAGE_SIZE; /* mask off page 0 */
1622 pa_indx = 0;
1623 phys_avail[pa_indx++] = physmap[0];
1624 phys_avail[pa_indx] = physmap[0];
b5b32410 1625 pte = CMAP1;
984263bc 1626
28abdbbb
HS
1627 /*
1628 * Get dcons buffer address
1629 */
1630 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1631 getenv_quad("dcons.size", &dcons_size) == 0)
1632 dcons_addr = 0;
1633
984263bc
MD
1634 /*
1635 * physmap is in bytes, so when converting to page boundaries,
1636 * round up the start address and round down the end address.
1637 */
1638 for (i = 0; i <= physmap_idx; i += 2) {
1639 vm_offset_t end;
1640
1641 end = ptoa(Maxmem);
1642 if (physmap[i + 1] < end)
1643 end = trunc_page(physmap[i + 1]);
1644 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1645 int tmp, page_bad;
1646#if 0
1647 int *ptr = 0;
1648#else
1649 int *ptr = (int *)CADDR1;
1650#endif
1651
1652 /*
1653 * block out kernel memory as not available.
1654 */
1655 if (pa >= 0x100000 && pa < first)
1656 continue;
1657
28abdbbb
HS
1658 /*
1659 * block out dcons buffer
1660 */
1661 if (dcons_addr > 0
1662 && pa >= trunc_page(dcons_addr)
1663 && pa < dcons_addr + dcons_size)
1664 continue;
1665
984263bc
MD
1666 page_bad = FALSE;
1667
1668 /*
1669 * map page into kernel: valid, read/write,non-cacheable
1670 */
1671 *pte = pa | PG_V | PG_RW | PG_N;
0f7a3396 1672 cpu_invltlb();
984263bc
MD
1673
1674 tmp = *(int *)ptr;
1675 /*
1676 * Test for alternating 1's and 0's
1677 */
1678 *(volatile int *)ptr = 0xaaaaaaaa;
1679 if (*(volatile int *)ptr != 0xaaaaaaaa) {
1680 page_bad = TRUE;
1681 }
1682 /*
1683 * Test for alternating 0's and 1's
1684 */
1685 *(volatile int *)ptr = 0x55555555;
1686 if (*(volatile int *)ptr != 0x55555555) {
1687 page_bad = TRUE;
1688 }
1689 /*
1690 * Test for all 1's
1691 */
1692 *(volatile int *)ptr = 0xffffffff;
1693 if (*(volatile int *)ptr != 0xffffffff) {
1694 page_bad = TRUE;
1695 }
1696 /*
1697 * Test for all 0's
1698 */
1699 *(volatile int *)ptr = 0x0;
1700 if (*(volatile int *)ptr != 0x0) {
1701 page_bad = TRUE;
1702 }
1703 /*
1704 * Restore original value.
1705 */
1706 *(int *)ptr = tmp;
1707
1708 /*
1709 * Adjust array of valid/good pages.
1710 */
1711 if (page_bad == TRUE) {
1712 continue;
1713 }
1714 /*
1715 * If this good page is a continuation of the
1716 * previous set of good pages, then just increase
1717 * the end pointer. Otherwise start a new chunk.
1718 * Note that "end" points one higher than end,
1719 * making the range >= start and < end.
1720 * If we're also doing a speculative memory
1721 * test and we at or past the end, bump up Maxmem
1722 * so that we keep going. The first bad page
1723 * will terminate the loop.
1724 */
1725 if (phys_avail[pa_indx] == pa) {
1726 phys_avail[pa_indx] += PAGE_SIZE;
1727 } else {
1728 pa_indx++;
ff1a75a1 1729 if (pa_indx >= PHYSMAP_ENTRIES*2) {
984263bc
MD
1730 printf("Too many holes in the physical address space, giving up\n");
1731 pa_indx--;
1732 break;
1733 }
1734 phys_avail[pa_indx++] = pa; /* start */
1735 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1736 }
1737 physmem++;
1738 }
1739 }
1740 *pte = 0;
0f7a3396 1741 cpu_invltlb();
984263bc
MD
1742
1743 /*
1744 * XXX
1745 * The last chunk must contain at least one page plus the message
1746 * buffer to avoid complicating other code (message buffer address
1747 * calculation, etc.).
1748 */
1749 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1750 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) {
1751 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1752 phys_avail[pa_indx--] = 0;
1753 phys_avail[pa_indx--] = 0;
1754 }
1755
1756 Maxmem = atop(phys_avail[pa_indx]);
1757
1758 /* Trim off space for the message buffer. */
1759 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE);
1760
1761 avail_end = phys_avail[pa_indx];
1762}
1763
f7bc9806
MD
1764/*
1765 * IDT VECTORS:
1766 * 0 Divide by zero
1767 * 1 Debug
1768 * 2 NMI
1769 * 3 BreakPoint
1770 * 4 OverFlow
1771 * 5 Bound-Range
1772 * 6 Invalid OpCode
1773 * 7 Device Not Available (x87)
1774 * 8 Double-Fault
1775 * 9 Coprocessor Segment overrun (unsupported, reserved)
1776 * 10 Invalid-TSS
1777 * 11 Segment not present
1778 * 12 Stack
1779 * 13 General Protection
1780 * 14 Page Fault
1781 * 15 Reserved
1782 * 16 x87 FP Exception pending
1783 * 17 Alignment Check
1784 * 18 Machine Check
1785 * 19 SIMD floating point
1786 * 20-31 reserved
1787 * 32-255 INTn/external sources
1788 */
984263bc 1789void
17a9f566 1790init386(int first)
984263bc
MD
1791{
1792 struct gate_descriptor *gdp;
1793 int gsel_tss, metadata_missing, off, x;
85100692 1794 struct mdglobaldata *gd;
984263bc
MD
1795
1796 /*
1797 * Prevent lowering of the ipl if we call tsleep() early.
1798 */
85100692 1799 gd = &CPU_prvspace[0].mdglobaldata;
8a8d5d85 1800 bzero(gd, sizeof(*gd));
984263bc 1801
85100692 1802 gd->mi.gd_curthread = &thread0;
984263bc
MD
1803
1804 atdevbase = ISA_HOLE_START + KERNBASE;
1805
1806 metadata_missing = 0;
1807 if (bootinfo.bi_modulep) {
1808 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1809 preload_bootstrap_relocate(KERNBASE);
1810 } else {
1811 metadata_missing = 1;
1812 }
1813 if (bootinfo.bi_envp)
1814 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1815
c5cc06e3
MD
1816 /*
1817 * start with one cpu. Note: ncpus2_shift and ncpus2_mask are left
1818 * at 0.
1819 */
4e8e646b 1820 ncpus = 1;
c5cc06e3 1821 ncpus2 = 1;
984263bc
MD
1822 /* Init basic tunables, hz etc */
1823 init_param1();
1824
1825 /*
1826 * make gdt memory segments, the code segment goes up to end of the
1827 * page with etext in it, the data segment goes to the end of
1828 * the address space
1829 */
1830 /*
1831 * XXX text protection is temporarily (?) disabled. The limit was
1832 * i386_btop(round_page(etext)) - 1.
1833 */
1834 gdt_segs[GCODE_SEL].ssd_limit = atop(0 - 1);
1835 gdt_segs[GDATA_SEL].ssd_limit = atop(0 - 1);
17a9f566 1836
984263bc
MD
1837 gdt_segs[GPRIV_SEL].ssd_limit =
1838 atop(sizeof(struct privatespace) - 1);
8ad65e08 1839 gdt_segs[GPRIV_SEL].ssd_base = (int) &CPU_prvspace[0];
984263bc 1840 gdt_segs[GPROC0_SEL].ssd_base =
85100692 1841 (int) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
17a9f566 1842
85100692 1843 gd->mi.gd_prvspace = &CPU_prvspace[0];
17a9f566 1844
84b592ba
MD
1845 /*
1846 * Note: on both UP and SMP curthread must be set non-NULL
1847 * early in the boot sequence because the system assumes
1848 * that 'curthread' is never NULL.
1849 */
984263bc
MD
1850
1851 for (x = 0; x < NGDT; x++) {
1852#ifdef BDE_DEBUGGER
1853 /* avoid overwriting db entries with APM ones */
1854 if (x >= GAPMCODE32_SEL && x <= GAPMDATA_SEL)
1855 continue;
1856#endif
1857 ssdtosd(&gdt_segs[x], &gdt[x].sd);
1858 }
1859
1860 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1861 r_gdt.rd_base = (int) gdt;
1862 lgdt(&r_gdt);
1863
73e4f7b9
MD
1864 mi_gdinit(&gd->mi, 0);
1865 cpu_gdinit(gd, 0);
f470d0c8 1866 lwkt_init_thread(&thread0, proc0paddr, LWKT_THREAD_STACK, 0, &gd->mi);
73e4f7b9
MD
1867 lwkt_set_comm(&thread0, "thread0");
1868 proc0.p_addr = (void *)thread0.td_kstack;
065b709a
SS
1869 LIST_INIT(&proc0.p_lwps);
1870 LIST_INSERT_HEAD(&proc0.p_lwps, &proc0.p_lwp, lwp_list);
1871 proc0.p_lwp.lwp_thread = &thread0;
1872 proc0.p_lwp.lwp_proc = &proc0;
a77ac49d 1873 proc0.p_usched = &usched_bsd4;
98a7f915 1874 varsymset_init(&proc0.p_varsymset, NULL);
d9eea1a5 1875 thread0.td_flags |= TDF_RUNNING;
73e4f7b9 1876 thread0.td_proc = &proc0;
ef09c3ed 1877 thread0.td_lwp = &proc0.p_lwp;
73e4f7b9 1878 thread0.td_switch = cpu_heavy_switch; /* YYY eventually LWKT */
e43a034f 1879 safepri = TDPRI_MAX;
73e4f7b9 1880
984263bc
MD
1881 /* make ldt memory segments */
1882 /*
1883 * XXX - VM_MAXUSER_ADDRESS is an end address, not a max. And it
1884 * should be spelled ...MAX_USER...
1885 */
1886 ldt_segs[LUCODE_SEL].ssd_limit = atop(VM_MAXUSER_ADDRESS - 1);
1887 ldt_segs[LUDATA_SEL].ssd_limit = atop(VM_MAXUSER_ADDRESS - 1);
1888 for (x = 0; x < sizeof ldt_segs / sizeof ldt_segs[0]; x++)
1889 ssdtosd(&ldt_segs[x], &ldt[x].sd);
1890
1891 _default_ldt = GSEL(GLDT_SEL, SEL_KPL);
1892 lldt(_default_ldt);
17a9f566 1893 gd->gd_currentldt = _default_ldt;
8a8d5d85
MD
1894 /* spinlocks and the BGL */
1895 init_locks();
984263bc
MD
1896
1897 /* exceptions */
f7bc9806
MD
1898 for (x = 0; x < NIDT; x++) {
1899#ifdef DEBUG_INTERRUPTS
1900 setidt(x, Xrsvdary[x], SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1901#else
1902 setidt(x, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1903#endif
1904 }
984263bc
MD
1905 setidt(0, &IDTVEC(div), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1906 setidt(1, &IDTVEC(dbg), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1907 setidt(2, &IDTVEC(nmi), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1908 setidt(3, &IDTVEC(bpt), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1909 setidt(4, &IDTVEC(ofl), SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
1910 setidt(5, &IDTVEC(bnd), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1911 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1912 setidt(7, &IDTVEC(dna), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1913 setidt(8, 0, SDT_SYSTASKGT, SEL_KPL, GSEL(GPANIC_SEL, SEL_KPL));
1914 setidt(9, &IDTVEC(fpusegm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1915 setidt(10, &IDTVEC(tss), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1916 setidt(11, &IDTVEC(missing), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1917 setidt(12, &IDTVEC(stk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1918 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1919 setidt(14, &IDTVEC(page), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
f7bc9806 1920 setidt(15, &IDTVEC(rsvd0), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
1921 setidt(16, &IDTVEC(fpu), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1922 setidt(17, &IDTVEC(align), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1923 setidt(18, &IDTVEC(mchk), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1924 setidt(19, &IDTVEC(xmm), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1925 setidt(0x80, &IDTVEC(int0x80_syscall),
1926 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
a64ba182
MD
1927 setidt(0x81, &IDTVEC(int0x81_syscall),
1928 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
7062f5b4
EN
1929 setidt(0x82, &IDTVEC(int0x82_syscall),
1930 SDT_SYS386TGT, SEL_UPL, GSEL(GCODE_SEL, SEL_KPL));
984263bc
MD
1931
1932 r_idt.rd_limit = sizeof(idt0) - 1;
1933 r_idt.rd_base = (int) idt;
1934 lidt(&r_idt);
1935
1936 /*
1937 * Initialize the console before we print anything out.
1938 */
1939 cninit();
1940
1941 if (metadata_missing)
1942 printf("WARNING: loader(8) metadata is missing!\n");
1943
984263bc
MD
1944#if NISA >0
1945 isa_defaultirq();
1946#endif
1947 rand_initialize();
1948
1949#ifdef DDB
1950 kdb_init();
1951 if (boothowto & RB_KDB)
1952 Debugger("Boot flags requested debugger");
1953#endif
1954
1955 finishidentcpu(); /* Final stage of CPU initialization */
1956 setidt(6, &IDTVEC(ill), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1957 setidt(13, &IDTVEC(prot), SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1958 initializecpu(); /* Initialize CPU registers */
1959
b7c628e4
MD
1960 /*
1961 * make an initial tss so cpu can get interrupt stack on syscall!
1962 * The 16 bytes is to save room for a VM86 context.
1963 */
17a9f566
MD
1964 gd->gd_common_tss.tss_esp0 = (int) thread0.td_pcb - 16;
1965 gd->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL) ;
984263bc 1966 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
17a9f566
MD
1967 gd->gd_tss_gdt = &gdt[GPROC0_SEL].sd;
1968 gd->gd_common_tssd = *gd->gd_tss_gdt;
85100692 1969 gd->gd_common_tss.tss_ioopt = (sizeof gd->gd_common_tss) << 16;
984263bc
MD
1970 ltr(gsel_tss);
1971
1972 dblfault_tss.tss_esp = dblfault_tss.tss_esp0 = dblfault_tss.tss_esp1 =
1973 dblfault_tss.tss_esp2 = (int) &dblfault_stack[sizeof(dblfault_stack)];
1974 dblfault_tss.tss_ss = dblfault_tss.tss_ss0 = dblfault_tss.tss_ss1 =
1975 dblfault_tss.tss_ss2 = GSEL(GDATA_SEL, SEL_KPL);
1976 dblfault_tss.tss_cr3 = (int)IdlePTD;
1977 dblfault_tss.tss_eip = (int) dblfault_handler;
1978 dblfault_tss.tss_eflags = PSL_KERNEL;
1979 dblfault_tss.tss_ds = dblfault_tss.tss_es =
1980 dblfault_tss.tss_gs = GSEL(GDATA_SEL, SEL_KPL);
1981 dblfault_tss.tss_fs = GSEL(GPRIV_SEL, SEL_KPL);
1982 dblfault_tss.tss_cs = GSEL(GCODE_SEL, SEL_KPL);
1983 dblfault_tss.tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
1984
1985 vm86_initialize();
1986 getmemsize(first);
1987 init_param2(physmem);
1988
1989 /* now running on new page tables, configured,and u/iom is accessible */
1990
1991 /* Map the message buffer. */
1992 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1993 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1994
1995 msgbufinit(msgbufp, MSGBUF_SIZE);
1996
1997 /* make a call gate to reenter kernel with */
1998 gdp = &ldt[LSYS5CALLS_SEL].gd;
1999
2000 x = (int) &IDTVEC(syscall);
2001 gdp->gd_looffset = x++;
2002 gdp->gd_selector = GSEL(GCODE_SEL,SEL_KPL);
2003 gdp->gd_stkcpy = 1;
2004 gdp->gd_type = SDT_SYS386CGT;
2005 gdp->gd_dpl = SEL_UPL;
2006 gdp->gd_p = 1;
2007 gdp->gd_hioffset = ((int) &IDTVEC(syscall)) >>16;
2008
2009 /* XXX does this work? */
2010 ldt[LBSDICALLS_SEL] = ldt[LSYS5CALLS_SEL];
2011 ldt[LSOL26CALLS_SEL] = ldt[LSYS5CALLS_SEL];
2012
2013 /* transfer to user mode */
2014
2015 _ucodesel = LSEL(LUCODE_SEL, SEL_UPL);
2016 _udatasel = LSEL(LUDATA_SEL, SEL_UPL);
2017
2018 /* setup proc 0's pcb */
b7c628e4
MD
2019 thread0.td_pcb->pcb_flags = 0;
2020 thread0.td_pcb->pcb_cr3 = (int)IdlePTD; /* should already be setup */
b7c628e4 2021 thread0.td_pcb->pcb_ext = 0;
065b709a 2022 proc0.p_lwp.lwp_md.md_regs = &proc0_tf;
984263bc
MD
2023}
2024
8ad65e08 2025/*
17a9f566
MD
2026 * Initialize machine-dependant portions of the global data structure.
2027 * Note that the global data area and cpu0's idlestack in the private
2028 * data space were allocated in locore.
ef0fdad1
MD
2029 *
2030 * Note: the idlethread's cpl is 0
73e4f7b9
MD
2031 *
2032 * WARNING! Called from early boot, 'mycpu' may not work yet.
8ad65e08
MD
2033 */
2034void
85100692 2035cpu_gdinit(struct mdglobaldata *gd, int cpu)
8ad65e08 2036{
7d0bac62 2037 if (cpu)
a2a5ad0d 2038 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
17a9f566 2039
f470d0c8
MD
2040 lwkt_init_thread(&gd->mi.gd_idlethread,
2041 gd->mi.gd_prvspace->idlestack,
2042 sizeof(gd->mi.gd_prvspace->idlestack), 0, &gd->mi);
a2a5ad0d
MD
2043 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2044 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2045 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2046 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
8ad65e08
MD
2047}
2048
0cd275af
MD
2049int
2050is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2051{
2052 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2053 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2054 return (TRUE);
2055 }
2056 return (FALSE);
2057}
2058
12e4aaff
MD
2059struct globaldata *
2060globaldata_find(int cpu)
2061{
2062 KKASSERT(cpu >= 0 && cpu < ncpus);
2063 return(&CPU_prvspace[cpu].mdglobaldata.mi);
2064}
2065
984263bc
MD
2066#if defined(I586_CPU) && !defined(NO_F00F_HACK)
2067static void f00f_hack(void *unused);
2068SYSINIT(f00f_hack, SI_SUB_INTRINSIC, SI_ORDER_FIRST, f00f_hack, NULL);
2069
2070static void
17a9f566
MD
2071f00f_hack(void *unused)
2072{
984263bc 2073 struct gate_descriptor *new_idt;
984263bc
MD
2074 vm_offset_t tmp;
2075
2076 if (!has_f00f_bug)
2077 return;
2078
2079 printf("Intel Pentium detected, installing workaround for F00F bug\n");
2080
2081 r_idt.rd_limit = sizeof(idt0) - 1;
2082
2083 tmp = kmem_alloc(kernel_map, PAGE_SIZE * 2);
2084 if (tmp == 0)
2085 panic("kmem_alloc returned 0");
2086 if (((unsigned int)tmp & (PAGE_SIZE-1)) != 0)
2087 panic("kmem_alloc returned non-page-aligned memory");
2088 /* Put the first seven entries in the lower page */
2089 new_idt = (struct gate_descriptor*)(tmp + PAGE_SIZE - (7*8));
2090 bcopy(idt, new_idt, sizeof(idt0));
2091 r_idt.rd_base = (int)new_idt;
2092 lidt(&r_idt);
2093 idt = new_idt;
2094 if (vm_map_protect(kernel_map, tmp, tmp + PAGE_SIZE,
2095 VM_PROT_READ, FALSE) != KERN_SUCCESS)
2096 panic("vm_map_protect failed");
2097 return;
2098}
2099#endif /* defined(I586_CPU) && !NO_F00F_HACK */
2100
2101int
2102ptrace_set_pc(p, addr)
2103 struct proc *p;
2104 unsigned long addr;
2105{
2106 p->p_md.md_regs->tf_eip = addr;
2107 return (0);
2108}
2109
2110int
2111ptrace_single_step(p)
2112 struct proc *p;
2113{
2114 p->p_md.md_regs->tf_eflags |= PSL_T;
2115 return (0);
2116}
2117
2118int ptrace_read_u_check(p, addr, len)
2119 struct proc *p;
2120 vm_offset_t addr;
2121 size_t len;
2122{
2123 vm_offset_t gap;
2124
2125 if ((vm_offset_t) (addr + len) < addr)
2126 return EPERM;
2127 if ((vm_offset_t) (addr + len) <= sizeof(struct user))
2128 return 0;
2129
2130 gap = (char *) p->p_md.md_regs - (char *) p->p_addr;
2131
2132 if ((vm_offset_t) addr < gap)
2133 return EPERM;
2134 if ((vm_offset_t) (addr + len) <=
2135 (vm_offset_t) (gap + sizeof(struct trapframe)))
2136 return 0;
2137 return EPERM;
2138}
2139
2140int ptrace_write_u(p, off, data)
2141 struct proc *p;
2142 vm_offset_t off;
2143 long data;
2144{
2145 struct trapframe frame_copy;
2146 vm_offset_t min;
2147 struct trapframe *tp;
2148
2149 /*
2150 * Privileged kernel state is scattered all over the user area.
2151 * Only allow write access to parts of regs and to fpregs.
2152 */
2153 min = (char *)p->p_md.md_regs - (char *)p->p_addr;
2154 if (off >= min && off <= min + sizeof(struct trapframe) - sizeof(int)) {
2155 tp = p->p_md.md_regs;
2156 frame_copy = *tp;
2157 *(int *)((char *)&frame_copy + (off - min)) = data;
2158 if (!EFL_SECURE(frame_copy.tf_eflags, tp->tf_eflags) ||
2159 !CS_SECURE(frame_copy.tf_cs))
2160 return (EINVAL);
2161 *(int*)((char *)p->p_addr + off) = data;
2162 return (0);
2163 }
b7c628e4
MD
2164
2165 /*
2166 * The PCB is at the end of the user area YYY
2167 */
2168 min = (char *)p->p_thread->td_pcb - (char *)p->p_addr;
2169 min += offsetof(struct pcb, pcb_save);
984263bc
MD
2170 if (off >= min && off <= min + sizeof(union savefpu) - sizeof(int)) {
2171 *(int*)((char *)p->p_addr + off) = data;
2172 return (0);
2173 }
2174 return (EFAULT);
2175}
2176
2177int
2178fill_regs(p, regs)
2179 struct proc *p;
2180 struct reg *regs;
2181{
2182 struct pcb *pcb;
2183 struct trapframe *tp;
2184
2185 tp = p->p_md.md_regs;
2186 regs->r_fs = tp->tf_fs;
2187 regs->r_es = tp->tf_es;
2188 regs->r_ds = tp->tf_ds;
2189 regs->r_edi = tp->tf_edi;
2190 regs->r_esi = tp->tf_esi;
2191 regs->r_ebp = tp->tf_ebp;
2192 regs->r_ebx = tp->tf_ebx;
2193 regs->r_edx = tp->tf_edx;
2194 regs->r_ecx = tp->tf_ecx;
2195 regs->r_eax = tp->tf_eax;
2196 regs->r_eip = tp->tf_eip;
2197 regs->r_cs = tp->tf_cs;
2198 regs->r_eflags = tp->tf_eflags;
2199 regs->r_esp = tp->tf_esp;
2200 regs->r_ss = tp->tf_ss;
b7c628e4 2201 pcb = p->p_thread->td_pcb;
984263bc
MD
2202 regs->r_gs = pcb->pcb_gs;
2203 return (0);
2204}
2205
2206int
2207set_regs(p, regs)
2208 struct proc *p;
2209 struct reg *regs;
2210{
2211 struct pcb *pcb;
2212 struct trapframe *tp;
2213
2214 tp = p->p_md.md_regs;
2215 if (!EFL_SECURE(regs->r_eflags, tp->tf_eflags) ||
2216 !CS_SECURE(regs->r_cs))
2217 return (EINVAL);
2218 tp->tf_fs = regs->r_fs;
2219 tp->tf_es = regs->r_es;
2220 tp->tf_ds = regs->r_ds;
2221 tp->tf_edi = regs->r_edi;
2222 tp->tf_esi = regs->r_esi;
2223 tp->tf_ebp = regs->r_ebp;
2224 tp->tf_ebx = regs->r_ebx;
2225 tp->tf_edx = regs->r_edx;
2226 tp->tf_ecx = regs->r_ecx;
2227 tp->tf_eax = regs->r_eax;
2228 tp->tf_eip = regs->r_eip;
2229 tp->tf_cs = regs->r_cs;
2230 tp->tf_eflags = regs->r_eflags;
2231 tp->tf_esp = regs->r_esp;
2232 tp->tf_ss = regs->r_ss;
b7c628e4 2233 pcb = p->p_thread->td_pcb;
984263bc
MD
2234 pcb->pcb_gs = regs->r_gs;
2235 return (0);
2236}
2237
642a6e88 2238#ifndef CPU_DISABLE_SSE
984263bc
MD
2239static void
2240fill_fpregs_xmm(sv_xmm, sv_87)
2241 struct savexmm *sv_xmm;
2242 struct save87 *sv_87;
2243{
c9faf524
RG
2244 struct env87 *penv_87 = &sv_87->sv_env;
2245 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2246 int i;
2247
2248 /* FPU control/status */
2249 penv_87->en_cw = penv_xmm->en_cw;
2250 penv_87->en_sw = penv_xmm->en_sw;
2251 penv_87->en_tw = penv_xmm->en_tw;
2252 penv_87->en_fip = penv_xmm->en_fip;
2253 penv_87->en_fcs = penv_xmm->en_fcs;
2254 penv_87->en_opcode = penv_xmm->en_opcode;
2255 penv_87->en_foo = penv_xmm->en_foo;
2256 penv_87->en_fos = penv_xmm->en_fos;
2257
2258 /* FPU registers */
2259 for (i = 0; i < 8; ++i)
2260 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2261
2262 sv_87->sv_ex_sw = sv_xmm->sv_ex_sw;
2263}
2264
2265static void
2266set_fpregs_xmm(sv_87, sv_xmm)
2267 struct save87 *sv_87;
2268 struct savexmm *sv_xmm;
2269{
c9faf524
RG
2270 struct env87 *penv_87 = &sv_87->sv_env;
2271 struct envxmm *penv_xmm = &sv_xmm->sv_env;
984263bc
MD
2272 int i;
2273
2274 /* FPU control/status */
2275 penv_xmm->en_cw = penv_87->en_cw;
2276 penv_xmm->en_sw = penv_87->en_sw;
2277 penv_xmm->en_tw = penv_87->en_tw;
2278 penv_xmm->en_fip = penv_87->en_fip;
2279 penv_xmm->en_fcs = penv_87->en_fcs;
2280 penv_xmm->en_opcode = penv_87->en_opcode;
2281 penv_xmm->en_foo = penv_87->en_foo;
2282 penv_xmm->en_fos = penv_87->en_fos;
2283
2284 /* FPU registers */
2285 for (i = 0; i < 8; ++i)
2286 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2287
2288 sv_xmm->sv_ex_sw = sv_87->sv_ex_sw;
2289}
642a6e88 2290#endif /* CPU_DISABLE_SSE */
984263bc
MD
2291
2292int
2293fill_fpregs(p, fpregs)
2294 struct proc *p;
2295 struct fpreg *fpregs;
2296{
642a6e88 2297#ifndef CPU_DISABLE_SSE
984263bc 2298 if (cpu_fxsr) {
b7c628e4 2299 fill_fpregs_xmm(&p->p_thread->td_pcb->pcb_save.sv_xmm,
984263bc
MD
2300 (struct save87 *)fpregs);
2301 return (0);
2302 }
642a6e88 2303#endif /* CPU_DISABLE_SSE */
b7c628e4 2304 bcopy(&p->p_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
984263bc
MD
2305 return (0);
2306}
2307
2308int
2309set_fpregs(p, fpregs)
2310 struct proc *p;
2311 struct fpreg *fpregs;
2312{
642a6e88 2313#ifndef CPU_DISABLE_SSE
984263bc
MD
2314 if (cpu_fxsr) {
2315 set_fpregs_xmm((struct save87 *)fpregs,
b7c628e4 2316 &p->p_thread->td_pcb->pcb_save.sv_xmm);
984263bc
MD
2317 return (0);
2318 }
642a6e88 2319#endif /* CPU_DISABLE_SSE */
b7c628e4 2320 bcopy(fpregs, &p->p_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
984263bc
MD
2321 return (0);
2322}
2323
2324int
2325fill_dbregs(p, dbregs)
2326 struct proc *p;
2327 struct dbreg *dbregs;
2328{
2329 struct pcb *pcb;
2330
2331 if (p == NULL) {
2332 dbregs->dr0 = rdr0();
2333 dbregs->dr1 = rdr1();
2334 dbregs->dr2 = rdr2();
2335 dbregs->dr3 = rdr3();
2336 dbregs->dr4 = rdr4();
2337 dbregs->dr5 = rdr5();
2338 dbregs->dr6 = rdr6();
2339 dbregs->dr7 = rdr7();
2340 }
2341 else {
b7c628e4 2342 pcb = p->p_thread->td_pcb;
984263bc
MD
2343 dbregs->dr0 = pcb->pcb_dr0;
2344 dbregs->dr1 = pcb->pcb_dr1;
2345 dbregs->dr2 = pcb->pcb_dr2;
2346 dbregs->dr3 = pcb->pcb_dr3;
2347 dbregs->dr4 = 0;
2348 dbregs->dr5 = 0;
2349 dbregs->dr6 = pcb->pcb_dr6;
2350 dbregs->dr7 = pcb->pcb_dr7;
2351 }
2352 return (0);
2353}
2354
2355int
2356set_dbregs(p, dbregs)
2357 struct proc *p;
2358 struct dbreg *dbregs;
2359{
2360 struct pcb *pcb;
2361 int i;
2362 u_int32_t mask1, mask2;
2363
2364 if (p == NULL) {
2365 load_dr0(dbregs->dr0);
2366 load_dr1(dbregs->dr1);
2367 load_dr2(dbregs->dr2);
2368 load_dr3(dbregs->dr3);
2369 load_dr4(dbregs->dr4);
2370 load_dr5(dbregs->dr5);
2371 load_dr6(dbregs->dr6);
2372 load_dr7(dbregs->dr7);
2373 }
2374 else {
2375 /*
2376 * Don't let an illegal value for dr7 get set. Specifically,
2377 * check for undefined settings. Setting these bit patterns
2378 * result in undefined behaviour and can lead to an unexpected
2379 * TRCTRAP.
2380 */
2381 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 8;
2382 i++, mask1 <<= 2, mask2 <<= 2)
2383 if ((dbregs->dr7 & mask1) == mask2)
2384 return (EINVAL);
2385
b7c628e4 2386 pcb = p->p_thread->td_pcb;
984263bc
MD
2387
2388 /*
2389 * Don't let a process set a breakpoint that is not within the
2390 * process's address space. If a process could do this, it
2391 * could halt the system by setting a breakpoint in the kernel
2392 * (if ddb was enabled). Thus, we need to check to make sure
2393 * that no breakpoints are being enabled for addresses outside
2394 * process's address space, unless, perhaps, we were called by
2395 * uid 0.
2396 *
2397 * XXX - what about when the watched area of the user's
2398 * address space is written into from within the kernel
2399 * ... wouldn't that still cause a breakpoint to be generated
2400 * from within kernel mode?
2401 */
2402
dadab5e9 2403 if (suser_cred(p->p_ucred, 0) != 0) {
984263bc
MD
2404 if (dbregs->dr7 & 0x3) {
2405 /* dr0 is enabled */
2406 if (dbregs->dr0 >= VM_MAXUSER_ADDRESS)
2407 return (EINVAL);
2408 }
2409
2410 if (dbregs->dr7 & (0x3<<2)) {
2411 /* dr1 is enabled */
2412 if (dbregs->dr1 >= VM_MAXUSER_ADDRESS)
2413 return (EINVAL);
2414 }
2415
2416 if (dbregs->dr7 & (0x3<<4)) {
2417 /* dr2 is enabled */
2418 if (dbregs->dr2 >= VM_MAXUSER_ADDRESS)
2419 return (EINVAL);
2420 }
2421
2422 if (dbregs->dr7 & (0x3<<6)) {
2423 /* dr3 is enabled */
2424 if (dbregs->dr3 >= VM_MAXUSER_ADDRESS)
2425 return (EINVAL);
2426 }
2427 }
2428
2429 pcb->pcb_dr0 = dbregs->dr0;
2430 pcb->pcb_dr1 = dbregs->dr1;
2431 pcb->pcb_dr2 = dbregs->dr2;
2432 pcb->pcb_dr3 = dbregs->dr3;
2433 pcb->pcb_dr6 = dbregs->dr6;
2434 pcb->pcb_dr7 = dbregs->dr7;
2435
2436 pcb->pcb_flags |= PCB_DBREGS;
2437 }
2438
2439 return (0);
2440}
2441
2442/*
2443 * Return > 0 if a hardware breakpoint has been hit, and the
2444 * breakpoint was in user space. Return 0, otherwise.
2445 */
2446int
2447user_dbreg_trap(void)
2448{
2449 u_int32_t dr7, dr6; /* debug registers dr6 and dr7 */
2450 u_int32_t bp; /* breakpoint bits extracted from dr6 */
2451 int nbp; /* number of breakpoints that triggered */
2452 caddr_t addr[4]; /* breakpoint addresses */
2453 int i;
2454
2455 dr7 = rdr7();
2456 if ((dr7 & 0x000000ff) == 0) {
2457 /*
2458 * all GE and LE bits in the dr7 register are zero,
2459 * thus the trap couldn't have been caused by the
2460 * hardware debug registers
2461 */
2462 return 0;
2463 }
2464
2465 nbp = 0;
2466 dr6 = rdr6();
2467 bp = dr6 & 0x0000000f;
2468
2469 if (!bp) {
2470 /*
2471 * None of the breakpoint bits are set meaning this
2472 * trap was not caused by any of the debug registers
2473 */
2474 return 0;
2475 }
2476
2477 /*
2478 * at least one of the breakpoints were hit, check to see
2479 * which ones and if any of them are user space addresses
2480 */
2481
2482 if (bp & 0x01) {
2483 addr[nbp++] = (caddr_t)rdr0();
2484 }
2485 if (bp & 0x02) {
2486 addr[nbp++] = (caddr_t)rdr1();
2487 }
2488 if (bp & 0x04) {
2489 addr[nbp++] = (caddr_t)rdr2();
2490 }
2491 if (bp & 0x08) {
2492 addr[nbp++] = (caddr_t)rdr3();
2493 }
2494
2495 for (i=0; i<nbp; i++) {
2496 if (addr[i] <
2497 (caddr_t)VM_MAXUSER_ADDRESS) {
2498 /*
2499 * addr[i] is in user space
2500 */
2501 return nbp;
2502 }
2503 }
2504
2505 /*
2506 * None of the breakpoints are in user space.
2507 */
2508 return 0;
2509}
2510
2511
2512#ifndef DDB
2513void
2514Debugger(const char *msg)
2515{
2516 printf("Debugger(\"%s\") called.\n", msg);
2517}
2518#endif /* no DDB */
2519
f9d8cd12
MD
2520#include <machine/apicvar.h>
2521
2522/*
2523 * Provide stub functions so that the MADT APIC enumerator in the acpi
2524 * kernel module will link against a kernel without 'option APIC_IO'.
2525 *
2526 * XXX - This is a gross hack.
2527 */
2528void
2529apic_register_enumerator(struct apic_enumerator *enumerator)
2530{
2531}
2532
2533void *
2534ioapic_create(uintptr_t addr, int32_t id, int intbase)
2535{
2536 return (NULL);
2537}
2538
2539int
2540ioapic_disable_pin(void *cookie, u_int pin)
2541{
2542 return (ENXIO);
2543}
2544
2545void
2546ioapic_enable_mixed_mode(void)
2547{
2548}
2549
2550int
2551ioapic_get_vector(void *cookie, u_int pin)
2552{
2553 return (-1);
2554}
2555
2556void
2557ioapic_register(void *cookie)
2558{
2559}
2560
2561int
2562ioapic_remap_vector(void *cookie, u_int pin, int vector)
2563{
2564 return (ENXIO);
2565}
2566
2567int
2568ioapic_set_extint(void *cookie, u_int pin)
2569{
2570 return (ENXIO);
2571}
2572
2573int
2574ioapic_set_nmi(void *cookie, u_int pin)
2575{
2576 return (ENXIO);
2577}
2578
2579int
2580ioapic_set_polarity(void *cookie, u_int pin, char activehi)
2581{
2582 return (ENXIO);
2583}
2584
2585int
2586ioapic_set_triggermode(void *cookie, u_int pin, char edgetrigger)
2587{
2588 return (ENXIO);
2589}
2590
2591void
2592lapic_create(u_int apic_id, int boot_cpu)
2593{
2594}
2595
2596void
2597lapic_init(uintptr_t addr)
2598{
2599}
2600
2601int
2602lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode)
2603{
2604 return (ENXIO);
2605}
2606
2607int
2608lapic_set_lvt_polarity(u_int apic_id, u_int lvt, u_char activehi)
2609{
2610 return (ENXIO);
2611}
2612
2613int
2614lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, u_char edgetrigger)
2615{
2616 return (ENXIO);
2617}
f9d8cd12 2618
984263bc
MD
2619#include <sys/disklabel.h>
2620
2621/*
2622 * Determine the size of the transfer, and make sure it is
2623 * within the boundaries of the partition. Adjust transfer
2624 * if needed, and signal errors or early completion.
2625 */
2626int
2627bounds_check_with_label(struct buf *bp, struct disklabel *lp, int wlabel)
2628{
2629 struct partition *p = lp->d_partitions + dkpart(bp->b_dev);
2630 int labelsect = lp->d_partitions[0].p_offset;
2631 int maxsz = p->p_size,
2632 sz = (bp->b_bcount + DEV_BSIZE - 1) >> DEV_BSHIFT;
2633
2634 /* overwriting disk label ? */
2635 /* XXX should also protect bootstrap in first 8K */
2636 if (bp->b_blkno + p->p_offset <= LABELSECTOR + labelsect &&
2637#if LABELSECTOR != 0
2638 bp->b_blkno + p->p_offset + sz > LABELSECTOR + labelsect &&
2639#endif
2640 (bp->b_flags & B_READ) == 0 && wlabel == 0) {
2641 bp->b_error = EROFS;
2642 goto bad;
2643 }
2644
2645#if defined(DOSBBSECTOR) && defined(notyet)
2646 /* overwriting master boot record? */
2647 if (bp->b_blkno + p->p_offset <= DOSBBSECTOR &&
2648 (bp->b_flags & B_READ) == 0 && wlabel == 0) {
2649 bp->b_error = EROFS;
2650 goto bad;
2651 }
2652#endif
2653
2654 /* beyond partition? */
2655 if (bp->b_blkno < 0 || bp->b_blkno + sz > maxsz) {
2656 /* if exactly at end of disk, return an EOF */
2657 if (bp->b_blkno == maxsz) {
2658 bp->b_resid = bp->b_bcount;
2659 return(0);
2660 }
2661 /* or truncate if part of it fits */
2662 sz = maxsz - bp->b_blkno;
2663 if (sz <= 0) {
2664 bp->b_error = EINVAL;
2665 goto bad;
2666 }
2667 bp->b_bcount = sz << DEV_BSHIFT;
2668 }
2669
2670 bp->b_pblkno = bp->b_blkno + p->p_offset;
2671 return(1);
2672
2673bad:
2674 bp->b_flags |= B_ERROR;
2675 return(-1);
2676}
2677
2678#ifdef DDB
2679
2680/*
2681 * Provide inb() and outb() as functions. They are normally only
2682 * available as macros calling inlined functions, thus cannot be
2683 * called inside DDB.
2684 *
2685 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2686 */
2687
2688#undef inb
2689#undef outb
2690
2691/* silence compiler warnings */
2692u_char inb(u_int);
2693void outb(u_int, u_char);
2694
2695u_char
2696inb(u_int port)
2697{
2698 u_char data;
2699 /*
2700 * We use %%dx and not %1 here because i/o is done at %dx and not at
2701 * %edx, while gcc generates inferior code (movw instead of movl)
2702 * if we tell it to load (u_short) port.
2703 */
2704 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2705 return (data);
2706}
2707
2708void
2709outb(u_int port, u_char data)
2710{
2711 u_char al;
2712 /*
2713 * Use an unnecessary assignment to help gcc's register allocator.
2714 * This make a large difference for gcc-1.40 and a tiny difference
2715 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2716 * best results. gcc-2.6.0 can't handle this.
2717 */
2718 al = data;
2719 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2720}
2721
2722#endif /* DDB */
8a8d5d85
MD
2723
2724
2725
2726#include "opt_cpu.h"
8a8d5d85
MD
2727
2728
2729/*
2730 * initialize all the SMP locks
2731 */
2732
2733/* critical region around IO APIC, apic_imen */
b1af91cb 2734struct spinlock_deprecated imen_spinlock;
8a8d5d85
MD
2735
2736/* Make FAST_INTR() routines sequential */
b1af91cb 2737struct spinlock_deprecated fast_intr_spinlock;
8a8d5d85
MD
2738
2739/* critical region for old style disable_intr/enable_intr */
b1af91cb 2740struct spinlock_deprecated mpintr_spinlock;
8a8d5d85
MD
2741
2742/* critical region around INTR() routines */
b1af91cb 2743struct spinlock_deprecated intr_spinlock;
8a8d5d85
MD
2744
2745/* lock region used by kernel profiling */
b1af91cb 2746struct spinlock_deprecated mcount_spinlock;
8a8d5d85
MD
2747
2748/* locks com (tty) data/hardware accesses: a FASTINTR() */
b1af91cb 2749struct spinlock_deprecated com_spinlock;
8a8d5d85
MD
2750
2751/* locks kernel printfs */
b1af91cb 2752struct spinlock_deprecated cons_spinlock;
8a8d5d85
MD
2753
2754/* lock regions around the clock hardware */
b1af91cb 2755struct spinlock_deprecated clock_spinlock;
8a8d5d85
MD
2756
2757/* lock around the MP rendezvous */
b1af91cb 2758struct spinlock_deprecated smp_rv_spinlock;
8a8d5d85
MD
2759
2760static void
2761init_locks(void)
2762{
2763 /*
2764 * mp_lock = 0; BSP already owns the MP lock
2765 */
2766 /*
2767 * Get the initial mp_lock with a count of 1 for the BSP.
2768 * This uses a LOGICAL cpu ID, ie BSP == 0.
2769 */
2770#ifdef SMP
2771 cpu_get_initial_mplock();
2772#endif
41a01a4d 2773 /* DEPRECATED */
8a8d5d85
MD
2774 spin_lock_init(&mcount_spinlock);
2775 spin_lock_init(&fast_intr_spinlock);
2776 spin_lock_init(&intr_spinlock);
2777 spin_lock_init(&mpintr_spinlock);
2778 spin_lock_init(&imen_spinlock);
2779 spin_lock_init(&smp_rv_spinlock);
2780 spin_lock_init(&com_spinlock);
2781 spin_lock_init(&clock_spinlock);
2782 spin_lock_init(&cons_spinlock);
41a01a4d
MD
2783
2784 /* our token pool needs to work early */
2785 lwkt_token_pool_init();
8a8d5d85
MD
2786}
2787