mii: regen
[dragonfly.git] / sys / dev / netif / mii_layer / miidevs.h
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1/*
2 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
984263bc 3 */
3a18dc9d 4/* $FreeBSD: src/sys/dev/mii/miidevs,v 1.4.2.13 2003/07/22 02:12:55 ps Exp $ */
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5/*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
6
7/*-
8 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
13 * NASA Ames Research Center.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the NetBSD
26 * Foundation, Inc. and its contributors.
27 * 4. Neither the name of The NetBSD Foundation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
42 */
43
44/*
45 * List of known MII OUIs.
46 * For a complete list see http://standards.ieee.org/regauth/oui/
47 *
48 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
49 * to the 16 bits available in the id registers. The MII_OUI() macro
50 * in "mii.h" reflects the most obvious way. If a vendor uses a
51 * different mapping, an "xx" prefixed OUI is defined here which is
52 * mangled accordingly to compensate.
53 */
54
55#define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
56#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
9f447151 57#define MII_OUI_ATHEROS 0x001374 /* Atheros Communications */
984263bc 58#define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
b381475d 59#define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
46ad174e 60#define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
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61#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
62#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
63#define MII_OUI_INTEL 0x00aa00 /* Intel */
64#define MII_OUI_JATO 0x00e083 /* Jato Technologies */
db864db0 65#define MII_OUI_JMICRON 0x001b8c /* JMicron Technologies */
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66#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
67#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
68#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
69#define MII_OUI_REALTEK 0x000020 /* RealTek Semicondctor */
46ad174e 70#define MII_OUI_REALTEK2 0x00e04c /* RealTek Semicondctor */
984263bc 71#define MII_OUI_SEEQ 0x00a07d /* Seeq */
9a5b6617 72#define MII_OUI_AGERE 0x00a0bc /* Agere Systems */
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73#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
74#define MII_OUI_TDK 0x00c039 /* TDK */
75#define MII_OUI_TI 0x080028 /* Texas Instruments */
76#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
77#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
46ad174e 78#define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
7896c317 79#define MII_OUI_VITESSE 0x0001c1 /* Vitesse Semiconductor */
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80
81/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
82#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
83
84/* Intel 82553 A/B steppings */
85#define MII_OUI_xxINTEL 0x00f800 /* Intel */
86
87/* some vendors have the bits swapped within bytes
88 (ie, ordered as on the wire) */
89#define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
90#define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
91#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
92#define MII_OUI_xxSEEQ 0x0005be /* Seeq */
93#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
94#define MII_OUI_xxTI 0x100014 /* Texas Instruments */
95#define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
96
97/* Level 1 is completely different - from right to left.
98 (Two bits get lost in the third OUI byte.) */
99#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
46ad174e 100#define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */
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101
102/* Don't know what's going on here. */
103#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
6ccf6638 104#define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom Corporation */
999c2ad1 105#define MII_OUI_xxBROADCOM3 0x00d897 /* Broadcom Corporation */
984263bc 106
7896c317 107/* This is the OUI of the gigE PHY in the RealTek 8211B/8169S/8110S chips */
e2d6d204 108#define MII_OUI_xxREALTEK 0x000732 /* */
984263bc 109
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110#define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
111#define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
112
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113/*
114 * List of known models. Grouped by oui.
115 */
116
9a5b6617 117/* Agere Systems PHYs */
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118#define MII_MODEL_AGERE_ET1011 0x0001
119#define MII_STR_AGERE_ET1011 "ET1011 10/100/1000baseT PHY"
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120#define MII_MODEL_AGERE_ET1011C 0x0004
121#define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
122
984263bc 123/* Altima Communications PHYs */
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124#define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001
125#define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 media interface"
126#define MII_MODEL_xxALTIMA_AC101L 0x0012
127#define MII_STR_xxALTIMA_AC101L "AC101L 10/100 media interface"
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128#define MII_MODEL_xxALTIMA_AC101 0x0021
129#define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
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130/* AMD Am79C875 have ALTIMA OUI */
131#define MII_MODEL_xxALTIMA_Am79C875 0x0014
132#define MII_STR_xxALTIMA_Am79C875 "Am79C875 10/100 media interface"
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133
134/* Advanced Micro Devices PHYs */
135#define MII_MODEL_xxAMD_79C873 0x0000
136#define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
137#define MII_MODEL_AMD_79c973phy 0x0036
138#define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
139#define MII_MODEL_AMD_79c978 0x0039
140#define MII_STR_AMD_79c978 "Am79c978 HomePNA PHY"
141
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142/* Atheros Communications/Attansic PHYs. */
143#define MII_MODEL_ATHEROS_F1 0x0001
144#define MII_STR_ATHEROS_F1 "Atheros F1 10/100/1000 PHY"
145#define MII_MODEL_ATHEROS_F2 0x0002
146#define MII_STR_ATHEROS_F2 "Atheros F2 10/100 PHY"
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147#define MII_MODEL_ATHEROS_F1_7 0x0007
148#define MII_STR_ATHEROS_F1_7 "Atheros F1 10/100/1000 PHY"
9f447151 149
984263bc 150/* Broadcom Corp. PHYs. */
46ad174e 151#define MII_MODEL_BROADCOM_BCM5400 0x0004
ede40c20 152#define MII_STR_BROADCOM_BCM5400 "BCM5400 100/1000baseT PHY"
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153#define MII_MODEL_BROADCOM_BCM5401 0x0005
154#define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY"
155#define MII_MODEL_BROADCOM_BCM5411 0x0007
156#define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY"
157#define MII_MODEL_BROADCOM_3C905B 0x0012
158#define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY"
159#define MII_MODEL_BROADCOM_3C905C 0x0017
160#define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
161#define MII_MODEL_BROADCOM_BCM5221 0x001e
162#define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY"
163#define MII_MODEL_BROADCOM_BCM5201 0x0021
164#define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY"
165#define MII_MODEL_BROADCOM_BCM5214 0x0028
166#define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY"
167#define MII_MODEL_BROADCOM_BCM5222 0x0032
168#define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY"
169#define MII_MODEL_BROADCOM_BCM5220 0x0033
170#define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY"
171#define MII_MODEL_BROADCOM_BCM4401 0x0036
172#define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY"
984263bc 173#define MII_MODEL_xxBROADCOM_BCM5400 0x0004
ede40c20 174#define MII_STR_xxBROADCOM_BCM5400 "Broadcom 100/1000baseT PHY"
984263bc 175#define MII_MODEL_xxBROADCOM_BCM5401 0x0005
ede40c20 176#define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY"
984263bc 177#define MII_MODEL_xxBROADCOM_BCM5411 0x0007
ede40c20 178#define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY"
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179#define MII_MODEL_xxBROADCOM_BCM5464 0x000b
180#define MII_STR_xxBROADCOM_BCM5464 "BCM5464 10/100/1000baseT PHY"
181#define MII_MODEL_xxBROADCOM_BCM5461 0x000c
182#define MII_STR_xxBROADCOM_BCM5461 "BCM5461 10/100/1000baseT PHY"
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183#define MII_MODEL_xxBROADCOM_BCM5462 0x000d
184#define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY"
185#define MII_MODEL_xxBROADCOM_BCM5421 0x000e
186#define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY"
187#define MII_MODEL_xxBROADCOM_BCM5752 0x0010
188#define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY"
984263bc 189#define MII_MODEL_xxBROADCOM_BCM5701 0x0011
ede40c20 190#define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY"
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191#define MII_MODEL_xxBROADCOM_BCM5706C 0x0015
192#define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY"
984263bc 193#define MII_MODEL_xxBROADCOM_BCM5703 0x0016
ede40c20 194#define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY"
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195#define MII_MODEL_xxBROADCOM_BCM5750 0x0018
196#define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY"
984263bc 197#define MII_MODEL_xxBROADCOM_BCM5704 0x0019
ede40c20 198#define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY"
7e40b8c5 199#define MII_MODEL_xxBROADCOM_BCM5705 0x001a
ede40c20 200#define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY"
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201#define MII_MODEL_xxBROADCOM_BCM54K2 0x002e
202#define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY"
203#define MII_MODEL_xxBROADCOM_BCM5714 0x0034
204#define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY"
205#define MII_MODEL_xxBROADCOM_BCM5780 0x0035
206#define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY"
207#define MII_MODEL_xxBROADCOM_BCM5708C 0x0036
208#define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY"
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209#define MII_MODEL_xxBROADCOM2_BCM54XX 0x0007
210#define MII_STR_xxBROADCOM2_BCM54XX "BCM54XX 10/100/1000baseT PHY"
211#define MII_MODEL_xxBROADCOM2_BCM5481 0x000a
212#define MII_STR_xxBROADCOM2_BCM5481 "BCM5481 10/100/1000baseT PHY"
213#define MII_MODEL_xxBROADCOM2_BCM5482 0x000b
214#define MII_STR_xxBROADCOM2_BCM5482 "BCM5482 10/100/1000baseT PHY"
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215#define MII_MODEL_xxBROADCOM2_BCM5755 0x000c
216#define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY"
217#define MII_MODEL_xxBROADCOM2_BCM5787 0x000e
218#define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY"
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219#define MII_MODEL_xxBROADCOM2_BCM5708S 0x0015
220#define MII_STR_xxBROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY"
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221#define MII_MODEL_xxBROADCOM2_BCM5709CAX 0x002c
222#define MII_STR_xxBROADCOM2_BCM5709CAX "BCM5709C(AX) 10/100/1000baseT PHY"
81f1f2b8 223#define MII_MODEL_xxBROADCOM2_BCM5722 0x002d
8d31e681 224#define MII_STR_xxBROADCOM2_BCM5722 "BCM5722 10/100/1000baseT PHY"
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225#define MII_MODEL_xxBROADCOM2_BCM5784 0x003a
226#define MII_STR_xxBROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY"
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227#define MII_MODEL_xxBROADCOM2_BCM5709C 0x003c
228#define MII_STR_xxBROADCOM2_BCM5709C "BCM5709C 10/100/1000baseT PHY"
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229#define MII_MODEL_xxBROADCOM2_BCM5761 0x003d
230#define MII_STR_xxBROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY"
231#define MII_MODEL_xxBROADCOM2_BCM5709S 0x003f
232#define MII_STR_xxBROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY"
233#define MII_MODEL_xxBROADCOM3_BCM57780 0x0019
234#define MII_STR_xxBROADCOM3_BCM57780 "BCM57780 10/100/1000baseT PHY"
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235#define MII_MODEL_xxBROADCOM3_BCM54640 0x001b
236#define MII_STR_xxBROADCOM3_BCM54640 "BCM54640 10/100/1000baseT PHY"
237#define MII_MODEL_xxBROADCOM3_BCM54680 0x001c
238#define MII_STR_xxBROADCOM3_BCM54680 "BCM54680 10/100/1000baseT PHY"
239#define MII_MODEL_xxBROADCOM3_BCM54685 0x001d
240#define MII_STR_xxBROADCOM3_BCM54685 "BCM54685 10/100/1000baseT PHY"
241#define MII_MODEL_xxBROADCOM3_BCM54880 0x001e
242#define MII_STR_xxBROADCOM3_BCM54880 "BCM54880 10/100/1000baseT PHY"
243#define MII_MODEL_xxBROADCOM3_BCM54881 0x001f
244#define MII_STR_xxBROADCOM3_BCM54881 "BCM54881 10/100/1000baseT PHY"
245#define MII_MODEL_xxBROADCOM3_BCM5720C 0x0020
246#define MII_STR_xxBROADCOM3_BCM5720C "BCM5717C 10/100/1000baseT PHY"
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247#define MII_MODEL_xxBROADCOM3_BCM5719C 0x0022
248#define MII_STR_xxBROADCOM3_BCM5719C "BCM5719C 10/100/1000baseT PHY"
249#define MII_MODEL_xxBROADCOM3_BCM57765 0x0024
250#define MII_STR_xxBROADCOM3_BCM57765 "BCM57765 10/100/1000baseT PHY"
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251#define MII_MODEL_xxBROADCOM3_BCM5718C 0x0036
252#define MII_STR_xxBROADCOM3_BCM5718C "BCM5718C 10/100/1000baseT PHY"
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253#define MII_MODEL_BROADCOM2_BCM5906 0x0004
254#define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX PHY"
984263bc 255
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256/* Cicada Semiconductor PHYs (now owned by Vitesse?) */
257#define MII_MODEL_CICADA_CS8201 0x0001
ede40c20 258#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
fda59c4c 259#define MII_MODEL_CICADA_CS8201A 0x0020
ede40c20 260#define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
fda59c4c 261#define MII_MODEL_CICADA_CS8201B 0x0021
ede40c20 262#define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
46ad174e 263#define MII_MODEL_xxCICADA_CS8201 0x0001
ede40c20 264#define MII_STR_xxCICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
46ad174e 265#define MII_MODEL_xxCICADA_CS8201A 0x0020
ede40c20 266#define MII_STR_xxCICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
46ad174e 267#define MII_MODEL_xxCICADA_CS8201B 0x0021
ede40c20 268#define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
fda59c4c 269
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270/* Davicom Semiconductor PHYs */
271#define MII_MODEL_xxDAVICOM_DM9101 0x0000
272#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
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273#define MII_MODEL_DAVICOM_DM9102 0x0004
274#define MII_STR_DAVICOM_DM9102 "DM9102 10/100 media interface"
275#define MII_MODEL_DAVICOM_DM9601 0x000c
276#define MII_STR_DAVICOM_DM9601 "DM9601 10/100 media interface"
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277
278/* Integrated Circuit Systems PHYs */
279#define MII_MODEL_xxICS_1890 0x0002
280#define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
281
282/* Intel PHYs */
283#define MII_MODEL_xxINTEL_I82553AB 0x0000
284#define MII_STR_xxINTEL_I82553AB "i83553 10/100 media interface"
285#define MII_MODEL_INTEL_I82555 0x0015
286#define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
287#define MII_MODEL_INTEL_I82562EM 0x0032
288#define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface"
289#define MII_MODEL_INTEL_I82562ET 0x0033
290#define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface"
291#define MII_MODEL_INTEL_I82553C 0x0035
292#define MII_STR_INTEL_I82553C "i82553 10/100 media interface"
293
294/* Jato Technologies PHYs */
295#define MII_MODEL_JATO_BASEX 0x0000
296#define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
297
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298/* JMicron Technologies PHYs */
299#define MII_MODEL_JMICRON_JMP211 0x0021
300#define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 media interface"
301#define MII_MODEL_JMICRON_JMP202 0x0022
302#define MII_STR_JMICRON_JMP202 "JMP202 10/100 media interface"
303
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304/* Level 1 PHYs */
305#define MII_MODEL_xxLEVEL1_LXT970 0x0000
306#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
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307#define MII_MODEL_xxLEVEL1a_LXT971 0x000e
308#define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 media interface"
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309
310/* National Semiconductor PHYs */
311#define MII_MODEL_NATSEMI_DP83840 0x0000
312#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
313#define MII_MODEL_NATSEMI_DP83843 0x0001
314#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
315#define MII_MODEL_NATSEMI_DP83891 0x0005
316#define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
317#define MII_MODEL_NATSEMI_DP83861 0x0006
318#define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
319
320/* Quality Semiconductor PHYs */
321#define MII_MODEL_QUALSEMI_QS6612 0x0000
322#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
323
324/* RealTek Semiconductor PHYs */
325#define MII_MODEL_REALTEK_RTL8201L 0x0020
326#define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 media interface"
e2d6d204 327#define MII_MODEL_xxREALTEK_RTL8169S 0x0011
7896c317 328#define MII_STR_xxREALTEK_RTL8169S "8211B/RTL8169S/8110S media interface"
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329#define MII_MODEL_REALTEK2_RTL8169S 0x0011
330#define MII_STR_REALTEK2_RTL8169S "RTL8169S/8110S media interface"
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331
332/* Seeq PHYs */
333#define MII_MODEL_xxSEEQ_80220 0x0003
334#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
335#define MII_MODEL_xxSEEQ_84220 0x0004
336#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
337
338/* Silicon Integrated Systems PHYs */
339#define MII_MODEL_xxSIS_900 0x0000
340#define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
341
342/* TDK */
343#define MII_MODEL_TDK_78Q2120 0x0014
344#define MII_STR_TDK_78Q2120 "TDK 78Q2120 media interface"
345
346/* Texas Instruments PHYs */
347#define MII_MODEL_xxTI_TLAN10T 0x0001
348#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
349#define MII_MODEL_xxTI_100VGPMI 0x0002
350#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
351
352/* XaQti Corp. PHYs. */
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353#define MII_MODEL_xxXAQTI_XMACII 0x0000
354#define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
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355
356/* Marvell Semiconductor PHYs */
357#define MII_MODEL_MARVELL_E1000 0x0000
358#define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"
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359#define MII_MODEL_MARVELL_E1011 0x0002
360#define MII_STR_MARVELL_E1011 "Marvell Semiconductor 88E1011 Gigabit PHY"
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361#define MII_MODEL_MARVELL_E1000_3 0x0003
362#define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
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363#define MII_MODEL_MARVELL_E1000S 0x0004
364#define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
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365#define MII_MODEL_MARVELL_E1000_5 0x0005
366#define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
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367#define MII_MODEL_MARVELL_E1101 0x0006
368#define MII_STR_MARVELL_E1101 "Marvell 88E1101 Gigabit PHY"
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369#define MII_MODEL_MARVELL_E3082 0x0008
370#define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 PHY"
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371#define MII_MODEL_MARVELL_E1112 0x0009
372#define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
373#define MII_MODEL_MARVELL_E1149 0x000b
374#define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
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375#define MII_MODEL_MARVELL_E1111 0x000c
376#define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
377#define MII_MODEL_MARVELL_E1116 0x0021
378#define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
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379#define MII_MODEL_MARVELL_E1118 0x0022
380#define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
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381#define MII_MODEL_MARVELL_E1116R 0x0024
382#define MII_STR_MARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
383#define MII_MODEL_MARVELL_E1149R 0x0025
384#define MII_STR_MARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY"
385#define MII_MODEL_MARVELL_E3016 0x0026
386#define MII_STR_MARVELL_E3016 "Marvell 88E3016 10/100 PHY"
387#define MII_MODEL_MARVELL_PHYG65G 0x0027
388#define MII_STR_MARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY"
389#define MII_MODEL_xxMARVELL_E1011 0x0002
390#define MII_STR_xxMARVELL_E1011 "Marvell 88E1000 Gigabit PHY"
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391#define MII_MODEL_xxMARVELL_E1000_3 0x0003
392#define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
393#define MII_MODEL_xxMARVELL_E1000_5 0x0005
394#define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
395#define MII_MODEL_xxMARVELL_E1111 0x000c
396#define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
397
398/* IC Plus Corp. PHYs */
399#define MII_MODEL_ICPLUS_IP101 0x0005
400#define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
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401#define MII_MODEL_ICPLUS_IP1000A 0x0008
402#define MII_STR_ICPLUS_IP1000A "IC Plus 10/100/1000 media interface"
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403
404/* Vitesse Semiconductor PHYs */
405#define MII_MODEL_VITESSE_VSC8601 0x0002
406#define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000TX PHY"
407