Misc interrupts/LWKT 1/2: interlock the idle thread. Put execution of
[dragonfly.git] / sys / i386 / i386 / swtch.s
CommitLineData
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1/*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
f1d1c3fa 4 * LWKT threads Copyright (c) 2003 Matthew Dillon
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5 *
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $
ef0fdad1 38 * $DragonFly: src/sys/i386/i386/Attic/swtch.s,v 1.16 2003/06/29 03:28:42 dillon Exp $
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39 */
40
41#include "npx.h"
42#include "opt_user_ldt.h"
43
44#include <sys/rtprio.h>
45
46#include <machine/asmacros.h>
47#include <machine/ipl.h>
48
49#ifdef SMP
50#include <machine/pmap.h>
51#include <machine/smptests.h> /** GRAB_LOPRIO */
52#include <machine/apic.h>
53#include <machine/lock.h>
54#endif /* SMP */
55
56#include "assym.s"
57
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58 .data
59
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60 .globl _panic
61
62#if defined(SWTCH_OPTIM_STATS)
63 .globl _swtch_optim_stats, _tlb_flush_count
64_swtch_optim_stats: .long 0 /* number of _swtch_optims */
65_tlb_flush_count: .long 0
66#endif
67
68 .text
69
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70
71/*
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72 * cpu_heavy_switch(next_thread)
73 *
74 * Switch from the current thread to a new thread. This entry
75 * is normally called via the thread->td_switch function, and will
76 * only be called when the current thread is a heavy weight process.
77 *
78 * YYY disable interrupts once giant is removed.
984263bc 79 */
8ad65e08 80ENTRY(cpu_heavy_switch)
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81 movl _curthread,%ecx
82 movl TD_PROC(%ecx),%ecx
984263bc 83
8ad65e08 84 cli
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85#ifdef SMP
86 movb P_ONCPU(%ecx), %al /* save "last" cpu */
87 movb %al, P_LASTCPU(%ecx)
88 movb $0xff, P_ONCPU(%ecx) /* "leave" the cpu */
89#endif /* SMP */
90 movl P_VMSPACE(%ecx), %edx
91#ifdef SMP
92 movl _cpuid, %eax
93#else
94 xorl %eax, %eax
95#endif /* SMP */
96 btrl %eax, VM_PMAP+PM_ACTIVE(%edx)
97
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98 /*
99 * Save general regs
100 */
101 movl P_THREAD(%ecx),%edx
b7c628e4 102 movl TD_PCB(%edx),%edx
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103 movl (%esp),%eax /* Hardware registers */
104 movl %eax,PCB_EIP(%edx)
105 movl %ebx,PCB_EBX(%edx)
106 movl %esp,PCB_ESP(%edx)
107 movl %ebp,PCB_EBP(%edx)
108 movl %esi,PCB_ESI(%edx)
109 movl %edi,PCB_EDI(%edx)
110 movl %gs,PCB_GS(%edx)
111
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112 /*
113 * Push the LWKT switch restore function, which resumes a heavy
114 * weight process. Note that the LWKT switcher is based on
115 * TD_SP, while the heavy weight process switcher is based on
116 * PCB_ESP. TD_SP is usually one pointer pushed relative to
117 * PCB_ESP.
118 */
119 movl P_THREAD(%ecx),%eax
120 pushl $cpu_heavy_restore
121 movl %esp,TD_SP(%eax)
122
123 /*
124 * Save debug regs if necessary
125 */
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126 movb PCB_FLAGS(%edx),%al
127 andb $PCB_DBREGS,%al
128 jz 1f /* no, skip over */
129 movl %dr7,%eax /* yes, do the save */
130 movl %eax,PCB_DR7(%edx)
131 andl $0x0000fc00, %eax /* disable all watchpoints */
132 movl %eax,%dr7
133 movl %dr6,%eax
134 movl %eax,PCB_DR6(%edx)
135 movl %dr3,%eax
136 movl %eax,PCB_DR3(%edx)
137 movl %dr2,%eax
138 movl %eax,PCB_DR2(%edx)
139 movl %dr1,%eax
140 movl %eax,PCB_DR1(%edx)
141 movl %dr0,%eax
142 movl %eax,PCB_DR0(%edx)
1431:
144
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145 /*
146 * Save BGL nesting count. Note that we hold the BGL with a
147 * count of at least 1 on entry to cpu_heavy_switch().
148 */
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149#ifdef SMP
150 movl _mp_lock, %eax
151 /* XXX FIXME: we should be saving the local APIC TPR */
152#ifdef DIAGNOSTIC
153 cmpl $FREE_LOCK, %eax /* is it free? */
154 je badsw4 /* yes, bad medicine! */
155#endif /* DIAGNOSTIC */
156 andl $COUNT_FIELD, %eax /* clear CPU portion */
157 movl %eax, PCB_MPNEST(%edx) /* store it */
158#endif /* SMP */
159
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160 /*
161 * Save the FP state if we have used the FP.
162 */
984263bc 163#if NNPX > 0
263e4574 164 movl P_THREAD(%ecx),%ecx
af0bff84 165 cmpl %ecx,_npxthread
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166 jne 1f
167 addl $PCB_SAVEFPU,%edx /* h/w bugs make saving complicated */
168 pushl %edx
169 call _npxsave /* do it in a big C function */
170 popl %eax
1711:
af0bff84 172 /* %ecx,%edx trashed */
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173#endif /* NNPX > 0 */
174
84b592ba 175 /*
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176 * Switch to the next thread, which was passed as an argument
177 * to cpu_heavy_switch(). Due to the switch-restore function we pushed,
178 * the argument is at 8(%esp). Set the current thread, load the
179 * stack pointer, and 'ret' into the switch-restore function.
84b592ba 180 */
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181 movl 8(%esp),%eax
182 movl %eax,_curthread
183 movl TD_SP(%eax),%esp
184 ret
984263bc 185
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186/*
187 * cpu_exit_switch()
188 *
189 * The switch function is changed to this when a thread is going away
190 * for good. We have to ensure that the MMU state is not cached, and
191 * we don't bother saving the existing thread state before switching.
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192 *
193 * At this point we are in a critical section and this cpu owns the
194 * thread's token, which serves as an interlock until the switchout is
195 * complete.
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196 */
197ENTRY(cpu_exit_switch)
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198 /*
199 * Get us out of the vmspace
200 */
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201 movl _IdlePTD,%ecx
202 movl %cr3,%eax
203 cmpl %ecx,%eax
204 je 1f
205 movl %ecx,%cr3
ae8050a4 206 movl _curthread,%ecx
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208 /*
209 * Switch to the next thread.
210 */
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211 cli
212 movl 4(%esp),%eax
213 movl %eax,_curthread
214 movl TD_SP(%eax),%esp
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215
216 /*
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217 * We are now the next thread, set the exited flag and wakeup
218 * any waiters.
ae8050a4 219 */
99df837e 220 orl $TDF_EXITED,TD_FLAGS(%ecx)
ae8050a4 221 pushl %eax
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222 pushl %ecx /* wakeup(oldthread) */
223 call wakeup
ae8050a4 224 addl $4,%esp
99df837e 225 popl %eax /* note: next thread expects curthread in %eax */
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226
227 /*
228 * Restore the next thread's state and resume it. Note: the
229 * restore function assumes that the next thread's address is
230 * in %eax.
231 */
8ad65e08 232 ret
984263bc 233
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234/*
235 * cpu_heavy_restore() (current thread in %eax on entry)
236 *
237 * Restore the thread after an LWKT switch. This entry is normally
238 * called via the LWKT switch restore function, which was pulled
239 * off the thread stack and jumped to.
240 *
241 * This entry is only called if the thread was previously saved
242 * using cpu_heavy_switch() (the heavy weight process thread switcher).
243 *
244 * YYY theoretically we do not have to restore everything here, a lot
245 * of this junk can wait until we return to usermode. But for now
246 * we restore everything.
247 *
248 * YYY STI/CLI sequencing.
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249 *
250 * YYY note: spl check is done in mi_switch when it splx()'s.
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251 */
252ENTRY(cpu_heavy_restore)
253 /* interrupts are disabled */
8f41e33b 254 movl TD_PCB(%eax),%edx
8ad65e08 255 movl TD_PROC(%eax),%ecx
984263bc 256#ifdef DIAGNOSTIC
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257 cmpb $SRUN,P_STAT(%ecx)
258 jne badsw2
259#endif
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260
261#if defined(SWTCH_OPTIM_STATS)
262 incl _swtch_optim_stats
263#endif
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264 /*
265 * Restore the MMU address space
266 */
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267 movl %cr3,%ebx
268 cmpl PCB_CR3(%edx),%ebx
269 je 4f
270#if defined(SWTCH_OPTIM_STATS)
271 decl _swtch_optim_stats
272 incl _tlb_flush_count
273#endif
274 movl PCB_CR3(%edx),%ebx
275 movl %ebx,%cr3
2764:
277
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278 /*
279 * Deal with the PCB extension, restore the private tss
280 */
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281#ifdef SMP
282 movl _cpuid, %esi
283#else
284 xorl %esi, %esi
285#endif
286 cmpl $0, PCB_EXT(%edx) /* has pcb extension? */
287 je 1f
288 btsl %esi, _private_tss /* mark use of private tss */
289 movl PCB_EXT(%edx), %edi /* new tss descriptor */
290 jmp 2f
2911:
292
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293 /*
294 * update common_tss.tss_esp0 pointer. This is the supervisor
295 * stack pointer on entry from user mode. Since the pcb is
296 * at the top of the supervisor stack esp0 starts just below it.
297 * We leave enough space for vm86 (16 bytes).
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298 *
299 * common_tss.tss_esp0 is needed when user mode traps into the
300 * kernel.
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301 */
302 leal -16(%edx),%ebx
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303 movl %ebx, _common_tss + TSS_ESP0
304
305 btrl %esi, _private_tss
306 jae 3f
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307
308 /*
309 * There is no way to get the address of a segment-accessed variable
310 * so we store a self-referential pointer at the base of the per-cpu
311 * data area and add the appropriate offset.
312 */
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313 movl $gd_common_tssd, %edi
314 addl %fs:0, %edi
17a9f566 315
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316 /*
317 * Move the correct TSS descriptor into the GDT slot, then reload
318 * tr. YYY not sure what is going on here
319 */
984263bc 3202:
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321 movl _tss_gdt, %ebx /* entry in GDT */
322 movl 0(%edi), %eax
323 movl %eax, 0(%ebx)
324 movl 4(%edi), %eax
325 movl %eax, 4(%ebx)
326 movl $GPROC0_SEL*8, %esi /* GSEL(entry, SEL_KPL) */
327 ltr %si
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328
329 /*
330 * Tell the pmap that our cpu is using the VMSPACE now.
331 */
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3323:
333 movl P_VMSPACE(%ecx), %ebx
984263bc 334 movl _cpuid, %eax
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335 btsl %eax, VM_PMAP+PM_ACTIVE(%ebx)
336
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337 /*
338 * Restore general registers.
339 */
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340 movl PCB_EBX(%edx),%ebx
341 movl PCB_ESP(%edx),%esp
342 movl PCB_EBP(%edx),%ebp
343 movl PCB_ESI(%edx),%esi
344 movl PCB_EDI(%edx),%edi
345 movl PCB_EIP(%edx),%eax
346 movl %eax,(%esp)
347
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348 /*
349 * SMP ickyness to direct interrupts.
350 */
351
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352#ifdef SMP
353#ifdef GRAB_LOPRIO /* hold LOPRIO for INTs */
354#ifdef CHEAP_TPR
355 movl $0, lapic_tpr
356#else
357 andl $~APIC_TPR_PRIO, lapic_tpr
358#endif /** CHEAP_TPR */
359#endif /** GRAB_LOPRIO */
360 movl _cpuid,%eax
361 movb %al, P_ONCPU(%ecx)
362#endif /* SMP */
984263bc 363
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364 /*
365 * Restore the BGL nesting count. Note that the nesting count will
366 * be at least 1.
367 */
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368#ifdef SMP
369 movl _cpu_lockid, %eax
370 orl PCB_MPNEST(%edx), %eax /* add next count from PROC */
371 movl %eax, _mp_lock /* load the mp_lock */
372 /* XXX FIXME: we should be restoring the local APIC TPR */
373#endif /* SMP */
374
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375 /*
376 * Restore the user LDT if we have one
377 */
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378#ifdef USER_LDT
379 cmpl $0, PCB_USERLDT(%edx)
380 jnz 1f
381 movl __default_ldt,%eax
382 cmpl _currentldt,%eax
383 je 2f
384 lldt __default_ldt
385 movl %eax,_currentldt
386 jmp 2f
3871: pushl %edx
388 call _set_user_ldt
389 popl %edx
3902:
391#endif
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392 /*
393 * Restore the %gs segment register, which must be done after
394 * loading the user LDT. Since user processes can modify the
395 * register via procfs, this may result in a fault which is
396 * detected by checking the fault address against cpu_switch_load_gs
397 * in i386/i386/trap.c
398 */
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399 .globl cpu_switch_load_gs
400cpu_switch_load_gs:
401 movl PCB_GS(%edx),%gs
402
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403 /*
404 * Restore the DEBUG register state if necessary.
405 */
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406 movb PCB_FLAGS(%edx),%al
407 andb $PCB_DBREGS,%al
408 jz 1f /* no, skip over */
409 movl PCB_DR6(%edx),%eax /* yes, do the restore */
410 movl %eax,%dr6
411 movl PCB_DR3(%edx),%eax
412 movl %eax,%dr3
413 movl PCB_DR2(%edx),%eax
414 movl %eax,%dr2
415 movl PCB_DR1(%edx),%eax
416 movl %eax,%dr1
417 movl PCB_DR0(%edx),%eax
418 movl %eax,%dr0
419 movl %dr7,%eax /* load dr7 so as not to disturb */
420 andl $0x0000fc00,%eax /* reserved bits */
421 pushl %ebx
422 movl PCB_DR7(%edx),%ebx
423 andl $~0x0000fc00,%ebx
424 orl %ebx,%eax
425 popl %ebx
426 movl %eax,%dr7
4271:
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428#if 0
429 /*
430 * Remove the heavy weight process from the heavy weight queue.
431 * this will also have the side effect of removing the thread from
432 * the run queue. YYY temporary?
433 *
434 * LWKT threads stay on the run queue until explicitly removed.
435 */
436 pushl %ecx
437 call remrunqueue
438 addl $4,%esp
439#endif
984263bc 440
8ad65e08 441 sti /* XXX */
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442 ret
443
444CROSSJUMPTARGET(sw1a)
445
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446badsw0:
447 pushl %eax
448 pushl $sw0_1
449 call _panic
450
451sw0_1: .asciz "cpu_switch: panic: %p"
452
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453#ifdef DIAGNOSTIC
454badsw1:
455 pushl $sw0_1
456 call _panic
457
458sw0_1: .asciz "cpu_switch: has wchan"
459
460badsw2:
461 pushl $sw0_2
462 call _panic
463
464sw0_2: .asciz "cpu_switch: not SRUN"
465#endif
466
467#if defined(SMP) && defined(DIAGNOSTIC)
468badsw4:
469 pushl $sw0_4
470 call _panic
471
472sw0_4: .asciz "cpu_switch: do not have lock"
473#endif /* SMP && DIAGNOSTIC */
474
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475string: .asciz "SWITCHING\n"
476
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477/*
478 * savectx(pcb)
479 * Update pcb, saving current processor state.
480 */
481ENTRY(savectx)
482 /* fetch PCB */
483 movl 4(%esp),%ecx
484
485 /* caller's return address - child won't execute this routine */
486 movl (%esp),%eax
487 movl %eax,PCB_EIP(%ecx)
488
489 movl %cr3,%eax
490 movl %eax,PCB_CR3(%ecx)
491
492 movl %ebx,PCB_EBX(%ecx)
493 movl %esp,PCB_ESP(%ecx)
494 movl %ebp,PCB_EBP(%ecx)
495 movl %esi,PCB_ESI(%ecx)
496 movl %edi,PCB_EDI(%ecx)
497 movl %gs,PCB_GS(%ecx)
498
499#if NNPX > 0
500 /*
af0bff84 501 * If npxthread == NULL, then the npx h/w state is irrelevant and the
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502 * state had better already be in the pcb. This is true for forks
503 * but not for dumps (the old book-keeping with FP flags in the pcb
504 * always lost for dumps because the dump pcb has 0 flags).
505 *
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506 * If npxthread != NULL, then we have to save the npx h/w state to
507 * npxthread's pcb and copy it to the requested pcb, or save to the
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508 * requested pcb and reload. Copying is easier because we would
509 * have to handle h/w bugs for reloading. We used to lose the
510 * parent's npx state for forks by forgetting to reload.
511 */
af0bff84 512 movl _npxthread,%eax
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513 testl %eax,%eax
514 je 1f
515
516 pushl %ecx
b7c628e4 517 movl TD_PCB(%eax),%eax
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518 leal PCB_SAVEFPU(%eax),%eax
519 pushl %eax
520 pushl %eax
521 call _npxsave
522 addl $4,%esp
523 popl %eax
524 popl %ecx
525
526 pushl $PCB_SAVEFPU_SIZE
527 leal PCB_SAVEFPU(%ecx),%ecx
528 pushl %ecx
529 pushl %eax
530 call _bcopy
531 addl $12,%esp
532#endif /* NNPX > 0 */
533
5341:
535 ret
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536
537/*
538 * cpu_idle_restore() (current thread in %eax on entry)
539 *
540 * Don't bother setting up any regs other then %ebp so backtraces
541 * don't die. This restore function is used to bootstrap into the
542 * cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for
543 * switching.
544 */
545ENTRY(cpu_idle_restore)
546 movl $0,%ebp
547 pushl $0
ef0fdad1 548 sti
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549 jmp cpu_idle
550
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551/*
552 * cpu_kthread_restore() (current thread is %eax on entry)
553 *
554 * Don't bother setting up any regs other then %ebp so backtraces
555 * don't die. This restore function is used to bootstrap into an
556 * LWKT based kernel thread only. cpu_lwkt_switch() will be used
557 * after this.
558 */
559ENTRY(cpu_kthread_restore)
560 movl TD_PCB(%eax),%ebx
561 movl $0,%ebp
ef0fdad1 562 sti
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563 popl %edx /* kthread exit function */
564 pushl PCB_EBX(%ebx) /* argument to ESI function */
565 pushl %edx /* set exit func as return address */
566 movl PCB_ESI(%ebx),%eax
567 jmp *%eax
568
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569/*
570 * cpu_lwkt_switch()
571 *
572 * Standard LWKT switching function. Only non-scratch registers are
573 * saved and we don't bother with the MMU state or anything else.
574 * YYY BGL, SPL
575 */
576ENTRY(cpu_lwkt_switch)
577 movl 4(%esp),%eax
578 pushl %ebp
579 pushl %ebx
580 pushl %esi
581 pushl %edi
582 pushfl
583 movl _curthread,%ecx
584 pushl $cpu_lwkt_restore
585 cli
586 movl %esp,TD_SP(%ecx)
587 movl %eax,_curthread
588 movl TD_SP(%eax),%esp
589 ret
590
591/*
592 * cpu_idle_restore() (current thread in %eax on entry)
593 *
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594 */
595ENTRY(cpu_lwkt_restore)
596 popfl
597 popl %edi
598 popl %esi
599 popl %ebx
600 popl %ebp
09f0701d 601 cmpl $0,_intr_nesting_level /* don't stack too deeply */
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602 jne 2f
603 testl _ipending,%ecx
604 jnz 1f
605 testl _fpending,%ecx
606 jz 2f
7d0bac62 6071:
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608 call splz /* execute unmasked ints */
6092:
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610 ret
611