mpt(4): Sync with FreeBSD.
[dragonfly.git] / sys / dev / disk / mpt / mpilib / mpi_ioc.h
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4c42baf4 1/* $FreeBSD: src/sys/dev/mpt/mpilib/mpi_ioc.h,v 1.11 2012/03/24 16:23:21 marius Exp $ */
d751f32e 2/*-
4c42baf4 3 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors.
d751f32e 4 * All rights reserved.
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5 *
6 * Redistribution and use in source and binary forms, with or without
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7 * modification, are permitted provided that the following conditions are
8 * met:
984263bc 9 * 1. Redistributions of source code must retain the above copyright
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10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * substantially similar to the "NO WARRANTY" disclaimer below
13 * ("Disclaimer") and any redistribution must be conditioned upon including
14 * a substantially similar Disclaimer requirement for further binary
15 * redistribution.
16 * 3. Neither the name of the LSI Logic Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
984263bc 19 *
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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
984263bc 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT
30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
984263bc 31 *
d751f32e 32 * Name: mpi_ioc.h
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33 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
34 * Creation Date: August 11, 2000
35 *
4c42baf4 36 * mpi_ioc.h Version: 01.05.16
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37 *
38 * Version History
39 * ---------------
40 *
41 * Date Version Description
42 * -------- -------- ------------------------------------------------------
43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
44 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure.
45 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY.
46 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure.
47 * Added _MSG_EVENT_ACK_REPLY structure.
48 * Added _MSG_FW_DOWNLOAD_REPLY structure.
49 * Added _MSG_TOOLBOX_REPLY structure.
50 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure.
51 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI,
52 * _LINK_STATUS, _LOOP_STATE and _LOGOUT.
53 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in
54 * _MSG_EVENT_ACK_REPLY structure to match specification.
55 * 11-02-00 01.01.01 Original release for post 1.0 work.
56 * Added a value for Manufacturer to WhoInit.
57 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and
58 * removed toolbox message.
59 * 01-09-01 01.01.03 Added event enabled and disabled defines.
60 * Added structures for FwHeader and DataHeader.
61 * Added ImageType to FwUpload reply.
62 * 02-20-01 01.01.04 Started using MPI_POINTER.
63 * 02-27-01 01.01.05 Added event for RAID status change and its event data.
64 * Added IocNumber field to MSG_IOC_FACTS_REPLY.
65 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER.
66 * Added structure offset comments.
67 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE.
68 * 08-08-01 01.02.01 Original release for v1.2 work.
69 * New format for FWVersion and ProductId in
70 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER.
71 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and
72 * related structure and defines.
73 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED.
74 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE.
75 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with
76 * IOCExceptions and changed DataImageSize to reserved.
77 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and
78 * MPI_FW_UPLOAD_ITYPE_NVDATA.
79 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID.
80 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field.
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81 * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY.
82 * 05-31-02 01.02.06 Added define for
83 * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID.
84 * Added AliasIndex to EVENT_DATA_LOGOUT structure.
85 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_.
86 * 06-26-03 01.02.08 Added new values to the product family defines.
87 * 04-29-04 01.02.09 Added IOCCapabilities field to MSG_IOC_FACTS_REPLY and
88 * added related defines.
89 * 05-11-04 01.03.01 Original release for MPI v1.3.
90 * 08-19-04 01.05.01 Added four new fields to MSG_IOC_INIT.
91 * Added three new fields to MSG_IOC_FACTS_REPLY.
92 * Defined four new bits for the IOCCapabilities field of
93 * the IOCFacts reply.
94 * Added two new PortTypes for the PortFacts reply.
95 * Added six new events along with their EventData
96 * structures.
97 * Added a new MsgFlag to the FwDownload request to
98 * indicate last segment.
99 * Defined a new image type of boot loader.
100 * Added FW family codes for SAS product families.
101 * 10-05-04 01.05.02 Added ReplyFifoHostSignalingAddr field to
102 * MSG_IOC_FACTS_REPLY.
103 * 12-07-04 01.05.03 Added more defines for SAS Discovery Error event.
104 * 12-09-04 01.05.04 Added Unsupported device to SAS Device event.
105 * 01-15-05 01.05.05 Added event data for SAS SES Event.
106 * 02-09-05 01.05.06 Added MPI_FW_UPLOAD_ITYPE_FW_BACKUP define.
107 * 02-22-05 01.05.07 Added Host Page Buffer Persistent flag to IOC Facts
108 * Reply and IOC Init Request.
109 * 03-11-05 01.05.08 Added family code for 1068E family.
110 * Removed IOCFacts Reply EEDP Capability bit.
111 * 06-24-05 01.05.09 Added 5 new IOCFacts Reply IOCCapabilities bits.
112 * Added Max SATA Targets to SAS Discovery Error event.
113 * 08-30-05 01.05.10 Added 4 new events and their event data structures.
114 * Added new ReasonCode value for SAS Device Status Change
115 * event.
116 * Added new family code for FC949E.
117 * 03-27-06 01.05.11 Added MPI_IOCFACTS_CAPABILITY_TLR.
118 * Added additional Reason Codes and more event data fields
119 * to EVENT_DATA_SAS_DEVICE_STATUS_CHANGE.
120 * Added EVENT_DATA_SAS_BROADCAST_PRIMITIVE structure and
121 * new event.
122 * Added MPI_EVENT_SAS_SMP_ERROR and event data structure.
123 * Added MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE and event
124 * data structure.
125 * Added MPI_EVENT_SAS_INIT_TABLE_OVERFLOW and event
126 * data structure.
127 * Added MPI_EXT_IMAGE_TYPE_INITIALIZATION.
128 * 10-11-06 01.05.12 Added MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED.
129 * Added MaxInitiators field to PortFacts reply.
130 * Added SAS Device Status Change ReasonCode for
131 * asynchronous notificaiton.
132 * Added MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE and event
133 * data structure.
134 * Added new ImageType values for FWDownload and FWUpload
135 * requests.
136 * 02-28-07 01.05.13 Added MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT for SAS
137 * Broadcast Event Data (replacing _RESERVED2).
138 * For Discovery Error Event Data DiscoveryStatus field,
139 * replaced _MULTPL_PATHS with _UNSUPPORTED_DEVICE and
140 * added _MULTI_PORT_DOMAIN.
141 * 05-24-07 01.05.14 Added Common Boot Block type to FWDownload Request.
142 * Added Common Boot Block type to FWUpload Request.
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143 * 08-07-07 01.05.15 Added MPI_EVENT_SAS_INIT_RC_REMOVED define.
144 * Added MPI_EVENT_IR2_RC_DUAL_PORT_ADDED and
145 * MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED for IR2 event data.
146 * Added SASAddress field to SAS Initiator Device Table
147 * Overflow event data structure.
148 * 03-28-08 01.05.16 Added two new ReasonCode values to SAS Device Status
149 * Change Event data to indicate completion of internally
150 * generated task management.
151 * Added MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE define.
152 * Added MPI_EVENT_SAS_INIT_RC_INACCESSIBLE define.
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153 * --------------------------------------------------------------------------
154 */
155
156#ifndef MPI_IOC_H
157#define MPI_IOC_H
158
159
160/*****************************************************************************
161*
162* I O C M e s s a g e s
163*
164*****************************************************************************/
165
166/****************************************************************************/
167/* IOCInit message */
168/****************************************************************************/
169
170typedef struct _MSG_IOC_INIT
171{
172 U8 WhoInit; /* 00h */
173 U8 Reserved; /* 01h */
174 U8 ChainOffset; /* 02h */
175 U8 Function; /* 03h */
176 U8 Flags; /* 04h */
177 U8 MaxDevices; /* 05h */
178 U8 MaxBuses; /* 06h */
179 U8 MsgFlags; /* 07h */
180 U32 MsgContext; /* 08h */
181 U16 ReplyFrameSize; /* 0Ch */
182 U8 Reserved1[2]; /* 0Eh */
183 U32 HostMfaHighAddr; /* 10h */
184 U32 SenseBufferHighAddr; /* 14h */
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185 U32 ReplyFifoHostSignalingAddr; /* 18h */
186 SGE_SIMPLE_UNION HostPageBufferSGE; /* 1Ch */
187 U16 MsgVersion; /* 28h */
188 U16 HeaderVersion; /* 2Ah */
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189} MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT,
190 IOCInit_t, MPI_POINTER pIOCInit_t;
191
192/* WhoInit values */
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193#define MPI_WHOINIT_NO_ONE (0x00)
194#define MPI_WHOINIT_SYSTEM_BIOS (0x01)
195#define MPI_WHOINIT_ROM_BIOS (0x02)
196#define MPI_WHOINIT_PCI_PEER (0x03)
197#define MPI_WHOINIT_HOST_DRIVER (0x04)
198#define MPI_WHOINIT_MANUFACTURER (0x05)
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199
200/* Flags values */
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201#define MPI_IOCINIT_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04)
202#define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02)
203#define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01)
204
205/* MsgVersion */
206#define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
207#define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
208#define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
209#define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
210
211/* HeaderVersion */
212#define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00)
213#define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8)
214#define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF)
215#define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0)
216
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217
218typedef struct _MSG_IOC_INIT_REPLY
219{
220 U8 WhoInit; /* 00h */
221 U8 Reserved; /* 01h */
222 U8 MsgLength; /* 02h */
223 U8 Function; /* 03h */
224 U8 Flags; /* 04h */
225 U8 MaxDevices; /* 05h */
226 U8 MaxBuses; /* 06h */
227 U8 MsgFlags; /* 07h */
228 U32 MsgContext; /* 08h */
229 U16 Reserved2; /* 0Ch */
230 U16 IOCStatus; /* 0Eh */
231 U32 IOCLogInfo; /* 10h */
232} MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY,
233 IOCInitReply_t, MPI_POINTER pIOCInitReply_t;
234
235
236
237/****************************************************************************/
238/* IOC Facts message */
239/****************************************************************************/
240
241typedef struct _MSG_IOC_FACTS
242{
243 U8 Reserved[2]; /* 00h */
244 U8 ChainOffset; /* 01h */
245 U8 Function; /* 02h */
246 U8 Reserved1[3]; /* 03h */
247 U8 MsgFlags; /* 04h */
248 U32 MsgContext; /* 08h */
249} MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS,
250 IOCFacts_t, MPI_POINTER pIOCFacts_t;
251
252typedef struct _MPI_FW_VERSION_STRUCT
253{
254 U8 Dev; /* 00h */
255 U8 Unit; /* 01h */
256 U8 Minor; /* 02h */
257 U8 Major; /* 03h */
258} MPI_FW_VERSION_STRUCT;
259
260typedef union _MPI_FW_VERSION
261{
262 MPI_FW_VERSION_STRUCT Struct;
263 U32 Word;
264} MPI_FW_VERSION;
265
266/* IOC Facts Reply */
267typedef struct _MSG_IOC_FACTS_REPLY
268{
269 U16 MsgVersion; /* 00h */
270 U8 MsgLength; /* 02h */
271 U8 Function; /* 03h */
d751f32e 272 U16 HeaderVersion; /* 04h */
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273 U8 IOCNumber; /* 06h */
274 U8 MsgFlags; /* 07h */
275 U32 MsgContext; /* 08h */
276 U16 IOCExceptions; /* 0Ch */
277 U16 IOCStatus; /* 0Eh */
278 U32 IOCLogInfo; /* 10h */
279 U8 MaxChainDepth; /* 14h */
280 U8 WhoInit; /* 15h */
281 U8 BlockSize; /* 16h */
282 U8 Flags; /* 17h */
283 U16 ReplyQueueDepth; /* 18h */
284 U16 RequestFrameSize; /* 1Ah */
285 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */
286 U16 ProductID; /* 1Eh */
287 U32 CurrentHostMfaHighAddr; /* 20h */
288 U16 GlobalCredits; /* 24h */
289 U8 NumberOfPorts; /* 26h */
290 U8 EventState; /* 27h */
291 U32 CurrentSenseBufferHighAddr; /* 28h */
292 U16 CurReplyFrameSize; /* 2Ch */
293 U8 MaxDevices; /* 2Eh */
294 U8 MaxBuses; /* 2Fh */
295 U32 FWImageSize; /* 30h */
d751f32e 296 U32 IOCCapabilities; /* 34h */
984263bc 297 MPI_FW_VERSION FWVersion; /* 38h */
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298 U16 HighPriorityQueueDepth; /* 3Ch */
299 U16 Reserved2; /* 3Eh */
300 SGE_SIMPLE_UNION HostPageBufferSGE; /* 40h */
301 U32 ReplyFifoHostSignalingAddr; /* 4Ch */
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302} MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY,
303 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t;
304
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305#define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
306#define MPI_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
307#define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
308#define MPI_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
309
310#define MPI_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
311#define MPI_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
312#define MPI_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
313#define MPI_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
314
315#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
316#define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
317#define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
318#define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (0x0008)
319#define MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
320
321#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01)
322#define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02)
323#define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04)
324
325#define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00)
326#define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01)
327
328#define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (0x00000001)
329#define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (0x00000002)
330#define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (0x00000004)
331#define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
332#define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
333#define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
334#define MPI_IOCFACTS_CAPABILITY_EEDP (0x00000040)
335#define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (0x00000080)
336#define MPI_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
337#define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (0x00000200)
338#define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (0x00000400)
339#define MPI_IOCFACTS_CAPABILITY_TLR (0x00000800)
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340
341
342/*****************************************************************************
343*
344* P o r t M e s s a g e s
345*
346*****************************************************************************/
347
348/****************************************************************************/
349/* Port Facts message and Reply */
350/****************************************************************************/
351
352typedef struct _MSG_PORT_FACTS
353{
354 U8 Reserved[2]; /* 00h */
355 U8 ChainOffset; /* 02h */
356 U8 Function; /* 03h */
357 U8 Reserved1[2]; /* 04h */
358 U8 PortNumber; /* 06h */
359 U8 MsgFlags; /* 07h */
360 U32 MsgContext; /* 08h */
361} MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS,
362 PortFacts_t, MPI_POINTER pPortFacts_t;
363
364typedef struct _MSG_PORT_FACTS_REPLY
365{
366 U16 Reserved; /* 00h */
367 U8 MsgLength; /* 02h */
368 U8 Function; /* 03h */
369 U16 Reserved1; /* 04h */
370 U8 PortNumber; /* 06h */
371 U8 MsgFlags; /* 07h */
372 U32 MsgContext; /* 08h */
373 U16 Reserved2; /* 0Ch */
374 U16 IOCStatus; /* 0Eh */
375 U32 IOCLogInfo; /* 10h */
376 U8 Reserved3; /* 14h */
377 U8 PortType; /* 15h */
378 U16 MaxDevices; /* 16h */
379 U16 PortSCSIID; /* 18h */
380 U16 ProtocolFlags; /* 1Ah */
381 U16 MaxPostedCmdBuffers; /* 1Ch */
382 U16 MaxPersistentIDs; /* 1Eh */
383 U16 MaxLanBuckets; /* 20h */
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384 U8 MaxInitiators; /* 22h */
385 U8 Reserved4; /* 23h */
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386 U32 Reserved5; /* 24h */
387} MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY,
388 PortFactsReply_t, MPI_POINTER pPortFactsReply_t;
389
390
391/* PortTypes values */
392
393#define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00)
394#define MPI_PORTFACTS_PORTTYPE_SCSI (0x01)
395#define MPI_PORTFACTS_PORTTYPE_FC (0x10)
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396#define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20)
397#define MPI_PORTFACTS_PORTTYPE_SAS (0x30)
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398
399/* ProtocolFlags values */
400
401#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01)
402#define MPI_PORTFACTS_PROTOCOL_LAN (0x02)
403#define MPI_PORTFACTS_PROTOCOL_TARGET (0x04)
404#define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08)
405
406
407/****************************************************************************/
408/* Port Enable Message */
409/****************************************************************************/
410
411typedef struct _MSG_PORT_ENABLE
412{
413 U8 Reserved[2]; /* 00h */
414 U8 ChainOffset; /* 02h */
415 U8 Function; /* 03h */
416 U8 Reserved1[2]; /* 04h */
417 U8 PortNumber; /* 06h */
418 U8 MsgFlags; /* 07h */
419 U32 MsgContext; /* 08h */
420} MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE,
421 PortEnable_t, MPI_POINTER pPortEnable_t;
422
423typedef struct _MSG_PORT_ENABLE_REPLY
424{
425 U8 Reserved[2]; /* 00h */
426 U8 MsgLength; /* 02h */
427 U8 Function; /* 03h */
428 U8 Reserved1[2]; /* 04h */
429 U8 PortNumber; /* 05h */
430 U8 MsgFlags; /* 07h */
431 U32 MsgContext; /* 08h */
432 U16 Reserved2; /* 0Ch */
433 U16 IOCStatus; /* 0Eh */
434 U32 IOCLogInfo; /* 10h */
435} MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY,
436 PortEnableReply_t, MPI_POINTER pPortEnableReply_t;
437
438
439/*****************************************************************************
440*
441* E v e n t M e s s a g e s
442*
443*****************************************************************************/
444
445/****************************************************************************/
446/* Event Notification messages */
447/****************************************************************************/
448
449typedef struct _MSG_EVENT_NOTIFY
450{
451 U8 Switch; /* 00h */
452 U8 Reserved; /* 01h */
453 U8 ChainOffset; /* 02h */
454 U8 Function; /* 03h */
455 U8 Reserved1[3]; /* 04h */
456 U8 MsgFlags; /* 07h */
457 U32 MsgContext; /* 08h */
458} MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY,
459 EventNotification_t, MPI_POINTER pEventNotification_t;
460
461/* Event Notification Reply */
462
463typedef struct _MSG_EVENT_NOTIFY_REPLY
464{
465 U16 EventDataLength; /* 00h */
466 U8 MsgLength; /* 02h */
467 U8 Function; /* 03h */
468 U8 Reserved1[2]; /* 04h */
469 U8 AckRequired; /* 06h */
470 U8 MsgFlags; /* 07h */
471 U32 MsgContext; /* 08h */
472 U8 Reserved2[2]; /* 0Ch */
473 U16 IOCStatus; /* 0Eh */
474 U32 IOCLogInfo; /* 10h */
475 U32 Event; /* 14h */
476 U32 EventContext; /* 18h */
477 U32 Data[1]; /* 1Ch */
478} MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY,
479 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t;
480
481/* Event Acknowledge */
482
483typedef struct _MSG_EVENT_ACK
484{
485 U8 Reserved[2]; /* 00h */
486 U8 ChainOffset; /* 02h */
487 U8 Function; /* 03h */
488 U8 Reserved1[3]; /* 04h */
489 U8 MsgFlags; /* 07h */
490 U32 MsgContext; /* 08h */
491 U32 Event; /* 0Ch */
492 U32 EventContext; /* 10h */
493} MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK,
494 EventAck_t, MPI_POINTER pEventAck_t;
495
496typedef struct _MSG_EVENT_ACK_REPLY
497{
498 U8 Reserved[2]; /* 00h */
499 U8 MsgLength; /* 02h */
500 U8 Function; /* 03h */
501 U8 Reserved1[3]; /* 04h */
502 U8 MsgFlags; /* 07h */
503 U32 MsgContext; /* 08h */
504 U16 Reserved2; /* 0Ch */
505 U16 IOCStatus; /* 0Eh */
506 U32 IOCLogInfo; /* 10h */
507} MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY,
508 EventAckReply_t, MPI_POINTER pEventAckReply_t;
509
510/* Switch */
511
512#define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00)
513#define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01)
514
515/* Event */
516
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517#define MPI_EVENT_NONE (0x00000000)
518#define MPI_EVENT_LOG_DATA (0x00000001)
519#define MPI_EVENT_STATE_CHANGE (0x00000002)
520#define MPI_EVENT_UNIT_ATTENTION (0x00000003)
521#define MPI_EVENT_IOC_BUS_RESET (0x00000004)
522#define MPI_EVENT_EXT_BUS_RESET (0x00000005)
523#define MPI_EVENT_RESCAN (0x00000006)
524#define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007)
525#define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008)
526#define MPI_EVENT_LOGOUT (0x00000009)
527#define MPI_EVENT_EVENT_CHANGE (0x0000000A)
528#define MPI_EVENT_INTEGRATED_RAID (0x0000000B)
529#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C)
530#define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D)
531#define MPI_EVENT_QUEUE_FULL (0x0000000E)
532#define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F)
533#define MPI_EVENT_SAS_SES (0x00000010)
534#define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011)
535#define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012)
536#define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013)
537#define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014)
538#define MPI_EVENT_IR2 (0x00000015)
539#define MPI_EVENT_SAS_DISCOVERY (0x00000016)
540#define MPI_EVENT_SAS_BROADCAST_PRIMITIVE (0x00000017)
541#define MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x00000018)
542#define MPI_EVENT_SAS_INIT_TABLE_OVERFLOW (0x00000019)
543#define MPI_EVENT_SAS_SMP_ERROR (0x0000001A)
544#define MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE (0x0000001B)
545#define MPI_EVENT_LOG_ENTRY_ADDED (0x00000021)
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546
547/* AckRequired field values */
548
549#define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
550#define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
551
552/* EventChange Event data */
553
554typedef struct _EVENT_DATA_EVENT_CHANGE
555{
556 U8 EventState; /* 00h */
557 U8 Reserved; /* 01h */
558 U16 Reserved1; /* 02h */
559} EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE,
560 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t;
561
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562/* LogEntryAdded Event data */
563
564/* this structure matches MPI_LOG_0_ENTRY in mpi_cnfg.h */
565#define MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH (0x1C)
566typedef struct _EVENT_DATA_LOG_ENTRY
567{
568 U32 TimeStamp; /* 00h */
569 U32 Reserved1; /* 04h */
570 U16 LogSequence; /* 08h */
571 U16 LogEntryQualifier; /* 0Ah */
572 U8 LogData[MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH]; /* 0Ch */
573} EVENT_DATA_LOG_ENTRY, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY,
574 MpiEventDataLogEntry_t, MPI_POINTER pMpiEventDataLogEntry_t;
575
576typedef struct _EVENT_DATA_LOG_ENTRY_ADDED
577{
578 U16 LogSequence; /* 00h */
579 U16 Reserved1; /* 02h */
580 U32 Reserved2; /* 04h */
581 EVENT_DATA_LOG_ENTRY LogEntry; /* 08h */
582} EVENT_DATA_LOG_ENTRY_ADDED, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY_ADDED,
583 MpiEventDataLogEntryAdded_t, MPI_POINTER pMpiEventDataLogEntryAdded_t;
584
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585/* SCSI Event data for Port, Bus and Device forms */
586
587typedef struct _EVENT_DATA_SCSI
588{
589 U8 TargetID; /* 00h */
590 U8 BusPort; /* 01h */
591 U16 Reserved; /* 02h */
592} EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI,
593 EventDataScsi_t, MPI_POINTER pEventDataScsi_t;
594
595/* SCSI Device Status Change Event data */
596
597typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE
598{
599 U8 TargetID; /* 00h */
600 U8 Bus; /* 01h */
601 U8 ReasonCode; /* 02h */
602 U8 LUN; /* 03h */
603 U8 ASC; /* 04h */
604 U8 ASCQ; /* 05h */
605 U16 Reserved; /* 06h */
606} EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE,
607 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE,
608 MpiEventDataScsiDeviceStatusChange_t,
609 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t;
610
611/* MPI SCSI Device Status Change Event data ReasonCode values */
612#define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03)
613#define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04)
614#define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05)
615
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616/* SAS Device Status Change Event data */
617
618typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
619{
620 U8 TargetID; /* 00h */
621 U8 Bus; /* 01h */
622 U8 ReasonCode; /* 02h */
623 U8 Reserved; /* 03h */
624 U8 ASC; /* 04h */
625 U8 ASCQ; /* 05h */
626 U16 DevHandle; /* 06h */
627 U32 DeviceInfo; /* 08h */
628 U16 ParentDevHandle; /* 0Ch */
629 U8 PhyNum; /* 0Eh */
630 U8 Reserved1; /* 0Fh */
631 U64 SASAddress; /* 10h */
632 U8 LUN[8]; /* 18h */
633 U16 TaskTag; /* 20h */
634 U16 Reserved2; /* 22h */
635} EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
636 MPI_POINTER PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
637 MpiEventDataSasDeviceStatusChange_t,
638 MPI_POINTER pMpiEventDataSasDeviceStatusChange_t;
639
640/* MPI SAS Device Status Change Event data ReasonCode values */
641#define MPI_EVENT_SAS_DEV_STAT_RC_ADDED (0x03)
642#define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING (0x04)
643#define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
644#define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED (0x06)
645#define MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
646#define MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
647#define MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
648#define MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
649#define MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
650#define MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
651#define MPI_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
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652#define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_INTERNAL_DEV_RESET (0x0E)
653#define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_TASK_ABORT_INTERNAL (0x0F)
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654
655
656/* SCSI Event data for Queue Full event */
657
658typedef struct _EVENT_DATA_QUEUE_FULL
659{
660 U8 TargetID; /* 00h */
661 U8 Bus; /* 01h */
662 U16 CurrentDepth; /* 02h */
663} EVENT_DATA_QUEUE_FULL, MPI_POINTER PTR_EVENT_DATA_QUEUE_FULL,
664 EventDataQueueFull_t, MPI_POINTER pEventDataQueueFull_t;
665
666/* MPI Integrated RAID Event data */
667
668typedef struct _EVENT_DATA_RAID
669{
670 U8 VolumeID; /* 00h */
671 U8 VolumeBus; /* 01h */
672 U8 ReasonCode; /* 02h */
673 U8 PhysDiskNum; /* 03h */
674 U8 ASC; /* 04h */
675 U8 ASCQ; /* 05h */
676 U16 Reserved; /* 06h */
677 U32 SettingsStatus; /* 08h */
678} EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID,
679 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t;
680
681/* MPI Integrated RAID Event data ReasonCode values */
682#define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00)
683#define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01)
684#define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02)
685#define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03)
686#define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04)
687#define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05)
688#define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06)
689#define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07)
690#define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08)
691#define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09)
692#define MPI_EVENT_RAID_RC_SMART_DATA (0x0A)
693#define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B)
694
695
696/* MPI Integrated RAID Resync Update Event data */
697
698typedef struct _MPI_EVENT_DATA_IR_RESYNC_UPDATE
699{
700 U8 VolumeID; /* 00h */
701 U8 VolumeBus; /* 01h */
702 U8 ResyncComplete; /* 02h */
703 U8 Reserved1; /* 03h */
704 U32 Reserved2; /* 04h */
705} MPI_EVENT_DATA_IR_RESYNC_UPDATE,
706 MPI_POINTER PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE,
707 MpiEventDataIrResyncUpdate_t, MPI_POINTER pMpiEventDataIrResyncUpdate_t;
708
709/* MPI IR2 Event data */
710
711/* MPI_LD_STATE or MPI_PD_STATE */
712typedef struct _IR2_STATE_CHANGED
713{
714 U16 PreviousState; /* 00h */
715 U16 NewState; /* 02h */
716} IR2_STATE_CHANGED, MPI_POINTER PTR_IR2_STATE_CHANGED;
717
718typedef struct _IR2_PD_INFO
719{
720 U16 DeviceHandle; /* 00h */
721 U8 TruncEnclosureHandle; /* 02h */
722 U8 TruncatedSlot; /* 03h */
723} IR2_PD_INFO, MPI_POINTER PTR_IR2_PD_INFO;
724
725typedef union _MPI_IR2_RC_EVENT_DATA
726{
727 IR2_STATE_CHANGED StateChanged;
728 U32 Lba;
729 IR2_PD_INFO PdInfo;
730} MPI_IR2_RC_EVENT_DATA, MPI_POINTER PTR_MPI_IR2_RC_EVENT_DATA;
731
732typedef struct _MPI_EVENT_DATA_IR2
733{
734 U8 TargetID; /* 00h */
735 U8 Bus; /* 01h */
736 U8 ReasonCode; /* 02h */
737 U8 PhysDiskNum; /* 03h */
738 MPI_IR2_RC_EVENT_DATA IR2EventData; /* 04h */
739} MPI_EVENT_DATA_IR2, MPI_POINTER PTR_MPI_EVENT_DATA_IR2,
740 MpiEventDataIR2_t, MPI_POINTER pMpiEventDataIR2_t;
741
742/* MPI IR2 Event data ReasonCode values */
743#define MPI_EVENT_IR2_RC_LD_STATE_CHANGED (0x01)
744#define MPI_EVENT_IR2_RC_PD_STATE_CHANGED (0x02)
745#define MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL (0x03)
746#define MPI_EVENT_IR2_RC_PD_INSERTED (0x04)
747#define MPI_EVENT_IR2_RC_PD_REMOVED (0x05)
748#define MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED (0x06)
749#define MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR (0x07)
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750#define MPI_EVENT_IR2_RC_DUAL_PORT_ADDED (0x08)
751#define MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED (0x09)
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752
753/* defines for logical disk states */
754#define MPI_LD_STATE_OPTIMAL (0x00)
755#define MPI_LD_STATE_DEGRADED (0x01)
756#define MPI_LD_STATE_FAILED (0x02)
757#define MPI_LD_STATE_MISSING (0x03)
758#define MPI_LD_STATE_OFFLINE (0x04)
759
760/* defines for physical disk states */
761#define MPI_PD_STATE_ONLINE (0x00)
762#define MPI_PD_STATE_MISSING (0x01)
763#define MPI_PD_STATE_NOT_COMPATIBLE (0x02)
764#define MPI_PD_STATE_FAILED (0x03)
765#define MPI_PD_STATE_INITIALIZING (0x04)
766#define MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST (0x05)
767#define MPI_PD_STATE_FAILED_AT_HOST_REQUEST (0x06)
768#define MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON (0xFF)
769
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770/* MPI Link Status Change Event data */
771
772typedef struct _EVENT_DATA_LINK_STATUS
773{
774 U8 State; /* 00h */
775 U8 Reserved; /* 01h */
776 U16 Reserved1; /* 02h */
777 U8 Reserved2; /* 04h */
778 U8 Port; /* 05h */
779 U16 Reserved3; /* 06h */
780} EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS,
781 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t;
782
783#define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000)
784#define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001)
785
786/* MPI Loop State Change Event data */
787
788typedef struct _EVENT_DATA_LOOP_STATE
789{
790 U8 Character4; /* 00h */
791 U8 Character3; /* 01h */
792 U8 Type; /* 02h */
793 U8 Reserved; /* 03h */
794 U8 Reserved1; /* 04h */
795 U8 Port; /* 05h */
796 U16 Reserved2; /* 06h */
797} EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE,
798 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t;
799
800#define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001)
801#define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002)
802#define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003)
803
804/* MPI LOGOUT Event data */
805
806typedef struct _EVENT_DATA_LOGOUT
807{
808 U32 NPortID; /* 00h */
d751f32e 809 U8 AliasIndex; /* 04h */
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810 U8 Port; /* 05h */
811 U16 Reserved1; /* 06h */
812} EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT,
813 EventDataLogout_t, MPI_POINTER pEventDataLogout_t;
814
d751f32e 815#define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF)
984263bc 816
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817/* SAS SES Event data */
818
819typedef struct _EVENT_DATA_SAS_SES
984263bc 820{
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821 U8 PhyNum; /* 00h */
822 U8 Port; /* 01h */
823 U8 PortWidth; /* 02h */
824 U8 Reserved1; /* 04h */
825} EVENT_DATA_SAS_SES, MPI_POINTER PTR_EVENT_DATA_SAS_SES,
826 MpiEventDataSasSes_t, MPI_POINTER pMpiEventDataSasSes_t;
827
828/* SAS Broadcast Primitive Event data */
829
830typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE
831{
832 U8 PhyNum; /* 00h */
833 U8 Port; /* 01h */
834 U8 PortWidth; /* 02h */
835 U8 Primitive; /* 04h */
836} EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
837 MPI_POINTER PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
838 MpiEventDataSasBroadcastPrimitive_t,
839 MPI_POINTER pMpiEventDataSasBroadcastPrimitive_t;
840
841#define MPI_EVENT_PRIMITIVE_CHANGE (0x01)
842#define MPI_EVENT_PRIMITIVE_EXPANDER (0x03)
843#define MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
844#define MPI_EVENT_PRIMITIVE_RESERVED3 (0x05)
845#define MPI_EVENT_PRIMITIVE_RESERVED4 (0x06)
846#define MPI_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
847#define MPI_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
848
849/* SAS Phy Link Status Event data */
850
851typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS
852{
853 U8 PhyNum; /* 00h */
854 U8 LinkRates; /* 01h */
855 U16 DevHandle; /* 02h */
856 U64 SASAddress; /* 04h */
857} EVENT_DATA_SAS_PHY_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS,
858 MpiEventDataSasPhyLinkStatus_t, MPI_POINTER pMpiEventDataSasPhyLinkStatus_t;
859
860/* defines for the LinkRates field of the SAS PHY Link Status event */
861#define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0)
862#define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4)
863#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F)
864#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0)
865#define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00)
866#define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01)
867#define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION (0x02)
868#define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03)
869#define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08)
870#define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09)
4c42baf4 871#define MPI_EVENT_SAS_PLS_LR_RATE_6_0 (0x0A)
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872
873/* SAS Discovery Event data */
874
875typedef struct _EVENT_DATA_SAS_DISCOVERY
876{
877 U32 DiscoveryStatus; /* 00h */
878 U32 Reserved1; /* 04h */
879} EVENT_DATA_SAS_DISCOVERY, MPI_POINTER PTR_EVENT_DATA_SAS_DISCOVERY,
880 EventDataSasDiscovery_t, MPI_POINTER pEventDataSasDiscovery_t;
881
882#define MPI_EVENT_SAS_DSCVRY_COMPLETE (0x00000000)
883#define MPI_EVENT_SAS_DSCVRY_IN_PROGRESS (0x00000001)
884#define MPI_EVENT_SAS_DSCVRY_PHY_BITS_MASK (0xFFFF0000)
885#define MPI_EVENT_SAS_DSCVRY_PHY_BITS_SHIFT (16)
886
887/* SAS Discovery Errror Event data */
888
889typedef struct _EVENT_DATA_DISCOVERY_ERROR
890{
891 U32 DiscoveryStatus; /* 00h */
892 U8 Port; /* 04h */
893 U8 Reserved1; /* 05h */
894 U16 Reserved2; /* 06h */
895} EVENT_DATA_DISCOVERY_ERROR, MPI_POINTER PTR_EVENT_DATA_DISCOVERY_ERROR,
896 EventDataDiscoveryError_t, MPI_POINTER pEventDataDiscoveryError_t;
897
898#define MPI_EVENT_DSCVRY_ERR_DS_LOOP_DETECTED (0x00000001)
899#define MPI_EVENT_DSCVRY_ERR_DS_UNADDRESSABLE_DEVICE (0x00000002)
900#define MPI_EVENT_DSCVRY_ERR_DS_MULTIPLE_PORTS (0x00000004)
901#define MPI_EVENT_DSCVRY_ERR_DS_EXPANDER_ERR (0x00000008)
902#define MPI_EVENT_DSCVRY_ERR_DS_SMP_TIMEOUT (0x00000010)
903#define MPI_EVENT_DSCVRY_ERR_DS_OUT_ROUTE_ENTRIES (0x00000020)
904#define MPI_EVENT_DSCVRY_ERR_DS_INDEX_NOT_EXIST (0x00000040)
905#define MPI_EVENT_DSCVRY_ERR_DS_SMP_FUNCTION_FAILED (0x00000080)
906#define MPI_EVENT_DSCVRY_ERR_DS_SMP_CRC_ERROR (0x00000100)
907#define MPI_EVENT_DSCVRY_ERR_DS_MULTPL_SUBTRACTIVE (0x00000200)
908#define MPI_EVENT_DSCVRY_ERR_DS_TABLE_TO_TABLE (0x00000400)
909#define MPI_EVENT_DSCVRY_ERR_DS_UNSUPPORTED_DEVICE (0x00000800)
910#define MPI_EVENT_DSCVRY_ERR_DS_MAX_SATA_TARGETS (0x00001000)
911#define MPI_EVENT_DSCVRY_ERR_DS_MULTI_PORT_DOMAIN (0x00002000)
4c42baf4 912#define MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE (0x00004000)
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913
914/* SAS SMP Error Event data */
915
916typedef struct _EVENT_DATA_SAS_SMP_ERROR
917{
918 U8 Status; /* 00h */
919 U8 Port; /* 01h */
920 U8 SMPFunctionResult; /* 02h */
921 U8 Reserved1; /* 03h */
922 U64 SASAddress; /* 04h */
923} EVENT_DATA_SAS_SMP_ERROR, MPI_POINTER PTR_EVENT_DATA_SAS_SMP_ERROR,
924 MpiEventDataSasSmpError_t, MPI_POINTER pMpiEventDataSasSmpError_t;
925
926/* defines for the Status field of the SAS SMP Error event */
927#define MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID (0x00)
928#define MPI_EVENT_SAS_SMP_CRC_ERROR (0x01)
929#define MPI_EVENT_SAS_SMP_TIMEOUT (0x02)
930#define MPI_EVENT_SAS_SMP_NO_DESTINATION (0x03)
931#define MPI_EVENT_SAS_SMP_BAD_DESTINATION (0x04)
932
933/* SAS Initiator Device Status Change Event data */
934
935typedef struct _EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
936{
937 U8 ReasonCode; /* 00h */
938 U8 Port; /* 01h */
939 U16 DevHandle; /* 02h */
940 U64 SASAddress; /* 04h */
941} EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
942 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
943 MpiEventDataSasInitDevStatusChange_t,
944 MPI_POINTER pMpiEventDataSasInitDevStatusChange_t;
945
946/* defines for the ReasonCode field of the SAS Initiator Device Status Change event */
947#define MPI_EVENT_SAS_INIT_RC_ADDED (0x01)
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948#define MPI_EVENT_SAS_INIT_RC_REMOVED (0x02)
949#define MPI_EVENT_SAS_INIT_RC_INACCESSIBLE (0x03)
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950
951/* SAS Initiator Device Table Overflow Event data */
952
953typedef struct _EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
954{
955 U8 MaxInit; /* 00h */
956 U8 CurrentInit; /* 01h */
957 U16 Reserved1; /* 02h */
4c42baf4 958 U64 SASAddress; /* 04h */
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959} EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
960 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
961 MpiEventDataSasInitTableOverflow_t,
962 MPI_POINTER pMpiEventDataSasInitTableOverflow_t;
963
964/* SAS Expander Status Change Event data */
965
966typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE
967{
968 U8 ReasonCode; /* 00h */
969 U8 Reserved1; /* 01h */
970 U16 Reserved2; /* 02h */
971 U8 PhysicalPort; /* 04h */
972 U8 Reserved3; /* 05h */
973 U16 EnclosureHandle; /* 06h */
974 U64 SASAddress; /* 08h */
975 U32 DiscoveryStatus; /* 10h */
976 U16 DevHandle; /* 14h */
977 U16 ParentDevHandle; /* 16h */
978 U16 ExpanderChangeCount; /* 18h */
979 U16 ExpanderRouteIndexes; /* 1Ah */
980 U8 NumPhys; /* 1Ch */
981 U8 SASLevel; /* 1Dh */
982 U8 Flags; /* 1Eh */
983 U8 Reserved4; /* 1Fh */
984} EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE,
985 MPI_POINTER PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE,
986 MpiEventDataSasExpanderStatusChange_t,
987 MPI_POINTER pMpiEventDataSasExpanderStatusChange_t;
988
989/* values for ReasonCode field of SAS Expander Status Change Event data */
990#define MPI_EVENT_SAS_EXP_RC_ADDED (0x00)
991#define MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING (0x01)
992
993/* values for DiscoveryStatus field of SAS Expander Status Change Event data */
994#define MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED (0x00000001)
995#define MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE (0x00000002)
996#define MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS (0x00000004)
997#define MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR (0x00000008)
998#define MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT (0x00000010)
999#define MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES (0x00000020)
1000#define MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST (0x00000040)
1001#define MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED (0x00000080)
1002#define MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR (0x00000100)
1003#define MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK (0x00000200)
1004#define MPI_EVENT_SAS_EXP_DS_TABLE_LINK (0x00000400)
1005#define MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE (0x00000800)
1006
1007/* values for Flags field of SAS Expander Status Change Event data */
1008#define MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG (0x02)
1009#define MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS (0x01)
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1011
1012
1013/*****************************************************************************
1014*
1015* F i r m w a r e L o a d M e s s a g e s
1016*
1017*****************************************************************************/
1018
1019/****************************************************************************/
1020/* Firmware Download message and associated structures */
1021/****************************************************************************/
1022
1023typedef struct _MSG_FW_DOWNLOAD
1024{
1025 U8 ImageType; /* 00h */
1026 U8 Reserved; /* 01h */
1027 U8 ChainOffset; /* 02h */
1028 U8 Function; /* 03h */
1029 U8 Reserved1[3]; /* 04h */
1030 U8 MsgFlags; /* 07h */
1031 U32 MsgContext; /* 08h */
1032 SGE_MPI_UNION SGL; /* 0Ch */
1033} MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD,
1034 FWDownload_t, MPI_POINTER pFWDownload_t;
1035
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1036#define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1037
1038#define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00)
1039#define MPI_FW_DOWNLOAD_ITYPE_FW (0x01)
1040#define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1041#define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03)
1042#define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER (0x04)
1043#define MPI_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1044#define MPI_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1045#define MPI_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1046#define MPI_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1047#define MPI_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
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1048
1049
1050typedef struct _FWDownloadTCSGE
1051{
1052 U8 Reserved; /* 00h */
1053 U8 ContextSize; /* 01h */
1054 U8 DetailsLength; /* 02h */
1055 U8 Flags; /* 03h */
1056 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */
1057 U32 ImageOffset; /* 08h */
1058 U32 ImageSize; /* 0Ch */
1059} FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE,
1060 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t;
1061
1062/* Firmware Download reply */
1063typedef struct _MSG_FW_DOWNLOAD_REPLY
1064{
1065 U8 ImageType; /* 00h */
1066 U8 Reserved; /* 01h */
1067 U8 MsgLength; /* 02h */
1068 U8 Function; /* 03h */
1069 U8 Reserved1[3]; /* 04h */
1070 U8 MsgFlags; /* 07h */
1071 U32 MsgContext; /* 08h */
1072 U16 Reserved2; /* 0Ch */
1073 U16 IOCStatus; /* 0Eh */
1074 U32 IOCLogInfo; /* 10h */
1075} MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY,
1076 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t;
1077
1078
1079/****************************************************************************/
1080/* Firmware Upload message and associated structures */
1081/****************************************************************************/
1082
1083typedef struct _MSG_FW_UPLOAD
1084{
1085 U8 ImageType; /* 00h */
1086 U8 Reserved; /* 01h */
1087 U8 ChainOffset; /* 02h */
1088 U8 Function; /* 03h */
1089 U8 Reserved1[3]; /* 04h */
1090 U8 MsgFlags; /* 07h */
1091 U32 MsgContext; /* 08h */
1092 SGE_MPI_UNION SGL; /* 0Ch */
1093} MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD,
1094 FWUpload_t, MPI_POINTER pFWUpload_t;
1095
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1096#define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00)
1097#define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1098#define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1099#define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03)
1100#define MPI_FW_UPLOAD_ITYPE_BOOTLOADER (0x04)
1101#define MPI_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1102#define MPI_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1103#define MPI_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1104#define MPI_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1105#define MPI_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1106#define MPI_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1107#define MPI_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
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1108
1109typedef struct _FWUploadTCSGE
1110{
1111 U8 Reserved; /* 00h */
1112 U8 ContextSize; /* 01h */
1113 U8 DetailsLength; /* 02h */
1114 U8 Flags; /* 03h */
1115 U32 Reserved1; /* 04h */
1116 U32 ImageOffset; /* 08h */
1117 U32 ImageSize; /* 0Ch */
1118} FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE,
1119 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t;
1120
1121/* Firmware Upload reply */
1122typedef struct _MSG_FW_UPLOAD_REPLY
1123{
1124 U8 ImageType; /* 00h */
1125 U8 Reserved; /* 01h */
1126 U8 MsgLength; /* 02h */
1127 U8 Function; /* 03h */
1128 U8 Reserved1[3]; /* 04h */
1129 U8 MsgFlags; /* 07h */
1130 U32 MsgContext; /* 08h */
1131 U16 Reserved2; /* 0Ch */
1132 U16 IOCStatus; /* 0Eh */
1133 U32 IOCLogInfo; /* 10h */
1134 U32 ActualImageSize; /* 14h */
1135} MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY,
1136 FWUploadReply_t, MPI_POINTER pFWUploadReply_t;
1137
1138
1139typedef struct _MPI_FW_HEADER
1140{
1141 U32 ArmBranchInstruction0; /* 00h */
1142 U32 Signature0; /* 04h */
1143 U32 Signature1; /* 08h */
1144 U32 Signature2; /* 0Ch */
1145 U32 ArmBranchInstruction1; /* 10h */
1146 U32 ArmBranchInstruction2; /* 14h */
1147 U32 Reserved; /* 18h */
1148 U32 Checksum; /* 1Ch */
1149 U16 VendorId; /* 20h */
1150 U16 ProductId; /* 22h */
1151 MPI_FW_VERSION FWVersion; /* 24h */
1152 U32 SeqCodeVersion; /* 28h */
1153 U32 ImageSize; /* 2Ch */
1154 U32 NextImageHeaderOffset; /* 30h */
1155 U32 LoadStartAddress; /* 34h */
1156 U32 IopResetVectorValue; /* 38h */
1157 U32 IopResetRegAddr; /* 3Ch */
1158 U32 VersionNameWhat; /* 40h */
1159 U8 VersionName[32]; /* 44h */
1160 U32 VendorNameWhat; /* 64h */
1161 U8 VendorName[32]; /* 68h */
1162} MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER,
1163 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t;
1164
1165#define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1166
1167/* defines for using the ProductId field */
1168#define MPI_FW_HEADER_PID_TYPE_MASK (0xF000)
1169#define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000)
1170#define MPI_FW_HEADER_PID_TYPE_FC (0x1000)
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1171#define MPI_FW_HEADER_PID_TYPE_SAS (0x2000)
1172
1173#define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A)
1174#define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5)
1175#define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA)
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1176
1177#define MPI_FW_HEADER_PID_PROD_MASK (0x0F00)
1178#define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100)
1179#define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1180#define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300)
1181#define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400)
1182#define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500)
1183#define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600)
d751f32e 1184#define MPI_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
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1185
1186#define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF)
d751f32e 1187/* SCSI */
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1188#define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001)
1189#define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002)
1190#define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003)
1191#define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004)
1192#define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005)
1193#define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006)
1194#define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007)
1195#define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008)
1196#define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009)
1197#define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A)
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1198#define MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI (0x000B)
1199#define MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI (0x000C)
1200/* Fibre Channel */
984263bc 1201#define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000)
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1202#define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) /* 919 and 929 */
1203#define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) /* 919X and 929X */
1204#define MPI_FW_HEADER_PID_FAMILY_919XL_FC (0x0003) /* 919XL and 929XL */
1205#define MPI_FW_HEADER_PID_FAMILY_939X_FC (0x0004) /* 939X and 949X */
1206#define MPI_FW_HEADER_PID_FAMILY_959_FC (0x0005)
1207#define MPI_FW_HEADER_PID_FAMILY_949E_FC (0x0006)
1208/* SAS */
1209#define MPI_FW_HEADER_PID_FAMILY_1064_SAS (0x0001)
1210#define MPI_FW_HEADER_PID_FAMILY_1068_SAS (0x0002)
1211#define MPI_FW_HEADER_PID_FAMILY_1078_SAS (0x0003)
1212#define MPI_FW_HEADER_PID_FAMILY_106xE_SAS (0x0004) /* 1068E, 1066E, and 1064E */
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1213
1214typedef struct _MPI_EXT_IMAGE_HEADER
1215{
1216 U8 ImageType; /* 00h */
1217 U8 Reserved; /* 01h */
1218 U16 Reserved1; /* 02h */
1219 U32 Checksum; /* 04h */
1220 U32 ImageSize; /* 08h */
1221 U32 NextImageHeaderOffset; /* 0Ch */
1222 U32 LoadStartAddress; /* 10h */
1223 U32 Reserved2; /* 14h */
1224} MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER,
1225 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t;
1226
1227/* defines for the ImageType field */
1228#define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1229#define MPI_EXT_IMAGE_TYPE_FW (0x01)
1230#define MPI_EXT_IMAGE_TYPE_NVDATA (0x03)
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1231#define MPI_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1232#define MPI_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
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1233
1234#endif