[dragonfly.git] / sys / dev / netif / re / if_revar.h

/*
 * Copyright (c) 2004
 *	Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
 *
 * Copyright (c) 1997, 1998-2003
 *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Bill Paul.
 * 4. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGE.
 *
 * $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
 * $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.31 2008/10/21 12:31:01 sephe Exp $
 */

#define RE_RX_DESC_CNT_8139CP	64
#define RE_TX_DESC_CNT_8139CP	64

#define RE_RX_DESC_CNT_DEF	256
#define RE_TX_DESC_CNT_DEF	256
#define RE_RX_DESC_CNT_MAX	1024
#define RE_TX_DESC_CNT_MAX	1024

#define RE_RX_LIST_SZ(sc)	((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
#define RE_TX_LIST_SZ(sc)	((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
#define RE_RING_ALIGN		256
#define RE_IFQ_MAXLEN		512
#define RE_MAXSEGS		16
#define RE_TXDESC_SPARE		5
#define RE_JBUF_COUNT(sc)	(((sc)->re_rx_desc_cnt * 3) / 2)

#define RE_RXDESC_INC(sc, x)	(x = (x + 1) % (sc)->re_rx_desc_cnt)
#define RE_TXDESC_INC(sc, x)	(x = (x + 1) % (sc)->re_tx_desc_cnt)
#define RE_OWN(x)		(le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
#define RE_RXBYTES(x)		(le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
#define RE_PKTSZ(x)		((x)/* >> 3*/)

#define RE_ADDR_LO(y)		((uint64_t) (y) & 0xFFFFFFFF)
#define RE_ADDR_HI(y)		((uint64_t) (y) >> 32)

#define RE_MTU_6K		(6 * 1024)
#define RE_MTU_9K		(9 * 1024)

#define RE_ETHER_EXTRA		(ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
#define RE_FRAMELEN(mtu)	((mtu) + RE_ETHER_EXTRA)

#define RE_FRAMELEN_6K		RE_FRAMELEN(RE_MTU_6K)
#define RE_FRAMELEN_9K		RE_FRAMELEN(RE_MTU_9K)
#define RE_FRAMELEN_MAX		RE_FRAMELEN_9K

#define RE_RXBUF_ALIGN		8
#define RE_JBUF_SIZE		roundup2(RE_FRAMELEN_MAX, RE_RXBUF_ALIGN)

#define	RE_TIMEOUT		1000

struct re_hwrev {
	uint32_t		re_hwrev;
	uint32_t		re_macver;	/* see RE_MACVER_ */
	int			re_maxmtu;
	uint32_t		re_caps;	/* see RE_C_ */
};

#define RE_MACVER_UNKN		0
#define RE_MACVER_03		0x03
#define RE_MACVER_04		0x04
#define RE_MACVER_05		0x05
#define RE_MACVER_06		0x06
#define RE_MACVER_11		0x11
#define RE_MACVER_12		0x12
#define RE_MACVER_13		0x13
#define RE_MACVER_14		0x14
#define RE_MACVER_15		0x15
#define RE_MACVER_16		0x16
#define RE_MACVER_21		0x21
#define RE_MACVER_22		0x22
#define RE_MACVER_23		0x23
#define RE_MACVER_24		0x24
#define RE_MACVER_25		0x25
#define RE_MACVER_26		0x26
#define RE_MACVER_27		0x27
#define RE_MACVER_28		0x28
#define RE_MACVER_29		0x29
#define RE_MACVER_2A		0x2a
#define RE_MACVER_2B		0x2b
#define RE_MACVER_2C		0x2c
#define RE_MACVER_2D		0x2d
#define RE_MACVER_2E		0x2e
#define RE_MACVER_2F		0x2f
#define RE_MACVER_30		0x30
#define RE_MACVER_31		0x31

struct re_softc;
struct re_jbuf {
	struct re_softc 	*re_sc;
	int			re_inuse;
	int			re_slot;
	caddr_t			re_buf;
	bus_addr_t		re_paddr;
	SLIST_ENTRY(re_jbuf)	re_link;
};

struct re_list_data {
	struct mbuf		**re_tx_mbuf;
	struct mbuf		**re_rx_mbuf;
	bus_addr_t		*re_rx_paddr;
	int			re_tx_prodidx;
	int			re_rx_prodidx;
	int			re_tx_considx;
	int			re_tx_free;
	bus_dmamap_t		*re_tx_dmamap;
	bus_dmamap_t		*re_rx_dmamap;
	bus_dmamap_t		re_rx_spare;
	bus_dma_tag_t		re_rx_mtag;	/* RX mbuf mapping tag */
	bus_dma_tag_t		re_tx_mtag;	/* TX mbuf mapping tag */
	bus_dma_tag_t		re_stag;	/* stats mapping tag */
	bus_dmamap_t		re_smap;	/* stats map */
	struct re_stats		*re_stats;
	bus_addr_t		re_stats_addr;
	bus_dma_tag_t		re_rx_list_tag;
	bus_dmamap_t		re_rx_list_map;
	struct re_desc		*re_rx_list;
	bus_addr_t		re_rx_list_addr;
	bus_dma_tag_t		re_tx_list_tag;
	bus_dmamap_t		re_tx_list_map;
	struct re_desc		*re_tx_list;
	bus_addr_t		re_tx_list_addr;

	bus_dma_tag_t		re_jpool_tag;
	bus_dmamap_t		re_jpool_map;
	caddr_t			re_jpool;
	struct re_jbuf		*re_jbuf;
	struct lwkt_serialize	re_jbuf_serializer;
	SLIST_HEAD(, re_jbuf)	re_jbuf_free;
};

struct re_softc {
	struct arpcom		arpcom;		/* interface info */
	device_t		re_dev;
	bus_space_handle_t	re_bhandle;	/* bus space handle */
	bus_space_tag_t		re_btag;	/* bus space tag */
	struct resource		*re_res;
	struct resource		*re_irq;
	void			*re_intrhand;
	device_t		re_miibus;
	bus_dma_tag_t		re_parent_tag;
	bus_dma_tag_t		re_tag;
	uint32_t		re_hwrev;
	struct re_list_data	re_ldata;
	struct callout		re_timer;
	struct mbuf		*re_head;
	struct mbuf		*re_tail;
	uint32_t		re_caps;	/* see RE_C_ */
	uint32_t		re_macver;	/* see RE_MACVER_ */
	uint32_t		re_rxlenmask;
	int			re_txstart;
	int			re_eewidth;
	int			re_maxmtu;
	int			re_rx_desc_cnt;
	int			re_tx_desc_cnt;
	int			re_bus_speed;
	int			rxcycles;
	int			re_rxbuf_size;
	int			(*re_newbuf)(struct re_softc *, int, int);
	int			re_irq_type;
	int			re_irq_rid;

	uint32_t		re_flags;	/* see RE_F_ */
	int			re_if_flags;	/* saved ifnet.if_flags */

	struct sysctl_ctx_list	re_sysctl_ctx;
	struct sysctl_oid	*re_sysctl_tree;
	uint16_t		re_intrs;
	uint16_t		re_tx_ack;
	uint16_t		re_rx_ack;
	int			re_tx_time;
	int			re_rx_time;
	int			re_sim_time;
	int			re_imtype;	/* see RE_IMTYPE_ */

	uint32_t		saved_maps[5];	/* pci data */
	uint32_t		saved_biosaddr;
	uint8_t			saved_intline;
	uint8_t			saved_cachelnsz;
	uint8_t			saved_lattimer;
};

#define RE_C_PCIE		0x1	/* PCI-E */
#define RE_C_PCI64		0x2	/* PCI64 */
#define RE_C_HWIM		0x4	/* hardware interrupt moderation */
#define RE_C_HWCSUM		0x8	/* hardware csum offload */
#define RE_C_8139CP		0x20	/* is 8139C+ */
#define RE_C_MAC2		0x40	/* MAC style 2 */
#define RE_C_PHYPMGT		0x80	/* PHY supports power mgmt */
#define RE_C_8169		0x100	/* is 8110/8169 */
#define RE_C_AUTOPAD		0x200	/* hardware auto-pad short frames */
#define RE_C_CONTIGRX		0x400	/* need contig buf to RX jumbo frames */
#define RE_C_STOP_RXTX		0x800	/* could stop RX/TX engine */
#define RE_C_FASTE		0x1000	/* 10/100 only NIC */

#define RE_IS_8139CP(sc)	((sc)->re_caps & RE_C_8139CP)
#define RE_IS_8169(sc)		((sc)->re_caps & RE_C_8169)

/* Interrupt moderation types */
#define RE_IMTYPE_NONE		0
#define RE_IMTYPE_SIM		1	/* simulated */
#define RE_IMTYPE_HW		2	/* hardware based */

#define RE_F_TIMER_INTR		0x1
#define RE_F_USE_JPOOL		0x2
#define RE_F_DROP_RXFRAG	0x4
#define RE_F_LINKED		0x8
#define RE_F_SUSPENDED		0x10
#define RE_F_TESTMODE		0x20

/*
 * register space access macros
 */
#define CSR_WRITE_STREAM_4(sc, reg, val)	\
	bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
#define CSR_WRITE_4(sc, reg, val)	\
	bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val)	\
	bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val)	\
	bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)

#define CSR_READ_4(sc, reg)		\
	bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
#define CSR_READ_2(sc, reg)		\
	bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
#define CSR_READ_1(sc, reg)		\
	bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)

#define CSR_SETBIT_1(sc, reg, val)	\
	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (val))
#define CSR_CLRBIT_1(sc, reg, val)	\
	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))
Commit	Line	Data
5d686fbb SZ	1	/*
	2	* Copyright (c) 2004
	3	* Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
	4	*
	5	* Copyright (c) 1997, 1998-2003
	6	* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
	7	*
	8	* Redistribution and use in source and binary forms, with or without
	9	* modification, are permitted provided that the following conditions
	10	* are met:
	11	* 1. Redistributions of source code must retain the above copyright
	12	* notice, this list of conditions and the following disclaimer.
	13	* 2. Redistributions in binary form must reproduce the above copyright
	14	* notice, this list of conditions and the following disclaimer in the
	15	* documentation and/or other materials provided with the distribution.
	16	* 3. All advertising materials mentioning features or use of this software
	17	* must display the following acknowledgement:
	18	* This product includes software developed by Bill Paul.
	19	* 4. Neither the name of the author nor the names of any co-contributors
	20	* may be used to endorse or promote products derived from this software
	21	* without specific prior written permission.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
	24	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	26	* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
	27	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	28	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	29	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	30	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
	31	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	32	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	33	* THE POSSIBILITY OF SUCH DAMAGE.
	34	*
	35	* $FreeBSD: src/sys/pci/if_rlreg.h,v 1.42 2004/05/24 19:39:23 jhb Exp $
76c6d5cf	36	* $DragonFly: src/sys/dev/netif/re/if_revar.h,v 1.31 2008/10/21 12:31:01 sephe Exp $
5d686fbb SZ	37	*/
5d686fbb SZ	38
39acdb23 SZ	39	#define RE_RX_DESC_CNT_8139CP 64
	40	#define RE_TX_DESC_CNT_8139CP 64
	41
70be79a4 SZ	42	#define RE_RX_DESC_CNT_DEF 256
70be79a4 SZ	43	#define RE_TX_DESC_CNT_DEF 256
53d4588a SZ	44	#define RE_RX_DESC_CNT_MAX 1024
	45	#define RE_TX_DESC_CNT_MAX 1024
	46
	47	#define RE_RX_LIST_SZ(sc) ((sc)->re_rx_desc_cnt * sizeof(struct re_desc))
	48	#define RE_TX_LIST_SZ(sc) ((sc)->re_tx_desc_cnt * sizeof(struct re_desc))
998e7079 SZ	49	#define RE_RING_ALIGN 256
	50	#define RE_IFQ_MAXLEN 512
	51	#define RE_MAXSEGS 16
6525b950	52	#define RE_TXDESC_SPARE 5
a7d57e62	53	#define RE_JBUF_COUNT(sc) (((sc)->re_rx_desc_cnt * 3) / 2)
998e7079	54
53d4588a SZ	55	#define RE_RXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_rx_desc_cnt)
53d4588a SZ	56	#define RE_TXDESC_INC(sc, x) (x = (x + 1) % (sc)->re_tx_desc_cnt)
998e7079 SZ	57	#define RE_OWN(x) (le32toh((x)->re_cmdstat) & RE_RDESC_STAT_OWN)
	58	#define RE_RXBYTES(x) (le32toh((x)->re_cmdstat) & sc->re_rxlenmask)
	59	#define RE_PKTSZ(x) ((x)/* >> 3*/)
	60
	61	#define RE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
	62	#define RE_ADDR_HI(y) ((uint64_t) (y) >> 32)
	63
b0c15aad SZ	64	#define RE_MTU_6K (6 * 1024)
	65	#define RE_MTU_9K (9 * 1024)
	66
	67	#define RE_ETHER_EXTRA (ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN)
	68	#define RE_FRAMELEN(mtu) ((mtu) + RE_ETHER_EXTRA)
	69
	70	#define RE_FRAMELEN_6K RE_FRAMELEN(RE_MTU_6K)
	71	#define RE_FRAMELEN_9K RE_FRAMELEN(RE_MTU_9K)
	72	#define RE_FRAMELEN_MAX RE_FRAMELEN_9K
	73
adfa5aa6 SZ	74	#define RE_RXBUF_ALIGN 8
adfa5aa6 SZ	75	#define RE_JBUF_SIZE roundup2(RE_FRAMELEN_MAX, RE_RXBUF_ALIGN)
a7d57e62	76
998e7079 SZ	77	#define RE_TIMEOUT 1000
998e7079 SZ	78
5d686fbb	79	struct re_hwrev {
a1b67fc3 SZ	80	uint32_t re_hwrev;
a1b67fc3 SZ	81	uint32_t re_macver; /* see RE_MACVER_ */
b0c15aad	82	int re_maxmtu;
5bed1fbd	83	uint32_t re_caps; /* see RE_C_ */
5d686fbb SZ	84	};
5d686fbb SZ	85
a1b67fc3 SZ	86	#define RE_MACVER_UNKN 0
	87	#define RE_MACVER_03 0x03
	88	#define RE_MACVER_04 0x04
	89	#define RE_MACVER_05 0x05
	90	#define RE_MACVER_06 0x06
	91	#define RE_MACVER_11 0x11
	92	#define RE_MACVER_12 0x12
	93	#define RE_MACVER_13 0x13
	94	#define RE_MACVER_14 0x14
	95	#define RE_MACVER_15 0x15
	96	#define RE_MACVER_16 0x16
	97	#define RE_MACVER_21 0x21
	98	#define RE_MACVER_22 0x22
	99	#define RE_MACVER_23 0x23
	100	#define RE_MACVER_24 0x24
	101	#define RE_MACVER_25 0x25
	102	#define RE_MACVER_26 0x26
	103	#define RE_MACVER_27 0x27
	104	#define RE_MACVER_28 0x28
	105	#define RE_MACVER_29 0x29
	106	#define RE_MACVER_2A 0x2a
	107	#define RE_MACVER_2B 0x2b
6feb3493 SZ	108	#define RE_MACVER_2C 0x2c
6feb3493 SZ	109	#define RE_MACVER_2D 0x2d
e74e67d8 SZ	110	#define RE_MACVER_2E 0x2e
e74e67d8 SZ	111	#define RE_MACVER_2F 0x2f
0f4de8aa SZ	112	#define RE_MACVER_30 0x30
0f4de8aa SZ	113	#define RE_MACVER_31 0x31
5d686fbb	114
a7d57e62 SZ	115	struct re_softc;
	116	struct re_jbuf {
	117	struct re_softc *re_sc;
	118	int re_inuse;
	119	int re_slot;
	120	caddr_t re_buf;
	121	bus_addr_t re_paddr;
	122	SLIST_ENTRY(re_jbuf) re_link;
	123	};
	124
5d686fbb	125	struct re_list_data {
53d4588a SZ	126	struct mbuf **re_tx_mbuf;
	127	struct mbuf **re_rx_mbuf;
	128	bus_addr_t *re_rx_paddr;
5d686fbb SZ	129	int re_tx_prodidx;
	130	int re_rx_prodidx;
	131	int re_tx_considx;
	132	int re_tx_free;
53d4588a SZ	133	bus_dmamap_t *re_tx_dmamap;
53d4588a SZ	134	bus_dmamap_t *re_rx_dmamap;
3580fc56	135	bus_dmamap_t re_rx_spare;
8aaa1e58 SZ	136	bus_dma_tag_t re_rx_mtag; /* RX mbuf mapping tag */
8aaa1e58 SZ	137	bus_dma_tag_t re_tx_mtag; /* TX mbuf mapping tag */
5d686fbb SZ	138	bus_dma_tag_t re_stag; /* stats mapping tag */
	139	bus_dmamap_t re_smap; /* stats map */
	140	struct re_stats *re_stats;
	141	bus_addr_t re_stats_addr;
	142	bus_dma_tag_t re_rx_list_tag;
	143	bus_dmamap_t re_rx_list_map;
	144	struct re_desc *re_rx_list;
	145	bus_addr_t re_rx_list_addr;
	146	bus_dma_tag_t re_tx_list_tag;
	147	bus_dmamap_t re_tx_list_map;
	148	struct re_desc *re_tx_list;
	149	bus_addr_t re_tx_list_addr;
a7d57e62 SZ	150
	151	bus_dma_tag_t re_jpool_tag;
	152	bus_dmamap_t re_jpool_map;
	153	caddr_t re_jpool;
	154	struct re_jbuf *re_jbuf;
	155	struct lwkt_serialize re_jbuf_serializer;
	156	SLIST_HEAD(, re_jbuf) re_jbuf_free;
5d686fbb SZ	157	};
	158
	159	struct re_softc {
	160	struct arpcom arpcom; /* interface info */
5d686fbb	161	device_t re_dev;
5d686fbb SZ	162	bus_space_handle_t re_bhandle; /* bus space handle */
	163	bus_space_tag_t re_btag; /* bus space tag */
	164	struct resource *re_res;
	165	struct resource *re_irq;
	166	void *re_intrhand;
	167	device_t re_miibus;
	168	bus_dma_tag_t re_parent_tag;
	169	bus_dma_tag_t re_tag;
089dc1b7	170	uint32_t re_hwrev;
5d686fbb SZ	171	struct re_list_data re_ldata;
	172	struct callout re_timer;
	173	struct mbuf *re_head;
	174	struct mbuf *re_tail;
5bed1fbd	175	uint32_t re_caps; /* see RE_C_ */
a1b67fc3	176	uint32_t re_macver; /* see RE_MACVER_ */
5d686fbb SZ	177	uint32_t re_rxlenmask;
5d686fbb SZ	178	int re_txstart;
5d686fbb	179	int re_eewidth;
089dc1b7	180	int re_maxmtu;
53d4588a SZ	181	int re_rx_desc_cnt;
53d4588a SZ	182	int re_tx_desc_cnt;
957a8760	183	int re_bus_speed;
5d686fbb	184	int rxcycles;
a7d57e62 SZ	185	int re_rxbuf_size;
a7d57e62 SZ	186	int (re_newbuf)(struct re_softc , int, int);
4dce912a TB	187	int re_irq_type;
4dce912a TB	188	int re_irq_rid;
5d686fbb	189
d4d77345	190	uint32_t re_flags; /* see RE_F_ */
76c6d5cf	191	int re_if_flags; /* saved ifnet.if_flags */
d4d77345	192
5d686fbb SZ	193	struct sysctl_ctx_list re_sysctl_ctx;
	194	struct sysctl_oid *re_sysctl_tree;
	195	uint16_t re_intrs;
	196	uint16_t re_tx_ack;
1bdb2a81	197	uint16_t re_rx_ack;
d4d77345 SZ	198	int re_tx_time;
	199	int re_rx_time;
	200	int re_sim_time;
	201	int re_imtype; /* see RE_IMTYPE_ */
5d686fbb	202
5d686fbb SZ	203	uint32_t saved_maps[5]; /* pci data */
	204	uint32_t saved_biosaddr;
	205	uint8_t saved_intline;
	206	uint8_t saved_cachelnsz;
	207	uint8_t saved_lattimer;
5d686fbb SZ	208	};
5d686fbb SZ	209
b7bb5f55	210	#define RE_C_PCIE 0x1 /* PCI-E */
0fa7d7f4	211	#define RE_C_PCI64 0x2 /* PCI64 */
5bed1fbd	212	#define RE_C_HWIM 0x4 /* hardware interrupt moderation */
b7bb5f55	213	#define RE_C_HWCSUM 0x8 /* hardware csum offload */
a1b67fc3	214	#define RE_C_8139CP 0x20 /* is 8139C+ */
b7bb5f55	215	#define RE_C_MAC2 0x40 /* MAC style 2 */
b24ce995	216	#define RE_C_PHYPMGT 0x80 /* PHY supports power mgmt */
b7bb5f55	217	#define RE_C_8169 0x100 /* is 8110/8169 */
afdeb9da	218	#define RE_C_AUTOPAD 0x200 /* hardware auto-pad short frames */
a7d57e62	219	#define RE_C_CONTIGRX 0x400 /* need contig buf to RX jumbo frames */
0d73dcef	220	#define RE_C_STOP_RXTX 0x800 /* could stop RX/TX engine */
0fa7d7f4	221	#define RE_C_FASTE 0x1000 /* 10/100 only NIC */
a1b67fc3 SZ	222
a1b67fc3 SZ	223	#define RE_IS_8139CP(sc) ((sc)->re_caps & RE_C_8139CP)
0d73dcef	224	#define RE_IS_8169(sc) ((sc)->re_caps & RE_C_8169)
043ecbf0	225
d4d77345 SZ	226	/* Interrupt moderation types */
	227	#define RE_IMTYPE_NONE 0
	228	#define RE_IMTYPE_SIM 1 /* simulated */
	229	#define RE_IMTYPE_HW 2 /* hardware based */
	230
	231	#define RE_F_TIMER_INTR 0x1
a7d57e62	232	#define RE_F_USE_JPOOL 0x2
ffa3a109 SZ	233	#define RE_F_DROP_RXFRAG 0x4
	234	#define RE_F_LINKED 0x8
	235	#define RE_F_SUSPENDED 0x10
	236	#define RE_F_TESTMODE 0x20
d4d77345	237
5d686fbb SZ	238	/*
	239	* register space access macros
	240	*/
	241	#define CSR_WRITE_STREAM_4(sc, reg, val) \
	242	bus_space_write_stream_4(sc->re_btag, sc->re_bhandle, reg, val)
	243	#define CSR_WRITE_4(sc, reg, val) \
	244	bus_space_write_4(sc->re_btag, sc->re_bhandle, reg, val)
	245	#define CSR_WRITE_2(sc, reg, val) \
	246	bus_space_write_2(sc->re_btag, sc->re_bhandle, reg, val)
	247	#define CSR_WRITE_1(sc, reg, val) \
	248	bus_space_write_1(sc->re_btag, sc->re_bhandle, reg, val)
	249
	250	#define CSR_READ_4(sc, reg) \
	251	bus_space_read_4(sc->re_btag, sc->re_bhandle, reg)
	252	#define CSR_READ_2(sc, reg) \
	253	bus_space_read_2(sc->re_btag, sc->re_bhandle, reg)
	254	#define CSR_READ_1(sc, reg) \
	255	bus_space_read_1(sc->re_btag, sc->re_bhandle, reg)
	256
	257	#define CSR_SETBIT_1(sc, reg, val) \
	258	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) \| (val))
	259	#define CSR_CLRBIT_1(sc, reg, val) \
	260	CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(val))