PCIe re(4) can't handle TCP csum offloading well if short packets
[dragonfly.git] / sys / dev / netif / re / if_re.c
CommitLineData
af51229a
JS
1/*
2 * Copyright (c) 2004
3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
4df76d5d 36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.31 2007/02/14 13:00:34 sephe Exp $
af51229a
JS
37 */
38
39/*
5d686fbb 40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
af51229a
JS
41 *
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47/*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
5d686fbb
SZ
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
af51229a
JS
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
25c5ec5f
MD
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
af51229a
JS
112 */
113
2b71c8f1
SZ
114#include "opt_polling.h"
115
af51229a 116#include <sys/param.h>
5d686fbb 117#include <sys/bus.h>
af51229a 118#include <sys/endian.h>
af51229a 119#include <sys/kernel.h>
5d686fbb
SZ
120#include <sys/malloc.h>
121#include <sys/mbuf.h>
122/* #include <sys/module.h> */
1f7ab7c9 123#include <sys/rman.h>
5d686fbb
SZ
124#include <sys/serialize.h>
125#include <sys/socket.h>
126#include <sys/sockio.h>
127#include <sys/sysctl.h>
af51229a 128
5d686fbb
SZ
129#include <net/bpf.h>
130#include <net/ethernet.h>
af51229a 131#include <net/if.h>
4d723e5a 132#include <net/ifq_var.h>
af51229a 133#include <net/if_arp.h>
af51229a
JS
134#include <net/if_dl.h>
135#include <net/if_media.h>
136#include <net/if_types.h>
137#include <net/vlan/if_vlan_var.h>
138
af51229a
JS
139#include <dev/netif/mii_layer/mii.h>
140#include <dev/netif/mii_layer/miivar.h>
141
3ff737e6 142#include <bus/pci/pcidevs.h>
af51229a
JS
143#include <bus/pci/pcireg.h>
144#include <bus/pci/pcivar.h>
145
5d686fbb 146/* "device miibus" required. See GENERIC if you get errors here. */
af51229a
JS
147#include "miibus_if.h"
148
149#include <dev/netif/re/if_rereg.h>
5d686fbb 150#include <dev/netif/re/if_revar.h>
af51229a
JS
151
152#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
5d686fbb 153#if 0
8497ad23 154#define RE_DISABLE_HWCSUM
5d686fbb 155#endif
af51229a
JS
156
157/*
158 * Various supported device vendors/types and their names.
159 */
7caafb85 160static const struct re_type re_devs[] = {
3ff737e6 161 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T, RE_HWREV_8169S,
25c5ec5f 162 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
3ff737e6 163 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139, RE_HWREV_8139CPLUS,
af51229a 164 "RealTek 8139C+ 10/100BaseTX" },
5d686fbb
SZ
165 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E, RE_HWREV_8101E,
166 "RealTek 8101E PCIe 10/100baseTX" },
167 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN1,
168 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
169 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168, RE_HWREV_8168_SPIN2,
170 "RealTek 8168/8111B PCIe Gigabit Ethernet" },
3ff737e6 171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169,
af51229a 172 "RealTek 8169 Gigabit Ethernet" },
3ff737e6 173 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169S,
af51229a 174 "RealTek 8169S Single-chip Gigabit Ethernet" },
5d686fbb
SZ
175 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8169_8110SB,
176 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC, RE_HWREV_8169_8110SC,
178 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
3ff737e6 179 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169, RE_HWREV_8110S,
af51229a 180 "RealTek 8110S Single-chip Gigabit Ethernet" },
139efd88
SZ
181 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT, RE_HWREV_8169S,
182 "Corega CG-LAPCIGT Gigabit Ethernet" },
5fdf38d0
SZ
183 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032, RE_HWREV_8169S,
184 "Linksys EG1032 Gigabit Ethernet" },
5d686fbb
SZ
185 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902, RE_HWREV_8169S,
186 "US Robotics 997902 Gigabit Ethernet" },
af51229a
JS
187 { 0, 0, 0, NULL }
188};
189
7caafb85
SZ
190static const struct re_hwrev re_hwrevs[] = {
191 { RE_HWREV_8139CPLUS, RE_8139CPLUS, RE_F_HASMPC, "C+" },
610fc460
SZ
192 { RE_HWREV_8168_SPIN1, RE_8169, RE_F_PCIE, "8168" },
193 { RE_HWREV_8168_SPIN2, RE_8169, RE_F_PCIE, "8168" },
7caafb85
SZ
194 { RE_HWREV_8169, RE_8169, RE_F_HASMPC, "8169" },
195 { RE_HWREV_8169S, RE_8169, RE_F_HASMPC, "8169S" },
196 { RE_HWREV_8110S, RE_8169, RE_F_HASMPC, "8110S" },
197 { RE_HWREV_8169_8110SB, RE_8169, RE_F_HASMPC, "8169SB" },
198 { RE_HWREV_8169_8110SC, RE_8169, 0, "8169SC" },
199 { RE_HWREV_8100E, RE_8169, RE_F_HASMPC, "8100E" },
610fc460 200 { RE_HWREV_8101E, RE_8169, RE_F_PCIE, "8101E" },
7caafb85 201 { 0, 0, 0, NULL }
af51229a
JS
202};
203
204static int re_probe(device_t);
205static int re_attach(device_t);
206static int re_detach(device_t);
207
8f77d350 208static int re_encap(struct re_softc *, struct mbuf **, int *, int *);
af51229a
JS
209
210static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
211static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
212 bus_size_t, int);
213static int re_allocmem(device_t, struct re_softc *);
214static int re_newbuf(struct re_softc *, int, struct mbuf *);
215static int re_rx_list_init(struct re_softc *);
216static int re_tx_list_init(struct re_softc *);
217static void re_rxeof(struct re_softc *);
218static void re_txeof(struct re_softc *);
219static void re_intr(void *);
220static void re_tick(void *);
78195a76 221static void re_tick_serialized(void *);
af51229a
JS
222static void re_start(struct ifnet *);
223static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
224static void re_init(void *);
225static void re_stop(struct re_softc *);
226static void re_watchdog(struct ifnet *);
227static int re_suspend(device_t);
228static int re_resume(device_t);
229static void re_shutdown(device_t);
230static int re_ifmedia_upd(struct ifnet *);
231static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
232
233static void re_eeprom_putbyte(struct re_softc *, int);
234static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
5d686fbb 235static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
af51229a
JS
236static int re_gmii_readreg(device_t, int, int);
237static int re_gmii_writereg(device_t, int, int, int);
238
239static int re_miibus_readreg(device_t, int, int);
240static int re_miibus_writereg(device_t, int, int, int);
241static void re_miibus_statchg(device_t);
242
243static void re_setmulti(struct re_softc *);
244static void re_reset(struct re_softc *);
245
5d686fbb 246#ifdef RE_DIAG
af51229a 247static int re_diag(struct re_softc *);
5d686fbb
SZ
248#endif
249
9c095379
MD
250#ifdef DEVICE_POLLING
251static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
252#endif
af51229a 253
5d686fbb
SZ
254static int re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS);
255
af51229a
JS
256static device_method_t re_methods[] = {
257 /* Device interface */
258 DEVMETHOD(device_probe, re_probe),
259 DEVMETHOD(device_attach, re_attach),
260 DEVMETHOD(device_detach, re_detach),
261 DEVMETHOD(device_suspend, re_suspend),
262 DEVMETHOD(device_resume, re_resume),
263 DEVMETHOD(device_shutdown, re_shutdown),
264
265 /* bus interface */
266 DEVMETHOD(bus_print_child, bus_generic_print_child),
267 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
268
269 /* MII interface */
270 DEVMETHOD(miibus_readreg, re_miibus_readreg),
271 DEVMETHOD(miibus_writereg, re_miibus_writereg),
272 DEVMETHOD(miibus_statchg, re_miibus_statchg),
273
274 { 0, 0 }
275};
276
277static driver_t re_driver = {
278 "re",
279 re_methods,
280 sizeof(struct re_softc)
281};
282
283static devclass_t re_devclass;
284
285DECLARE_DUMMY_MODULE(if_re);
286DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
287DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
288DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
289
290#define EE_SET(x) \
291 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
292
293#define EE_CLR(x) \
294 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
295
296/*
297 * Send a read command and address to the EEPROM, check for ACK.
298 */
299static void
300re_eeprom_putbyte(struct re_softc *sc, int addr)
301{
302 int d, i;
303
5d686fbb 304 d = addr | (RE_9346_READ << sc->re_eewidth);
af51229a
JS
305
306 /*
307 * Feed in each bit and strobe the clock.
308 */
5d686fbb 309 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
af51229a
JS
310 if (d & i)
311 EE_SET(RE_EE_DATAIN);
312 else
313 EE_CLR(RE_EE_DATAIN);
314 DELAY(100);
315 EE_SET(RE_EE_CLK);
316 DELAY(150);
317 EE_CLR(RE_EE_CLK);
318 DELAY(100);
319 }
320}
321
322/*
323 * Read a word of data stored in the EEPROM at address 'addr.'
324 */
325static void
326re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
327{
328 int i;
329 uint16_t word = 0;
330
af51229a
JS
331 /*
332 * Send address of word we want to read.
333 */
334 re_eeprom_putbyte(sc, addr);
335
af51229a
JS
336 /*
337 * Start reading bits from EEPROM.
338 */
339 for (i = 0x8000; i != 0; i >>= 1) {
340 EE_SET(RE_EE_CLK);
341 DELAY(100);
342 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
343 word |= i;
344 EE_CLR(RE_EE_CLK);
345 DELAY(100);
346 }
347
af51229a
JS
348 *dest = word;
349}
350
351/*
352 * Read a sequence of words from the EEPROM.
353 */
354static void
5d686fbb 355re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
af51229a
JS
356{
357 int i;
358 uint16_t word = 0, *ptr;
359
5d686fbb
SZ
360 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
361 DELAY(100);
362
af51229a 363 for (i = 0; i < cnt; i++) {
5d686fbb 364 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
af51229a 365 re_eeprom_getword(sc, off + i, &word);
5d686fbb
SZ
366 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
367 ptr = (uint16_t *)(dest + (i * 2));
368 *ptr = word;
af51229a 369 }
5d686fbb
SZ
370
371 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
af51229a
JS
372}
373
374static int
375re_gmii_readreg(device_t dev, int phy, int reg)
376{
377 struct re_softc *sc = device_get_softc(dev);
378 u_int32_t rval;
379 int i;
380
381 if (phy != 1)
382 return(0);
383
384 /* Let the rgephy driver read the GMEDIASTAT register */
385
386 if (reg == RE_GMEDIASTAT)
387 return(CSR_READ_1(sc, RE_GMEDIASTAT));
388
389 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
390 DELAY(1000);
391
392 for (i = 0; i < RE_TIMEOUT; i++) {
393 rval = CSR_READ_4(sc, RE_PHYAR);
394 if (rval & RE_PHYAR_BUSY)
395 break;
396 DELAY(100);
397 }
398
399 if (i == RE_TIMEOUT) {
400 device_printf(dev, "PHY read failed\n");
401 return(0);
402 }
403
404 return(rval & RE_PHYAR_PHYDATA);
405}
406
407static int
408re_gmii_writereg(device_t dev, int phy, int reg, int data)
409{
410 struct re_softc *sc = device_get_softc(dev);
411 uint32_t rval;
412 int i;
413
414 CSR_WRITE_4(sc, RE_PHYAR,
415 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
416 DELAY(1000);
417
418 for (i = 0; i < RE_TIMEOUT; i++) {
419 rval = CSR_READ_4(sc, RE_PHYAR);
420 if ((rval & RE_PHYAR_BUSY) == 0)
421 break;
422 DELAY(100);
423 }
424
425 if (i == RE_TIMEOUT)
426 device_printf(dev, "PHY write failed\n");
427
428 return(0);
429}
430
431static int
432re_miibus_readreg(device_t dev, int phy, int reg)
433{
434 struct re_softc *sc = device_get_softc(dev);
435 uint16_t rval = 0;
436 uint16_t re8139_reg = 0;
437
438 if (sc->re_type == RE_8169) {
439 rval = re_gmii_readreg(dev, phy, reg);
440 return(rval);
441 }
442
443 /* Pretend the internal PHY is only at address 0 */
444 if (phy)
445 return(0);
446
447 switch(reg) {
448 case MII_BMCR:
449 re8139_reg = RE_BMCR;
450 break;
451 case MII_BMSR:
452 re8139_reg = RE_BMSR;
453 break;
454 case MII_ANAR:
455 re8139_reg = RE_ANAR;
456 break;
457 case MII_ANER:
458 re8139_reg = RE_ANER;
459 break;
460 case MII_ANLPAR:
461 re8139_reg = RE_LPAR;
462 break;
463 case MII_PHYIDR1:
464 case MII_PHYIDR2:
465 return(0);
466 /*
467 * Allow the rlphy driver to read the media status
468 * register. If we have a link partner which does not
469 * support NWAY, this is the register which will tell
470 * us the results of parallel detection.
471 */
472 case RE_MEDIASTAT:
473 return(CSR_READ_1(sc, RE_MEDIASTAT));
474 default:
475 device_printf(dev, "bad phy register\n");
476 return(0);
477 }
478 rval = CSR_READ_2(sc, re8139_reg);
5d686fbb
SZ
479 if (sc->re_type == RE_8139CPLUS && re8139_reg == RE_BMCR) {
480 /* 8139C+ has different bit layout. */
481 rval &= ~(BMCR_LOOP | BMCR_ISO);
482 }
af51229a
JS
483 return(rval);
484}
485
486static int
487re_miibus_writereg(device_t dev, int phy, int reg, int data)
488{
489 struct re_softc *sc= device_get_softc(dev);
490 u_int16_t re8139_reg = 0;
491
492 if (sc->re_type == RE_8169)
493 return(re_gmii_writereg(dev, phy, reg, data));
494
495 /* Pretend the internal PHY is only at address 0 */
496 if (phy)
497 return(0);
498
499 switch(reg) {
500 case MII_BMCR:
501 re8139_reg = RE_BMCR;
5d686fbb
SZ
502 if (sc->re_type == RE_8139CPLUS) {
503 /* 8139C+ has different bit layout. */
504 data &= ~(BMCR_LOOP | BMCR_ISO);
505 }
af51229a
JS
506 break;
507 case MII_BMSR:
508 re8139_reg = RE_BMSR;
509 break;
510 case MII_ANAR:
511 re8139_reg = RE_ANAR;
512 break;
513 case MII_ANER:
514 re8139_reg = RE_ANER;
515 break;
516 case MII_ANLPAR:
517 re8139_reg = RE_LPAR;
518 break;
519 case MII_PHYIDR1:
520 case MII_PHYIDR2:
521 return(0);
522 default:
523 device_printf(dev, "bad phy register\n");
524 return(0);
525 }
526 CSR_WRITE_2(sc, re8139_reg, data);
527 return(0);
528}
529
530static void
531re_miibus_statchg(device_t dev)
532{
533}
534
535/*
536 * Program the 64-bit multicast hash filter.
537 */
538static void
539re_setmulti(struct re_softc *sc)
540{
541 struct ifnet *ifp = &sc->arpcom.ac_if;
542 int h = 0;
543 uint32_t hashes[2] = { 0, 0 };
544 struct ifmultiaddr *ifma;
545 uint32_t rxfilt;
546 int mcnt = 0;
547
548 rxfilt = CSR_READ_4(sc, RE_RXCFG);
549
550 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
551 rxfilt |= RE_RXCFG_RX_MULTI;
552 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
553 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
554 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
555 return;
556 }
557
558 /* first, zot all the existing hash bits */
559 CSR_WRITE_4(sc, RE_MAR0, 0);
560 CSR_WRITE_4(sc, RE_MAR4, 0);
561
562 /* now program new ones */
563 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
564 if (ifma->ifma_addr->sa_family != AF_LINK)
565 continue;
566 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
567 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
568 if (h < 32)
569 hashes[0] |= (1 << h);
570 else
571 hashes[1] |= (1 << (h - 32));
572 mcnt++;
573 }
574
575 if (mcnt)
576 rxfilt |= RE_RXCFG_RX_MULTI;
577 else
578 rxfilt &= ~RE_RXCFG_RX_MULTI;
579
580 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
581 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
582 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
583}
584
585static void
586re_reset(struct re_softc *sc)
587{
588 int i;
589
590 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
591
592 for (i = 0; i < RE_TIMEOUT; i++) {
593 DELAY(10);
594 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
595 break;
596 }
597 if (i == RE_TIMEOUT)
598 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
599
600 CSR_WRITE_1(sc, 0x82, 1);
601}
602
5d686fbb 603#ifdef RE_DIAG
af51229a
JS
604/*
605 * The following routine is designed to test for a defect on some
606 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
607 * lines connected to the bus, however for a 32-bit only card, they
608 * should be pulled high. The result of this defect is that the
609 * NIC will not work right if you plug it into a 64-bit slot: DMA
610 * operations will be done with 64-bit transfers, which will fail
611 * because the 64-bit data lines aren't connected.
612 *
613 * There's no way to work around this (short of talking a soldering
614 * iron to the board), however we can detect it. The method we use
615 * here is to put the NIC into digital loopback mode, set the receiver
616 * to promiscuous mode, and then try to send a frame. We then compare
617 * the frame data we sent to what was received. If the data matches,
618 * then the NIC is working correctly, otherwise we know the user has
619 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
620 * slot. In the latter case, there's no way the NIC can work correctly,
621 * so we print out a message on the console and abort the device attach.
622 */
623
624static int
625re_diag(struct re_softc *sc)
626{
627 struct ifnet *ifp = &sc->arpcom.ac_if;
628 struct mbuf *m0;
629 struct ether_header *eh;
630 struct re_desc *cur_rx;
631 uint16_t status;
632 uint32_t rxstat;
5d686fbb 633 int total_len, i, error = 0, phyaddr;
af51229a
JS
634 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
635 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
636
637 /* Allocate a single mbuf */
638
639 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
640 if (m0 == NULL)
641 return(ENOBUFS);
642
643 /*
644 * Initialize the NIC in test mode. This sets the chip up
645 * so that it can send and receive frames, but performs the
646 * following special functions:
647 * - Puts receiver in promiscuous mode
648 * - Enables digital loopback mode
649 * - Leaves interrupts turned off
650 */
651
652 ifp->if_flags |= IFF_PROMISC;
653 sc->re_testmode = 1;
5d686fbb 654 re_reset(sc);
af51229a 655 re_init(sc);
5d686fbb
SZ
656 sc->re_link = 1;
657 if (sc->re_type == RE_8169)
658 phyaddr = 1;
659 else
660 phyaddr = 0;
661
662 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
663 for (i = 0; i < RE_TIMEOUT; i++) {
664 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
665 if (!(status & BMCR_RESET))
666 break;
667 }
668
669 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
670 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
671
af51229a 672 DELAY(100000);
af51229a
JS
673
674 /* Put some data in the mbuf */
675
676 eh = mtod(m0, struct ether_header *);
677 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
678 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
679 eh->ether_type = htons(ETHERTYPE_IP);
680 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
681
682 /*
683 * Queue the packet, start transmission.
4d723e5a 684 * Note: ifq_handoff() ultimately calls re_start() for us.
af51229a
JS
685 */
686
687 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
4d723e5a
JS
688 error = ifq_handoff(ifp, m0, NULL);
689 if (error) {
690 m0 = NULL;
691 goto done;
692 }
af51229a
JS
693 m0 = NULL;
694
695 /* Wait for it to propagate through the chip */
696
697 DELAY(100000);
698 for (i = 0; i < RE_TIMEOUT; i++) {
699 status = CSR_READ_2(sc, RE_ISR);
5d686fbb 700 CSR_WRITE_2(sc, RE_ISR, status);
af51229a
JS
701 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
702 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
703 break;
704 DELAY(10);
705 }
706
707 if (i == RE_TIMEOUT) {
708 if_printf(ifp, "diagnostic failed to receive packet "
709 "in loopback mode\n");
710 error = EIO;
711 goto done;
712 }
713
714 /*
715 * The packet should have been dumped into the first
716 * entry in the RX DMA ring. Grab it from there.
717 */
718
719 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
720 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
721 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
722 BUS_DMASYNC_POSTWRITE);
723 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
724
725 m0 = sc->re_ldata.re_rx_mbuf[0];
726 sc->re_ldata.re_rx_mbuf[0] = NULL;
727 eh = mtod(m0, struct ether_header *);
728
729 cur_rx = &sc->re_ldata.re_rx_list[0];
730 total_len = RE_RXBYTES(cur_rx);
731 rxstat = le32toh(cur_rx->re_cmdstat);
732
733 if (total_len != ETHER_MIN_LEN) {
734 if_printf(ifp, "diagnostic failed, received short packet\n");
735 error = EIO;
736 goto done;
737 }
738
739 /* Test that the received packet data matches what we sent. */
740
741 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
742 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
743 be16toh(eh->ether_type) != ETHERTYPE_IP) {
744 if_printf(ifp, "WARNING, DMA FAILURE!\n");
745 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
746 dst, ":", src, ":", ETHERTYPE_IP);
747 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
748 eh->ether_dhost, ":", eh->ether_shost, ":",
749 ntohs(eh->ether_type));
750 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
751 "into a 64-bit PCI slot.\n");
752 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
753 "for proper operation.\n");
754 if_printf(ifp, "Read the re(4) man page for more details.\n");
755 error = EIO;
756 }
757
758done:
759 /* Turn interface off, release resources */
760
761 sc->re_testmode = 0;
5d686fbb 762 sc->re_link = 0;
af51229a
JS
763 ifp->if_flags &= ~IFF_PROMISC;
764 re_stop(sc);
765 if (m0 != NULL)
766 m_freem(m0);
767
768 return (error);
769}
5d686fbb 770#endif /* RE_DIAG */
af51229a
JS
771
772/*
773 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
774 * IDs against our list and return a device name if we find a match.
775 */
776static int
777re_probe(device_t dev)
778{
7caafb85 779 const struct re_type *t;
af51229a
JS
780 struct re_softc *sc;
781 int rid;
782 uint32_t hwrev;
783 uint16_t vendor, product;
784
785 t = re_devs;
786
787 vendor = pci_get_vendor(dev);
788 product = pci_get_device(dev);
789
5fdf38d0
SZ
790 /*
791 * Only attach to rev.3 of the Linksys EG1032 adapter.
792 * Rev.2 is supported by sk(4).
793 */
794 if (vendor == PCI_VENDOR_LINKSYS &&
795 product == PCI_PRODUCT_LINKSYS_EG1032 &&
796 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
797 return ENXIO;
798
af51229a
JS
799 for (t = re_devs; t->re_name != NULL; t++) {
800 if (product == t->re_did && vendor == t->re_vid)
801 break;
802 }
803
804 /*
805 * Check if we found a RealTek device.
806 */
807 if (t->re_name == NULL)
808 return(ENXIO);
809
810 /*
811 * Temporarily map the I/O space so we can read the chip ID register.
812 */
efda3bd0 813 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
ecd80f47
JS
814 rid = RE_PCI_LOIO;
815 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
af51229a
JS
816 RF_ACTIVE);
817 if (sc->re_res == NULL) {
818 device_printf(dev, "couldn't map ports/memory\n");
efda3bd0 819 kfree(sc, M_TEMP);
af51229a
JS
820 return(ENXIO);
821 }
822
823 sc->re_btag = rman_get_bustag(sc->re_res);
824 sc->re_bhandle = rman_get_bushandle(sc->re_res);
825
826 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
ecd80f47 827 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
efda3bd0 828 kfree(sc, M_TEMP);
af51229a
JS
829
830 /*
831 * and continue matching for the specific chip...
832 */
833 for (; t->re_name != NULL; t++) {
834 if (product == t->re_did && vendor == t->re_vid &&
835 t->re_basetype == hwrev) {
836 device_set_desc(dev, t->re_name);
837 return(0);
838 }
839 }
840 return(ENXIO);
841}
842
843/*
844 * This routine takes the segment list provided as the result of
845 * a bus_dma_map_load() operation and assigns the addresses/lengths
846 * to RealTek DMA descriptors. This can be called either by the RX
847 * code or the TX code. In the RX case, we'll probably wind up mapping
848 * at most one segment. For the TX case, there could be any number of
849 * segments since TX packets may span multiple mbufs. In either case,
850 * if the number of segments is larger than the re_maxsegs limit
851 * specified by the caller, we abort the mapping operation. Sadly,
852 * whoever designed the buffer mapping API did not provide a way to
853 * return an error from here, so we have to fake it a bit.
854 */
855
856static void
857re_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg,
858 bus_size_t mapsize, int error)
859{
860 struct re_dmaload_arg *ctx;
861 struct re_desc *d = NULL;
862 int i = 0, idx;
863 uint32_t cmdstat;
864
865 if (error)
866 return;
867
868 ctx = arg;
869
870 /* Signal error to caller if there's too many segments */
871 if (nseg > ctx->re_maxsegs) {
872 ctx->re_maxsegs = 0;
873 return;
874 }
875
876 /*
877 * Map the segment array into descriptors. Note that we set the
878 * start-of-frame and end-of-frame markers for either TX or RX, but
879 * they really only have meaning in the TX case. (In the RX case,
880 * it's the chip that tells us where packets begin and end.)
881 * We also keep track of the end of the ring and set the
882 * end-of-ring bits as needed, and we set the ownership bits
883 * in all except the very first descriptor. (The caller will
884 * set this descriptor later when it start transmission or
885 * reception.)
886 */
887 idx = ctx->re_idx;
888 for (;;) {
889 d = &ctx->re_ring[idx];
890 if (le32toh(d->re_cmdstat) & RE_RDESC_STAT_OWN) {
891 ctx->re_maxsegs = 0;
892 return;
893 }
894 cmdstat = segs[i].ds_len;
895 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
896 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
897 if (i == 0)
898 cmdstat |= RE_TDESC_CMD_SOF;
899 else
900 cmdstat |= RE_TDESC_CMD_OWN;
901 if (idx == (RE_RX_DESC_CNT - 1))
902 cmdstat |= RE_TDESC_CMD_EOR;
903 d->re_cmdstat = htole32(cmdstat | ctx->re_flags);
904 i++;
905 if (i == nseg)
906 break;
907 RE_DESC_INC(idx);
908 }
909
910 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
911 ctx->re_maxsegs = nseg;
912 ctx->re_idx = idx;
913}
914
915/*
916 * Map a single buffer address.
917 */
918
919static void
920re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
921{
922 uint32_t *addr;
923
924 if (error)
925 return;
926
927 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
928 addr = arg;
929 *addr = segs->ds_addr;
930}
931
932static int
933re_allocmem(device_t dev, struct re_softc *sc)
934{
935 int error, i, nseg;
936
937 /*
938 * Allocate map for RX mbufs.
939 */
940 nseg = 32;
941 error = bus_dma_tag_create(sc->re_parent_tag, ETHER_ALIGN, 0,
942 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
943 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
944 &sc->re_ldata.re_mtag);
945 if (error) {
946 device_printf(dev, "could not allocate dma tag\n");
947 return(error);
948 }
949
950 /*
951 * Allocate map for TX descriptor list.
952 */
953 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
954 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
955 NULL, RE_TX_LIST_SZ, 1, RE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
956 &sc->re_ldata.re_tx_list_tag);
957 if (error) {
958 device_printf(dev, "could not allocate dma tag\n");
959 return(error);
960 }
961
962 /* Allocate DMA'able memory for the TX ring */
963
964 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
965 (void **)&sc->re_ldata.re_tx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
966 &sc->re_ldata.re_tx_list_map);
967 if (error) {
968 device_printf(dev, "could not allocate TX ring\n");
969 return(error);
970 }
971
972 /* Load the map for the TX ring. */
973
974 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
975 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
976 RE_TX_LIST_SZ, re_dma_map_addr,
977 &sc->re_ldata.re_tx_list_addr, BUS_DMA_NOWAIT);
978 if (error) {
979 device_printf(dev, "could not get addres of TX ring\n");
980 return(error);
981 }
982
983 /* Create DMA maps for TX buffers */
984
985 for (i = 0; i < RE_TX_DESC_CNT; i++) {
986 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
987 &sc->re_ldata.re_tx_dmamap[i]);
988 if (error) {
989 device_printf(dev, "can't create DMA map for TX\n");
990 return(error);
991 }
992 }
993
994 /*
995 * Allocate map for RX descriptor list.
996 */
997 error = bus_dma_tag_create(sc->re_parent_tag, RE_RING_ALIGN,
998 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
7b4b20cd 999 NULL, RE_RX_LIST_SZ, 1, RE_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
af51229a
JS
1000 &sc->re_ldata.re_rx_list_tag);
1001 if (error) {
1002 device_printf(dev, "could not allocate dma tag\n");
1003 return(error);
1004 }
1005
1006 /* Allocate DMA'able memory for the RX ring */
1007
1008 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1009 (void **)&sc->re_ldata.re_rx_list, BUS_DMA_WAITOK | BUS_DMA_ZERO,
1010 &sc->re_ldata.re_rx_list_map);
1011 if (error) {
1012 device_printf(dev, "could not allocate RX ring\n");
1013 return(error);
1014 }
1015
1016 /* Load the map for the RX ring. */
1017
1018 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1019 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
7b4b20cd 1020 RE_RX_LIST_SZ, re_dma_map_addr,
af51229a
JS
1021 &sc->re_ldata.re_rx_list_addr, BUS_DMA_NOWAIT);
1022 if (error) {
1023 device_printf(dev, "could not get address of RX ring\n");
1024 return(error);
1025 }
1026
1027 /* Create DMA maps for RX buffers */
1028
1029 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1030 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1031 &sc->re_ldata.re_rx_dmamap[i]);
1032 if (error) {
1033 device_printf(dev, "can't create DMA map for RX\n");
1034 return(ENOMEM);
1035 }
1036 }
1037
1038 return(0);
1039}
1040
1041/*
1042 * Attach the interface. Allocate softc structures, do ifmedia
1043 * setup and ethernet/BPF attach.
1044 */
1045static int
1046re_attach(device_t dev)
1047{
1048 struct re_softc *sc = device_get_softc(dev);
1049 struct ifnet *ifp;
7caafb85 1050 const struct re_hwrev *hw_rev;
af51229a 1051 uint8_t eaddr[ETHER_ADDR_LEN];
5d686fbb 1052 uint16_t as[ETHER_ADDR_LEN / 2];
5d686fbb 1053 uint16_t re_did = 0;
7caafb85 1054 uint32_t hwrev;
af51229a
JS
1055 int error = 0, rid, i;
1056
1057 callout_init(&sc->re_timer);
5d686fbb
SZ
1058#ifdef RE_DIAG
1059 sc->re_dev = dev;
1060#endif
1061
1062 RE_ENABLE_TX_MODERATION(sc);
1063
1064 sysctl_ctx_init(&sc->re_sysctl_ctx);
1065 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1066 SYSCTL_STATIC_CHILDREN(_hw),
1067 OID_AUTO,
1068 device_get_nameunit(dev),
1069 CTLFLAG_RD, 0, "");
1070 if (sc->re_sysctl_tree == NULL) {
1071 device_printf(dev, "can't add sysctl node\n");
1072 error = ENXIO;
1073 goto fail;
1074 }
1075 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1076 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1077 OID_AUTO, "tx_moderation",
1078 CTLTYPE_INT | CTLFLAG_RW,
1079 sc, 0, re_sysctl_tx_moderation, "I",
1080 "Enable/Disable TX moderation");
af51229a
JS
1081
1082#ifndef BURN_BRIDGES
1083 /*
1084 * Handle power management nonsense.
1085 */
1086
1087 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1088 uint32_t membase, irq;
1089
1090 /* Save important PCI config data. */
1091 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1092 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1093
1094 /* Reset the power state. */
1095 device_printf(dev, "chip is is in D%d power mode "
1096 "-- setting to D0\n", pci_get_powerstate(dev));
1097
1098 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1099
1100 /* Restore PCI config data. */
1101 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1102 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1103 }
1104#endif
1105 /*
1106 * Map control/status registers.
1107 */
1108 pci_enable_busmaster(dev);
1109
ecd80f47
JS
1110 rid = RE_PCI_LOIO;
1111 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
af51229a
JS
1112 RF_ACTIVE);
1113
1114 if (sc->re_res == NULL) {
5d686fbb 1115 device_printf(dev, "couldn't map ports\n");
af51229a
JS
1116 error = ENXIO;
1117 goto fail;
1118 }
1119
1120 sc->re_btag = rman_get_bustag(sc->re_res);
1121 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1122
1123 /* Allocate interrupt */
1124 rid = 0;
1125 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1126 RF_SHAREABLE | RF_ACTIVE);
1127
1128 if (sc->re_irq == NULL) {
1129 device_printf(dev, "couldn't map interrupt\n");
1130 error = ENXIO;
1131 goto fail;
1132 }
1133
1134 /* Reset the adapter. */
1135 re_reset(sc);
1136
1137 hwrev = CSR_READ_4(sc, RE_TXCFG) & RE_TXCFG_HWREV;
1138 for (hw_rev = re_hwrevs; hw_rev->re_desc != NULL; hw_rev++) {
1139 if (hw_rev->re_rev == hwrev) {
1140 sc->re_type = hw_rev->re_type;
7caafb85 1141 sc->re_flags = hw_rev->re_flags;
af51229a
JS
1142 break;
1143 }
1144 }
1145
5d686fbb
SZ
1146 sc->re_eewidth = 6;
1147 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1148 if (re_did != 0x8129)
1149 sc->re_eewidth = 8;
1150
1151 /*
1152 * Get station address from the EEPROM.
1153 */
1154 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
1155 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1156 as[i] = le16toh(as[i]);
1157 bcopy(as, eaddr, sizeof(eaddr));
1158
af51229a
JS
1159 if (sc->re_type == RE_8169) {
1160 /* Set RX length mask */
1161 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
5d686fbb 1162 sc->re_txstart = RE_GTXSTART;
af51229a 1163 } else {
af51229a
JS
1164 /* Set RX length mask */
1165 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
5d686fbb 1166 sc->re_txstart = RE_TXSTART;
af51229a
JS
1167 }
1168
1169 /*
1170 * Allocate the parent bus DMA tag appropriate for PCI.
1171 */
1172#define RE_NSEG_NEW 32
1173 error = bus_dma_tag_create(NULL, /* parent */
1174 1, 0, /* alignment, boundary */
1175 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1176 BUS_SPACE_MAXADDR, /* highaddr */
1177 NULL, NULL, /* filter, filterarg */
1178 MAXBSIZE, RE_NSEG_NEW, /* maxsize, nsegments */
1179 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1180 BUS_DMA_ALLOCNOW, /* flags */
1181 &sc->re_parent_tag);
1182 if (error)
1183 goto fail;
1184
1185 error = re_allocmem(dev, sc);
1186
1187 if (error)
1188 goto fail;
1189
1190 /* Do MII setup */
1191 if (mii_phy_probe(dev, &sc->re_miibus,
1192 re_ifmedia_upd, re_ifmedia_sts)) {
1193 device_printf(dev, "MII without any phy!\n");
1194 error = ENXIO;
1195 goto fail;
1196 }
1197
1198 ifp = &sc->arpcom.ac_if;
1199 ifp->if_softc = sc;
1200 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1201 ifp->if_mtu = ETHERMTU;
1202 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1203 ifp->if_ioctl = re_ioctl;
af51229a
JS
1204 ifp->if_capabilities = IFCAP_VLAN_MTU;
1205 ifp->if_start = re_start;
af51229a
JS
1206 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1207#ifdef DEVICE_POLLING
9c095379 1208 ifp->if_poll = re_poll;
af51229a
JS
1209#endif
1210 ifp->if_watchdog = re_watchdog;
1211 ifp->if_init = re_init;
1212 if (sc->re_type == RE_8169)
1213 ifp->if_baudrate = 1000000000;
1214 else
1215 ifp->if_baudrate = 100000000;
000181b2
JS
1216 ifq_set_maxlen(&ifp->if_snd, RE_IFQ_MAXLEN);
1217 ifq_set_ready(&ifp->if_snd);
610fc460 1218
8497ad23
MD
1219#ifdef RE_DISABLE_HWCSUM
1220 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1221 ifp->if_hwassist = 0;
1222#else
4df76d5d
SZ
1223 ifp->if_capenable = ifp->if_capabilities;
1224 ifp->if_hwassist = RE_CSUM_FEATURES;
610fc460 1225#endif /* RE_DISABLE_HWCSUM */
af51229a 1226
af51229a
JS
1227 /*
1228 * Call MI attach routine.
1229 */
78195a76 1230 ether_ifattach(ifp, eaddr, NULL);
af51229a 1231
5d686fbb
SZ
1232#ifdef RE_DIAG
1233 /*
1234 * Perform hardware diagnostic on the original RTL8169.
1235 * Some 32-bit cards were incorrectly wired and would
1236 * malfunction if plugged into a 64-bit slot.
1237 */
1238 if (hwrev == RE_HWREV_8169) {
1239 lwkt_serialize_enter(ifp->if_serializer);
1240 error = re_diag(sc);
1241 lwkt_serialize_exit(ifp->if_serializer);
af51229a 1242
5d686fbb
SZ
1243 if (error) {
1244 device_printf(dev, "hardware diagnostic failure\n");
1245 ether_ifdetach(ifp);
1246 goto fail;
1247 }
af51229a 1248 }
5d686fbb 1249#endif /* RE_DIAG */
af51229a
JS
1250
1251 /* Hook interrupt last to avoid having to lock softc */
78195a76
MD
1252 error = bus_setup_intr(dev, sc->re_irq, INTR_NETSAFE, re_intr, sc,
1253 &sc->re_intrhand, ifp->if_serializer);
af51229a
JS
1254
1255 if (error) {
1256 device_printf(dev, "couldn't set up irq\n");
1257 ether_ifdetach(ifp);
1258 goto fail;
1259 }
1260
1261fail:
1262 if (error)
1263 re_detach(dev);
1264
1265 return (error);
1266}
1267
1268/*
1269 * Shutdown hardware and free up resources. This can be called any
1270 * time after the mutex has been initialized. It is called in both
1271 * the error case in attach and the normal detach case so it needs
1272 * to be careful about only freeing resources that have actually been
1273 * allocated.
1274 */
1275static int
1276re_detach(device_t dev)
1277{
1278 struct re_softc *sc = device_get_softc(dev);
1279 struct ifnet *ifp = &sc->arpcom.ac_if;
f0ee8b5b 1280 int i;
af51229a 1281
af51229a
JS
1282 /* These should only be active if attach succeeded */
1283 if (device_is_attached(dev)) {
cdf89432 1284 lwkt_serialize_enter(ifp->if_serializer);
af51229a 1285 re_stop(sc);
cdf89432
SZ
1286 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1287 lwkt_serialize_exit(ifp->if_serializer);
1288
af51229a
JS
1289 ether_ifdetach(ifp);
1290 }
1291 if (sc->re_miibus)
1292 device_delete_child(dev, sc->re_miibus);
1293 bus_generic_detach(dev);
1294
af51229a
JS
1295 if (sc->re_irq)
1296 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
cdf89432 1297 if (sc->re_res) {
6ffa456d 1298 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
af51229a 1299 sc->re_res);
cdf89432 1300 }
af51229a
JS
1301
1302 /* Unload and free the RX DMA ring memory and map */
1303
1304 if (sc->re_ldata.re_rx_list_tag) {
1305 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1306 sc->re_ldata.re_rx_list_map);
1307 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1308 sc->re_ldata.re_rx_list,
1309 sc->re_ldata.re_rx_list_map);
1310 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1311 }
1312
1313 /* Unload and free the TX DMA ring memory and map */
1314
1315 if (sc->re_ldata.re_tx_list_tag) {
1316 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1317 sc->re_ldata.re_tx_list_map);
1318 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1319 sc->re_ldata.re_tx_list,
1320 sc->re_ldata.re_tx_list_map);
1321 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1322 }
1323
1324 /* Destroy all the RX and TX buffer maps */
1325
1326 if (sc->re_ldata.re_mtag) {
1327 for (i = 0; i < RE_TX_DESC_CNT; i++)
1328 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1329 sc->re_ldata.re_tx_dmamap[i]);
1330 for (i = 0; i < RE_RX_DESC_CNT; i++)
1331 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1332 sc->re_ldata.re_rx_dmamap[i]);
1333 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1334 }
1335
1336 /* Unload and free the stats buffer and map */
1337
1338 if (sc->re_ldata.re_stag) {
1339 bus_dmamap_unload(sc->re_ldata.re_stag,
1340 sc->re_ldata.re_rx_list_map);
1341 bus_dmamem_free(sc->re_ldata.re_stag,
1342 sc->re_ldata.re_stats,
1343 sc->re_ldata.re_smap);
1344 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1345 }
1346
1347 if (sc->re_parent_tag)
1348 bus_dma_tag_destroy(sc->re_parent_tag);
1349
af51229a
JS
1350 return(0);
1351}
1352
1353static int
1354re_newbuf(struct re_softc *sc, int idx, struct mbuf *m)
1355{
1356 struct re_dmaload_arg arg;
1357 struct mbuf *n = NULL;
1358 int error;
1359
1360 if (m == NULL) {
1361 n = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1362 if (n == NULL)
1363 return(ENOBUFS);
1364 m = n;
1365 } else
1366 m->m_data = m->m_ext.ext_buf;
1367
7caafb85
SZ
1368 m->m_len = m->m_pkthdr.len = MCLBYTES;
1369
af51229a 1370 /*
7caafb85
SZ
1371 * NOTE:
1372 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1373 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
af51229a 1374 */
af51229a
JS
1375
1376 arg.sc = sc;
1377 arg.re_idx = idx;
1378 arg.re_maxsegs = 1;
1379 arg.re_flags = 0;
1380 arg.re_ring = sc->re_ldata.re_rx_list;
1381
1382 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1383 sc->re_ldata.re_rx_dmamap[idx], m, re_dma_map_desc,
1384 &arg, BUS_DMA_NOWAIT);
1385 if (error || arg.re_maxsegs != 1) {
1386 if (n != NULL)
1387 m_freem(n);
1388 return (ENOMEM);
1389 }
1390
1391 sc->re_ldata.re_rx_list[idx].re_cmdstat |= htole32(RE_RDESC_CMD_OWN);
1392 sc->re_ldata.re_rx_mbuf[idx] = m;
1393
1394 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[idx],
1395 BUS_DMASYNC_PREREAD);
1396
1397 return(0);
1398}
1399
1400static int
1401re_tx_list_init(struct re_softc *sc)
1402{
1403 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ);
1404 bzero(&sc->re_ldata.re_tx_mbuf, RE_TX_DESC_CNT * sizeof(struct mbuf *));
1405
1406 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1407 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1408 sc->re_ldata.re_tx_prodidx = 0;
1409 sc->re_ldata.re_tx_considx = 0;
1410 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT;
1411
1412 return(0);
1413}
1414
1415static int
1416re_rx_list_init(struct re_softc *sc)
1417{
1418 int i, error;
1419
1420 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ);
1421 bzero(&sc->re_ldata.re_rx_mbuf, RE_RX_DESC_CNT * sizeof(struct mbuf *));
1422
1423 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1424 error = re_newbuf(sc, i, NULL);
1425 if (error)
1426 return(error);
1427 }
1428
1429 /* Flush the RX descriptors */
1430
1431 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
7b4b20cd 1432 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
af51229a
JS
1433
1434 sc->re_ldata.re_rx_prodidx = 0;
1435 sc->re_head = sc->re_tail = NULL;
1436
1437 return(0);
1438}
1439
1440/*
1441 * RX handler for C+ and 8169. For the gigE chips, we support
1442 * the reception of jumbo frames that have been fragmented
1443 * across multiple 2K mbuf cluster buffers.
1444 */
1445static void
1446re_rxeof(struct re_softc *sc)
1447{
1448 struct ifnet *ifp = &sc->arpcom.ac_if;
1449 struct mbuf *m;
1450 struct re_desc *cur_rx;
af51229a
JS
1451 uint32_t rxstat, rxvlan;
1452 int i, total_len;
1453
1454 /* Invalidate the descriptor memory */
1455
1456 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1457 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1458
1459 for (i = sc->re_ldata.re_rx_prodidx;
1460 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0 ; RE_DESC_INC(i)) {
1461 cur_rx = &sc->re_ldata.re_rx_list[i];
1462 m = sc->re_ldata.re_rx_mbuf[i];
1463 total_len = RE_RXBYTES(cur_rx);
1464 rxstat = le32toh(cur_rx->re_cmdstat);
1465 rxvlan = le32toh(cur_rx->re_vlanctl);
1466
1467 /* Invalidate the RX mbuf and unload its map */
1468
1469 bus_dmamap_sync(sc->re_ldata.re_mtag,
1470 sc->re_ldata.re_rx_dmamap[i],
1471 BUS_DMASYNC_POSTWRITE);
1472 bus_dmamap_unload(sc->re_ldata.re_mtag,
1473 sc->re_ldata.re_rx_dmamap[i]);
1474
1475 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1476 m->m_len = MCLBYTES - ETHER_ALIGN;
1477 if (sc->re_head == NULL) {
1478 sc->re_head = sc->re_tail = m;
1479 } else {
af51229a
JS
1480 sc->re_tail->m_next = m;
1481 sc->re_tail = m;
1482 }
1483 re_newbuf(sc, i, NULL);
1484 continue;
1485 }
1486
1487 /*
1488 * NOTE: for the 8139C+, the frame length field
1489 * is always 12 bits in size, but for the gigE chips,
1490 * it is 13 bits (since the max RX frame length is 16K).
1491 * Unfortunately, all 32 bits in the status word
1492 * were already used, so to make room for the extra
1493 * length bit, RealTek took out the 'frame alignment
1494 * error' bit and shifted the other status bits
1495 * over one slot. The OWN, EOR, FS and LS bits are
1496 * still in the same places. We have already extracted
1497 * the frame length and checked the OWN bit, so rather
1498 * than using an alternate bit mapping, we shift the
1499 * status bits one space to the right so we can evaluate
1500 * them using the 8169 status as though it was in the
1501 * same format as that of the 8139C+.
1502 */
1503 if (sc->re_type == RE_8169)
1504 rxstat >>= 1;
1505
1506 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1507 ifp->if_ierrors++;
1508 /*
1509 * If this is part of a multi-fragment packet,
1510 * discard all the pieces.
1511 */
1512 if (sc->re_head != NULL) {
1513 m_freem(sc->re_head);
1514 sc->re_head = sc->re_tail = NULL;
1515 }
1516 re_newbuf(sc, i, m);
1517 continue;
1518 }
1519
1520 /*
1521 * If allocating a replacement mbuf fails,
1522 * reload the current one.
1523 */
1524
1525 if (re_newbuf(sc, i, NULL)) {
1526 ifp->if_ierrors++;
1527 if (sc->re_head != NULL) {
1528 m_freem(sc->re_head);
1529 sc->re_head = sc->re_tail = NULL;
1530 }
1531 re_newbuf(sc, i, m);
1532 continue;
1533 }
1534
af51229a
JS
1535 if (sc->re_head != NULL) {
1536 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1537 /*
1538 * Special case: if there's 4 bytes or less
1539 * in this buffer, the mbuf can be discarded:
1540 * the last 4 bytes is the CRC, which we don't
1541 * care about anyway.
1542 */
1543 if (m->m_len <= ETHER_CRC_LEN) {
1544 sc->re_tail->m_len -=
1545 (ETHER_CRC_LEN - m->m_len);
1546 m_freem(m);
1547 } else {
1548 m->m_len -= ETHER_CRC_LEN;
af51229a
JS
1549 sc->re_tail->m_next = m;
1550 }
1551 m = sc->re_head;
1552 sc->re_head = sc->re_tail = NULL;
1553 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1554 } else
1555 m->m_pkthdr.len = m->m_len =
1556 (total_len - ETHER_CRC_LEN);
1557
1558 ifp->if_ipackets++;
af51229a 1559 m->m_pkthdr.rcvif = ifp;
af51229a
JS
1560
1561 /* Do RX checksumming if enabled */
1562
1563 if (ifp->if_capenable & IFCAP_RXCSUM) {
1564
1565 /* Check IP header checksum */
1566 if (rxstat & RE_RDESC_STAT_PROTOID)
1567 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1568 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
1569 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1570
1571 /* Check TCP/UDP checksum */
1572 if ((RE_TCPPKT(rxstat) &&
1573 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
1574 (RE_UDPPKT(rxstat) &&
1575 (rxstat & RE_RDESC_STAT_UDPSUMBAD)) == 0) {
1576 m->m_pkthdr.csum_flags |=
1577 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1578 m->m_pkthdr.csum_data = 0xffff;
1579 }
1580 }
1581
78195a76 1582 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
3013ac0e
JS
1583 VLAN_INPUT_TAG(m,
1584 be16toh((rxvlan & RE_RDESC_VLANCTL_DATA)));
78195a76
MD
1585 } else {
1586 ifp->if_input(ifp, m);
1587 }
af51229a
JS
1588 }
1589
1590 /* Flush the RX DMA ring */
1591
1592 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
7b4b20cd 1593 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
af51229a
JS
1594
1595 sc->re_ldata.re_rx_prodidx = i;
1596}
1597
1598static void
1599re_txeof(struct re_softc *sc)
1600{
1601 struct ifnet *ifp = &sc->arpcom.ac_if;
1602 uint32_t txstat;
1603 int idx;
1604
1605 /* Invalidate the TX descriptor list */
1606
1607 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
7b4b20cd 1608 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
af51229a
JS
1609
1610 for (idx = sc->re_ldata.re_tx_considx;
5d686fbb 1611 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT; RE_DESC_INC(idx)) {
af51229a
JS
1612 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
1613 if (txstat & RE_TDESC_CMD_OWN)
1614 break;
1615
5d686fbb
SZ
1616 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
1617
af51229a
JS
1618 /*
1619 * We only stash mbufs in the last descriptor
1620 * in a fragment chain, which also happens to
1621 * be the only place where the TX status bits
1622 * are valid.
1623 */
1624 if (txstat & RE_TDESC_CMD_EOF) {
1625 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
1626 sc->re_ldata.re_tx_mbuf[idx] = NULL;
1627 bus_dmamap_unload(sc->re_ldata.re_mtag,
1628 sc->re_ldata.re_tx_dmamap[idx]);
1629 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
1630 RE_TDESC_STAT_COLCNT))
1631 ifp->if_collisions++;
1632 if (txstat & RE_TDESC_STAT_TXERRSUM)
1633 ifp->if_oerrors++;
1634 else
1635 ifp->if_opackets++;
1636 }
1637 sc->re_ldata.re_tx_free++;
1638 }
1639
1640 /* No changes made to the TX ring, so no flush needed */
5d686fbb 1641 if (sc->re_ldata.re_tx_free) {
af51229a
JS
1642 sc->re_ldata.re_tx_considx = idx;
1643 ifp->if_flags &= ~IFF_OACTIVE;
1644 ifp->if_timer = 0;
1645 }
1646
5d686fbb
SZ
1647 /*
1648 * Some chips will ignore a second TX request issued while an
1649 * existing transmission is in progress. If the transmitter goes
1650 * idle but there are still packets waiting to be sent, we need
1651 * to restart the channel here to flush them out. This only seems
1652 * to be required with the PCIe devices.
1653 */
1654 if (sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
1655 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
1656
af51229a
JS
1657 /*
1658 * If not all descriptors have been released reaped yet,
1659 * reload the timer so that we will eventually get another
1660 * interrupt that will cause us to re-enter this routine.
1661 * This is done in case the transmitter has gone idle.
1662 */
5d686fbb
SZ
1663 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
1664 sc->re_ldata.re_tx_free < RE_TX_DESC_CNT)
af51229a
JS
1665 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
1666}
1667
1668static void
1669re_tick(void *xsc)
1670{
1671 struct re_softc *sc = xsc;
af51229a 1672
78195a76
MD
1673 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1674 re_tick_serialized(xsc);
1675 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1676}
1677
1678static void
1679re_tick_serialized(void *xsc)
1680{
1681 struct re_softc *sc = xsc;
5d686fbb 1682 struct ifnet *ifp = &sc->arpcom.ac_if;
78195a76 1683 struct mii_data *mii;
af51229a
JS
1684
1685 mii = device_get_softc(sc->re_miibus);
1686 mii_tick(mii);
5d686fbb
SZ
1687 if (sc->re_link) {
1688 if (!(mii->mii_media_status & IFM_ACTIVE))
1689 sc->re_link = 0;
1690 } else {
1691 if (mii->mii_media_status & IFM_ACTIVE &&
1692 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1693 sc->re_link = 1;
1694 if (!ifq_is_empty(&ifp->if_snd))
1695 ifp->if_start(ifp);
1696 }
1697 }
af51229a
JS
1698
1699 callout_reset(&sc->re_timer, hz, re_tick, sc);
af51229a
JS
1700}
1701
1702#ifdef DEVICE_POLLING
9c095379 1703
af51229a
JS
1704static void
1705re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1706{
1707 struct re_softc *sc = ifp->if_softc;
1708
9c095379
MD
1709 switch(cmd) {
1710 case POLL_REGISTER:
1711 /* disable interrupts */
1712 CSR_WRITE_2(sc, RE_IMR, 0x0000);
1713 break;
1714 case POLL_DEREGISTER:
1715 /* enable interrupts */
5d686fbb 1716 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
9c095379
MD
1717 break;
1718 default:
1719 sc->rxcycles = count;
1720 re_rxeof(sc);
1721 re_txeof(sc);
af51229a 1722
9c095379
MD
1723 if (!ifq_is_empty(&ifp->if_snd))
1724 (*ifp->if_start)(ifp);
af51229a 1725
9c095379
MD
1726 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1727 uint16_t status;
af51229a 1728
9c095379
MD
1729 status = CSR_READ_2(sc, RE_ISR);
1730 if (status == 0xffff)
1731 return;
1732 if (status)
1733 CSR_WRITE_2(sc, RE_ISR, status);
af51229a 1734
9c095379
MD
1735 /*
1736 * XXX check behaviour on receiver stalls.
1737 */
af51229a 1738
9c095379
MD
1739 if (status & RE_ISR_SYSTEM_ERR) {
1740 re_reset(sc);
1741 re_init(sc);
1742 }
af51229a 1743 }
9c095379 1744 break;
af51229a
JS
1745 }
1746}
1747#endif /* DEVICE_POLLING */
1748
1749static void
1750re_intr(void *arg)
1751{
1752 struct re_softc *sc = arg;
1753 struct ifnet *ifp = &sc->arpcom.ac_if;
1754 uint16_t status;
af51229a
JS
1755
1756 if (sc->suspended || (ifp->if_flags & IFF_UP) == 0)
1757 return;
1758
af51229a
JS
1759 for (;;) {
1760 status = CSR_READ_2(sc, RE_ISR);
1761 /* If the card has gone away the read returns 0xffff. */
1762 if (status == 0xffff)
1763 break;
1764 if (status)
1765 CSR_WRITE_2(sc, RE_ISR, status);
1766
5d686fbb 1767 if ((status & sc->re_intrs) == 0)
af51229a
JS
1768 break;
1769
5d686fbb 1770 if (status & (RE_ISR_RX_OK | RE_ISR_RX_ERR | RE_ISR_FIFO_OFLOW))
af51229a
JS
1771 re_rxeof(sc);
1772
5d686fbb 1773 if ((status & sc->re_tx_ack) ||
af51229a
JS
1774 (status & RE_ISR_TX_ERR) ||
1775 (status & RE_ISR_TX_DESC_UNAVAIL))
1776 re_txeof(sc);
1777
1778 if (status & RE_ISR_SYSTEM_ERR) {
1779 re_reset(sc);
1780 re_init(sc);
1781 }
1782
5d686fbb
SZ
1783 if (status & RE_ISR_LINKCHG) {
1784 callout_stop(&sc->re_timer);
78195a76 1785 re_tick_serialized(sc);
5d686fbb 1786 }
af51229a
JS
1787 }
1788
000181b2 1789 if (!ifq_is_empty(&ifp->if_snd))
af51229a 1790 (*ifp->if_start)(ifp);
af51229a
JS
1791}
1792
1793static int
8f77d350 1794re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx, int *called_defrag)
af51229a
JS
1795{
1796 struct ifnet *ifp = &sc->arpcom.ac_if;
8f77d350 1797 struct mbuf *m, *m_new = NULL;
af51229a
JS
1798 struct re_dmaload_arg arg;
1799 bus_dmamap_t map;
1800 int error;
1801
8f77d350 1802 *called_defrag = 0;
af51229a
JS
1803 if (sc->re_ldata.re_tx_free <= 4)
1804 return(EFBIG);
1805
8f77d350
JS
1806 m = *m_head;
1807
af51229a
JS
1808 /*
1809 * Set up checksum offload. Note: checksum offload bits must
1810 * appear in all descriptors of a multi-descriptor transmit
1811 * attempt. (This is according to testing done with an 8169
1812 * chip. I'm not sure if this is a requirement or a bug.)
1813 */
1814
1815 arg.re_flags = 0;
1816
8f77d350 1817 if (m->m_pkthdr.csum_flags & CSUM_IP)
af51229a 1818 arg.re_flags |= RE_TDESC_CMD_IPCSUM;
8f77d350 1819 if (m->m_pkthdr.csum_flags & CSUM_TCP)
af51229a 1820 arg.re_flags |= RE_TDESC_CMD_TCPCSUM;
8f77d350 1821 if (m->m_pkthdr.csum_flags & CSUM_UDP)
af51229a
JS
1822 arg.re_flags |= RE_TDESC_CMD_UDPCSUM;
1823
1824 arg.sc = sc;
1825 arg.re_idx = *idx;
1826 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1827 if (arg.re_maxsegs > 4)
1828 arg.re_maxsegs -= 4;
1829 arg.re_ring = sc->re_ldata.re_tx_list;
1830
1831 map = sc->re_ldata.re_tx_dmamap[*idx];
5d686fbb
SZ
1832
1833 /*
1834 * With some of the RealTek chips, using the checksum offload
1835 * support in conjunction with the autopadding feature results
1836 * in the transmission of corrupt frames. For example, if we
1837 * need to send a really small IP fragment that's less than 60
1838 * bytes in size, and IP header checksumming is enabled, the
1839 * resulting ethernet frame that appears on the wire will
1840 * have garbled payload. To work around this, if TX checksum
1841 * offload is enabled, we always manually pad short frames out
1842 * to the minimum ethernet frame size. We do this by pretending
1843 * the mbuf chain has too many fragments so the coalescing code
1844 * below can assemble the packet into a single buffer that's
1845 * padded out to the mininum frame size.
4df76d5d
SZ
1846 *
1847 * Note: this appears unnecessary for TCP, and doing it for TCP
1848 * with PCIe adapters seems to result in bad checksums.
5d686fbb 1849 */
4df76d5d
SZ
1850 if (arg.re_flags && !(arg.re_flags & RE_TDESC_CMD_TCPCSUM) &&
1851 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
5d686fbb
SZ
1852 error = EFBIG;
1853 } else {
1854 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
1855 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1856 }
af51229a
JS
1857
1858 if (error && error != EFBIG) {
1859 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1860 return(ENOBUFS);
1861 }
1862
1863 /* Too many segments to map, coalesce into a single mbuf */
1864
1865 if (error || arg.re_maxsegs == 0) {
8f77d350 1866 m_new = m_defrag_nofree(m, MB_DONTWAIT);
4df76d5d 1867 if (m_new == NULL) {
af51229a 1868 return(1);
4df76d5d 1869 } else {
8f77d350
JS
1870 m = m_new;
1871 *m_head = m;
1872 }
af51229a 1873
5d686fbb
SZ
1874 /*
1875 * Manually pad short frames, and zero the pad space
1876 * to avoid leaking data.
1877 */
1878 if (m_new->m_pkthdr.len < RE_MIN_FRAMELEN) {
1879 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len,
1880 RE_MIN_FRAMELEN - m_new->m_pkthdr.len);
1881 m_new->m_pkthdr.len += RE_MIN_FRAMELEN -
1882 m_new->m_pkthdr.len;
1883 m_new->m_len = m_new->m_pkthdr.len;
1884 }
1885
8f77d350 1886 *called_defrag = 1;
af51229a
JS
1887 arg.sc = sc;
1888 arg.re_idx = *idx;
1889 arg.re_maxsegs = sc->re_ldata.re_tx_free;
1890 arg.re_ring = sc->re_ldata.re_tx_list;
1891
1892 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map,
8f77d350 1893 m, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
af51229a 1894 if (error) {
8f77d350 1895 m_freem(m);
af51229a
JS
1896 if_printf(ifp, "can't map mbuf (error %d)\n", error);
1897 return(EFBIG);
1898 }
1899 }
1900
1901 /*
1902 * Insure that the map for this transmission
1903 * is placed at the array index of the last descriptor
1904 * in this chain.
1905 */
1906 sc->re_ldata.re_tx_dmamap[*idx] =
1907 sc->re_ldata.re_tx_dmamap[arg.re_idx];
1908 sc->re_ldata.re_tx_dmamap[arg.re_idx] = map;
1909
8f77d350 1910 sc->re_ldata.re_tx_mbuf[arg.re_idx] = m;
af51229a
JS
1911 sc->re_ldata.re_tx_free -= arg.re_maxsegs;
1912
1913 /*
1914 * Set up hardware VLAN tagging. Note: vlan tag info must
1915 * appear in the first descriptor of a multi-descriptor
1916 * transmission attempt.
1917 */
1918
8f77d350
JS
1919 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1920 m->m_pkthdr.rcvif != NULL &&
1921 m->m_pkthdr.rcvif->if_type == IFT_L2VLAN) {
af51229a 1922 struct ifvlan *ifv;
8f77d350 1923 ifv = m->m_pkthdr.rcvif->if_softc;
af51229a
JS
1924 if (ifv != NULL)
1925 sc->re_ldata.re_tx_list[*idx].re_vlanctl =
1926 htole32(htobe16(ifv->ifv_tag) | RE_TDESC_VLANCTL_TAG);
1927 }
1928
1929 /* Transfer ownership of packet to the chip. */
1930
1931 sc->re_ldata.re_tx_list[arg.re_idx].re_cmdstat |=
1932 htole32(RE_TDESC_CMD_OWN);
1933 if (*idx != arg.re_idx)
1934 sc->re_ldata.re_tx_list[*idx].re_cmdstat |=
1935 htole32(RE_TDESC_CMD_OWN);
1936
1937 RE_DESC_INC(arg.re_idx);
1938 *idx = arg.re_idx;
1939
1940 return(0);
1941}
1942
1943/*
1944 * Main transmit routine for C+ and gigE NICs.
1945 */
1946
1947static void
1948re_start(struct ifnet *ifp)
1949{
1950 struct re_softc *sc = ifp->if_softc;
d2c71fa0
MD
1951 struct mbuf *m_head;
1952 struct mbuf *m_head2;
2f54d1d2 1953 int called_defrag, idx, need_trans;
af51229a 1954
5d686fbb
SZ
1955 if (!sc->re_link || (ifp->if_flags & IFF_OACTIVE))
1956 return;
1957
af51229a
JS
1958 idx = sc->re_ldata.re_tx_prodidx;
1959
2f54d1d2 1960 need_trans = 0;
af51229a 1961 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
000181b2 1962 m_head = ifq_poll(&ifp->if_snd);
af51229a
JS
1963 if (m_head == NULL)
1964 break;
d2c71fa0
MD
1965 m_head2 = m_head;
1966 if (re_encap(sc, &m_head2, &idx, &called_defrag)) {
1967 /*
1968 * If we could not encapsulate the defragged packet,
1969 * the returned m_head2 is garbage and we must dequeue
1970 * and throw away the original packet.
1971 */
8f77d350 1972 if (called_defrag) {
d2c71fa0
MD
1973 ifq_dequeue(&ifp->if_snd, m_head);
1974 m_freem(m_head);
8f77d350 1975 }
af51229a
JS
1976 ifp->if_flags |= IFF_OACTIVE;
1977 break;
1978 }
8f77d350 1979
d2c71fa0
MD
1980 /*
1981 * Clean out the packet we encapsulated. If we defragged
1982 * the packet the m_head2 is the one that got encapsulated
1983 * and the original must be thrown away. Otherwise m_head2
1984 * *IS* the original.
1985 */
1986 ifq_dequeue(&ifp->if_snd, m_head);
8f77d350 1987 if (called_defrag)
d2c71fa0 1988 m_freem(m_head);
2f54d1d2 1989 need_trans = 1;
af51229a
JS
1990
1991 /*
1992 * If there's a BPF listener, bounce a copy of this frame
1993 * to him.
1994 */
d2c71fa0 1995 BPF_MTAP(ifp, m_head2);
af51229a
JS
1996 }
1997
2f54d1d2 1998 if (!need_trans) {
5d686fbb
SZ
1999 if (RE_TX_MODERATION_IS_ENABLED(sc) &&
2000 sc->re_ldata.re_tx_free != RE_TX_DESC_CNT)
2001 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2f54d1d2
SZ
2002 return;
2003 }
2004
af51229a
JS
2005 /* Flush the TX descriptors */
2006 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
7b4b20cd 2007 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
af51229a
JS
2008
2009 sc->re_ldata.re_tx_prodidx = idx;
2010
2011 /*
2012 * RealTek put the TX poll request register in a different
2013 * location on the 8169 gigE chip. I don't know why.
2014 */
5d686fbb 2015 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
af51229a 2016
5d686fbb
SZ
2017 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2018 /*
2019 * Use the countdown timer for interrupt moderation.
2020 * 'TX done' interrupts are disabled. Instead, we reset the
2021 * countdown timer, which will begin counting until it hits
2022 * the value in the TIMERINT register, and then trigger an
2023 * interrupt. Each time we write to the TIMERCNT register,
2024 * the timer count is reset to 0.
2025 */
2026 CSR_WRITE_4(sc, RE_TIMERCNT, 1);
2027 }
af51229a 2028
af51229a
JS
2029 /*
2030 * Set a timeout in case the chip goes out to lunch.
2031 */
2032 ifp->if_timer = 5;
2033}
2034
2035static void
2036re_init(void *xsc)
2037{
2038 struct re_softc *sc = xsc;
2039 struct ifnet *ifp = &sc->arpcom.ac_if;
2040 struct mii_data *mii;
2041 uint32_t rxcfg = 0;
af51229a 2042
af51229a
JS
2043 mii = device_get_softc(sc->re_miibus);
2044
2045 /*
2046 * Cancel pending I/O and free all RX/TX buffers.
2047 */
2048 re_stop(sc);
2049
2050 /*
2051 * Enable C+ RX and TX mode, as well as VLAN stripping and
2052 * RX checksum offload. We must configure the C+ register
2053 * before all others.
2054 */
2055 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2056 RE_CPLUSCMD_PCI_MRW | RE_CPLUSCMD_VLANSTRIP |
2057 (ifp->if_capenable & IFCAP_RXCSUM ?
2058 RE_CPLUSCMD_RXCSUM_ENB : 0));
2059
2060 /*
2061 * Init our MAC address. Even though the chipset
2062 * documentation doesn't mention it, we need to enter "Config
2063 * register write enable" mode to modify the ID registers.
2064 */
2065 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
5d686fbb
SZ
2066 CSR_WRITE_4(sc, RE_IDR0,
2067 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
7caafb85
SZ
2068 CSR_WRITE_2(sc, RE_IDR4,
2069 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
af51229a
JS
2070 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2071
2072 /*
2073 * For C+ mode, initialize the RX descriptors and mbufs.
2074 */
2075 re_rx_list_init(sc);
2076 re_tx_list_init(sc);
2077
7caafb85
SZ
2078 /*
2079 * Load the addresses of the RX and TX lists into the chip.
2080 */
2081 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2082 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2083 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2084 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2085
2086 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2087 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2088 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2089 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2090
af51229a
JS
2091 /*
2092 * Enable transmit and receive.
2093 */
2094 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2095
2096 /*
2097 * Set the initial TX and RX configuration.
2098 */
2099 if (sc->re_testmode) {
2100 if (sc->re_type == RE_8169)
2101 CSR_WRITE_4(sc, RE_TXCFG,
2102 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2103 else
2104 CSR_WRITE_4(sc, RE_TXCFG,
2105 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2106 } else
2107 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
7caafb85
SZ
2108
2109 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, 16);
2110
af51229a
JS
2111 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2112
2113 /* Set the individual bit to receive frames for this host only. */
2114 rxcfg = CSR_READ_4(sc, RE_RXCFG);
2115 rxcfg |= RE_RXCFG_RX_INDIV;
2116
2117 /* If we want promiscuous mode, set the allframes bit. */
2118 if (ifp->if_flags & IFF_PROMISC) {
2119 rxcfg |= RE_RXCFG_RX_ALLPHYS;
2120 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2121 } else {
2122 rxcfg &= ~RE_RXCFG_RX_ALLPHYS;
2123 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2124 }
2125
2126 /*
2127 * Set capture broadcast bit to capture broadcast frames.
2128 */
2129 if (ifp->if_flags & IFF_BROADCAST) {
2130 rxcfg |= RE_RXCFG_RX_BROAD;
2131 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2132 } else {
2133 rxcfg &= ~RE_RXCFG_RX_BROAD;
2134 CSR_WRITE_4(sc, RE_RXCFG, rxcfg);
2135 }
2136
2137 /*
2138 * Program the multicast filter, if necessary.
2139 */
2140 re_setmulti(sc);
2141
2142#ifdef DEVICE_POLLING
2143 /*
2144 * Disable interrupts if we are polling.
2145 */
2146 if (ifp->if_flags & IFF_POLLING)
2147 CSR_WRITE_2(sc, RE_IMR, 0);
2148 else /* otherwise ... */
2149#endif /* DEVICE_POLLING */
2150 /*
2151 * Enable interrupts.
2152 */
2153 if (sc->re_testmode)
2154 CSR_WRITE_2(sc, RE_IMR, 0);
2155 else
5d686fbb
SZ
2156 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
2157 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
af51229a
JS
2158
2159 /* Set initial TX threshold */
2160 sc->re_txthresh = RE_TX_THRESH_INIT;
2161
2162 /* Start RX/TX process. */
7caafb85
SZ
2163 if (sc->re_flags & RE_F_HASMPC)
2164 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
af51229a
JS
2165#ifdef notdef
2166 /* Enable receiver and transmitter. */
2167 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2168#endif
af51229a 2169
5d686fbb
SZ
2170 if (RE_TX_MODERATION_IS_ENABLED(sc)) {
2171 /*
2172 * Initialize the timer interrupt register so that
2173 * a timer interrupt will be generated once the timer
2174 * reaches a certain number of ticks. The timer is
2175 * reloaded on each transmit. This gives us TX interrupt
2176 * moderation, which dramatically improves TX frame rate.
2177 */
2178 if (sc->re_type == RE_8169)
2179 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0x800);
2180 else
2181 CSR_WRITE_4(sc, RE_TIMERINT, 0x400);
2182 }
af51229a
JS
2183
2184 /*
2185 * For 8169 gigE NICs, set the max allowed RX packet
2186 * size so we can receive jumbo frames.
2187 */
2188 if (sc->re_type == RE_8169)
2189 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2190
2191 if (sc->re_testmode) {
af51229a
JS
2192 return;
2193 }
2194
2195 mii_mediachg(mii);
2196
2197 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2198
2199 ifp->if_flags |= IFF_RUNNING;
2200 ifp->if_flags &= ~IFF_OACTIVE;
2201
5d686fbb 2202 sc->re_link = 0;
af51229a 2203 callout_reset(&sc->re_timer, hz, re_tick, sc);
af51229a
JS
2204}
2205
2206/*
2207 * Set media options.
2208 */
2209static int
2210re_ifmedia_upd(struct ifnet *ifp)
2211{
2212 struct re_softc *sc = ifp->if_softc;
2213 struct mii_data *mii;
2214
2215 mii = device_get_softc(sc->re_miibus);
2216 mii_mediachg(mii);
2217
2218 return(0);
2219}
2220
2221/*
2222 * Report current media status.
2223 */
2224static void
2225re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2226{
2227 struct re_softc *sc = ifp->if_softc;
2228 struct mii_data *mii;
2229
2230 mii = device_get_softc(sc->re_miibus);
2231
2232 mii_pollstat(mii);
2233 ifmr->ifm_active = mii->mii_media_active;
2234 ifmr->ifm_status = mii->mii_media_status;
2235}
2236
2237static int
2238re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2239{
2240 struct re_softc *sc = ifp->if_softc;
2241 struct ifreq *ifr = (struct ifreq *) data;
2242 struct mii_data *mii;
f0ee8b5b 2243 int error = 0;
af51229a 2244
af51229a
JS
2245 switch(command) {
2246 case SIOCSIFMTU:
2247 if (ifr->ifr_mtu > RE_JUMBO_MTU)
2248 error = EINVAL;
2249 ifp->if_mtu = ifr->ifr_mtu;
2250 break;
2251 case SIOCSIFFLAGS:
2252 if (ifp->if_flags & IFF_UP)
2253 re_init(sc);
2254 else if (ifp->if_flags & IFF_RUNNING)
5d686fbb 2255 re_stop(sc);
af51229a
JS
2256 break;
2257 case SIOCADDMULTI:
2258 case SIOCDELMULTI:
2259 re_setmulti(sc);
2260 error = 0;
2261 break;
2262 case SIOCGIFMEDIA:
2263 case SIOCSIFMEDIA:
2264 mii = device_get_softc(sc->re_miibus);
2265 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2266 break;
2267 case SIOCSIFCAP:
9c095379 2268 ifp->if_capenable &= ~(IFCAP_HWCSUM);
af51229a 2269 ifp->if_capenable |=
9c095379 2270 ifr->ifr_reqcap & (IFCAP_HWCSUM);
af51229a
JS
2271 if (ifp->if_capenable & IFCAP_TXCSUM)
2272 ifp->if_hwassist = RE_CSUM_FEATURES;
2273 else
2274 ifp->if_hwassist = 0;
2275 if (ifp->if_flags & IFF_RUNNING)
2276 re_init(sc);
2277 break;
2278 default:
2279 error = ether_ioctl(ifp, command, data);
2280 break;
2281 }
af51229a
JS
2282 return(error);
2283}
2284
2285static void
2286re_watchdog(struct ifnet *ifp)
2287{
2288 struct re_softc *sc = ifp->if_softc;
af51229a 2289
af51229a 2290 if_printf(ifp, "watchdog timeout\n");
f0ee8b5b 2291
af51229a
JS
2292 ifp->if_oerrors++;
2293
2294 re_txeof(sc);
2295 re_rxeof(sc);
2296
2297 re_init(sc);
2298
2f54d1d2
SZ
2299 if (!ifq_is_empty(&ifp->if_snd))
2300 ifp->if_start(ifp);
af51229a
JS
2301}
2302
2303/*
2304 * Stop the adapter and free any mbufs allocated to the
2305 * RX and TX lists.
2306 */
2307static void
2308re_stop(struct re_softc *sc)
2309{
2310 struct ifnet *ifp = &sc->arpcom.ac_if;
f0ee8b5b
JS
2311 int i;
2312
af51229a
JS
2313 ifp->if_timer = 0;
2314 callout_stop(&sc->re_timer);
2315
2316 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
af51229a
JS
2317
2318 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2319 CSR_WRITE_2(sc, RE_IMR, 0x0000);
5d686fbb 2320 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
af51229a
JS
2321
2322 if (sc->re_head != NULL) {
2323 m_freem(sc->re_head);
2324 sc->re_head = sc->re_tail = NULL;
2325 }
2326
2327 /* Free the TX list buffers. */
2328 for (i = 0; i < RE_TX_DESC_CNT; i++) {
2329 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2330 bus_dmamap_unload(sc->re_ldata.re_mtag,
2331 sc->re_ldata.re_tx_dmamap[i]);
2332 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2333 sc->re_ldata.re_tx_mbuf[i] = NULL;
2334 }
2335 }
2336
2337 /* Free the RX list buffers. */
2338 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2339 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2340 bus_dmamap_unload(sc->re_ldata.re_mtag,
2341 sc->re_ldata.re_rx_dmamap[i]);
2342 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2343 sc->re_ldata.re_rx_mbuf[i] = NULL;
2344 }
2345 }
af51229a
JS
2346}
2347
2348/*
2349 * Device suspend routine. Stop the interface and save some PCI
2350 * settings in case the BIOS doesn't restore them properly on
2351 * resume.
2352 */
2353static int
2354re_suspend(device_t dev)
2355{
2356#ifndef BURN_BRIDGES
2357 int i;
2358#endif
2359 struct re_softc *sc = device_get_softc(dev);
2360
2361 re_stop(sc);
2362
2363#ifndef BURN_BRIDGES
2364 for (i = 0; i < 5; i++)
2365 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2366 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2367 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2368 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2369 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2370#endif
2371
2372 sc->suspended = 1;
2373
2374 return (0);
2375}
2376
2377/*
2378 * Device resume routine. Restore some PCI settings in case the BIOS
2379 * doesn't, re-enable busmastering, and restart the interface if
2380 * appropriate.
2381 */
2382static int
2383re_resume(device_t dev)
2384{
2385 struct re_softc *sc = device_get_softc(dev);
2386 struct ifnet *ifp = &sc->arpcom.ac_if;
2387#ifndef BURN_BRIDGES
2388 int i;
2389#endif
2390
2391#ifndef BURN_BRIDGES
2392 /* better way to do this? */
2393 for (i = 0; i < 5; i++)
2394 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2395 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2396 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2397 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2398 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2399
2400 /* reenable busmastering */
2401 pci_enable_busmaster(dev);
ecd80f47 2402 pci_enable_io(dev, SYS_RES_IOPORT);
af51229a
JS
2403#endif
2404
2405 /* reinitialize interface if necessary */
2406 if (ifp->if_flags & IFF_UP)
2407 re_init(sc);
2408
2409 sc->suspended = 0;
2410
2411 return (0);
2412}
2413
2414/*
2415 * Stop all chip I/O so that the kernel's probe routines don't
2416 * get confused by errant DMAs when rebooting.
2417 */
2418static void
2419re_shutdown(device_t dev)
2420{
2421 struct re_softc *sc = device_get_softc(dev);
5d686fbb 2422 struct ifnet *ifp = &sc->arpcom.ac_if;
af51229a 2423
5d686fbb 2424 lwkt_serialize_enter(ifp->if_serializer);
af51229a 2425 re_stop(sc);
5d686fbb
SZ
2426 lwkt_serialize_exit(ifp->if_serializer);
2427}
2428
2429static int
2430re_sysctl_tx_moderation(SYSCTL_HANDLER_ARGS)
2431{
2432 struct re_softc *sc = arg1;
2433 struct ifnet *ifp = &sc->arpcom.ac_if;
2434 int error = 0, mod, mod_old;
2435
2436 lwkt_serialize_enter(ifp->if_serializer);
2437
2438 mod_old = mod = RE_TX_MODERATION_IS_ENABLED(sc);
2439
2440 error = sysctl_handle_int(oidp, &mod, 0, req);
2441 if (error || req->newptr == NULL || mod == mod_old)
2442 goto back;
2443 if (mod != 0 && mod != 1) {
2444 error = EINVAL;
2445 goto back;
2446 }
2447
2448 if (mod)
2449 RE_ENABLE_TX_MODERATION(sc);
2450 else
2451 RE_DISABLE_TX_MODERATION(sc);
2452
7caafb85
SZ
2453 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP)) == (IFF_RUNNING | IFF_UP))
2454 re_init(sc);
5d686fbb
SZ
2455back:
2456 lwkt_serialize_exit(ifp->if_serializer);
2457 return error;
af51229a 2458}