bge: In bge_stop, don't isolate PHY; it is unnecessary
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
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1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
011c0f93 33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
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34 */
35
36/*
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
41 */
42
43/*
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
54 * into the driver.
55 *
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58 *
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
62 *
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
65 *
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
70 * ring.
71 */
72
315fe0ee 73#include "opt_polling.h"
a7db2caa 74
984263bc 75#include <sys/param.h>
62be1357 76#include <sys/bus.h>
20c9a969 77#include <sys/endian.h>
62be1357 78#include <sys/kernel.h>
6b880771 79#include <sys/ktr.h>
9db4b353 80#include <sys/interrupt.h>
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81#include <sys/mbuf.h>
82#include <sys/malloc.h>
984263bc 83#include <sys/queue.h>
62be1357 84#include <sys/rman.h>
16dca0df 85#include <sys/serialize.h>
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86#include <sys/socket.h>
87#include <sys/sockio.h>
055d06f0 88#include <sys/sysctl.h>
984263bc 89
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90#include <net/bpf.h>
91#include <net/ethernet.h>
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92#include <net/if.h>
93#include <net/if_arp.h>
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94#include <net/if_dl.h>
95#include <net/if_media.h>
984263bc 96#include <net/if_types.h>
62be1357 97#include <net/ifq_var.h>
1f2de5d4 98#include <net/vlan/if_vlan_var.h>
b637f170 99#include <net/vlan/if_vlan_ether.h>
984263bc 100
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101#include <dev/netif/mii_layer/mii.h>
102#include <dev/netif/mii_layer/miivar.h>
1f2de5d4 103#include <dev/netif/mii_layer/brgphyreg.h>
984263bc 104
f952ab63 105#include <bus/pci/pcidevs.h>
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106#include <bus/pci/pcireg.h>
107#include <bus/pci/pcivar.h>
984263bc 108
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109#include <dev/netif/bge/if_bgereg.h>
110
111/* "device miibus" required. See GENERIC if you get errors here. */
112#include "miibus_if.h"
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113
114#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
cb623c48 115#define BGE_MIN_FRAME 60
984263bc 116
d265721a 117static const struct bge_type bge_devs[] = {
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118 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119 "3COM 3C996 Gigabit Ethernet" },
120
f952ab63 121 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
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122 "Alteon BCM5700 Gigabit Ethernet" },
123 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124 "Alteon BCM5701 Gigabit Ethernet" },
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125
126 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127 "Altima AC1000 Gigabit Ethernet" },
128 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129 "Altima AC1002 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131 "Altima AC9100 Gigabit Ethernet" },
132
133 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134 "Apple BCM5701 Gigabit Ethernet" },
135
f952ab63 136 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
984263bc 137 "Broadcom BCM5700 Gigabit Ethernet" },
f952ab63 138 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
984263bc 139 "Broadcom BCM5701 Gigabit Ethernet" },
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140 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141 "Broadcom BCM5702 Gigabit Ethernet" },
f952ab63 142 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
984263bc 143 "Broadcom BCM5702X Gigabit Ethernet" },
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144 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145 "Broadcom BCM5702 Gigabit Ethernet" },
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146 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147 "Broadcom BCM5703 Gigabit Ethernet" },
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148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149 "Broadcom BCM5703X Gigabit Ethernet" },
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150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151 "Broadcom BCM5703 Gigabit Ethernet" },
f952ab63 152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
984263bc 153 "Broadcom BCM5704C Dual Gigabit Ethernet" },
f952ab63 154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
984263bc 155 "Broadcom BCM5704S Dual Gigabit Ethernet" },
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156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157 "Broadcom BCM5704S Dual Gigabit Ethernet" },
f952ab63 158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
7e40b8c5 159 "Broadcom BCM5705 Gigabit Ethernet" },
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160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161 "Broadcom BCM5705F Gigabit Ethernet" },
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162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163 "Broadcom BCM5705K Gigabit Ethernet" },
f952ab63 164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
7e40b8c5 165 "Broadcom BCM5705M Gigabit Ethernet" },
9a6ee7e2 166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
7e40b8c5 167 "Broadcom BCM5705M Gigabit Ethernet" },
92decf65 168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
9a6ee7e2 169 "Broadcom BCM5714C Gigabit Ethernet" },
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170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171 "Broadcom BCM5714S Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173 "Broadcom BCM5715 Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175 "Broadcom BCM5715S Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177 "Broadcom BCM5720 Gigabit Ethernet" },
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178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179 "Broadcom BCM5721 Gigabit Ethernet" },
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180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181 "Broadcom BCM5722 Gigabit Ethernet" },
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182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183 "Broadcom BCM5723 Gigabit Ethernet" },
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184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185 "Broadcom BCM5750 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187 "Broadcom BCM5750M Gigabit Ethernet" },
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188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189 "Broadcom BCM5751 Gigabit Ethernet" },
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190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191 "Broadcom BCM5751F Gigabit Ethernet" },
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192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193 "Broadcom BCM5751M Gigabit Ethernet" },
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194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195 "Broadcom BCM5752 Gigabit Ethernet" },
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196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197 "Broadcom BCM5752M Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199 "Broadcom BCM5753 Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201 "Broadcom BCM5753F Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203 "Broadcom BCM5753M Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205 "Broadcom BCM5754 Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207 "Broadcom BCM5754M Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209 "Broadcom BCM5755 Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211 "Broadcom BCM5755M Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213 "Broadcom BCM5756 Gigabit Ethernet" },
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214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215 "Broadcom BCM5761 Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217 "Broadcom BCM5761E Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219 "Broadcom BCM5761S Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221 "Broadcom BCM5761SE Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223 "Broadcom BCM5764 Gigabit Ethernet" },
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224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225 "Broadcom BCM5780 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227 "Broadcom BCM5780S Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229 "Broadcom BCM5781 Gigabit Ethernet" },
f952ab63 230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
7e40b8c5 231 "Broadcom BCM5782 Gigabit Ethernet" },
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232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233 "Broadcom BCM5784 Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235 "Broadcom BCM5785F Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237 "Broadcom BCM5785G Gigabit Ethernet" },
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238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239 "Broadcom BCM5786 Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241 "Broadcom BCM5787 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243 "Broadcom BCM5787F Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245 "Broadcom BCM5787M Gigabit Ethernet" },
9a6ee7e2 246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
f952ab63 247 "Broadcom BCM5788 Gigabit Ethernet" },
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248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249 "Broadcom BCM5789 Gigabit Ethernet" },
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250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251 "Broadcom BCM5901 Fast Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253 "Broadcom BCM5901A2 Fast Ethernet" },
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254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255 "Broadcom BCM5903M Fast Ethernet" },
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256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257 "Broadcom BCM5906 Fast Ethernet"},
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259 "Broadcom BCM5906M Fast Ethernet"},
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260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261 "Broadcom BCM57760 Gigabit Ethernet"},
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263 "Broadcom BCM57780 Gigabit Ethernet"},
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265 "Broadcom BCM57788 Gigabit Ethernet"},
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267 "Broadcom BCM57790 Gigabit Ethernet"},
f952ab63 268 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
984263bc 269 "SysKonnect Gigabit Ethernet" },
0ecb11d7 270
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271 { 0, 0, NULL }
272};
273
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274#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
275#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
f47afe1a 279#define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
0ecb11d7 280
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281typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
282
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283static int bge_probe(device_t);
284static int bge_attach(device_t);
285static int bge_detach(device_t);
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286static void bge_txeof(struct bge_softc *);
287static void bge_rxeof(struct bge_softc *);
288
289static void bge_tick(void *);
290static void bge_stats_update(struct bge_softc *);
291static void bge_stats_update_regs(struct bge_softc *);
4a607ed6 292static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
33c39a69 293
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294#ifdef DEVICE_POLLING
295static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
296#endif
33c39a69 297static void bge_intr(void *);
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298static void bge_enable_intr(struct bge_softc *);
299static void bge_disable_intr(struct bge_softc *);
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300static void bge_start(struct ifnet *);
301static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
302static void bge_init(void *);
303static void bge_stop(struct bge_softc *);
304static void bge_watchdog(struct ifnet *);
305static void bge_shutdown(device_t);
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306static int bge_suspend(device_t);
307static int bge_resume(device_t);
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308static int bge_ifmedia_upd(struct ifnet *);
309static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
310
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311static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
312static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
313
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314static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
315static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
316
33c39a69 317static void bge_setmulti(struct bge_softc *);
6439b28a 318static void bge_setpromisc(struct bge_softc *);
33c39a69 319
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320static int bge_alloc_jumbo_mem(struct bge_softc *);
321static void bge_free_jumbo_mem(struct bge_softc *);
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322static struct bge_jslot
323 *bge_jalloc(struct bge_softc *);
324static void bge_jfree(void *);
325static void bge_jref(void *);
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326static int bge_newbuf_std(struct bge_softc *, int, int);
327static int bge_newbuf_jumbo(struct bge_softc *, int, int);
328static void bge_setup_rxdesc_std(struct bge_softc *, int);
329static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
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330static int bge_init_rx_ring_std(struct bge_softc *);
331static void bge_free_rx_ring_std(struct bge_softc *);
332static int bge_init_rx_ring_jumbo(struct bge_softc *);
333static void bge_free_rx_ring_jumbo(struct bge_softc *);
334static void bge_free_tx_ring(struct bge_softc *);
335static int bge_init_tx_ring(struct bge_softc *);
336
337static int bge_chipinit(struct bge_softc *);
338static int bge_blockinit(struct bge_softc *);
984263bc 339
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340static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
341static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
984263bc 342#ifdef notdef
33c39a69 343static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
984263bc 344#endif
33c39a69 345static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
0ecb11d7 346static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
591dfc77 347static void bge_writembx(struct bge_softc *, int, int);
984263bc 348
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349static int bge_miibus_readreg(device_t, int, int);
350static int bge_miibus_writereg(device_t, int, int, int);
351static void bge_miibus_statchg(device_t);
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352static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
353static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
354static void bge_copper_link_upd(struct bge_softc *, uint32_t);
984263bc 355
33c39a69 356static void bge_reset(struct bge_softc *);
984263bc 357
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358static int bge_dma_alloc(struct bge_softc *);
359static void bge_dma_free(struct bge_softc *);
360static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
361 bus_dma_tag_t *, bus_dmamap_t *,
362 void **, bus_addr_t *);
363static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
364
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365static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
366static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
367static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
368static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
369
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370static void bge_coal_change(struct bge_softc *);
371static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
372static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
373static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
374static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
375static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
376
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377/*
378 * Set following tunable to 1 for some IBM blade servers with the DNLK
379 * switch module. Auto negotiation is broken for those configurations.
380 */
381static int bge_fake_autoneg = 0;
382TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
383
055d06f0 384/* Interrupt moderation control variables. */
61b4fa0a 385static int bge_rx_coal_ticks = 100; /* usec */
83015dae 386static int bge_tx_coal_ticks = 1023; /* usec */
b02a2d90 387static int bge_rx_max_coal_bds = 80;
77dee542 388static int bge_tx_max_coal_bds = 128;
055d06f0
SZ
389
390TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
391TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
392TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
393TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
394
6b880771
SZ
395#if !defined(KTR_IF_BGE)
396#define KTR_IF_BGE KTR_ALL
397#endif
398KTR_INFO_MASTER(if_bge);
5bf48697
AE
399KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
400KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
401KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
6b880771
SZ
402#define logif(name) KTR_LOG(if_bge_ ## name)
403
984263bc
MD
404static device_method_t bge_methods[] = {
405 /* Device interface */
406 DEVMETHOD(device_probe, bge_probe),
407 DEVMETHOD(device_attach, bge_attach),
408 DEVMETHOD(device_detach, bge_detach),
409 DEVMETHOD(device_shutdown, bge_shutdown),
aa65409c
SZ
410 DEVMETHOD(device_suspend, bge_suspend),
411 DEVMETHOD(device_resume, bge_resume),
984263bc
MD
412
413 /* bus interface */
414 DEVMETHOD(bus_print_child, bus_generic_print_child),
415 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
416
417 /* MII interface */
418 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
419 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
420 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
421
422 { 0, 0 }
423};
424
33c39a69 425static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
984263bc
MD
426static devclass_t bge_devclass;
427
32832096 428DECLARE_DUMMY_MODULE(if_bge);
aa2b9d05
SW
429DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
430DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
984263bc 431
33c39a69
JS
432static uint32_t
433bge_readmem_ind(struct bge_softc *sc, uint32_t off)
984263bc 434{
33c39a69 435 device_t dev = sc->bge_dev;
0ecb11d7 436 uint32_t val;
984263bc
MD
437
438 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
0ecb11d7
SZ
439 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
440 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
441 return (val);
984263bc
MD
442}
443
444static void
33c39a69 445bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 446{
33c39a69 447 device_t dev = sc->bge_dev;
984263bc
MD
448
449 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
450 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
0ecb11d7 451 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
984263bc
MD
452}
453
454#ifdef notdef
33c39a69
JS
455static uint32_t
456bge_readreg_ind(struct bge_softc *sc, uin32_t off)
984263bc 457{
33c39a69 458 device_t dev = sc->bge_dev;
984263bc
MD
459
460 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
461 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
462}
463#endif
464
465static void
33c39a69 466bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
984263bc 467{
33c39a69 468 device_t dev = sc->bge_dev;
984263bc
MD
469
470 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
471 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
984263bc
MD
472}
473
0ecb11d7
SZ
474static void
475bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
476{
477 CSR_WRITE_4(sc, off, val);
478}
479
591dfc77
SZ
480static void
481bge_writembx(struct bge_softc *sc, int off, int val)
482{
483 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
484 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
485
486 CSR_WRITE_4(sc, off, val);
487}
488
489static uint8_t
490bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
491{
492 uint32_t access, byte = 0;
493 int i;
494
495 /* Lock. */
496 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
497 for (i = 0; i < 8000; i++) {
498 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
499 break;
500 DELAY(20);
501 }
502 if (i == 8000)
503 return (1);
504
505 /* Enable access. */
506 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
507 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
508
509 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
510 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
511 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
512 DELAY(10);
513 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
514 DELAY(10);
515 break;
516 }
517 }
518
519 if (i == BGE_TIMEOUT * 10) {
520 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
521 return (1);
522 }
523
524 /* Get result. */
525 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
526
527 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
528
529 /* Disable access. */
530 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
531
532 /* Unlock. */
533 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
534 CSR_READ_4(sc, BGE_NVRAM_SWARB);
535
536 return (0);
537}
538
539/*
540 * Read a sequence of bytes from NVRAM.
541 */
542static int
543bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
544{
545 int err = 0, i;
546 uint8_t byte = 0;
547
548 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
549 return (1);
550
551 for (i = 0; i < cnt; i++) {
552 err = bge_nvram_getbyte(sc, off + i, &byte);
553 if (err)
554 break;
555 *(dest + i) = byte;
556 }
557
558 return (err ? 1 : 0);
559}
560
984263bc
MD
561/*
562 * Read a byte of data stored in the EEPROM at address 'addr.' The
563 * BCM570x supports both the traditional bitbang interface and an
564 * auto access interface for reading the EEPROM. We use the auto
565 * access method.
566 */
33c39a69
JS
567static uint8_t
568bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
984263bc
MD
569{
570 int i;
33c39a69 571 uint32_t byte = 0;
984263bc
MD
572
573 /*
574 * Enable use of auto EEPROM access so we can avoid
575 * having to use the bitbang method.
576 */
577 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
578
579 /* Reset the EEPROM, load the clock period. */
580 CSR_WRITE_4(sc, BGE_EE_ADDR,
581 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
582 DELAY(20);
583
584 /* Issue the read EEPROM command. */
585 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
586
587 /* Wait for completion */
588 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
589 DELAY(10);
590 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
591 break;
592 }
593
594 if (i == BGE_TIMEOUT) {
c6fd6f3b 595 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
7b47d9c2 596 return(1);
984263bc
MD
597 }
598
599 /* Get result. */
600 byte = CSR_READ_4(sc, BGE_EE_DATA);
601
602 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
603
604 return(0);
605}
606
607/*
608 * Read a sequence of bytes from the EEPROM.
609 */
610static int
33c39a69 611bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
984263bc 612{
33c39a69
JS
613 size_t i;
614 int err;
615 uint8_t byte;
984263bc 616
33c39a69 617 for (byte = 0, err = 0, i = 0; i < len; i++) {
984263bc
MD
618 err = bge_eeprom_getbyte(sc, off + i, &byte);
619 if (err)
620 break;
621 *(dest + i) = byte;
622 }
623
624 return(err ? 1 : 0);
625}
626
627static int
33c39a69 628bge_miibus_readreg(device_t dev, int phy, int reg)
984263bc 629{
f7a1f3ba
SZ
630 struct bge_softc *sc = device_get_softc(dev);
631 struct ifnet *ifp = &sc->arpcom.ac_if;
33c39a69 632 uint32_t val, autopoll;
984263bc
MD
633 int i;
634
7e40b8c5
HP
635 /*
636 * Broadcom's own driver always assumes the internal
637 * PHY is at GMII address 1. On some chips, the PHY responds
638 * to accesses at all addresses, which could cause us to
639 * bogusly attach the PHY 32 times at probe type. Always
640 * restricting the lookup to address 1 is simpler than
641 * trying to figure out which chips revisions should be
642 * special-cased.
643 */
984263bc 644 if (phy != 1)
7e40b8c5 645 return(0);
984263bc
MD
646
647 /* Reading with autopolling on may trigger PCI errors */
648 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
649 if (autopoll & BGE_MIMODE_AUTOPOLL) {
650 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
651 DELAY(40);
652 }
653
654 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
655 BGE_MIPHY(phy)|BGE_MIREG(reg));
656
657 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba 658 DELAY(10);
984263bc
MD
659 val = CSR_READ_4(sc, BGE_MI_COMM);
660 if (!(val & BGE_MICOMM_BUSY))
661 break;
662 }
663
664 if (i == BGE_TIMEOUT) {
f7a1f3ba
SZ
665 if_printf(ifp, "PHY read timed out "
666 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
984263bc
MD
667 val = 0;
668 goto done;
669 }
670
f7a1f3ba 671 DELAY(5);
984263bc
MD
672 val = CSR_READ_4(sc, BGE_MI_COMM);
673
674done:
675 if (autopoll & BGE_MIMODE_AUTOPOLL) {
676 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
677 DELAY(40);
678 }
679
680 if (val & BGE_MICOMM_READFAIL)
681 return(0);
682
683 return(val & 0xFFFF);
684}
685
686static int
33c39a69 687bge_miibus_writereg(device_t dev, int phy, int reg, int val)
984263bc 688{
f7a1f3ba 689 struct bge_softc *sc = device_get_softc(dev);
33c39a69 690 uint32_t autopoll;
984263bc
MD
691 int i;
692
f7a1f3ba
SZ
693 /*
694 * See the related comment in bge_miibus_readreg()
695 */
696 if (phy != 1)
697 return(0);
984263bc 698
591dfc77
SZ
699 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701 return(0);
702
984263bc
MD
703 /* Reading with autopolling on may trigger PCI errors */
704 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
705 if (autopoll & BGE_MIMODE_AUTOPOLL) {
706 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
707 DELAY(40);
708 }
709
710 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
711 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
712
713 for (i = 0; i < BGE_TIMEOUT; i++) {
f7a1f3ba
SZ
714 DELAY(10);
715 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716 DELAY(5);
717 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
984263bc 718 break;
f7a1f3ba 719 }
984263bc
MD
720 }
721
722 if (autopoll & BGE_MIMODE_AUTOPOLL) {
723 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
724 DELAY(40);
725 }
726
727 if (i == BGE_TIMEOUT) {
f7a1f3ba
SZ
728 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
729 "(phy %d, reg %d, val %d)\n", phy, reg, val);
984263bc
MD
730 return(0);
731 }
732
733 return(0);
734}
735
736static void
33c39a69 737bge_miibus_statchg(device_t dev)
984263bc
MD
738{
739 struct bge_softc *sc;
740 struct mii_data *mii;
741
742 sc = device_get_softc(dev);
743 mii = device_get_softc(sc->bge_miibus);
744
745 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
7f259627 746 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
984263bc
MD
747 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
748 } else {
749 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
750 }
751
752 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
753 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
754 } else {
755 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
756 }
984263bc
MD
757}
758
759/*
984263bc
MD
760 * Memory management for jumbo frames.
761 */
984263bc 762static int
33c39a69 763bge_alloc_jumbo_mem(struct bge_softc *sc)
984263bc 764{
20c9a969 765 struct ifnet *ifp = &sc->arpcom.ac_if;
2aa9b12f 766 struct bge_jslot *entry;
20c9a969
SZ
767 uint8_t *ptr;
768 bus_addr_t paddr;
769 int i, error;
984263bc 770
20c9a969
SZ
771 /*
772 * Create tag for jumbo mbufs.
773 * This is really a bit of a kludge. We allocate a special
774 * jumbo buffer pool which (thanks to the way our DMA
775 * memory allocation works) will consist of contiguous
776 * pages. This means that even though a jumbo buffer might
777 * be larger than a page size, we don't really need to
778 * map it into more than one DMA segment. However, the
779 * default mbuf tag will result in multi-segment mappings,
780 * so we have to create a special jumbo mbuf tag that
781 * lets us get away with mapping the jumbo buffers as
782 * a single segment. I think eventually the driver should
783 * be changed so that it uses ordinary mbufs and cluster
784 * buffers, i.e. jumbo frames can span multiple DMA
785 * descriptors. But that's a project for another day.
786 */
984263bc 787
20c9a969
SZ
788 /*
789 * Create DMA stuffs for jumbo RX ring.
790 */
791 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
792 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
793 &sc->bge_cdata.bge_rx_jumbo_ring_map,
da44240f 794 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
20c9a969
SZ
795 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
796 if (error) {
797 if_printf(ifp, "could not create jumbo RX ring\n");
798 return error;
799 }
800
801 /*
802 * Create DMA stuffs for jumbo buffer block.
803 */
804 error = bge_dma_block_alloc(sc, BGE_JMEM,
805 &sc->bge_cdata.bge_jumbo_tag,
806 &sc->bge_cdata.bge_jumbo_map,
807 (void **)&sc->bge_ldata.bge_jumbo_buf,
808 &paddr);
809 if (error) {
810 if_printf(ifp, "could not create jumbo buffer\n");
811 return error;
984263bc
MD
812 }
813
814 SLIST_INIT(&sc->bge_jfree_listhead);
984263bc
MD
815
816 /*
817 * Now divide it up into 9K pieces and save the addresses
818 * in an array. Note that we play an evil trick here by using
819 * the first few bytes in the buffer to hold the the address
820 * of the softc structure for this interface. This is because
821 * bge_jfree() needs it, but it is called by the mbuf management
822 * code which will not pass it to us explicitly.
823 */
20c9a969 824 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
2aa9b12f
JS
825 entry = &sc->bge_cdata.bge_jslots[i];
826 entry->bge_sc = sc;
827 entry->bge_buf = ptr;
20c9a969 828 entry->bge_paddr = paddr;
2aa9b12f
JS
829 entry->bge_inuse = 0;
830 entry->bge_slot = i;
831 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
20c9a969 832
2aa9b12f 833 ptr += BGE_JLEN;
20c9a969 834 paddr += BGE_JLEN;
984263bc 835 }
20c9a969 836 return 0;
984263bc
MD
837}
838
839static void
33c39a69 840bge_free_jumbo_mem(struct bge_softc *sc)
984263bc 841{
20c9a969
SZ
842 /* Destroy jumbo RX ring. */
843 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
844 sc->bge_cdata.bge_rx_jumbo_ring_map,
845 sc->bge_ldata.bge_rx_jumbo_ring);
846
847 /* Destroy jumbo buffer block. */
848 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
849 sc->bge_cdata.bge_jumbo_map,
850 sc->bge_ldata.bge_jumbo_buf);
984263bc
MD
851}
852
853/*
854 * Allocate a jumbo buffer.
855 */
2aa9b12f 856static struct bge_jslot *
33c39a69 857bge_jalloc(struct bge_softc *sc)
984263bc 858{
2aa9b12f 859 struct bge_jslot *entry;
33c39a69 860
16dca0df 861 lwkt_serialize_enter(&sc->bge_jslot_serializer);
984263bc 862 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
16dca0df
MD
863 if (entry) {
864 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
865 entry->bge_inuse = 1;
866 } else {
c6fd6f3b 867 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
984263bc 868 }
16dca0df 869 lwkt_serialize_exit(&sc->bge_jslot_serializer);
2aa9b12f 870 return(entry);
984263bc
MD
871}
872
873/*
874 * Adjust usage count on a jumbo buffer.
875 */
876static void
2aa9b12f 877bge_jref(void *arg)
984263bc 878{
2aa9b12f
JS
879 struct bge_jslot *entry = (struct bge_jslot *)arg;
880 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
881
882 if (sc == NULL)
883 panic("bge_jref: can't find softc pointer!");
884
16dca0df 885 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc
MD
886 panic("bge_jref: asked to reference buffer "
887 "that we don't manage!");
16dca0df 888 } else if (entry->bge_inuse == 0) {
984263bc 889 panic("bge_jref: buffer already free!");
16dca0df
MD
890 } else {
891 atomic_add_int(&entry->bge_inuse, 1);
892 }
984263bc
MD
893}
894
895/*
896 * Release a jumbo buffer.
897 */
898static void
2aa9b12f 899bge_jfree(void *arg)
984263bc 900{
2aa9b12f
JS
901 struct bge_jslot *entry = (struct bge_jslot *)arg;
902 struct bge_softc *sc = entry->bge_sc;
984263bc
MD
903
904 if (sc == NULL)
905 panic("bge_jfree: can't find softc pointer!");
906
16dca0df 907 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
984263bc 908 panic("bge_jfree: asked to free buffer that we don't manage!");
16dca0df 909 } else if (entry->bge_inuse == 0) {
984263bc 910 panic("bge_jfree: buffer already free!");
16dca0df
MD
911 } else {
912 /*
913 * Possible MP race to 0, use the serializer. The atomic insn
914 * is still needed for races against bge_jref().
915 */
916 lwkt_serialize_enter(&sc->bge_jslot_serializer);
917 atomic_subtract_int(&entry->bge_inuse, 1);
918 if (entry->bge_inuse == 0) {
919 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
920 entry, jslot_link);
921 }
922 lwkt_serialize_exit(&sc->bge_jslot_serializer);
923 }
984263bc
MD
924}
925
926
927/*
928 * Intialize a standard receive ring descriptor.
929 */
930static int
1436f9a0 931bge_newbuf_std(struct bge_softc *sc, int i, int init)
984263bc 932{
33c39a69 933 struct mbuf *m_new = NULL;
20c9a969 934 bus_dma_segment_t seg;
1436f9a0 935 bus_dmamap_t map;
2de621e9 936 int error, nsegs;
984263bc 937
1436f9a0
SZ
938 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
939 if (m_new == NULL)
940 return ENOBUFS;
20c9a969 941 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
984263bc 942
0ecb11d7 943 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
984263bc 944 m_adj(m_new, ETHER_ALIGN);
20c9a969 945
2de621e9
SZ
946 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
947 sc->bge_cdata.bge_rx_tmpmap, m_new,
948 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
949 if (error) {
1436f9a0 950 m_freem(m_new);
2de621e9 951 return error;
20c9a969
SZ
952 }
953
1436f9a0
SZ
954 if (!init) {
955 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
956 sc->bge_cdata.bge_rx_std_dmamap[i],
957 BUS_DMASYNC_POSTREAD);
958 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
959 sc->bge_cdata.bge_rx_std_dmamap[i]);
960 }
20c9a969 961
1436f9a0
SZ
962 map = sc->bge_cdata.bge_rx_tmpmap;
963 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
964 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
965
966 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
2de621e9 967 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1436f9a0
SZ
968
969 bge_setup_rxdesc_std(sc, i);
20c9a969 970 return 0;
984263bc
MD
971}
972
1436f9a0
SZ
973static void
974bge_setup_rxdesc_std(struct bge_softc *sc, int i)
975{
976 struct bge_rxchain *rc;
977 struct bge_rx_bd *r;
978
979 rc = &sc->bge_cdata.bge_rx_std_chain[i];
980 r = &sc->bge_ldata.bge_rx_std_ring[i];
981
982 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
983 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
984 r->bge_len = rc->bge_mbuf->m_len;
985 r->bge_idx = i;
986 r->bge_flags = BGE_RXBDFLAG_END;
987}
988
984263bc
MD
989/*
990 * Initialize a jumbo receive ring descriptor. This allocates
991 * a jumbo buffer from the pool managed internally by the driver.
992 */
993static int
1436f9a0 994bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
984263bc
MD
995{
996 struct mbuf *m_new = NULL;
20c9a969 997 struct bge_jslot *buf;
20c9a969 998 bus_addr_t paddr;
984263bc 999
1436f9a0
SZ
1000 /* Allocate the mbuf. */
1001 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1002 if (m_new == NULL)
1003 return ENOBUFS;
2aa9b12f 1004
1436f9a0
SZ
1005 /* Allocate the jumbo buffer */
1006 buf = bge_jalloc(sc);
1007 if (buf == NULL) {
1008 m_freem(m_new);
1009 return ENOBUFS;
984263bc 1010 }
1436f9a0
SZ
1011
1012 /* Attach the buffer to the mbuf. */
1013 m_new->m_ext.ext_arg = buf;
1014 m_new->m_ext.ext_buf = buf->bge_buf;
1015 m_new->m_ext.ext_free = bge_jfree;
1016 m_new->m_ext.ext_ref = bge_jref;
1017 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1018
1019 m_new->m_flags |= M_EXT;
1020
20c9a969
SZ
1021 m_new->m_data = m_new->m_ext.ext_buf;
1022 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
984263bc 1023
20c9a969 1024 paddr = buf->bge_paddr;
0ecb11d7 1025 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
984263bc 1026 m_adj(m_new, ETHER_ALIGN);
20c9a969
SZ
1027 paddr += ETHER_ALIGN;
1028 }
1029
1436f9a0
SZ
1030 /* Save necessary information */
1031 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1032 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1033
984263bc 1034 /* Set up the descriptor. */
1436f9a0
SZ
1035 bge_setup_rxdesc_jumbo(sc, i);
1036 return 0;
1037}
1038
1039static void
1040bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1041{
1042 struct bge_rx_bd *r;
1043 struct bge_rxchain *rc;
20c9a969
SZ
1044
1045 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1436f9a0 1046 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
984263bc 1047
1436f9a0
SZ
1048 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1049 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1050 r->bge_len = rc->bge_mbuf->m_len;
1051 r->bge_idx = i;
1052 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
984263bc
MD
1053}
1054
984263bc 1055static int
33c39a69 1056bge_init_rx_ring_std(struct bge_softc *sc)
984263bc 1057{
1436f9a0 1058 int i, error;
984263bc 1059
1436f9a0
SZ
1060 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1061 error = bge_newbuf_std(sc, i, 1);
1062 if (error)
1063 return error;
984263bc
MD
1064 };
1065
1436f9a0 1066 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
591dfc77 1067 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc
MD
1068
1069 return(0);
1070}
1071
1072static void
33c39a69 1073bge_free_rx_ring_std(struct bge_softc *sc)
984263bc
MD
1074{
1075 int i;
1076
1077 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1436f9a0
SZ
1078 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1079
1080 if (rc->bge_mbuf != NULL) {
ddca511d 1081 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
20c9a969 1082 sc->bge_cdata.bge_rx_std_dmamap[i]);
1436f9a0
SZ
1083 m_freem(rc->bge_mbuf);
1084 rc->bge_mbuf = NULL;
984263bc 1085 }
20c9a969 1086 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
984263bc
MD
1087 sizeof(struct bge_rx_bd));
1088 }
984263bc
MD
1089}
1090
1091static int
33c39a69 1092bge_init_rx_ring_jumbo(struct bge_softc *sc)
984263bc 1093{
984263bc 1094 struct bge_rcb *rcb;
1436f9a0 1095 int i, error;
984263bc
MD
1096
1097 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1098 error = bge_newbuf_jumbo(sc, i, 1);
1099 if (error)
1100 return error;
984263bc
MD
1101 };
1102
1436f9a0 1103 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
984263bc 1104
20c9a969 1105 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
984263bc
MD
1106 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1107 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1108
591dfc77 1109 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
1110
1111 return(0);
1112}
1113
1114static void
33c39a69 1115bge_free_rx_ring_jumbo(struct bge_softc *sc)
984263bc
MD
1116{
1117 int i;
1118
1119 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1436f9a0
SZ
1120 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1121
1122 if (rc->bge_mbuf != NULL) {
1123 m_freem(rc->bge_mbuf);
1124 rc->bge_mbuf = NULL;
984263bc 1125 }
20c9a969 1126 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
984263bc
MD
1127 sizeof(struct bge_rx_bd));
1128 }
984263bc
MD
1129}
1130
1131static void
33c39a69 1132bge_free_tx_ring(struct bge_softc *sc)
984263bc
MD
1133{
1134 int i;
1135
984263bc
MD
1136 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1137 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
ddca511d 1138 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 1139 sc->bge_cdata.bge_tx_dmamap[i]);
984263bc
MD
1140 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1141 sc->bge_cdata.bge_tx_chain[i] = NULL;
1142 }
20c9a969 1143 bzero(&sc->bge_ldata.bge_tx_ring[i],
984263bc
MD
1144 sizeof(struct bge_tx_bd));
1145 }
984263bc
MD
1146}
1147
1148static int
33c39a69 1149bge_init_tx_ring(struct bge_softc *sc)
984263bc
MD
1150{
1151 sc->bge_txcnt = 0;
1152 sc->bge_tx_saved_considx = 0;
94db8384
SZ
1153 sc->bge_tx_prodidx = 0;
1154
1155 /* Initialize transmit producer index for host-memory send ring. */
591dfc77 1156 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1157
984263bc
MD
1158 /* 5700 b2 errata */
1159 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1160 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
984263bc 1161
591dfc77 1162 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1163 /* 5700 b2 errata */
1164 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 1165 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
984263bc
MD
1166
1167 return(0);
1168}
1169
984263bc 1170static void
33c39a69 1171bge_setmulti(struct bge_softc *sc)
984263bc
MD
1172{
1173 struct ifnet *ifp;
1174 struct ifmultiaddr *ifma;
33c39a69 1175 uint32_t hashes[4] = { 0, 0, 0, 0 };
984263bc
MD
1176 int h, i;
1177
1178 ifp = &sc->arpcom.ac_if;
1179
1180 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1181 for (i = 0; i < 4; i++)
1182 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1183 return;
1184 }
1185
1186 /* First, zot all the existing filters. */
1187 for (i = 0; i < 4; i++)
1188 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1189
1190 /* Now program new ones. */
441d34b2 1191 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
984263bc
MD
1192 if (ifma->ifma_addr->sa_family != AF_LINK)
1193 continue;
3b4ec5b8
JS
1194 h = ether_crc32_le(
1195 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1196 ETHER_ADDR_LEN) & 0x7f;
984263bc
MD
1197 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1198 }
1199
1200 for (i = 0; i < 4; i++)
1201 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
984263bc
MD
1202}
1203
1204/*
1205 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1206 * self-test results.
1207 */
1208static int
33c39a69 1209bge_chipinit(struct bge_softc *sc)
984263bc 1210{
33c39a69
JS
1211 int i;
1212 uint32_t dma_rw_ctl;
984263bc 1213
20c9a969
SZ
1214 /* Set endian type before we access any non-PCI registers. */
1215 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
984263bc 1216
984263bc
MD
1217 /* Clear the MAC control register */
1218 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1219
1220 /*
1221 * Clear the MAC statistics block in the NIC's
1222 * internal memory.
1223 */
1224 for (i = BGE_STATS_BLOCK;
33c39a69 1225 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1226 BGE_MEMWIN_WRITE(sc, i, 0);
1227
1228 for (i = BGE_STATUS_BLOCK;
33c39a69 1229 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
984263bc
MD
1230 BGE_MEMWIN_WRITE(sc, i, 0);
1231
1232 /* Set up the PCI DMA control register. */
0ecb11d7 1233 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
1234 /* PCI Express */
1235 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1236 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1237 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1238 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
984263bc 1239 /* PCI-X bus */
0ecb11d7
SZ
1240 if (BGE_IS_5714_FAMILY(sc)) {
1241 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1242 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1243 /* XXX magic values, Broadcom-supplied Linux driver */
1244 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1245 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1246 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1247 } else {
1248 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1249 }
1250 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1251 /*
1252 * The 5704 uses a different encoding of read/write
1253 * watermarks.
1254 */
984263bc
MD
1255 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1256 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1257 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
0ecb11d7 1258 } else {
984263bc
MD
1259 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1260 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1261 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1262 (0x0F);
0ecb11d7 1263 }
984263bc
MD
1264
1265 /*
1266 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1267 * for hardware bugs.
1268 */
1269 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1270 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
33c39a69 1271 uint32_t tmp;
984263bc
MD
1272
1273 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1274 if (tmp == 0x6 || tmp == 0x7)
1275 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1276 }
0ecb11d7
SZ
1277 } else {
1278 /* Conventional PCI bus */
1279 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1280 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1281 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1282 (0x0F);
984263bc
MD
1283 }
1284
1285 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
7e40b8c5 1286 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
0ecb11d7 1287 sc->bge_asicrev == BGE_ASICREV_BCM5705)
984263bc
MD
1288 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1289 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1290
1291 /*
1292 * Set up general mode register.
1293 */
20c9a969 1294 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
984263bc 1295 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
bf29e666 1296 BGE_MODECTL_TX_NO_PHDR_CSUM);
984263bc
MD
1297
1298 /*
33dd4678
SZ
1299 * BCM5701 B5 have a bug causing data corruption when using
1300 * 64-bit DMA reads, which can be terminated early and then
1301 * completed later as 32-bit accesses, in combination with
1302 * certain bridges.
1303 */
1304 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1305 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1306 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1307
1308 /*
984263bc
MD
1309 * Disable memory write invalidate. Apparently it is not supported
1310 * properly by these devices.
1311 */
1312 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1313
984263bc
MD
1314 /* Set the timer prescaler (always 66Mhz) */
1315 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1316
591dfc77
SZ
1317 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1318 DELAY(40); /* XXX */
1319
1320 /* Put PHY into ready state */
1321 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1322 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1323 DELAY(40);
1324 }
1325
984263bc
MD
1326 return(0);
1327}
1328
1329static int
33c39a69 1330bge_blockinit(struct bge_softc *sc)
984263bc
MD
1331{
1332 struct bge_rcb *rcb;
20c9a969
SZ
1333 bus_size_t vrcb;
1334 bge_hostaddr taddr;
0ecb11d7 1335 uint32_t val;
984263bc
MD
1336 int i;
1337
1338 /*
1339 * Initialize the memory window pointer register so that
1340 * we can access the first 32K of internal NIC RAM. This will
1341 * allow us to set up the TX send ring RCBs and the RX return
1342 * ring RCBs, plus other things which live in NIC memory.
1343 */
1344 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1345
7e40b8c5
HP
1346 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1347
0ecb11d7 1348 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5 1349 /* Configure mbuf memory pool */
0ecb11d7
SZ
1350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1351 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1352 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1353 else
1354 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
984263bc 1355
7e40b8c5
HP
1356 /* Configure DMA resource pool */
1357 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1358 BGE_DMA_DESCRIPTORS);
1359 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1360 }
984263bc
MD
1361
1362 /* Configure mbuf pool watermarks */
591dfc77 1363 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1364 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1365 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
591dfc77
SZ
1366 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1367 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1368 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1369 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1370 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1371 } else {
1372 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1373 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1374 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
7e40b8c5 1375 }
984263bc
MD
1376
1377 /* Configure DMA resource watermarks */
1378 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1379 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1380
1381 /* Enable buffer manager */
0ecb11d7 1382 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1383 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1384 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
984263bc 1385
7e40b8c5
HP
1386 /* Poll for buffer manager start indication */
1387 for (i = 0; i < BGE_TIMEOUT; i++) {
1388 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1389 break;
1390 DELAY(10);
1391 }
984263bc 1392
7e40b8c5 1393 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1394 if_printf(&sc->arpcom.ac_if,
1395 "buffer manager failed to start\n");
7e40b8c5
HP
1396 return(ENXIO);
1397 }
984263bc
MD
1398 }
1399
1400 /* Enable flow-through queues */
1401 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1402 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1403
1404 /* Wait until queue initialization is complete */
1405 for (i = 0; i < BGE_TIMEOUT; i++) {
1406 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1407 break;
1408 DELAY(10);
1409 }
1410
1411 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1412 if_printf(&sc->arpcom.ac_if,
1413 "flow-through queue init failed\n");
984263bc
MD
1414 return(ENXIO);
1415 }
1416
1417 /* Initialize the standard RX ring control block */
20c9a969
SZ
1418 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1419 rcb->bge_hostaddr.bge_addr_lo =
1420 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1421 rcb->bge_hostaddr.bge_addr_hi =
1422 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
0ecb11d7 1423 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
1424 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1425 else
1426 rcb->bge_maxlen_flags =
1427 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
0ecb11d7 1428 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
984263bc
MD
1429 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1430 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1431 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1432 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1433
1434 /*
1435 * Initialize the jumbo RX ring control block
1436 * We set the 'ring disabled' bit in the flags
1437 * field until we're actually ready to start
1438 * using this ring (i.e. once we set the MTU
1439 * high enough to require it).
1440 */
0ecb11d7 1441 if (BGE_IS_JUMBO_CAPABLE(sc)) {
20c9a969
SZ
1442 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1443
1444 rcb->bge_hostaddr.bge_addr_lo =
1445 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1446 rcb->bge_hostaddr.bge_addr_hi =
1447 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
7e40b8c5
HP
1448 rcb->bge_maxlen_flags =
1449 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1450 BGE_RCB_FLAG_RING_DISABLED);
0ecb11d7 1451 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
7e40b8c5
HP
1452 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1453 rcb->bge_hostaddr.bge_addr_hi);
1454 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1455 rcb->bge_hostaddr.bge_addr_lo);
1456 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1457 rcb->bge_maxlen_flags);
1458 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1459
1460 /* Set up dummy disabled mini ring RCB */
20c9a969 1461 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
7e40b8c5
HP
1462 rcb->bge_maxlen_flags =
1463 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1464 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1465 rcb->bge_maxlen_flags);
1466 }
984263bc
MD
1467
1468 /*
1469 * Set the BD ring replentish thresholds. The recommended
1470 * values are 1/8th the number of descriptors allocated to
1471 * each ring.
1472 */
0ecb11d7
SZ
1473 if (BGE_IS_5705_PLUS(sc))
1474 val = 8;
1475 else
1476 val = BGE_STD_RX_RING_CNT / 8;
1477 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
984263bc
MD
1478 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1479
1480 /*
1481 * Disable all unused send rings by setting the 'ring disabled'
1482 * bit in the flags field of all the TX send ring control blocks.
1483 * These are located in NIC memory.
1484 */
20c9a969 1485 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
984263bc 1486 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
20c9a969
SZ
1487 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1488 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1489 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1490 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1491 }
1492
1493 /* Configure TX RCB 0 (we use only the first ring) */
20c9a969
SZ
1494 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1495 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1496 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1497 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1498 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1499 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
0ecb11d7 1500 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1501 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1502 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1503 }
984263bc
MD
1504
1505 /* Disable all unused RX return rings */
20c9a969 1506 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
984263bc 1507 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
20c9a969
SZ
1508 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1509 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1510 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
7e40b8c5 1511 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
20c9a969
SZ
1512 BGE_RCB_FLAG_RING_DISABLED));
1513 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
591dfc77 1514 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
33c39a69 1515 (i * (sizeof(uint64_t))), 0);
20c9a969 1516 vrcb += sizeof(struct bge_rcb);
984263bc
MD
1517 }
1518
1519 /* Initialize RX ring indexes */
591dfc77
SZ
1520 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1521 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1522 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
984263bc
MD
1523
1524 /*
1525 * Set up RX return ring 0
1526 * Note that the NIC address for RX return rings is 0x00000000.
1527 * The return rings live entirely within the host, so the
1528 * nicaddr field in the RCB isn't used.
1529 */
20c9a969
SZ
1530 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1531 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1532 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1533 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1534 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1535 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1536 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
984263bc
MD
1537
1538 /* Set random backoff seed for TX */
1539 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1540 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1541 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1542 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1543 BGE_TX_BACKOFF_SEED_MASK);
1544
1545 /* Set inter-packet gap */
1546 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1547
1548 /*
1549 * Specify which ring to use for packets that don't match
1550 * any RX rules.
1551 */
1552 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1553
1554 /*
1555 * Configure number of RX lists. One interrupt distribution
1556 * list, sixteen active lists, one bad frames class.
1557 */
1558 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1559
1560 /* Inialize RX list placement stats mask. */
1561 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1562 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1563
1564 /* Disable host coalescing until we get it set up */
1565 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1566
1567 /* Poll to make sure it's shut down. */
1568 for (i = 0; i < BGE_TIMEOUT; i++) {
1569 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1570 break;
1571 DELAY(10);
1572 }
1573
1574 if (i == BGE_TIMEOUT) {
c6fd6f3b
JS
1575 if_printf(&sc->arpcom.ac_if,
1576 "host coalescing engine failed to idle\n");
984263bc
MD
1577 return(ENXIO);
1578 }
1579
1580 /* Set up host coalescing defaults */
1581 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1582 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1583 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1584 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
0ecb11d7 1585 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
1586 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1587 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1588 }
ba39cc82
SZ
1589 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1590 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
984263bc
MD
1591
1592 /* Set up address of statistics block */
0ecb11d7 1593 if (!BGE_IS_5705_PLUS(sc)) {
20c9a969
SZ
1594 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1595 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
7e40b8c5 1596 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
20c9a969 1597 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
7e40b8c5
HP
1598
1599 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1600 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1601 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1602 }
984263bc
MD
1603
1604 /* Set up address of status block */
20c9a969
SZ
1605 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1606 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
984263bc 1607 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
20c9a969
SZ
1608 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1609 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1610 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
984263bc
MD
1611
1612 /* Turn on host coalescing state machine */
1613 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1614
1615 /* Turn on RX BD completion state machine and enable attentions */
1616 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1617 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1618
1619 /* Turn on RX list placement state machine */
1620 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1621
1622 /* Turn on RX list selector state machine. */
0ecb11d7 1623 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1624 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
1625
1626 /* Turn on DMA, clear stats */
1627 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1628 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1629 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1630 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
0ecb11d7
SZ
1631 ((sc->bge_flags & BGE_FLAG_TBI) ?
1632 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
984263bc
MD
1633
1634 /* Set misc. local control, enable interrupts on attentions */
1635 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1636
1637#ifdef notdef
1638 /* Assert GPIO pins for PHY reset */
1639 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1640 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1641 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1642 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1643#endif
1644
1645 /* Turn on DMA completion state machine */
0ecb11d7 1646 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1647 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
1648
1649 /* Turn on write DMA state machine */
0ecb11d7 1650 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
832863d2
SZ
1651 if (BGE_IS_5755_PLUS(sc)) {
1652 /* Enable host coalescing bug fix. */
1653 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1654 }
0ecb11d7 1655 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
671bd7ed
SZ
1656 DELAY(40);
1657
984263bc 1658 /* Turn on read DMA state machine */
671bd7ed 1659 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
f47afe1a
MN
1660 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1661 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1662 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1663 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1664 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1665 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
671bd7ed
SZ
1666 if (sc->bge_flags & BGE_FLAG_PCIE)
1667 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1668 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1669 DELAY(40);
984263bc
MD
1670
1671 /* Turn on RX data completion state machine */
1672 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1673
1674 /* Turn on RX BD initiator state machine */
1675 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1676
1677 /* Turn on RX data and RX BD initiator state machine */
1678 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1679
1680 /* Turn on Mbuf cluster free state machine */
0ecb11d7 1681 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 1682 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
1683
1684 /* Turn on send BD completion state machine */
1685 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1686
1687 /* Turn on send data completion state machine */
f47afe1a
MN
1688 val = BGE_SDCMODE_ENABLE;
1689 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1690 val |= BGE_SDCMODE_CDELAY;
1691 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
984263bc
MD
1692
1693 /* Turn on send data initiator state machine */
1694 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1695
1696 /* Turn on send BD initiator state machine */
1697 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1698
1699 /* Turn on send BD selector state machine */
1700 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1701
1702 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1703 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1704 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1705
1706 /* ack/clear link change events */
1707 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
7e40b8c5
HP
1708 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1709 BGE_MACSTAT_LINK_CHANGED);
20c9a969 1710 CSR_WRITE_4(sc, BGE_MI_STS, 0);
984263bc
MD
1711
1712 /* Enable PHY auto polling (for MII/GMII only) */
0ecb11d7 1713 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
1714 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1715 } else {
1716 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
db861466
SZ
1717 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1718 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
984263bc
MD
1719 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1720 BGE_EVTENB_MI_INTERRUPT);
db861466 1721 }
984263bc
MD
1722 }
1723
db861466
SZ
1724 /*
1725 * Clear any pending link state attention.
1726 * Otherwise some link state change events may be lost until attention
1727 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1728 * It's not necessary on newer BCM chips - perhaps enabling link
1729 * state change attentions implies clearing pending attention.
1730 */
1731 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1732 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1733 BGE_MACSTAT_LINK_CHANGED);
1734
984263bc
MD
1735 /* Enable link state change attentions. */
1736 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1737
1738 return(0);
1739}
1740
1741/*
1742 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1743 * against our list and return its name if we find a match. Note
1744 * that since the Broadcom controller contains VPD support, we
1745 * can get the device name string from the controller itself instead
1746 * of the compiled-in string. This is a little slow, but it guarantees
1747 * we'll always announce the right product name.
1748 */
1749static int
33c39a69 1750bge_probe(device_t dev)
984263bc 1751{
d265721a 1752 const struct bge_type *t;
33c39a69
JS
1753 uint16_t product, vendor;
1754
1755 product = pci_get_device(dev);
1756 vendor = pci_get_vendor(dev);
1757
1758 for (t = bge_devs; t->bge_name != NULL; t++) {
1759 if (vendor == t->bge_vid && product == t->bge_did)
1760 break;
1761 }
33c39a69
JS
1762 if (t->bge_name == NULL)
1763 return(ENXIO);
984263bc 1764
d265721a
SZ
1765 device_set_desc(dev, t->bge_name);
1766 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL) {
1767 struct bge_softc *sc = device_get_softc(dev);
0ecb11d7 1768 sc->bge_flags |= BGE_FLAG_NO_3LED;
d265721a 1769 }
33c39a69 1770 return(0);
984263bc
MD
1771}
1772
1773static int
33c39a69 1774bge_attach(device_t dev)
984263bc 1775{
984263bc
MD
1776 struct ifnet *ifp;
1777 struct bge_softc *sc;
33c39a69 1778 uint32_t hwcfg = 0;
c6fd6f3b 1779 int error = 0, rid;
0a8b5977 1780 uint8_t ether_addr[ETHER_ADDR_LEN];
984263bc 1781
984263bc 1782 sc = device_get_softc(dev);
984263bc 1783 sc->bge_dev = dev;
263489fb 1784 callout_init(&sc->bge_stat_timer);
16dca0df 1785 lwkt_serialize_init(&sc->bge_jslot_serializer);
984263bc 1786
591dfc77
SZ
1787#ifndef BURN_BRIDGES
1788 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1789 uint32_t irq, mem;
1790
1791 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1792 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1793
1794 device_printf(dev, "chip is in D%d power mode "
1795 "-- setting to D0\n", pci_get_powerstate(dev));
1796
1797 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1798
1799 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1800 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1801 }
1802#endif /* !BURN_BRIDGE */
1803
984263bc
MD
1804 /*
1805 * Map control/status registers.
1806 */
cc8ddf9e 1807 pci_enable_busmaster(dev);
984263bc
MD
1808
1809 rid = BGE_PCI_BAR0;
cc8ddf9e
JS
1810 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1811 RF_ACTIVE);
984263bc
MD
1812
1813 if (sc->bge_res == NULL) {
c6fd6f3b 1814 device_printf(dev, "couldn't map memory\n");
baf731bb 1815 return ENXIO;
984263bc
MD
1816 }
1817
1818 sc->bge_btag = rman_get_bustag(sc->bge_res);
1819 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
984263bc 1820
d265721a 1821 /* Save various chip information */
9a6ee7e2 1822 sc->bge_chipid =
f47afe1a
MN
1823 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1824 BGE_PCIMISCCTL_ASICREV_SHIFT;
1825 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1826 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
9a6ee7e2
JS
1827 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1828 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1829
0ecb11d7
SZ
1830 /* Save chipset family. */
1831 switch (sc->bge_asicrev) {
f47afe1a
MN
1832 case BGE_ASICREV_BCM5755:
1833 case BGE_ASICREV_BCM5761:
1834 case BGE_ASICREV_BCM5784:
1835 case BGE_ASICREV_BCM5785:
1836 case BGE_ASICREV_BCM5787:
1837 case BGE_ASICREV_BCM57780:
1838 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
1839 BGE_FLAG_5705_PLUS;
1840 break;
1841
0ecb11d7
SZ
1842 case BGE_ASICREV_BCM5700:
1843 case BGE_ASICREV_BCM5701:
1844 case BGE_ASICREV_BCM5703:
1845 case BGE_ASICREV_BCM5704:
1846 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1847 break;
1848
1849 case BGE_ASICREV_BCM5714_A0:
1850 case BGE_ASICREV_BCM5780:
1851 case BGE_ASICREV_BCM5714:
1852 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1853 /* Fall through */
1854
1855 case BGE_ASICREV_BCM5750:
1856 case BGE_ASICREV_BCM5752:
591dfc77 1857 case BGE_ASICREV_BCM5906:
0ecb11d7
SZ
1858 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1859 /* Fall through */
1860
1861 case BGE_ASICREV_BCM5705:
1862 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1863 break;
1864 }
9a6ee7e2 1865
591dfc77
SZ
1866 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
1867 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
1868
9a6ee7e2 1869 /*
0ecb11d7 1870 * Set various quirk flags.
9a6ee7e2 1871 */
9a6ee7e2 1872
0ecb11d7
SZ
1873 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1874 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1875 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1876 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1877 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1878 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1879 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1880
1881 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1882 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1883 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1884
1885 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1886 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1887 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1888
1889 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1890 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1891
f47afe1a
MN
1892 if (BGE_IS_5705_PLUS(sc) &&
1893 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) {
0ecb11d7 1894 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
f47afe1a
MN
1895 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1896 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
0ecb11d7 1897 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
f47afe1a
MN
1898 if (sc->bge_chipid != BGE_CHIPID_BCM5722_A0)
1899 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
0ecb11d7
SZ
1900 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1901 sc->bge_flags |= BGE_FLAG_BER_BUG;
9a6ee7e2
JS
1902 }
1903 }
1904
0ecb11d7
SZ
1905 /* Allocate interrupt */
1906 rid = 0;
1907
1908 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1909 RF_SHAREABLE | RF_ACTIVE);
1910
1911 if (sc->bge_irq == NULL) {
1912 device_printf(dev, "couldn't map interrupt\n");
1913 error = ENXIO;
1914 goto fail;
1915 }
1916
1917 /*
1918 * Check if this is a PCI-X or PCI Express device.
1919 */
1920 if (BGE_IS_5705_PLUS(sc)) {
32159cc2 1921 if (pci_is_pcie(dev)) {
0ecb11d7 1922 sc->bge_flags |= BGE_FLAG_PCIE;
01c9014b 1923 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
671bd7ed 1924 }
0ecb11d7
SZ
1925 } else {
1926 /*
1927 * Check if the device is in PCI-X Mode.
1928 * (This bit is not valid on PCI Express controllers.)
1929 */
1930 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1931 BGE_PCISTATE_PCI_BUSMODE) == 0)
1932 sc->bge_flags |= BGE_FLAG_PCIX;
1933 }
1934
d265721a
SZ
1935 device_printf(dev, "CHIP ID 0x%08x; "
1936 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
1937 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
1938 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
1939 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
1940 "PCI-E" : "PCI"));
b197e64e 1941
d723dbb5
SZ
1942 /*
1943 * All controllers that are not 5755 or higher have 4GB
1944 * boundary DMA bug.
1945 * Whenever an address crosses a multiple of the 4GB boundary
1946 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
1947 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
1948 * state machine will lockup and cause the device to hang.
1949 */
1950 if (BGE_IS_5755_PLUS(sc) == 0)
1951 sc->bge_flags |= BGE_FLAG_BOUNDARY_4G;
1952
1953 /*
1954 * The 40bit DMA bug applies to the 5714/5715 controllers and is
1955 * not actually a MAC controller bug but an issue with the embedded
1956 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
1957 */
1958 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
1959 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
1960
c6fd6f3b
JS
1961 ifp = &sc->arpcom.ac_if;
1962 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
984263bc
MD
1963
1964 /* Try to reset the chip. */
1965 bge_reset(sc);
1966
1967 if (bge_chipinit(sc)) {
c6fd6f3b 1968 device_printf(dev, "chip initialization failed\n");
984263bc
MD
1969 error = ENXIO;
1970 goto fail;
1971 }
1972
1973 /*
591dfc77 1974 * Get station address
984263bc 1975 */
591dfc77
SZ
1976 error = bge_get_eaddr(sc, ether_addr);
1977 if (error) {
c6fd6f3b 1978 device_printf(dev, "failed to read station address\n");
984263bc
MD
1979 goto fail;
1980 }
1981
20c9a969 1982 /* 5705/5750 limits RX return ring to 512 entries. */
0ecb11d7 1983 if (BGE_IS_5705_PLUS(sc))
20c9a969
SZ
1984 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1985 else
1986 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
984263bc 1987
20c9a969
SZ
1988 error = bge_dma_alloc(sc);
1989 if (error)
984263bc 1990 goto fail;
984263bc
MD
1991
1992 /* Set default tuneable values. */
1993 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
055d06f0
SZ
1994 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1995 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1996 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1997 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
984263bc
MD
1998
1999 /* Set up ifnet structure */
984263bc 2000 ifp->if_softc = sc;
984263bc
MD
2001 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2002 ifp->if_ioctl = bge_ioctl;
984263bc 2003 ifp->if_start = bge_start;
315fe0ee
MD
2004#ifdef DEVICE_POLLING
2005 ifp->if_poll = bge_poll;
2006#endif
984263bc
MD
2007 ifp->if_watchdog = bge_watchdog;
2008 ifp->if_init = bge_init;
2009 ifp->if_mtu = ETHERMTU;
cb623c48 2010 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
936ff230
JS
2011 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2012 ifq_set_ready(&ifp->if_snd);
cb623c48
SZ
2013
2014 /*
2015 * 5700 B0 chips do not support checksumming correctly due
2016 * to hardware bugs.
2017 */
2018 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2019 ifp->if_capabilities |= IFCAP_HWCSUM;
2020 ifp->if_hwassist = BGE_CSUM_FEATURES;
2021 }
984263bc
MD
2022 ifp->if_capenable = ifp->if_capabilities;
2023
984263bc
MD
2024 /*
2025 * Figure out what sort of media we have by checking the
2026 * hardware config word in the first 32k of NIC internal memory,
2027 * or fall back to examining the EEPROM if necessary.
2028 * Note: on some BCM5700 cards, this value appears to be unset.
2029 * If that's the case, we have to rely on identifying the NIC
2030 * by its PCI subsystem ID, as we do below for the SysKonnect
2031 * SK-9D41.
2032 */
2033 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
2034 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2035 else {
7b47d9c2
SZ
2036 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2037 sizeof(hwcfg))) {
2038 device_printf(dev, "failed to read EEPROM\n");
2039 error = ENXIO;
2040 goto fail;
2041 }
984263bc
MD
2042 hwcfg = ntohl(hwcfg);
2043 }
2044
2045 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
0ecb11d7 2046 sc->bge_flags |= BGE_FLAG_TBI;
984263bc
MD
2047
2048 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
cc8ddf9e 2049 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
0ecb11d7 2050 sc->bge_flags |= BGE_FLAG_TBI;
984263bc 2051
0ecb11d7 2052 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
2053 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2054 bge_ifmedia_upd, bge_ifmedia_sts);
2055 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2056 ifmedia_add(&sc->bge_ifmedia,
2057 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2058 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2059 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
70059b3c 2060 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
984263bc
MD
2061 } else {
2062 /*
2063 * Do transceiver setup.
2064 */
2065 if (mii_phy_probe(dev, &sc->bge_miibus,
2066 bge_ifmedia_upd, bge_ifmedia_sts)) {
c6fd6f3b 2067 device_printf(dev, "MII without any PHY!\n");
984263bc
MD
2068 error = ENXIO;
2069 goto fail;
2070 }
2071 }
2072
2073 /*
2074 * When using the BCM5701 in PCI-X mode, data corruption has
2075 * been observed in the first few bytes of some received packets.
2076 * Aligning the packet buffer in memory eliminates the corruption.
2077 * Unfortunately, this misaligns the packet payloads. On platforms
2078 * which do not support unaligned accesses, we will realign the
2079 * payloads by copying the received packets.
2080 */
0ecb11d7
SZ
2081 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2082 (sc->bge_flags & BGE_FLAG_PCIX))
2083 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
984263bc 2084
db861466
SZ
2085 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2086 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2087 sc->bge_link_upd = bge_bcm5700_link_upd;
2088 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
0ecb11d7 2089 } else if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2090 sc->bge_link_upd = bge_tbi_link_upd;
2091 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2092 } else {
2093 sc->bge_link_upd = bge_copper_link_upd;
2094 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2095 }
2096
984263bc 2097 /*
055d06f0
SZ
2098 * Create sysctl nodes.
2099 */
2100 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2101 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2102 SYSCTL_STATIC_CHILDREN(_hw),
2103 OID_AUTO,
2104 device_get_nameunit(dev),
2105 CTLFLAG_RD, 0, "");
2106 if (sc->bge_sysctl_tree == NULL) {
2107 device_printf(dev, "can't add sysctl node\n");
2108 error = ENXIO;
2109 goto fail;
2110 }
2111
2112 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2113 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2114 OID_AUTO, "rx_coal_ticks",
2115 CTLTYPE_INT | CTLFLAG_RW,
2116 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2117 "Receive coalescing ticks (usec).");
2118 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2119 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2120 OID_AUTO, "tx_coal_ticks",
2121 CTLTYPE_INT | CTLFLAG_RW,
2122 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2123 "Transmit coalescing ticks (usec).");
2124 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2125 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2126 OID_AUTO, "rx_max_coal_bds",
2127 CTLTYPE_INT | CTLFLAG_RW,
2128 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2129 "Receive max coalesced BD count.");
2130 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2131 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2132 OID_AUTO, "tx_max_coal_bds",
2133 CTLTYPE_INT | CTLFLAG_RW,
2134 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2135 "Transmit max coalesced BD count.");
2136
2137 /*
984263bc
MD
2138 * Call MI attach routine.
2139 */
78195a76 2140 ether_ifattach(ifp, ether_addr, NULL);
984263bc 2141
95893fe4 2142 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
78195a76
MD
2143 bge_intr, sc, &sc->bge_intrhand,
2144 ifp->if_serializer);
9a717c15
JS
2145 if (error) {
2146 ether_ifdetach(ifp);
2147 device_printf(dev, "couldn't set up irq\n");
2148 goto fail;
2149 }
9db4b353 2150
28e81a28 2151 ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
9db4b353
SZ
2152 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2153
9a717c15 2154 return(0);
984263bc 2155fail:
9a717c15 2156 bge_detach(dev);
984263bc
MD
2157 return(error);
2158}
2159
2160static int
33c39a69 2161bge_detach(device_t dev)
984263bc 2162{
9a717c15 2163 struct bge_softc *sc = device_get_softc(dev);
984263bc 2164
9a717c15 2165 if (device_is_attached(dev)) {
baf731bb
SZ
2166 struct ifnet *ifp = &sc->arpcom.ac_if;
2167
cdf89432 2168 lwkt_serialize_enter(ifp->if_serializer);
9a717c15
JS
2169 bge_stop(sc);
2170 bge_reset(sc);
cdf89432
SZ
2171 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2172 lwkt_serialize_exit(ifp->if_serializer);
984263bc 2173
cdf89432
SZ
2174 ether_ifdetach(ifp);
2175 }
baf731bb 2176
0ecb11d7 2177 if (sc->bge_flags & BGE_FLAG_TBI)
984263bc 2178 ifmedia_removeall(&sc->bge_ifmedia);
cbf32d7e 2179 if (sc->bge_miibus)
984263bc 2180 device_delete_child(dev, sc->bge_miibus);
9a717c15 2181 bus_generic_detach(dev);
984263bc 2182
984263bc
MD
2183 if (sc->bge_irq != NULL)
2184 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2185
2186 if (sc->bge_res != NULL)
2187 bus_release_resource(dev, SYS_RES_MEMORY,
2188 BGE_PCI_BAR0, sc->bge_res);
baf731bb 2189
055d06f0
SZ
2190 if (sc->bge_sysctl_tree != NULL)
2191 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2192
baf731bb
SZ
2193 bge_dma_free(sc);
2194
2195 return 0;
984263bc
MD
2196}
2197
2198static void
33c39a69 2199bge_reset(struct bge_softc *sc)
984263bc
MD
2200{
2201 device_t dev;
9a6ee7e2 2202 uint32_t cachesize, command, pcistate, reset;
0ecb11d7 2203 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
984263bc
MD
2204 int i, val = 0;
2205
2206 dev = sc->bge_dev;
2207
591dfc77
SZ
2208 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2209 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
0ecb11d7
SZ
2210 if (sc->bge_flags & BGE_FLAG_PCIE)
2211 write_op = bge_writemem_direct;
2212 else
2213 write_op = bge_writemem_ind;
2214 } else {
2215 write_op = bge_writereg_ind;
2216 }
2217
984263bc
MD
2218 /* Save some important PCI state. */
2219 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2220 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2221 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2222
2223 pci_write_config(dev, BGE_PCI_MISC_CTL,
2224 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 2225 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc 2226
0ecb11d7
SZ
2227 /* Disable fastboot on controllers that support it. */
2228 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
832863d2 2229 BGE_IS_5755_PLUS(sc)) {
0ecb11d7
SZ
2230 if (bootverbose)
2231 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2232 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2233 }
2234
2235 /*
2236 * Write the magic number to SRAM at offset 0xB50.
2237 * When firmware finishes its initialization it will
2238 * write ~BGE_MAGIC_NUMBER to the same location.
2239 */
2240 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2241
9a6ee7e2
JS
2242 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2243
2244 /* XXX: Broadcom Linux driver. */
0ecb11d7 2245 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2246 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2247 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2248 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2249 /* Prevent PCIE link training during global reset */
2250 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2251 reset |= (1<<29);
2252 }
2253 }
2254
0ecb11d7
SZ
2255 /*
2256 * Set GPHY Power Down Override to leave GPHY
2257 * powered up in D0 uninitialized.
2258 */
2259 if (BGE_IS_5705_PLUS(sc))
2260 reset |= 0x04000000;
2261
984263bc 2262 /* Issue global reset */
0ecb11d7 2263 write_op(sc, BGE_MISC_CFG, reset);
984263bc 2264
591dfc77
SZ
2265 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2266 uint32_t status, ctrl;
2267
2268 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2269 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2270 status | BGE_VCPU_STATUS_DRV_RESET);
2271 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2272 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2273 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2274 }
2275
984263bc
MD
2276 DELAY(1000);
2277
9a6ee7e2 2278 /* XXX: Broadcom Linux driver. */
0ecb11d7 2279 if (sc->bge_flags & BGE_FLAG_PCIE) {
9a6ee7e2
JS
2280 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2281 uint32_t v;
2282
2283 DELAY(500000); /* wait for link training to complete */
2284 v = pci_read_config(dev, 0xc4, 4);
2285 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2286 }
0ecb11d7
SZ
2287 /*
2288 * Set PCIE max payload size to 128 bytes and
2289 * clear error status.
2290 */
9a6ee7e2
JS
2291 pci_write_config(dev, 0xd8, 0xf5000, 4);
2292 }
2293
984263bc
MD
2294 /* Reset some of the PCI state that got zapped by reset */
2295 pci_write_config(dev, BGE_PCI_MISC_CTL,
2296 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
20c9a969 2297 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
984263bc
MD
2298 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2299 pci_write_config(dev, BGE_PCI_CMD, command, 4);
0ecb11d7 2300 write_op(sc, BGE_MISC_CFG, (65 << 1));
984263bc 2301
a313b56f 2302 /* Enable memory arbiter. */
0ecb11d7
SZ
2303 if (BGE_IS_5714_FAMILY(sc)) {
2304 uint32_t val;
2305
2306 val = CSR_READ_4(sc, BGE_MARB_MODE);
2307 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2308 } else {
a313b56f 2309 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
0ecb11d7 2310 }
a313b56f 2311
591dfc77
SZ
2312 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2313 for (i = 0; i < BGE_TIMEOUT; i++) {
2314 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2315 if (val & BGE_VCPU_STATUS_INIT_DONE)
2316 break;
2317 DELAY(100);
2318 }
2319 if (i == BGE_TIMEOUT) {
2320 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2321 return;
2322 }
2323 } else {
2324 /*
2325 * Poll until we see the 1's complement of the magic number.
2326 * This indicates that the firmware initialization
2327 * is complete.
2328 */
d880f7b3 2329 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
591dfc77
SZ
2330 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2331 if (val == ~BGE_MAGIC_NUMBER)
2332 break;
2333 DELAY(10);
2334 }
d880f7b3 2335 if (i == BGE_FIRMWARE_TIMEOUT) {
591dfc77
SZ
2336 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2337 "timed out, found 0x%08x\n", val);
2338 return;
2339 }
984263bc
MD
2340 }
2341
2342 /*
2343 * XXX Wait for the value of the PCISTATE register to
2344 * return to its original pre-reset state. This is a
2345 * fairly good indicator of reset completion. If we don't
2346 * wait for the reset to fully complete, trying to read
2347 * from the device's non-PCI registers may yield garbage
2348 * results.
2349 */
2350 for (i = 0; i < BGE_TIMEOUT; i++) {
2351 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2352 break;
2353 DELAY(10);
2354 }
2355
0ecb11d7
SZ
2356 if (sc->bge_flags & BGE_FLAG_PCIE) {
2357 reset = bge_readmem_ind(sc, 0x7c00);
2358 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2359 }
2360
984263bc 2361 /* Fix up byte swapping */
20c9a969 2362 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
984263bc
MD
2363 BGE_MODECTL_BYTESWAP_DATA);
2364
2365 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2366
70059b3c
JS
2367 /*
2368 * The 5704 in TBI mode apparently needs some special
2369 * adjustment to insure the SERDES drive level is set
2370 * to 1.2V.
2371 */
0ecb11d7
SZ
2372 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2373 (sc->bge_flags & BGE_FLAG_TBI)) {
70059b3c
JS
2374 uint32_t serdescfg;
2375
2376 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2377 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2378 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2379 }
2380
9a6ee7e2 2381 /* XXX: Broadcom Linux driver. */
0ecb11d7
SZ
2382 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2383 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
9a6ee7e2 2384 uint32_t v;
984263bc 2385
9a6ee7e2
JS
2386 v = CSR_READ_4(sc, 0x7c00);
2387 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2388 }
2389
2390 DELAY(10000);
984263bc
MD
2391}
2392
2393/*
2394 * Frame reception handling. This is called if there's a frame
2395 * on the receive return list.
2396 *
2397 * Note: we have to be able to handle two possibilities here:
2398 * 1) the frame is from the jumbo recieve ring
2399 * 2) the frame is from the standard receive ring
2400 */
2401
2402static void
33c39a69 2403bge_rxeof(struct bge_softc *sc)
984263bc
MD
2404{
2405 struct ifnet *ifp;
2406 int stdcnt = 0, jumbocnt = 0;
2407
449e06cc 2408 if (sc->bge_rx_saved_considx ==
20c9a969 2409 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
449e06cc
SZ
2410 return;
2411
984263bc
MD
2412 ifp = &sc->arpcom.ac_if;
2413
20c9a969
SZ
2414 while (sc->bge_rx_saved_considx !=
2415 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
984263bc 2416 struct bge_rx_bd *cur_rx;
33c39a69 2417 uint32_t rxidx;
984263bc 2418 struct mbuf *m = NULL;
33c39a69 2419 uint16_t vlan_tag = 0;
984263bc
MD
2420 int have_tag = 0;
2421
2422 cur_rx =
20c9a969 2423 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
984263bc
MD
2424
2425 rxidx = cur_rx->bge_idx;
7e40b8c5 2426 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
6b880771 2427 logif(rx_pkt);
984263bc
MD
2428
2429 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2430 have_tag = 1;
2431 vlan_tag = cur_rx->bge_vlan_tag;
2432 }
2433
2434 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2435 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
984263bc 2436 jumbocnt++;
1436f9a0
SZ
2437
2438 if (rxidx != sc->bge_jumbo) {
2439 ifp->if_ierrors++;
2440 if_printf(ifp, "sw jumbo index(%d) "
2441 "and hw jumbo index(%d) mismatch, drop!\n",
2442 sc->bge_jumbo, rxidx);
2443 bge_setup_rxdesc_jumbo(sc, rxidx);
2444 continue;
2445 }
2446
2447 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
984263bc
MD
2448 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2449 ifp->if_ierrors++;
1436f9a0 2450 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2451 continue;
2452 }
1436f9a0 2453 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
984263bc 2454 ifp->if_ierrors++;
1436f9a0 2455 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
984263bc
MD
2456 continue;
2457 }
2458 } else {
2459 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
984263bc 2460 stdcnt++;
1436f9a0
SZ
2461
2462 if (rxidx != sc->bge_std) {
2463 ifp->if_ierrors++;
2464 if_printf(ifp, "sw std index(%d) "
2465 "and hw std index(%d) mismatch, drop!\n",
2466 sc->bge_std, rxidx);
2467 bge_setup_rxdesc_std(sc, rxidx);
2468 continue;
2469 }
2470
2471 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
984263bc
MD
2472 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2473 ifp->if_ierrors++;
1436f9a0 2474 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2475 continue;
2476 }
1436f9a0 2477 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
984263bc 2478 ifp->if_ierrors++;
1436f9a0 2479 bge_setup_rxdesc_std(sc, sc->bge_std);
984263bc
MD
2480 continue;
2481 }
2482 }
2483
2484 ifp->if_ipackets++;
2485#ifndef __i386__
2486 /*
2487 * The i386 allows unaligned accesses, but for other
2488 * platforms we must make sure the payload is aligned.
2489 */
0ecb11d7 2490 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
984263bc
MD
2491 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2492 cur_rx->bge_len);
2493 m->m_data += ETHER_ALIGN;
2494 }
2495#endif
160185fa 2496 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
984263bc
MD
2497 m->m_pkthdr.rcvif = ifp;
2498
cb623c48
SZ
2499 if (ifp->if_capenable & IFCAP_RXCSUM) {
2500 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2501 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2502 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2503 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2504 }
17240569 2505 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
cb623c48 2506 m->m_pkthdr.len >= BGE_MIN_FRAME) {
984263bc 2507 m->m_pkthdr.csum_data =
17240569 2508 cur_rx->bge_tcp_udp_csum;
bf29e666
SZ
2509 m->m_pkthdr.csum_flags |=
2510 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
984263bc
MD
2511 }
2512 }
984263bc
MD
2513
2514 /*
2515 * If we received a packet with a vlan tag, pass it
2516 * to vlan_input() instead of ether_input().
2517 */
2518 if (have_tag) {
e6b5847c
SZ
2519 m->m_flags |= M_VLANTAG;
2520 m->m_pkthdr.ether_vlantag = vlan_tag;
984263bc 2521 have_tag = vlan_tag = 0;
984263bc 2522 }
eda7db08 2523 ifp->if_input(ifp, m);
984263bc
MD
2524 }
2525
591dfc77 2526 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
984263bc 2527 if (stdcnt)
591dfc77 2528 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
984263bc 2529 if (jumbocnt)
591dfc77 2530 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
984263bc
MD
2531}
2532
2533static void
33c39a69 2534bge_txeof(struct bge_softc *sc)
984263bc
MD
2535{
2536 struct bge_tx_bd *cur_tx = NULL;
2537 struct ifnet *ifp;
2538
449e06cc 2539 if (sc->bge_tx_saved_considx ==
20c9a969 2540 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
449e06cc
SZ
2541 return;
2542
984263bc
MD
2543 ifp = &sc->arpcom.ac_if;
2544
2545 /*
2546 * Go through our tx ring and free mbufs for those
2547 * frames that have been sent.
2548 */
2549 while (sc->bge_tx_saved_considx !=
20c9a969
SZ
2550 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2551 uint32_t idx = 0;
984263bc
MD
2552
2553 idx = sc->bge_tx_saved_considx;
20c9a969 2554 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
984263bc
MD
2555 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2556 ifp->if_opackets++;
2557 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
ddca511d 2558 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
20c9a969 2559 sc->bge_cdata.bge_tx_dmamap[idx]);
984263bc
MD
2560 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2561 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2562 }
2563 sc->bge_txcnt--;
2564 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
6b880771 2565 logif(tx_pkt);
984263bc
MD
2566 }
2567
20c9a969
SZ
2568 if (cur_tx != NULL &&
2569 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2570 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
984263bc 2571 ifp->if_flags &= ~IFF_OACTIVE;
20c9a969 2572
142ca760
SZ
2573 if (sc->bge_txcnt == 0)
2574 ifp->if_timer = 0;
2575
20c9a969 2576 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 2577 if_devstart(ifp);
984263bc
MD
2578}
2579
315fe0ee
MD
2580#ifdef DEVICE_POLLING
2581
2582static void
2583bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2584{
2585 struct bge_softc *sc = ifp->if_softc;
2586 uint32_t status;
2587
2588 switch(cmd) {
2589 case POLL_REGISTER:
ba39cc82 2590 bge_disable_intr(sc);
315fe0ee
MD
2591 break;
2592 case POLL_DEREGISTER:
ba39cc82 2593 bge_enable_intr(sc);
315fe0ee
MD
2594 break;
2595 case POLL_AND_CHECK_STATUS:
315fe0ee
MD
2596 /*
2597 * Process link state changes.
2598 */
2599 status = CSR_READ_4(sc, BGE_MAC_STS);
2600 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2601 sc->bge_link_evt = 0;
2602 sc->bge_link_upd(sc, status);
2603 }
2604 /* fall through */
2605 case POLL_ONLY:
2606 if (ifp->if_flags & IFF_RUNNING) {
2607 bge_rxeof(sc);
2608 bge_txeof(sc);
2609 }
2610 break;
2611 }
2612}
2613
2614#endif
2615
984263bc 2616static void
33c39a69 2617bge_intr(void *xsc)
984263bc 2618{
bf522c7f 2619 struct bge_softc *sc = xsc;
33c39a69 2620 struct ifnet *ifp = &sc->arpcom.ac_if;
6b880771
SZ
2621 uint32_t status;
2622
2623 logif(intr);
0029ccf6 2624
142ca760
SZ
2625 /*
2626 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2627 * disable interrupts by writing nonzero like we used to, since with
2628 * our current organization this just gives complications and
2629 * pessimizations for re-enabling interrupts. We used to have races
2630 * instead of the necessary complications. Disabling interrupts
2631 * would just reduce the chance of a status update while we are
2632 * running (by switching to the interrupt-mode coalescence
2633 * parameters), but this chance is already very low so it is more
2634 * efficient to get another interrupt than prevent it.
2635 *
2636 * We do the ack first to ensure another interrupt if there is a
2637 * status update after the ack. We don't check for the status
2638 * changing later because it is more efficient to get another
2639 * interrupt than prevent it, not quite as above (not checking is
2640 * a smaller optimization than not toggling the interrupt enable,
2641 * since checking doesn't involve PCI accesses and toggling require
2642 * the status check). So toggling would probably be a pessimization
2643 * even with MSI. It would only be needed for using a task queue.
2644 */
591dfc77 2645 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
142ca760 2646
984263bc
MD
2647 /*
2648 * Process link state changes.
984263bc 2649 */
db861466
SZ
2650 status = CSR_READ_4(sc, BGE_MAC_STS);
2651 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2652 sc->bge_link_evt = 0;
2653 sc->bge_link_upd(sc, status);
984263bc
MD
2654 }
2655
2656 if (ifp->if_flags & IFF_RUNNING) {
2657 /* Check RX return ring producer/consumer */
2658 bge_rxeof(sc);
2659
2660 /* Check TX ring producer/consumer */
2661 bge_txeof(sc);
2662 }
055d06f0
SZ
2663
2664 if (sc->bge_coal_chg)
2665 bge_coal_change(sc);
984263bc
MD
2666}
2667
2668static void
33c39a69 2669bge_tick(void *xsc)
984263bc 2670{
33c39a69
JS
2671 struct bge_softc *sc = xsc;
2672 struct ifnet *ifp = &sc->arpcom.ac_if;
78195a76
MD
2673
2674 lwkt_serialize_enter(ifp->if_serializer);
984263bc 2675
0ecb11d7 2676 if (BGE_IS_5705_PLUS(sc))
7e40b8c5
HP
2677 bge_stats_update_regs(sc);
2678 else
2679 bge_stats_update(sc);
9a717c15 2680
0ecb11d7 2681 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
2682 /*
2683 * Since in TBI mode auto-polling can't be used we should poll
2684 * link status manually. Here we register pending link event
2685 * and trigger interrupt.
2686 */
2687 sc->bge_link_evt++;
2688 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3f82ed83 2689 } else if (!sc->bge_link) {
db861466 2690 mii_tick(device_get_softc(sc->bge_miibus));
984263bc
MD
2691 }
2692
db861466
SZ
2693 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2694
2695 lwkt_serialize_exit(ifp->if_serializer);
984263bc
MD
2696}
2697
2698static void
33c39a69 2699bge_stats_update_regs(struct bge_softc *sc)
7e40b8c5 2700{
33c39a69 2701 struct ifnet *ifp = &sc->arpcom.ac_if;
7e40b8c5 2702 struct bge_mac_stats_regs stats;
33c39a69 2703 uint32_t *s;
7e40b8c5
HP
2704 int i;
2705
33c39a69 2706 s = (uint32_t *)&stats;
7e40b8c5
HP
2707 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2708 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2709 s++;
2710 }
2711
2712 ifp->if_collisions +=
2713 (stats.dot3StatsSingleCollisionFrames +
2714 stats.dot3StatsMultipleCollisionFrames +
2715 stats.dot3StatsExcessiveCollisions +
2716 stats.dot3StatsLateCollisions) -
2717 ifp->if_collisions;
7e40b8c5
HP
2718}
2719
2720static void
33c39a69 2721bge_stats_update(struct bge_softc *sc)
984263bc 2722{
33c39a69 2723 struct ifnet *ifp = &sc->arpcom.ac_if;
20c9a969
SZ
2724 bus_size_t stats;
2725
2726 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
984263bc 2727
20c9a969
SZ
2728#define READ_STAT(sc, stats, stat) \
2729 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
984263bc
MD
2730
2731 ifp->if_collisions +=
20c9a969
SZ
2732 (READ_STAT(sc, stats,
2733 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2734 READ_STAT(sc, stats,
2735 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2736 READ_STAT(sc, stats,
2737 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2738 READ_STAT(sc, stats,
2739 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
984263bc
MD
2740 ifp->if_collisions;
2741
20c9a969
SZ
2742#undef READ_STAT
2743
984263bc
MD
2744#ifdef notdef
2745 ifp->if_collisions +=
2746 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2747 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2748 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2749 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2750 ifp->if_collisions;
2751#endif
984263bc
MD
2752}
2753
2754/*
2755 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2756 * pointers to descriptors.
2757 */
2758static int
4a607ed6 2759bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
984263bc 2760{
20c9a969 2761 struct bge_tx_bd *d = NULL;
33c39a69 2762 uint16_t csum_flags = 0;
20c9a969
SZ
2763 bus_dma_segment_t segs[BGE_NSEG_NEW];
2764 bus_dmamap_t map;
2de621e9 2765 int error, maxsegs, nsegs, idx, i;
4a607ed6 2766 struct mbuf *m_head = *m_head0;
984263bc 2767
984263bc
MD
2768 if (m_head->m_pkthdr.csum_flags) {
2769 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2770 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2771 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2772 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2773 if (m_head->m_flags & M_LASTFRAG)
2774 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2775 else if (m_head->m_flags & M_FRAG)
2776 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2777 }
20c9a969
SZ
2778
2779 idx = *txidx;
2780 map = sc->bge_cdata.bge_tx_dmamap[idx];
2781
2782 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2783 KASSERT(maxsegs >= BGE_NSEG_SPARE,
ed20d0e3 2784 ("not enough segments %d", maxsegs));
20c9a969
SZ
2785
2786 if (maxsegs > BGE_NSEG_NEW)
2787 maxsegs = BGE_NSEG_NEW;
2788
cb623c48
SZ
2789 /*
2790 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2791 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2792 * but when such padded frames employ the bge IP/TCP checksum
2793 * offload, the hardware checksum assist gives incorrect results
2794 * (possibly from incorporating its own padding into the UDP/TCP
2795 * checksum; who knows). If we pad such runts with zeros, the
2679514c 2796 * onboard checksum comes out correct.
cb623c48
SZ
2797 */
2798 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2799 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
cf12ba3c 2800 error = m_devpad(m_head, BGE_MIN_FRAME);
2679514c
SZ
2801 if (error)
2802 goto back;
cb623c48 2803 }
2679514c 2804
2de621e9
SZ
2805 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
2806 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2807 if (error)
20c9a969 2808 goto back;
984263bc 2809
2de621e9 2810 m_head = *m_head0;
ddca511d 2811 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
984263bc 2812
20c9a969
SZ
2813 for (i = 0; ; i++) {
2814 d = &sc->bge_ldata.bge_tx_ring[idx];
984263bc 2815
2de621e9
SZ
2816 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2817 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
20c9a969
SZ
2818 d->bge_len = segs[i].ds_len;
2819 d->bge_flags = csum_flags;
984263bc 2820
2de621e9 2821 if (i == nsegs - 1)
20c9a969
SZ
2822 break;
2823 BGE_INC(idx, BGE_TX_RING_CNT);
2824 }
2825 /* Mark the last segment as end of packet... */
2826 d->bge_flags |= BGE_TXBDFLAG_END;
984263bc 2827
20c9a969
SZ
2828 /* Set vlan tag to the first segment of the packet. */
2829 d = &sc->bge_ldata.bge_tx_ring[*txidx];
83790f85 2830 if (m_head->m_flags & M_VLANTAG) {
20c9a969 2831 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
83790f85 2832 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
20c9a969
SZ
2833 } else {
2834 d->bge_vlan_tag = 0;
2835 }
2836
2837 /*
2838 * Insure that the map for this transmission is placed at
2839 * the array index of the last descriptor in this chain.
2840 */
2841 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2842 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2843 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2de621e9 2844 sc->bge_txcnt += nsegs;
20c9a969
SZ
2845
2846 BGE_INC(idx, BGE_TX_RING_CNT);
2847 *txidx = idx;
2848back:
4a607ed6 2849 if (error) {
2de621e9 2850 m_freem(*m_head0);
4a607ed6
SZ
2851 *m_head0 = NULL;
2852 }
20c9a969 2853 return error;
984263bc
MD
2854}
2855
2856/*
2857 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2858 * to the mbuf data regions directly in the transmit descriptors.
2859 */
2860static void
33c39a69 2861bge_start(struct ifnet *ifp)
984263bc 2862{
20c9a969 2863 struct bge_softc *sc = ifp->if_softc;
984263bc 2864 struct mbuf *m_head = NULL;
20c9a969 2865 uint32_t prodidx;
2f54d1d2 2866 int need_trans;
984263bc 2867
d47d96f2 2868 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
984263bc
MD
2869 return;
2870
94db8384 2871 prodidx = sc->bge_tx_prodidx;
984263bc 2872
2f54d1d2 2873 need_trans = 0;
75544bcd 2874 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
9db4b353 2875 m_head = ifq_dequeue(&ifp->if_snd, NULL);
984263bc
MD
2876 if (m_head == NULL)
2877 break;
2878
2879 /*
2880 * XXX
cb623c48
SZ
2881 * The code inside the if() block is never reached since we
2882 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2883 * requests to checksum TCP/UDP in a fragmented packet.
2884 *
2885 * XXX
984263bc
MD
2886 * safety overkill. If this is a fragmented packet chain
2887 * with delayed TCP/UDP checksums, then only encapsulate
2888 * it if we have enough descriptors to handle the entire
2889 * chain at once.
2890 * (paranoia -- may not actually be needed)
2891 */
9db4b353
SZ
2892 if ((m_head->m_flags & M_FIRSTFRAG) &&
2893 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
984263bc 2894 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
9db4b353 2895 m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
984263bc 2896 ifp->if_flags |= IFF_OACTIVE;
9db4b353 2897 ifq_prepend(&ifp->if_snd, m_head);
984263bc
MD
2898 break;
2899 }
2900 }
2901
2902 /*
20c9a969
SZ
2903 * Sanity check: avoid coming within BGE_NSEG_RSVD
2904 * descriptors of the end of the ring. Also make
2905 * sure there are BGE_NSEG_SPARE descriptors for
2906 * jumbo buffers' defragmentation.
2907 */
2908 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2909 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2910 ifp->if_flags |= IFF_OACTIVE;
9db4b353 2911 ifq_prepend(&ifp->if_snd, m_head);
20c9a969
SZ
2912 break;
2913 }
2914
2915 /*
984263bc
MD
2916 * Pack the data into the transmit ring. If we
2917 * don't have room, set the OACTIVE flag and wait
2918 * for the NIC to drain the ring.
2919 */
4a607ed6 2920 if (bge_encap(sc, &m_head, &prodidx)) {
984263bc 2921 ifp->if_flags |= IFF_OACTIVE;
2679514c 2922 ifp->if_oerrors++;
984263bc
MD
2923 break;
2924 }
2f54d1d2 2925 need_trans = 1;
984263bc 2926
b637f170 2927 ETHER_BPF_MTAP(ifp, m_head);
984263bc
MD
2928 }
2929
2f54d1d2
SZ
2930 if (!need_trans)
2931 return;
2932
984263bc 2933 /* Transmit */
591dfc77 2934 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
984263bc
MD
2935 /* 5700 b2 errata */
2936 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
591dfc77 2937 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
984263bc 2938
94db8384
SZ
2939 sc->bge_tx_prodidx = prodidx;
2940
984263bc
MD
2941 /*
2942 * Set a timeout in case the chip goes out to lunch.
2943 */
2944 ifp->if_timer = 5;
984263bc
MD
2945}
2946
2947static void
33c39a69 2948bge_init(void *xsc)
984263bc
MD
2949{
2950 struct bge_softc *sc = xsc;
33c39a69
JS
2951 struct ifnet *ifp = &sc->arpcom.ac_if;
2952 uint16_t *m;
984263bc 2953
aa65409c
SZ
2954 ASSERT_SERIALIZED(ifp->if_serializer);
2955
2956 if (ifp->if_flags & IFF_RUNNING)
984263bc 2957 return;
984263bc
MD
2958
2959 /* Cancel pending I/O and flush buffers. */
2960 bge_stop(sc);
2961 bge_reset(sc);
2962 bge_chipinit(sc);
2963
2964 /*
2965 * Init the various state machines, ring
2966 * control blocks and firmware.
2967 */
2968 if (bge_blockinit(sc)) {
c6fd6f3b 2969 if_printf(ifp, "initialization failure\n");
1436f9a0 2970 bge_stop(sc);
984263bc
MD
2971 return;
2972 }
2973
984263bc
MD
2974 /* Specify MTU. */
2975 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
011c0f93 2976 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
984263bc
MD
2977
2978 /* Load our MAC address. */
33c39a69 2979 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
984263bc
MD
2980 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2981 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2982
2983 /* Enable or disable promiscuous mode as needed. */
6439b28a 2984 bge_setpromisc(sc);
984263bc
MD
2985
2986 /* Program multicast filter. */
2987 bge_setmulti(sc);
2988
2989 /* Init RX ring. */
1436f9a0
SZ
2990 if (bge_init_rx_ring_std(sc)) {
2991 if_printf(ifp, "RX ring initialization failed\n");
2992 bge_stop(sc);
2993 return;
2994 }
984263bc 2995
7e40b8c5
HP
2996 /*
2997 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2998 * memory to insure that the chip has in fact read the first
2999 * entry of the ring.
3000 */
3001 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
33c39a69 3002 uint32_t v, i;
7e40b8c5
HP
3003 for (i = 0; i < 10; i++) {
3004 DELAY(20);
3005 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3006 if (v == (MCLBYTES - ETHER_ALIGN))
3007 break;
3008 }
3009 if (i == 10)
c6fd6f3b 3010 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
7e40b8c5
HP
3011 }
3012
984263bc 3013 /* Init jumbo RX ring. */
1436f9a0
SZ
3014 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3015 if (bge_init_rx_ring_jumbo(sc)) {
3016 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3017 bge_stop(sc);
3018 return;
3019 }
3020 }
984263bc
MD
3021
3022 /* Init our RX return ring index */
3023 sc->bge_rx_saved_considx = 0;
3024
3025 /* Init TX ring. */
3026 bge_init_tx_ring(sc);
3027
3028 /* Turn on transmitter */
3029 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
3030
3031 /* Turn on receiver */
3032 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3033
3034 /* Tell firmware we're alive. */
3035 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3036
ba39cc82 3037 /* Enable host interrupts if polling(4) is not enabled. */
984263bc 3038 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
315fe0ee 3039#ifdef DEVICE_POLLING
ba39cc82
SZ
3040 if (ifp->if_flags & IFF_POLLING)
3041 bge_disable_intr(sc);
3042 else
315fe0ee 3043#endif
ba39cc82 3044 bge_enable_intr(sc);
984263bc
MD
3045
3046 bge_ifmedia_upd(ifp);
3047
3048 ifp->if_flags |= IFF_RUNNING;
3049 ifp->if_flags &= ~IFF_OACTIVE;
3050
263489fb 3051 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
984263bc
MD
3052}
3053
3054/*
3055 * Set media options.
3056 */
3057static int
33c39a69 3058bge_ifmedia_upd(struct ifnet *ifp)
984263bc 3059{
33c39a69 3060 struct bge_softc *sc = ifp->if_softc;
984263bc
MD
3061
3062 /* If this is a 1000baseX NIC, enable the TBI port. */
0ecb11d7 3063 if (sc->bge_flags & BGE_FLAG_TBI) {
db861466
SZ
3064 struct ifmedia *ifm = &sc->bge_ifmedia;
3065
984263bc
MD
3066 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3067 return(EINVAL);
db861466 3068
984263bc
MD
3069 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3070 case IFM_AUTO:
70059b3c
JS
3071 /*
3072 * The BCM5704 ASIC appears to have a special
3073 * mechanism for programming the autoneg
3074 * advertisement registers in TBI mode.
3075 */
5c56d5d8
SZ
3076 if (!bge_fake_autoneg &&
3077 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
70059b3c
JS
3078 uint32_t sgdig;
3079
3080 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3081 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3082 sgdig |= BGE_SGDIGCFG_AUTO |
3083 BGE_SGDIGCFG_PAUSE_CAP |
3084 BGE_SGDIGCFG_ASYM_PAUSE;
3085 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3086 sgdig | BGE_SGDIGCFG_SEND);
3087 DELAY(5);
3088 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3089 }
984263bc
MD
3090 break;
3091 case IFM_1000_SX:
3092 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3093 BGE_CLRBIT(sc, BGE_MAC_MODE,
3094 BGE_MACMODE_HALF_DUPLEX);
3095 } else {
3096 BGE_SETBIT(sc, BGE_MAC_MODE,
3097 BGE_MACMODE_HALF_DUPLEX);
3098 }
3099 break;
3100 default:
3101 return(EINVAL);
3102 }
db861466
SZ
3103 } else {
3104 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 3105
db861466 3106 sc->bge_link_evt++;
3f82ed83 3107 sc->bge_link = 0;
db861466
SZ
3108 if (mii->mii_instance) {
3109 struct mii_softc *miisc;
984263bc 3110
db861466
SZ
3111 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3112 mii_phy_reset(miisc);
3113 }
3114 mii_mediachg(mii);
3115 }
984263bc
MD
3116 return(0);
3117}
3118
3119/*
3120 * Report current media status.
3121 */
3122static void
33c39a69 3123bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
984263bc 3124{
33c39a69 3125 struct bge_softc *sc = ifp->if_softc;
984263bc 3126
0ecb11d7 3127 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
3128 ifmr->ifm_status = IFM_AVALID;
3129 ifmr->ifm_active = IFM_ETHER;
3130 if (CSR_READ_4(sc, BGE_MAC_STS) &
db861466 3131 BGE_MACSTAT_TBI_PCS_SYNCHED) {
984263bc 3132 ifmr->ifm_status |= IFM_ACTIVE;
db861466
SZ
3133 } else {
3134 ifmr->ifm_active |= IFM_NONE;
3135 return;
3136 }
3137
984263bc
MD
3138 ifmr->ifm_active |= IFM_1000_SX;
3139 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3140 ifmr->ifm_active |= IFM_HDX;
3141 else
3142 ifmr->ifm_active |= IFM_FDX;
db861466
SZ
3143 } else {
3144 struct mii_data *mii = device_get_softc(sc->bge_miibus);
984263bc 3145
db861466
SZ
3146 mii_pollstat(mii);
3147 ifmr->ifm_active = mii->mii_media_active;
3148 ifmr->ifm_status = mii->mii_media_status;
3149 }
984263bc
MD
3150}
3151
3152static int
33c39a69 3153bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
984263bc
MD
3154{
3155 struct bge_softc *sc = ifp->if_softc;
98dabdac 3156 struct ifreq *ifr = (struct ifreq *)data;
9a717c15 3157 int mask, error = 0;
984263bc 3158
aa65409c
SZ
3159 ASSERT_SERIALIZED(ifp->if_serializer);
3160
98dabdac 3161 switch (command) {
984263bc 3162 case SIOCSIFMTU:
0ecb11d7
SZ
3163 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3164 (BGE_IS_JUMBO_CAPABLE(sc) &&
3165 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
984263bc 3166 error = EINVAL;
0ecb11d7 3167 } else if (ifp->if_mtu != ifr->ifr_mtu) {
984263bc
MD
3168 ifp->if_mtu = ifr->ifr_mtu;
3169 ifp->if_flags &= ~IFF_RUNNING;
3170 bge_init(sc);
3171 }
3172 break;
3173 case SIOCSIFFLAGS:
3174 if (ifp->if_flags & IFF_UP) {
6439b28a 3175 if (ifp->if_flags & IFF_RUNNING) {
98dabdac 3176 mask = ifp->if_flags ^ sc->bge_if_flags;
6439b28a
SZ
3177
3178 /*
3179 * If only the state of the PROMISC flag
3180 * changed, then just use the 'set promisc
3181 * mode' command instead of reinitializing
3182 * the entire NIC. Doing a full re-init
3183 * means reloading the firmware and waiting
3184 * for it to start up, which may take a
3185 * second or two. Similarly for ALLMULTI.
3186 */
98dabdac 3187 if (mask & IFF_PROMISC)
6439b28a 3188 bge_setpromisc(sc);
98dabdac 3189 if (mask & IFF_ALLMULTI)
6439b28a
SZ
3190 bge_setmulti(sc);
3191 } else {
984263bc 3192 bge_init(sc);
6439b28a 3193 }
984263bc 3194 } else {
aa65409c 3195 if (ifp->if_flags & IFF_RUNNING)
984263bc 3196 bge_stop(sc);
984263bc
MD
3197 }
3198 sc->bge_if_flags = ifp->if_flags;
984263bc
MD
3199 break;
3200 case SIOCADDMULTI:
3201 case SIOCDELMULTI:
98dabdac 3202 if (ifp->if_flags & IFF_RUNNING)
984263bc 3203 bge_setmulti(sc);
984263bc
MD
3204 break;
3205 case SIOCSIFMEDIA:
3206 case SIOCGIFMEDIA:
0ecb11d7 3207 if (sc->bge_flags & BGE_FLAG_TBI) {
984263bc
MD
3208 error = ifmedia_ioctl(ifp, ifr,
3209 &sc->bge_ifmedia, command);
3210 } else {
98dabdac
SZ
3211 struct mii_data *mii;
3212
984263bc
MD
3213 mii = device_get_softc(sc->bge_miibus);
3214 error = ifmedia_ioctl(ifp, ifr,
98dabdac 3215 &mii->mii_media, command);
984263bc
MD
3216 }
3217 break;
3218 case SIOCSIFCAP:
3219 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3220 if (mask & IFCAP_HWCSUM) {
71e2c3e7 3221 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
984263bc 3222 if (IFCAP_HWCSUM & ifp->if_capenable)
cb623c48 3223 ifp->if_hwassist = BGE_CSUM_FEATURES;
984263bc 3224 else
cb623c48 3225 ifp->if_hwassist = 0;
984263bc 3226 }
984263bc
MD
3227 break;
3228 default:
4cde4dd5 3229 error = ether_ioctl(ifp, command, data);
984263bc
MD
3230 break;
3231 }
98dabdac 3232 return error;
984263bc
MD
3233}
3234
3235static void
33c39a69 3236bge_watchdog(struct ifnet *ifp)
984263bc 3237{
33c39a69 3238 struct bge_softc *sc = ifp->if_softc;
984263bc 3239
c6fd6f3b 3240 if_printf(ifp, "watchdog timeout -- resetting\n");
984263bc
MD
3241
3242 ifp->if_flags &= ~IFF_RUNNING;
3243 bge_init(sc);
3244
3245 ifp->if_oerrors++;
2f54d1d2
SZ
3246
3247 if (!ifq_is_empty(&ifp->if_snd))
9db4b353 3248 if_devstart(ifp);
984263bc
MD
3249}
3250
3251/*
3252 * Stop the adapter and free any mbufs allocated to the
3253 * RX and TX lists.
3254 */
3255static void
33c39a69 3256bge_stop(struct bge_softc *sc)
984263bc 3257{
33c39a69 3258 struct ifnet *ifp = &sc->arpcom.ac_if;
984263bc 3259
aa65409c
SZ
3260 ASSERT_SERIALIZED(ifp->if_serializer);
3261
263489fb 3262 callout_stop(&sc->bge_stat_timer);
984263bc
MD
3263
3264 /*
3265 * Disable all of the receiver blocks
3266 */
3267 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3268 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3269 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
0ecb11d7 3270 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3271 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
984263bc
MD
3272 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3273 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3274 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3275
3276 /*
3277 * Disable all of the transmit blocks
3278 */
3279 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3280 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3281 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3282 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3283 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
0ecb11d7 3284 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3285 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
984263bc
MD
3286 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3287
3288 /*
3289 * Shut down all of the memory managers and related
3290 * state machines.
3291 */
3292 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3293 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
0ecb11d7 3294 if (!BGE_IS_5705_PLUS(sc))
7e40b8c5 3295 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
984263bc
MD
3296 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3297 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
0ecb11d7 3298 if (!BGE_IS_5705_PLUS(sc)) {
7e40b8c5
HP
3299 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3300 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3301 }
984263bc
MD
3302
3303 /* Disable host interrupts. */
ba39cc82 3304 bge_disable_intr(sc);
984263bc
MD
3305