twa(4): Sync with FreeBSD (twa(4) version 3.80.06.003).
[dragonfly.git] / sys / dev / raid / twa / tw_cl_fwif.h
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1/*
2 * Copyright (c) 2004-07 Applied Micro Circuits Corporation.
3 * Copyright (c) 2004-05 Vinod Kashyap
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
4fbf05f9 27 * $FreeBSD: src/sys/dev/twa/tw_cl_fwif.h,v 1.5 2010/08/30 19:15:04 delphij Exp $
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28 */
29
30/*
31 * AMCC'S 3ware driver for 9000 series storage controllers.
32 *
33 * Author: Vinod Kashyap
34 * Modifications by: Adam Radford
35 */
36
37
38
39#ifndef TW_CL_FWIF_H
40
41#define TW_CL_FWIF_H
42
43
44/*
45 * Macros and data structures for interfacing with the firmware.
46 */
47
48
49/* Register offsets from base address. */
50#define TWA_CONTROL_REGISTER_OFFSET 0x0
51#define TWA_STATUS_REGISTER_OFFSET 0x4
52#define TWA_COMMAND_QUEUE_OFFSET 0x8
53#define TWA_RESPONSE_QUEUE_OFFSET 0xC
54#define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20
55#define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24
56#define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30
57
58
59/* Control register bit definitions. */
60#define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
61#define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040
62#define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080
63#define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100
64#define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
65#define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
66#define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
67#define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
68#define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
69#define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
70#define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000
71#define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
72#define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000
73
74
75/* Status register bit definitions. */
76#define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002
77#define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
78#define TWA_STATUS_MICROCONTROLLER_READY 0x00002000
79#define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
80#define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000
81#define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000
82#define TWA_STATUS_COMMAND_INTERRUPT 0x00020000
83#define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000
84#define TWA_STATUS_HOST_INTERRUPT 0x00080000
85#define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000
86#define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000
87#define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000
88#define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000
89#define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000
90#define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000
91
4fbf05f9 92#define TWA_STATUS_UNEXPECTED_BITS 0x00D00000
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93
94
95/* PCI related defines. */
96#define TWA_IO_CONFIG_REG 0x10
97
98#define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100
99#define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000
100
101#define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF
102#define TWA_RESET_PHASE1_WAIT_TIME_MS 500
103
104
105/* Command packet opcodes. */
106#define TWA_FW_CMD_NOP 0x00
107#define TWA_FW_CMD_INIT_CONNECTION 0x01
108#define TWA_FW_CMD_READ 0x02
109#define TWA_FW_CMD_WRITE 0x03
110#define TWA_FW_CMD_READVERIFY 0x04
111#define TWA_FW_CMD_VERIFY 0x05
112#define TWA_FW_CMD_ZEROUNIT 0x08
113#define TWA_FW_CMD_REPLACEUNIT 0x09
114#define TWA_FW_CMD_HOTSWAP 0x0A
115#define TWA_FW_CMD_SELFTESTS 0x0B
116#define TWA_FW_CMD_SYNC_PARAM 0x0C
117#define TWA_FW_CMD_REORDER_UNITS 0x0D
118
119#define TWA_FW_CMD_EXECUTE_SCSI 0x10
120#define TWA_FW_CMD_ATA_PASSTHROUGH 0x11
121#define TWA_FW_CMD_GET_PARAM 0x12
122#define TWA_FW_CMD_SET_PARAM 0x13
123#define TWA_FW_CMD_CREATEUNIT 0x14
124#define TWA_FW_CMD_DELETEUNIT 0x15
125#define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16
126#define TWA_FW_CMD_REBUILDUNIT 0x17
127#define TWA_FW_CMD_POWER_MANAGEMENT 0x18
128
129#define TWA_FW_CMD_REMOTE_PRINT 0x1B
130#define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C
131#define TWA_FW_CMD_DEBUG 0x1D
132
133#define TWA_FW_CMD_DIAGNOSTICS 0x1F
134
135
136/* Misc defines. */
137#define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001
138#define TWA_64BIT_SG_ADDRESSES 0x00000001
139#define TWA_EXTENDED_INIT_CONNECT 0x00000002
140#define TWA_BASE_MODE 1
141#define TWA_BASE_FW_SRL 24
142#define TWA_BASE_FW_BRANCH 0
143#define TWA_BASE_FW_BUILD 1
144#define TWA_CURRENT_FW_SRL 41
145#define TWA_CURRENT_FW_BRANCH_9K 4
146#define TWA_CURRENT_FW_BUILD_9K 8
147#define TWA_CURRENT_FW_BRANCH_9K_X 8
148#define TWA_CURRENT_FW_BUILD_9K_X 4
149#define TWA_MULTI_LUN_FW_SRL 28
150#define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */
151#define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */
152#define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001
153#define TWA_CTLR_FW_COMPATIBLE 0x00000002
154#define TWA_SENSE_DATA_LENGTH 18
155
156
157#define TWA_ARCH_ID(device_id) \
158 (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \
159 TWA_ARCH_ID_9K_X)
160#define TWA_CURRENT_FW_BRANCH(arch_id) \
161 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \
162 TWA_CURRENT_FW_BRANCH_9K_X)
163#define TWA_CURRENT_FW_BUILD(arch_id) \
164 (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \
165 TWA_CURRENT_FW_BUILD_9K_X)
166
167/*
168 * All SG addresses and DMA'able memory allocated by the OSL should be
169 * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of
170 * TWA_SG_ELEMENT_SIZE_FACTOR.
171 */
172#define TWA_ALIGNMENT(device_id) 0x4
173#define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \
174 (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4)
175
176
177/*
178 * Some errors of interest (in cmd_hdr->status_block.error) when a command
179 * is completed by the firmware with a bad status.
180 */
181#define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a
182#define TWA_ERROR_UNIT_OFFLINE 0x0128
183#define TWA_ERROR_MORE_DATA 0x0231
184
185
186/* AEN codes of interest. */
187#define TWA_AEN_QUEUE_EMPTY 0x00
188#define TWA_AEN_SOFT_RESET 0x01
189#define TWA_AEN_SYNC_TIME_WITH_HOST 0x31
190
191
192/* Table #'s and id's of parameters of interest in firmware's param table. */
193#define TWA_PARAM_VERSION_TABLE 0x0402
194#define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */
195#define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
196#define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */
197
198#define TWA_PARAM_CONTROLLER_TABLE 0x0403
199#define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */
200
201#define TWA_PARAM_TIME_TABLE 0x40A
202#define TWA_PARAM_TIME_SCHED_TIME 0x3
203
204#define TWA_9K_PARAM_DESCRIPTOR 0x8000
205
206
207#pragma pack(1)
208/* 7000 structures. */
209struct tw_cl_command_init_connect {
210 TW_UINT8 res1__opcode; /* 3:5 */
211 TW_UINT8 size;
212 TW_UINT8 request_id;
213 TW_UINT8 res2;
214 TW_UINT8 status;
215 TW_UINT8 flags;
216 TW_UINT16 message_credits;
217 TW_UINT32 features;
218 TW_UINT16 fw_srl;
219 TW_UINT16 fw_arch_id;
220 TW_UINT16 fw_branch;
221 TW_UINT16 fw_build;
222 TW_UINT32 result;
223};
224
225
226/* Structure for downloading firmware onto the controller. */
227struct tw_cl_command_download_firmware {
228 TW_UINT8 sgl_off__opcode;/* 3:5 */
229 TW_UINT8 size;
230 TW_UINT8 request_id;
231 TW_UINT8 unit;
232 TW_UINT8 status;
233 TW_UINT8 flags;
234 TW_UINT16 param;
235 TW_UINT8 sgl[1];
236};
237
238
239/* Structure for hard resetting the controller. */
240struct tw_cl_command_reset_firmware {
241 TW_UINT8 res1__opcode; /* 3:5 */
242 TW_UINT8 size;
243 TW_UINT8 request_id;
244 TW_UINT8 unit;
245 TW_UINT8 status;
246 TW_UINT8 flags;
247 TW_UINT8 res2;
248 TW_UINT8 param;
249};
250
251
252/* Structure for sending get/set param commands. */
253struct tw_cl_command_param {
254 TW_UINT8 sgl_off__opcode;/* 3:5 */
255 TW_UINT8 size;
256 TW_UINT8 request_id;
257 TW_UINT8 host_id__unit; /* 4:4 */
258 TW_UINT8 status;
259 TW_UINT8 flags;
260 TW_UINT16 param_count;
261 TW_UINT8 sgl[1];
262};
263
264
265/* Generic command packet. */
266struct tw_cl_command_generic {
267 TW_UINT8 sgl_off__opcode;/* 3:5 */
268 TW_UINT8 size;
269 TW_UINT8 request_id;
270 TW_UINT8 host_id__unit; /* 4:4 */
271 TW_UINT8 status;
272 TW_UINT8 flags;
273 TW_UINT16 count; /* block cnt, parameter cnt, message credits */
274};
275
276
277/* Command packet header. */
278struct tw_cl_command_header {
279 TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH];
280 struct {
281 TW_INT8 reserved[4];
282 TW_UINT16 error;
283 TW_UINT8 padding;
284 TW_UINT8 res__severity; /* 5:3 */
285 } status_block;
286 TW_UINT8 err_specific_desc[98];
287 struct {
288 TW_UINT8 size_header;
289 TW_UINT16 reserved;
290 TW_UINT8 size_sense;
291 } header_desc;
292};
293
294
295/* 7000 Command packet. */
296union tw_cl_command_7k {
297 struct tw_cl_command_init_connect init_connect;
298 struct tw_cl_command_download_firmware download_fw;
299 struct tw_cl_command_reset_firmware reset_fw;
300 struct tw_cl_command_param param;
301 struct tw_cl_command_generic generic;
302 TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)];
303};
304
305
306/* 9000 Command Packet. */
307struct tw_cl_command_9k {
308 TW_UINT8 res__opcode; /* 3:5 */
309 TW_UINT8 unit;
310 TW_UINT16 lun_l4__req_id; /* 4:12 */
311 TW_UINT8 status;
312 TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the
313 end of sgl_entries */
314 TW_UINT16 lun_h4__sgl_entries;
315 TW_UINT8 cdb[16];
316 TW_UINT8 sg_list[872];/* total struct size =
317 1024-sizeof(cmd_hdr) */
318};
319
320
321/* Full command packet. */
322struct tw_cl_command_packet {
323 struct tw_cl_command_header cmd_hdr;
324 union {
325 union tw_cl_command_7k cmd_pkt_7k;
326 struct tw_cl_command_9k cmd_pkt_9k;
327 } command;
328};
329
330
331/* Structure describing payload for get/set param commands. */
332struct tw_cl_param_9k {
333 TW_UINT16 table_id;
334 TW_UINT8 parameter_id;
335 TW_UINT8 reserved;
336 TW_UINT16 parameter_size_bytes;
337 TW_UINT16 parameter_actual_size_bytes;
338 TW_UINT8 data[1];
339};
340#pragma pack()
341
342
343/* Functions to read from, and write to registers */
344#define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \
345 tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4)
346
347
348#define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \
349 tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4)
350
351
352#define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \
353 if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \
354 /* First write the low 4 bytes, then the high 4. */ \
355 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \
356 (TW_UINT32)(value), 4); \
357 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
358 (TW_UINT32)(((TW_UINT64)value)>>32), 4); \
359 } else \
360 tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \
361 (TW_UINT32)(value), 4); \
362} while (0)
363
364
365#define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \
366 tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4)
367
368
369#define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \
370 tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4)
371
372
373#define TW_CLI_SOFT_RESET(ctlr) \
374 TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \
375 TWA_CONTROL_ISSUE_SOFT_RESET | \
376 TWA_CONTROL_CLEAR_HOST_INTERRUPT | \
377 TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
378 TWA_CONTROL_MASK_COMMAND_INTERRUPT | \
379 TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \
380 TWA_CONTROL_DISABLE_INTERRUPTS)
381
382/* Detect inconsistencies in the status register. */
383#define TW_CLI_STATUS_ERRORS(x) \
384 ((x & TWA_STATUS_UNEXPECTED_BITS) && \
385 (x & TWA_STATUS_MICROCONTROLLER_READY))
386
387
388/*
389 * Functions for making transparent, the bit fields in firmware
390 * interface structures.
391 */
392#define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \
393 ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
394
395#define BUILD_RES__OPCODE(res, opcode) \
396 ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */
397
398#define BUILD_HOST_ID__UNIT(host_id, unit) \
399 ((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */
400
401#define BUILD_RES__SEVERITY(res, severity) \
402 ((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */
403
404#define BUILD_LUN_L4__REQ_ID(lun, req_id) \
405 (((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */
406
407#define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \
408 (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */
409
410
411#define GET_OPCODE(sgl_off__opcode) \
412 (sgl_off__opcode & 0x1F) /* 3:5 */
413
414#define GET_SGL_OFF(sgl_off__opcode) \
415 ((sgl_off__opcode >> 5) & 0x7) /* 3:5 */
416
417#define GET_UNIT(host_id__unit) \
418 (host_id__unit & 0xF) /* 4:4 */
419
420#define GET_HOST_ID(host_id__unit) \
421 ((host_id__unit >> 4) & 0xF) /* 4:4 */
422
423#define GET_SEVERITY(res__severity) \
424 (res__severity & 0x7) /* 5:3 */
425
426#define GET_RESP_ID(undef2__resp_id__undef1) \
427 ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */
428
429#define GET_RESP_ID_9K_X(undef2__resp_id) \
430 ((undef2__resp_id) & 0xFFF) /* 20:12 */
431
432#define GET_LARGE_RESP_ID(misc__large_resp_id) \
433 ((misc__large_resp_id) & 0xFFFF) /* 16:16 */
434
435#define GET_REQ_ID(lun_l4__req_id) \
436 (lun_l4__req_id & 0xFFF) /* 4:12 */
437
438#define GET_LUN_L4(lun_l4__req_id) \
439 ((lun_l4__req_id >> 12) & 0xF) /* 4:12 */
440
441#define GET_SGL_ENTRIES(lun_h4__sgl_entries) \
442 (lun_h4__sgl_entries & 0xFFF) /* 4:12 */
443
444#define GET_LUN_H4(lun_h4__sgl_entries) \
445 ((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */
446
447
448
449#endif /* TW_CL_FWIF_H */